Display device and electronic device including the same

Abstract

The utility model provides a kind of display device and electronic equipment comprising the display device.In a kind of display device comprising pixel, pixel includes: light emitting element;First transistor, control the driving current flowing through light emitting element, and including connect to the gate of first node, connect to the first electrode of second node and connect to the second electrode of third node;Second transistor, in response to first gate signal, data voltage is transmitted to fourth node;Storage capacitor, between first node and fourth node is connected;And eighth transistor, in response to second gate signal or first light emitting signal, first power voltage is transmitted to second node, and including receiving first light emitting signal's first gate and receiving second gate signal's second gate, the eighth transistor is oxide NMOS transistor.

Description

Technical Field

[0001] This utility model relates to a display device. Background Technology

[0002] The display device may include a display panel containing multiple pixels, a gate driver that provides gate signals to the pixels, and a data driver that provides data voltages to the pixels. Increasing the number of gate signals provided to each pixel may increase the power consumption and area of ​​the gate driver, thereby potentially increasing the power consumption and inactive areas of the display device.

[0003] The display device may include a demultiplexer that selectively connects multiple data lines to a channel of a data driver based on selection signals. Increasing the number of selection signals may increase the power consumption and area of ​​the demultiplexer, thereby potentially increasing the power consumption and inactive areas of the display device. Utility Model Content

[0004] One objective of this invention is to provide a display device with reduced power consumption and reduced ineffective areas, as well as an electronic device including the display device.

[0005] However, the purpose of this utility model is not limited to the purpose described above. Various expansions can be made without departing from the concept and scope of this utility model.

[0006] To achieve the aforementioned objective of this utility model, in a display device including pixels according to an embodiment, the pixel may include: a light-emitting element; a first transistor, controlling the driving current flowing through the light-emitting element, and including a gate connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor, transmitting a data voltage to a fourth node in response to a first gate signal; a storage capacitor, connected between the first node and the fourth node; and an eighth transistor, transmitting a first power supply voltage to the second node in response to a second gate signal or a first light-emitting signal, and including a first gate receiving the first light-emitting signal and a second gate receiving the second gate signal, wherein the eighth transistor is an oxide NMOS transistor.

[0007] In one embodiment, the pixel may further include: a third transistor that connects the first node to the third node in response to the second gate signal; a fourth transistor that transmits a first initialization voltage to the first node in response to the third gate signal; and a fifth transistor that transmits a reference voltage to the fourth node in response to the second gate signal.

[0008] In one embodiment, during the compensation interval, the eighth transistor can be turned on in response to the second gate signal having an activation level, and the first power supply voltage, which compensates for the threshold voltage of the first transistor, can be applied to the first node through the eighth transistor, the first transistor, and the third transistor.

[0009] In one embodiment, the pixel may further include: a sixth transistor that connects the third node to the anode of the light-emitting element in response to the first light-emitting signal; and a seventh transistor that transmits a second initialization voltage to the anode of the light-emitting element in response to the second light-emitting signal.

[0010] In one embodiment, in the light-emitting region, the eighth transistor can be turned on in response to the first light-emitting signal having an activation level, and the path of the drive current can be formed through the eighth transistor, the first transistor, and the sixth transistor.

[0011] In one embodiment, each of the first to seventh transistors may be an oxide NMOS transistor.

[0012] In one embodiment, the pixel may further include: a holding capacitor, including a first electrode connected to the fourth node and a second electrode receiving the first power supply voltage.

[0013] In one embodiment, the pixel may further include a ninth transistor that provides a bias voltage to the second node in response to the second light emission signal.

[0014] In one embodiment, the first transistor may be a polysilicon PMOS transistor, and each of the second to sixth transistors may be an oxide NMOS transistor.

[0015] In one embodiment, the seventh transistor and the ninth transistor may each be a polysilicon PMOS transistor.

[0016] To achieve the aforementioned objective of this utility model, a display device according to an embodiment may include: a substrate; a first gate electrode disposed on the substrate; a first insulating layer disposed on the first gate electrode; an active layer disposed on the first insulating layer, overlapping the first gate electrode, and comprising an oxide semiconductor; a second insulating layer disposed on the active layer; and a second gate electrode disposed on the second insulating layer, overlapping the active layer. The thickness ratio of the first insulating layer to the second insulating layer may be less than 2:1.

[0017] In one embodiment, the thickness of the first insulating layer may be greater than the thickness of the second insulating layer, but may be less than twice the thickness of the second insulating layer.

[0018] In one embodiment, when the first gate electrode is applied a signal with an activation level and the second gate electrode is applied a signal with an inactive level, a first channel may be formed in the portion of the active layer adjacent to the first insulating layer along the direction from the drain of the active layer to the source of the active layer.

[0019] In one embodiment, when the second gate electrode is applied with a signal having an activation level and the first gate electrode is applied with a signal having an inactive level, a second channel may be formed in the portion of the active layer adjacent to the second insulating layer along the direction from the drain to the source.

[0020] In one embodiment, the active layer may include at least one oxide semiconductor selected from indium gallium zinc oxide (IGZO), indium tin gallium zinc oxide (ITGZO), and indium gallium oxide (IGO).

[0021] To achieve the aforementioned objective of this utility model, a display device according to an embodiment may include: a display panel including a first pixel column connected to a first data line and a second pixel column connected to a second data line; a data driver including channels providing a first data voltage and a second data voltage to the first data line and the second data line, respectively; and a demultiplexer selectively connecting the channels to the first data line and the second data line. The demultiplexer may include: a first selection transistor that connects the channel to the first data line in response to a selection signal, the first selection transistor being a first type of transistor; and a second selection transistor that connects the channel to the second data line in response to the selection signal, the second selection transistor being a second type of transistor different from the first type of transistor.

[0022] In one embodiment, the first selection transistor may be an NMOS transistor, and the second selection transistor may be a PMOS transistor.

[0023] In one embodiment, the selection signal may have a logic high level in a first interval within a horizontal interval, and may have a logic low level in a second interval within the same horizontal interval immediately following the first interval.

[0024] In one embodiment, the first pixel column and the second pixel column may be adjacent in a first direction.

[0025] In one embodiment, the first pixel column may include red and blue pixels arranged alternately in a second direction intersecting the first direction, and the second pixel column may include green pixels arranged in the second direction.

[0026] To achieve the aforementioned objective of this utility model, in an electronic device according to an embodiment comprising a display device including pixels and a processor controlling the display device, the pixel may include: a light-emitting element; a first transistor for controlling a drive current flowing through the light-emitting element, and including a gate connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor for transmitting a data voltage to a fourth node in response to a first gate signal; a storage capacitor connected between the first node and the fourth node; and an eighth transistor for transmitting a first power supply voltage to the second node in response to a second gate signal or a first light-emitting signal, including a first gate receiving the first light-emitting signal and a second gate receiving the second gate signal, wherein the eighth transistor is an oxide NMOS transistor.

[0027] In the display device and electronic device including the display device according to embodiments of the present invention, since the eighth transistor of the pixel is turned on in response to the second gate signal or the first light emission signal, the number of signals provided to the pixel can be reduced, and the power consumption and invalid area of ​​the display device can be reduced. Furthermore, since the first selection transistor and the second selection transistor of the demultiplexer are turned on in response to the selection signal, the number of selection signals can be reduced, and the power consumption and invalid area of ​​the display device can be reduced.

[0028] However, the effects of this utility model are not limited to those described above. Various expansions can be made without departing from the concept and scope of this utility model. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating a display device according to one embodiment.

[0030] Figure 2 It is shown Figure 1 A circuit diagram of an example pixel.

[0031] Figure 3 It shows that it is provided to Figure 2 Timing diagram of the gate signal and light emission signal of the pixel.

[0032] Figures 4 to 8 It is used for explanation Figure 2 A diagram showing the operations of pixels.

[0033] Figure 9 It is shown Figure 1 An example circuit diagram of pixels.

[0034] Figure 10 It is shown Figure 2 and Figure 9 A cross-sectional view of the eighth transistor.

[0035] Figure 11 and Figure 12 It is used for explanation Figure 10 A diagram showing the operation of the eighth transistor.

[0036] Figure 13 This is a block diagram illustrating a display device according to one embodiment.

[0037] Figure 14 It is shown Figure 13 A circuit diagram of an example demultiplexer.

[0038] Figure 15 It shows that it is provided to Figure 14 Timing diagram of the selection signal of the demultiplexer.

[0039] Figure 16 This is a block diagram illustrating an electronic device according to one embodiment.

[0040] Explanation of reference numerals in the attached figures

[0041] Detailed Implementation

[0042] Hereinafter, with reference to the accompanying drawings, a display device and electronic device according to embodiments of the present invention will be described in more detail. The same or similar reference numerals are used for the same constituent elements in the drawings.

[0043] Figure 1 This is a block diagram illustrating a display device 100 according to an embodiment.

[0044] Reference Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a light-emitting driver 130, a data driver 140, and a controller 150.

[0045] The display panel 110 may include multiple pixels PX, multiple gate lines, multiple light-emitting lines, and multiple data lines DL1, DL2, ..., DL2m-1, DL2m (where m is a natural number greater than 2). Pixels PX may be connected to the gate lines, light-emitting lines, and data lines DL1, DL2, ..., DL2m-1, DL2m.

[0046] The gate lines may extend along a first direction D1 and may be arranged along a second direction D2 intersecting the first direction D1. The gate lines may transmit gate signals GW, GC, and GI. The gate signals GW, GC, and GI may include a first gate signal GW, a second gate signal GC, and a third gate signal GI.

[0047] The light-emitting lines can extend along a first direction D1 and can be arranged along a second direction D2. The light-emitting lines can transmit light-emitting signals EM and EB. The light-emitting signals EM and EB can include a first light-emitting signal EM and a second light-emitting signal EB.

[0048] Data lines DL1, DL2, ..., DL2m-1, DL2m can extend along the second direction D2 and can be arranged along the first direction D1. Data lines DL1, DL2, ..., DL2m-1, DL2m can transmit data voltages VDAT1, VDAT2, ..., VDAT2m-1, VDAT2m.

[0049] The gate driver 120 can output gate signals GW, GC, and GI to the gate line. The gate driver 120 can generate gate signals GW, GC, and GI based on the gate control signal GCNT. The gate control signal GCNT may include a gate clock signal, a gate enable signal, etc.

[0050] The LED driver 130 can output LED signals EM and EB to the LED line. The LED driver 130 can generate LED signals EM and EB based on the LED control signal ECNT. The LED control signal ECNT may include an LED clock signal, an LED start signal, etc.

[0051] Data driver 140 can output data voltages VDAT1, VDAT2, ..., VDAT2m-1, and VDAT2m to data lines DL1, DL2, ..., DL2m-1, DL2m. Data driver 140 can generate data voltages VDAT1, VDAT2, ..., VDAT2m-1, and VDAT2m based on the data signal DATA and the data control signal DCNT. Data driver 140 can convert the digital data signal DATA into analog data voltages VDAT1, VDAT2, ..., VDAT2m-1, and VDAT2m. The data control signal DCNT may include a data clock signal, a load signal, etc.

[0052] The data driver 140 may include multiple channels CH1, CH2, ..., CH2m-1, CH2m that respectively provide data voltages VDAT1, VDAT2, ..., VDAT2m-1, VDAT2m to data lines DL1, DL2, ..., DL2m-1, DL2m. The number of channels CH1, CH2, ..., CH2m-1, CH2m may be the same as the number of data lines DL1, DL2, ..., DL2m-1, DL2m.

[0053] The controller 150 can control the operation of the gate driver 120, the light-emitting driver 130, and the data driver 140. The controller 150 can provide the gate control signal GCNT to the gate driver 120, the light-emitting control signal ECNT to the light-emitting driver 130, and the data signal DATA and the data control signal DCNT to the data driver 140. The controller 150 can generate the gate control signal GCNT, the light-emitting control signal ECNT, the data signal DATA, and the data control signal DCNT based on the image data IMG and the controller control signal CTRL. The image data IMG may include the grayscale corresponding to pixels PX. The controller control signal CTRL may include a master clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, etc.

[0054] Figure 2 It is shown Figure 1 A circuit diagram of an example pixel PX1.

[0055] Reference Figure 2 Pixel PX1 can receive a first gate signal GW, a second gate signal GC, a third gate signal GI, a first light emission signal EM, a second light emission signal EB, a data voltage VDAT, a first initialization voltage VINIT, a second initialization voltage VAINIT, a reference voltage VREF, a first power supply voltage ELVDD, and a second power supply voltage ELVSS. Pixel PX1 may include a light-emitting element LED, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a storage capacitor CST, and a holding capacitor CHD.

[0056] The light-emitting element (LED) can emit light with a brightness corresponding to the driving current. The LED may include an anode connected to the fifth node N5 and a cathode that receives a second power supply voltage ELVSS.

[0057] The first transistor T1 can control the driving current flowing through the light-emitting element LED. The first transistor T1 may include a gate connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3.

[0058] The second transistor T2 can transmit a data voltage VDAT to the fourth node N4 in response to the first gate signal GW. The second transistor T2 may include a gate for receiving the first gate signal GW, a first electrode for receiving the data voltage VDAT, and a second electrode connected to the fourth node N4.

[0059] The third transistor T3 can connect the first node N1 and the third node N3 in response to the second gate signal GC. The third transistor T3 may include a gate for receiving the second gate signal GC, a first electrode connected to the third node N3, and a second electrode connected to the first node N1.

[0060] The fourth transistor T4 can transmit a first initialization voltage VINIT to the first node N1 in response to the third gate signal GI. The fourth transistor T4 may include a gate for receiving the third gate signal GI, a first electrode for receiving the first initialization voltage VINIT, and a second electrode connected to the first node N1.

[0061] The fifth transistor T5 can transmit a reference voltage VREF to the fourth node N4 in response to the second gate signal GC. The fifth transistor T5 may include a gate for receiving the second gate signal GC, a first electrode for receiving the reference voltage VREF, and a second electrode connected to the fourth node N4.

[0062] The sixth transistor T6 can connect the third node N3 and the fifth node N5 in response to the first light-emitting signal EM. The sixth transistor T6 may include a gate for receiving the first light-emitting signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fifth node N5.

[0063] The seventh transistor T7 can transmit a second initialization voltage VAINIT to the fifth node N5 in response to the second light emission signal EB. The seventh transistor T7 may include a gate for receiving the second light emission signal EB, a first electrode for receiving the second initialization voltage VAINIT, and a second electrode connected to the fifth node N5.

[0064] In one embodiment, each of the first transistor T1 to the seventh transistor T7 may be an oxide NMOS transistor. An oxide NMOS transistor may be an NMOS transistor comprising oxide semiconductor. However, the present invention is not limited thereto; in another embodiment, at least one of the first transistor T1 to the seventh transistor T7 may also be a polysilicon PMOS transistor. A polysilicon PMOS transistor may be a PMOS transistor comprising polysilicon semiconductor.

[0065] The eighth transistor T8 can transmit a first power supply voltage ELVDD to the second node N2 in response to a second gate signal GC or a first light-emitting signal EM. The eighth transistor T8 may include a first gate receiving the first light-emitting signal EM, a second gate receiving the second gate signal GC, a first electrode receiving the first power supply voltage ELVDD, and a second electrode connected to the second node N2. The eighth transistor T8 may be an oxide NMOS transistor.

[0066] The eighth transistor T8 can be turned on in response to a signal applied to the first gate or a signal applied to the second gate. In other words, the eighth transistor T8 can be turned on when a first light-emitting signal EM with an activation level is applied to the first gate or when a second gate signal GC with an activation level is applied to the second gate.

[0067] The storage capacitor CST can store the signal of the first node N1 and can transmit the signal changes of the fourth node N4 back to the first node N1 using the coupling effect. The storage capacitor CST can be connected between the first node N1 and the fourth node N4.

[0068] The holding capacitor CHD can store the signal of the fourth node N4. The holding capacitor CHD may include a first electrode connected to the fourth node N4 and a second electrode receiving the first power supply voltage ELVDD.

[0069] Figure 3 It shows that it is provided to Figure 2 Timing diagram of the gate signals GW, GC, GI and the light emission signals EM, EB of pixel PX1. Figures 4 to 8 It is used for explanation Figure 2 A diagram showing the operation of pixel PX1.

[0070] Reference Figure 3 and Figure 4 In the first initialization interval PI1, the fourth transistor T4 can be turned on in response to the third gate signal GI with an activation level, and a first initialization voltage VINIT can be applied to the first node N1 through the fourth transistor T4. Accordingly, the charge stored in the first node N1 can be discharged to the line transmitting the first initialization voltage VINIT, and the first transistor T1 can be turned on.

[0071] Reference Figure 3 and Figure 5In the first compensation interval PC1, the eighth transistor T8 and the third transistor T3 can be turned on in response to the second gate signal GC with an activation level, and a first power supply voltage ELVDD, which compensates for the threshold voltage of the first transistor T1, can be applied to the first node N1 through the eighth transistor T8, the first transistor T1, and the third transistor T3. The first power supply voltage ELVDD, which compensates for the threshold voltage of the first transistor T1, can correspond to the value obtained by subtracting the threshold voltage of the first transistor T1 from the first power supply voltage ELVDD. Furthermore, the fifth transistor T5 can be turned on in response to the second gate signal GC with an activation level, and a reference voltage VREF can be applied to the fourth node N4 through the fifth transistor T5. In the first initialization interval PI1, the previous data voltage can be stored in the fourth node N4, and the voltage difference between the reference voltage VREF and the previous data voltage can be transmitted to the first node N1 through the coupling effect of the storage capacitor CST. Accordingly, the value of the first power supply voltage ELVDD, which compensates for the threshold voltage of the first transistor T1, plus the voltage difference between the reference voltage VREF and the previous data voltage, can be stored in the first node N1.

[0072] Refer again Figure 3 and Figure 4 In the second initialization interval PI2, the fourth transistor T4 can be turned on in response to the third gate signal GI with an activation level, and a first initialization voltage VINIT can be applied to the first node N1 through the fourth transistor T4. Accordingly, the charge stored in the first node N1 can be discharged to the line transmitting the first initialization voltage VINIT, and the first transistor T1 can be turned on.

[0073] Refer again Figure 3 and Figure 5 In the second compensation interval PC2, the eighth transistor T8 and the third transistor T3 can be turned on in response to the second gate signal GC with an activation level, and a first power supply voltage ELVDD, which compensates for the threshold voltage of the first transistor T1, can be applied to the first node N1 through the eighth transistor T8, the first transistor T1, and the third transistor T3. Furthermore, the fifth transistor T5 can be turned on in response to the second gate signal GC with an activation level, and a reference voltage VREF can be applied to the fourth node N4 through the fifth transistor T5. In the second initialization interval PI2, the reference voltage VREF can be stored in the fourth node N4, and the signal of the fourth node N4 can remain unchanged. Accordingly, the first power supply voltage ELVDD, which compensates for the threshold voltage of the first transistor T1, can be stored in the first node N1.

[0074] Reference Figure 3 and Figure 6In the data write interval PW, the second transistor T2 can be turned on in response to the first gate signal GW with an activation level, and the data voltage VDAT can be applied to the fourth node N4 through the second transistor T2. In the second compensation interval PC2, the reference voltage VREF can be stored at the fourth node N4, and the voltage difference between the data voltage VDAT and the reference voltage VREF can be transmitted to the first node N1 through the coupling effect of the storage capacitor CST. Accordingly, the value of the first power supply voltage ELVDD, which compensates for the threshold voltage of the first transistor T1, plus the voltage difference between the data voltage VDAT and the reference voltage VREF can be stored in the first node N1.

[0075] Reference Figure 3 and Figure 7 In the bypass interval PB, the seventh transistor T7 can be turned on in response to the second light-emitting signal EB with an activation level, and the second initialization voltage VAINIT can be applied to the fifth node N5 through the seventh transistor T7. Accordingly, the charge stored in the fifth node N5 can be discharged to the line transmitting the second initialization voltage VAINIT, and the light-emitting element LED can be initialized.

[0076] Reference Figure 3 and Figure 8 In the light-emitting region PE, the eighth transistor T8 and the sixth transistor T6 can be turned on in response to the first light-emitting signal EM with an activation level, and a path for the driving current can be formed through the eighth transistor T8, the first transistor T1, and the sixth transistor T6. The driving current can correspond to the value of the voltage difference between the gate and the first electrode of the first transistor T1 minus the threshold voltage of the first transistor T1, and the light-emitting element LED can emit light with a brightness corresponding to the driving current.

[0077] Figure 9 It is shown Figure 1 A circuit diagram of an example pixel PX2.

[0078] Reference Figure 9 Pixel PX2 can receive a first gate signal GW, a second gate signal GC, a third gate signal GI, a first light emission signal EM, a second light emission signal EB, a data voltage VDAT, a first initialization voltage VINIT, a second initialization voltage VAINIT, a reference voltage VREF, a first power supply voltage ELVDD, a second power supply voltage ELVSS, and a bias voltage VBIAS. Pixel PX2 may include a light-emitting element LED, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a storage capacitor CST, and a holding capacitor CHD.

[0079] In reference Figure 9 In the description of pixel PX2, the reference is omitted. Figures 2 to 8 The description describes the structure of pixels PX1 that are substantially the same or similar.

[0080] The ninth transistor T9 can transmit a bias voltage VBIAS to the second node N2 in response to the second light-emitting signal EB. The ninth transistor T9 may include a gate for receiving the second light-emitting signal EB, a first electrode for receiving the bias voltage VBIAS, and a second electrode connected to the second node N2.

[0081] In one embodiment, each of the first transistor T1, the seventh transistor T7, and the ninth transistor T9 may be a polysilicon PMOS transistor, and each of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may be an oxide NMOS transistor. However, the present invention is not limited thereto; in another embodiment, at least one of the seventh transistor T7 and the ninth transistor T9 may also be an oxide NMOS transistor.

[0082] Reference Figure 3 and Figure 9 In the bypass interval PB, the ninth transistor T9 can be turned on in response to the second light-emitting signal EB with an activation level, and a bias voltage VBIAS can be applied to the second node N2 through the ninth transistor T9. Accordingly, the hysteresis of the first transistor T1 can be reduced, and the shift of the threshold voltage of the first transistor T1 can be decreased.

[0083] In the display device 100 according to this embodiment, since the eighth transistor T8 of the pixels PX1 and PX2 is turned on in response to the second gate signal GC or the first light emission signal EM, the number of signals provided to the pixels PX1 and PX2 can be reduced, and the power consumption and invalid area of ​​the display device 100 can be reduced.

[0084] Figure 10 It is shown Figure 2 and Figure 9 A cross-sectional view of the eighth transistor T8.

[0085] Reference Figure 10 The display device may include a substrate SUB, a buffer layer BUF, a first gate electrode GE1, a first insulating layer INS1, an active layer ACT, a second insulating layer INS2, and a second gate electrode GE2. An eighth transistor T8 may be defined by the first gate electrode GE1, the first insulating layer INS1, the active layer ACT, the second insulating layer INS2, and the second gate electrode GE2.

[0086] The buffer layer (BUF) can be disposed on the substrate (SUB). The buffer layer (BUF) may include silicon compounds such as silicon nitride, silicon oxide, and silicon oxide nitride.

[0087] The first gate electrode GE1 can be disposed on the buffer layer BUF. The first gate electrode GE1 can include metals such as molybdenum (Mo), titanium (Ti), and aluminum (Al). The first gate electrode GE1 can correspond to the second gate of the eighth transistor T8.

[0088] Although Figure 10 The illustration shows a case where a buffer layer BUF is arranged between the substrate SUB and the first gate electrode GE1, but the present invention is not limited thereto. In one embodiment, an additional insulating layer may be arranged between the substrate SUB and the first gate electrode GE1 in addition to the buffer layer BUF. In one embodiment, a buffer layer BUF may not be arranged between the substrate SUB and the first gate electrode GE1.

[0089] A first insulating layer INS1 may be disposed on the first gate electrode GE1. The first insulating layer INS1 can insulate the active layer ACT from the first gate electrode GE1. The first insulating layer INS1 may include silicon compounds such as silicon nitride, silicon oxide, and silicon nitride.

[0090] The active layer ACT can be disposed on the first insulating layer INS1 and can overlap with the first gate electrode GE1. An active electrode SC can be formed at the first end of the active layer ACT, and a drain electrode DR can be formed at the second end of the active layer ACT opposite to the first end. The drain electrode DR can correspond to the first electrode of the eighth transistor T8, and the source electrode SC can correspond to the second electrode of the eighth transistor T8.

[0091] The active layer ACT may include an oxide semiconductor. In one embodiment, the active layer ACT may include at least one oxide semiconductor selected from indium gallium zinc oxide (IGZO), indium tin gallium zinc oxide (ITGZO), and indium gallium oxide (IGO). Accordingly, the active layer ACT can have a relatively high charge mobility.

[0092] The second insulating layer INS2 can be disposed on the active layer ACT. The second insulating layer INS2 can insulate the second gate electrode GE2 from the active layer ACT. The second insulating layer INS2 may include silicon compounds such as silicon nitride, silicon oxide, and silicon oxynitride.

[0093] The second gate electrode GE2 can be disposed on the second insulating layer INS2 and can overlap with the active layer ACT. The second gate electrode GE2 can include metals such as molybdenum (Mo), titanium (Ti), and aluminum (Al). The second gate electrode GE2 can correspond to the first gate of the eighth transistor T8.

[0094] The thickness ratio of the first insulating layer INS1 to the second insulating layer INS2 can be less than 2:1. In one embodiment, the thickness TH1 of the first insulating layer INS1 can be greater than the thickness TH2 of the second insulating layer INS2, but less than twice the thickness TH2 of the second insulating layer INS2.

[0095] Figure 11 and Figure 12 It is used for explanation Figure 10 The diagram shows the operation of the eighth transistor T8.

[0096] Reference Figure 11 and Figure 12 When an activation level ACL signal is applied to the first gate electrode GE1 or the second gate electrode GE2, the eighth transistor T8 can be turned on. When the thickness ratio of the first insulating layer INS1 to the second insulating layer INS2 is less than 2:1 and the active layer ACT has a relatively high charge mobility, the eighth transistor T8 can be turned on in response to an activation level ACL signal applied to one of the first gate electrode GE1 or the second gate electrode GE2.

[0097] like Figure 11 As shown, when a signal with an activation level ACL is applied to the first gate electrode GE1 and a signal with an inactive level DACL is applied to the second gate electrode GE2, a first channel CN1 can be formed in the portion of the active layer ACT adjacent to the first insulating layer INS1 along the direction from the drain DR to the source SC. Accordingly, the eighth transistor T8 can be turned on, and current can flow from the drain DR to the source SC through the first channel CN1.

[0098] like Figure 12 As shown, when a signal with an activation level ACL is applied to the second gate electrode GE2 and a signal with an inactive level DACL is applied to the first gate electrode GE1, a second channel CN2 can be formed in the portion of the active layer ACT adjacent to the second insulating layer INS2 along the direction from the drain DR to the source SC. Accordingly, the eighth transistor T8 can be turned on, and current can flow from the drain DR to the source SC through the second channel CN2.

[0099] Figure 13 This is a block diagram illustrating a display device 101 according to an embodiment.

[0100] Reference Figure 13 The display device 101 may include a display panel 110, a gate driver 120, a light-emitting driver 130, a data driver 141, a demultiplexer 160, and a controller 150.

[0101] In reference Figure 13 In the description of the display device 101, references are omitted. Figure 1 The description describes a configuration that is substantially the same as or similar to that of the display device 100.

[0102] Data driver 141 can output data voltages VDAT1, VDAT2, ..., VDAT2m-1, VDAT2m to output lines OL1, ..., OLm. Data driver 141 may include multiple channels CH1, ..., CHm that respectively provide data voltages VDAT1, VDAT2, ..., VDAT2m-1, VDAT2m to data lines DL1, DL2, ..., DL2m-1, DL2m. The number of channels CH1, ..., CHm may be the same as the number of output lines OL1, ..., OLm, and may be less than the number of data lines DL1, DL2, ..., DL2m-1, DL2m. In one embodiment, the number of channels CH1, ..., CHm may be half the number of data lines DL1, DL2, ..., DL2m-1, DL2m.

[0103] Demultiplexer 160 can selectively connect channels CH1, ..., CHm to data lines DL1, DL2, ..., DL2m-1, DL2m. Demultiplexer 160 can selectively connect output lines OL1, ..., OLm, which are respectively connected to channels CH1, ..., CHm, to data lines DL1, DL2, ..., DL2m-1, DL2m. Because demultiplexer 160 selectively connects channels CH1, ..., CHm to data lines DL1, DL2, ..., DL2m-1, DL2m, the number of channels CH1, ..., CHm in data driver 141 can be reduced, and the power consumption and area of ​​data driver 141 can be reduced.

[0104] Figure 14 It is shown Figure 13 A circuit diagram of an example of a demultiplexer 160. Figure 15 It shows that it is provided to Figure 14 Timing diagram of the selection signal SEL of demultiplexer 160.

[0105] Reference Figure 14 and Figure 15The display panel 110 may include a plurality of pixel columns C1, C2, C3, C4, C5, C6, ... extending along a second direction D2 and arranged in a first direction D1. Each of the pixel columns C1, C2, C3, C4, C5, C6, ... may include a plurality of pixels R, G, B. The first pixel column C1 may be connected to a first data line DL1, and the second pixel column C2 may be connected to a second data line DL2. The first pixel column C1 and the second pixel column C2 may be adjacent in the first direction D1. In one embodiment, the first pixel column C1 may include red pixels R and blue pixels B arranged alternately in the second direction D2, and the second pixel column C2 may include green pixels G arranged in the second direction D2. Since the third pixel column C3 and the fifth pixel column C5 are substantially the same as or similar to the first pixel column C1, and the fourth pixel column C4 and the sixth pixel column C6 are substantially the same as or similar to the second pixel column C2, the description of the third pixel column C3 to the sixth pixel column C6 is omitted.

[0106] Demultiplexer 160 can selectively connect the first channel CH1 to the first data line DL1 and the second data line DL2, selectively connect the second channel CH2 to the third data line DL3 and the fourth data line DL4, and selectively connect the third channel CH3 to the fifth data line DL5 and the sixth data line DL6. Demultiplexer 160 may include a plurality of selection transistors TS1, TS2, TS3, TS4, TS5, TS6, ... arranged in the first direction D1. The selection transistors TS1, TS2, TS3, TS4, TS5, TS6, ... can be turned on in response to the selection signal SEL.

[0107] The first selection transistor TS1 can connect the first channel CH1 to the first data line DL1 in response to the selection signal SEL. The first selection transistor TS1 may include a gate for receiving the selection signal SEL, a first electrode connected to the first output line OL1, and a second electrode connected to the first data line DL1.

[0108] The second selection transistor TS2 can connect the first channel CH1 to the second data line DL2 in response to the selection signal SEL. The second selection transistor TS2 may include a gate for receiving the selection signal SEL, a first electrode connected to the first output line OL1, and a second electrode connected to the second data line DL2.

[0109] The first selection transistor TS1 can be a first type of transistor, and the second selection transistor TS2 can be a second type of transistor, different from the first type of transistor. In one embodiment, the first selection transistor TS1 can be an NMOS transistor, and the second selection transistor TS2 can be a PMOS transistor.

[0110] In one embodiment, the selection signal SEL can have a logic high level in a first interval P1 of a horizontal interval 1H, and can have a logic low level in a second interval P2 of a horizontal interval 1H immediately following the first interval P1.

[0111] In the first interval P1, in response to a selection signal SEL with a logic high level, the first selection transistor TS1 can be turned on, and the second selection transistor TS2 can be turned off. Accordingly, in the first interval P1, the first data voltage VDAT1 output from the first channel CH1 can be provided to the first data line DL1 through the first selection transistor TS1.

[0112] In the second interval P2, in response to the selection signal SEL with a logic low level, the first selection transistor TS1 can be turned off, and the second selection transistor TS2 can be turned on. Accordingly, in the second interval P2, the second data voltage VDAT2 output from the first channel CH1 can be provided to the second data line DL2 through the second selection transistor TS2.

[0113] Since the third selection transistor TS3 and the fifth selection transistor TS5 are substantially the same as or similar to the first selection transistor TS1, and the fourth selection transistor TS4 and the sixth selection transistor TS6 are substantially the same as or similar to the second selection transistor TS2, the description of the third selection transistor TS3 to the sixth selection transistor TS6 is omitted.

[0114] In the display device 101 according to this embodiment, since the selection transistors TS1, TS2, TS3, TS4, TS5, TS6, ... of the demultiplexer 160 are turned on in response to the selection signal SEL, the number of selection signals SEL can be reduced, and the power consumption and invalid areas of the display device 101 can be reduced.

[0115] Figure 16 This is a block diagram illustrating an electronic device 1000 according to an embodiment.

[0116] Reference Figure 16 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. The electronic device 1000 may also include multiple ports capable of communicating with graphics cards, sound cards, memory cards, USB devices, etc., or with other systems.

[0117] Processor 1010 can perform specific calculations or tasks. In one embodiment, processor 1010 can be a microprocessor, central processing unit (CPU), etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In one embodiment, processor 1010 can also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0118] Processor 1010 can control display device 1060. In one embodiment, processor 1010 can generate image data ( Figure 1 and Figure 13 Image data (IMG) and controller control signals ( Figure 1 and Figure 13 The controller control signal CTRL can be used to provide image data IMG and the controller control signal CTRL to the display device 1060.

[0119] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), and / or volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), and mobile DRAM.

[0120] Storage device 1030 may include a solid-state drive (SSD), a hard disk drive (HDD), a read-only optical disc drive (CD-ROM), etc. Input / output device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, mouse, etc., and output devices such as speakers, printers, etc. Power supply 1050 provides the power required for the operation of electronic device 1000. Display device 1060 can be connected to other components via the bus or other communication links. Display device 1060 may correspond to... Figure 1 The display device 100 or Figure 13 The display device 101.

[0121] In the display device 1060, since the eighth transistor of the pixel is turned on in response to the second gate signal or the first light emission signal, the number of signals supplied to the pixel can be reduced, and the power consumption and invalid area of ​​the display device 1060 can be reduced. Furthermore, since the first selection transistor and the second selection transistor of the demultiplexer are turned on in response to the selection signal, the number of selection signals can be reduced, and the power consumption and invalid area of ​​the display device 1060 can be reduced.

[0122] Industrial availability

[0123] The display device according to the exemplary embodiments of the present invention can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, smartwatches, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, etc.

[0124] The display device and electronic device according to exemplary embodiments of the present invention have been described above with reference to the accompanying drawings. However, the foregoing embodiments are merely exemplary, and modifications and alterations can be made by those skilled in the art without departing from the scope of the technical concept of the present invention as set forth in the claims.

Claims

1. A display device comprising pixels, characterized in that, The pixels include: Light-emitting elements; The first transistor controls the driving current flowing through the light-emitting element and includes a gate connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. The second transistor transmits data voltage to the fourth node in response to the first gate signal; A storage capacitor is connected between the first node and the fourth node; and The eighth transistor transmits a first power supply voltage to the second node in response to a second gate signal or a first light emission signal, and includes a first gate for receiving the first light emission signal and a second gate for receiving the second gate signal. The eighth transistor is an oxide NMOS transistor.

2. The display device according to claim 1, characterized in that, The pixels also include: The third transistor connects the first node and the third node in response to the second gate signal; A fourth transistor, in response to a third gate signal, transmits a first initialization voltage to the first node; and The fifth transistor transmits a reference voltage to the fourth node in response to the second gate signal.

3. The display device according to claim 2, characterized in that, During the compensation interval, the eighth transistor is turned on in response to the second gate signal having an activation level, and the first power supply voltage, which compensates for the threshold voltage of the first transistor, is applied to the first node through the eighth transistor, the first transistor, and the third transistor.

4. The display device according to claim 2, characterized in that, The pixels also include: A sixth transistor, in response to the first light-emitting signal, connects the third node to the anode of the light-emitting element; and The seventh transistor transmits a second initialization voltage to the anode of the light-emitting element in response to the second light-emitting signal.

5. The display device according to claim 4, characterized in that, In the light-emitting region, the eighth transistor is turned on in response to the first light-emitting signal having an activation level, and the path of the drive current is formed through the eighth transistor, the first transistor, and the sixth transistor.

6. The display device according to claim 4, characterized in that, Each of the first to seventh transistors is an oxide NMOS transistor.

7. The display device according to claim 4, characterized in that, The pixels also include: The holding capacitor includes a first electrode connected to the fourth node and a second electrode that receives the first power supply voltage.

8. The display device according to claim 4, characterized in that, The pixels also include: The ninth transistor provides a bias voltage to the second node in response to the second light-emitting signal.

9. The display device according to claim 8, characterized in that, The first transistor is a polysilicon PMOS transistor. Each of the second to the sixth transistors is an oxide NMOS transistor.

10. The display device according to claim 8, characterized in that, The seventh transistor and the ninth transistor are both polysilicon PMOS transistors.

11. A display device, characterized in that, include: substrate; A first gate electrode is disposed on the substrate; A first insulating layer is disposed on the first gate electrode; An active layer is disposed on the first insulating layer, overlaps with the first gate electrode, and includes an oxide semiconductor. A second insulating layer is disposed on the active layer; as well as The second gate electrode is disposed on the second insulating layer and overlaps with the active layer. Wherein, the thickness ratio of the first insulating layer to the second insulating layer is less than 2:

1.

12. The display device according to claim 11, characterized in that, The thickness of the first insulating layer is greater than the thickness of the second insulating layer, but less than twice the thickness of the second insulating layer.

13. The display device according to claim 11, characterized in that, When a signal with an activation level is applied to the first gate electrode and a signal with an inactivation level is applied to the second gate electrode, a first channel is formed in the portion of the active layer adjacent to the first insulating layer along the direction from the drain of the active layer to the source of the active layer.

14. The display device according to claim 13, characterized in that, When a signal with an activation level is applied to the second gate electrode and a signal with an inactive level is applied to the first gate electrode, a second channel is formed in the portion of the active layer adjacent to the second insulating layer along the direction from the drain to the source.

15. A display device, characterized in that, include: The display panel includes a first pixel column connected to a first data line and a second pixel column connected to a second data line; A data driver includes channels that provide a first data voltage and a second data voltage to the first data line and the second data line, respectively; as well as The demultiplexer selectively connects the channel to the first data line and the second data line. The demultiplexer includes: A first selection transistor, in response to a selection signal, connects the channel to the first data line, wherein the first selection transistor is a first type of transistor; and A second selection transistor connects the channel to the second data line in response to the selection signal. The second selection transistor is a second type of transistor different from the first type of transistor.

16. The display device according to claim 15, characterized in that, The first selection transistor is an NMOS transistor, and the second selection transistor is a PMOS transistor.

17. The display device according to claim 15, characterized in that, The selection signal has a logic high level in a first interval within a horizontal interval, and a logic low level in a second interval within the same horizontal interval immediately following the first interval.

18. The display device according to claim 15, characterized in that, The first pixel column and the second pixel column are adjacent in a first direction.

19. The display device according to claim 18, characterized in that, The first pixel column includes red and blue pixels arranged alternately in a second direction intersecting the first direction, and the second pixel column includes green pixels arranged in the second direction.

20. An electronic device comprising a display device and a processor for controlling the display device, characterized in that, The display device is the display device according to any one of claims 1 to 19.

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