Pixel driving circuit, display panel and display device

Abstract

The present disclosure relates to the technical field of display, and provides a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a driving circuit, a first light-emitting control circuit, a second light-emitting control circuit, a third light-emitting control circuit and a first reset circuit. The driving circuit is configured to form a driving current between a second node and a third node according to a voltage of a first node; the first light-emitting control circuit is configured to connect a first power supply end and the second node in response to a signal of a first enable signal end; the second light-emitting control circuit is configured to connect the third node and a fourth node in response to a signal of a second enable signal end; the third light-emitting control circuit is configured to connect the fourth node and a fifth node in response to a signal of a third enable signal end, and the fifth node is configured to connect a light-emitting unit; and the first reset circuit is configured to transmit a signal of a first initial signal end to the fourth node in response to a signal of a first reset signal end. The display panel has a better display effect.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a display device. Background Technology

[0002] In related technologies, the pixel driving circuit resets the anode of the light-emitting unit and the output terminal of the driving transistor through a reset circuit. However, the reset effect of the output terminal of the driving transistor in related technologies is poor, which affects the display effect of the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a pixel driving circuit is provided, wherein the pixel driving circuit includes:

[0005] A driving circuit is connected to a first node, a second node, and a third node. The driving circuit is used to generate a driving current between the second node and the third node based on the voltage of the first node.

[0006] A first light-emitting control circuit is connected to a first power supply terminal, a second node, and a first enable signal terminal. The first light-emitting control circuit is used to respond to the signal of the first enable signal terminal to connect the first power supply terminal and the second node.

[0007] The second light-emitting control circuit is connected to the third node, the second enable signal terminal, and the fourth node. The second light-emitting control circuit is used to respond to the signal of the second enable signal terminal to connect the third node and the fourth node.

[0008] The third light-emitting control circuit is connected to the fourth node, the third enable signal terminal, and the fifth node. The third light-emitting control circuit is used to respond to the signal of the third enable signal terminal to connect the fourth node and the fifth node. The fifth node is used to connect the light-emitting unit.

[0009] A first reset circuit is connected to the fourth node, a first initial signal terminal, and a first reset signal terminal. The first reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initial signal terminal to the fourth node.

[0010] In one exemplary embodiment of this disclosure, the driving circuit includes:

[0011] A driving transistor, with its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the first node;

[0012] The first light-emitting control circuit includes:

[0013] The first transistor has a first terminal connected to the first power supply terminal, a second terminal connected to the second node, and a gate connected to the first enable signal terminal.

[0014] The second light-emitting control circuit includes:

[0015] The second transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the second enable signal terminal.

[0016] The third light-emitting control circuit includes:

[0017] The fourth transistor has its first terminal connected to the fourth node, its second terminal connected to the fifth node, and its gate connected to the third enable signal terminal.

[0018] The first reset circuit includes:

[0019] The fifth transistor has its first terminal connected to the first initial signal terminal, its second terminal connected to the fourth node, and its gate connected to the first reset signal terminal.

[0020] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0021] The first capacitor has its first electrode connected to the first node;

[0022] The second capacitor has its first electrode connected to the second electrode of the first capacitor.

[0023] An initialization circuit is connected to the first or second electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the first or second electrode of the second capacitor.

[0024] In one exemplary embodiment of this disclosure, the first reset circuit is multiplexed as the initialization circuit, the first reset circuit is also connected to the first electrode or the second electrode of the second capacitor, and the first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the first electrode or the second electrode of the second capacitor using the first initial signal terminal.

[0025] In one exemplary embodiment of this disclosure, the second electrode of the first capacitor and the first electrode of the second capacitor are connected to the third node;

[0026] The pixel driving circuit also includes:

[0027] The second reset circuit is connected to the first node, the reference voltage terminal, and the second reset signal terminal. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the first node.

[0028] A data writing circuit is connected to the first node or the fourth node, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the first node or the fourth node.

[0029] The initialization circuit is connected to the second electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the second electrode of the second capacitor;

[0030] The second electrode of the second capacitor is also connected to the fourth node, and the first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the second electrode of the second capacitor using the first initial signal terminal.

[0031] In one exemplary embodiment of this disclosure, the second reset circuit includes:

[0032] The sixth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the first node, and its gate connected to the second reset signal terminal.

[0033] The data writing circuit includes:

[0034] The seventh transistor has its first terminal connected to the data signal terminal, its second terminal connected to the first node or the fourth node, and its gate connected to the first gate drive signal terminal.

[0035] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0036] A connection circuit is provided to connect the second electrode and the fourth node of the second capacitor in response to a control signal.

[0037] In an exemplary embodiment of this disclosure, the connection circuit is connected to a third gate drive signal terminal, and the connection circuit is used to connect the second electrode of the second capacitor and the fourth node in response to a signal from the third gate drive signal terminal.

[0038] The connection circuit includes:

[0039] The eighth transistor has its first electrode connected to the second electrode of the second capacitor, its second electrode connected to the fourth node, and its gate connected to the third gate drive signal terminal.

[0040] In one exemplary embodiment of this disclosure, the second electrode of the second capacitor is connected to the third node;

[0041] The pixel driving circuit also includes:

[0042] The second reset circuit is connected to the first node, the reference voltage terminal, and the second reset signal terminal. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the first node.

[0043] A data writing circuit is connected to the first node, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the first node.

[0044] The initialization circuit is connected to the first electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the first electrode of the second capacitor;

[0045] The first reset circuit is connected to the first electrode of the second capacitor, and the first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the first electrode of the second capacitor using the first initial signal terminal.

[0046] In one exemplary embodiment of this disclosure, the second reset circuit includes:

[0047] The sixth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the first node, and its gate connected to the second reset signal terminal.

[0048] The data writing circuit includes:

[0049] The seventh transistor has its first electrode connected to the data signal terminal, its second electrode connected to the first node, and its gate connected to the first gate drive signal terminal.

[0050] The second electrode of the fifth transistor is also connected to the first electrode of the second capacitor.

[0051] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0052] The second reset circuit is connected to the second electrode of the second capacitor, the reference voltage terminal, and the second reset signal terminal. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the second electrode of the second capacitor.

[0053] A data writing circuit is provided, which is connected to the second electrode of the second capacitor, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the second electrode of the second capacitor.

[0054] A compensation circuit is connected to the first node, the third node, and the second gate drive signal terminal. The compensation circuit is used to respond to the signal of the second gate drive signal terminal to connect the first node and the third node.

[0055] The initialization circuit is connected to the first electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the first electrode of the second capacitor;

[0056] The first reset circuit is connected to the first electrode of the second capacitor, and the first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the first electrode of the second capacitor using the first initial signal terminal.

[0057] In one exemplary embodiment of this disclosure, the second reset circuit includes:

[0058] The sixth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the second electrode of the second capacitor, and its gate connected to the second reset signal terminal.

[0059] The data writing circuit includes:

[0060] The seventh transistor has its first electrode connected to the data signal terminal, its second electrode connected to the second electrode of the second capacitor, and its gate connected to the first gate drive signal terminal.

[0061] The compensation circuit includes:

[0062] The tenth transistor has its first electrode connected to the first node, its second electrode connected to the third node, and its gate connected to the second gate drive signal terminal.

[0063] The second electrode of the fifth transistor is also connected to the first electrode of the second capacitor.

[0064] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0065] The second reset circuit is connected to the first electrode, the reference voltage terminal, and the second reset signal terminal of the second capacitor. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the first electrode of the second capacitor.

[0066] A data writing circuit is provided, which is connected to the second electrode of the second capacitor, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the second electrode of the second capacitor.

[0067] A compensation circuit is connected to the first node, the third node, and the second gate drive signal terminal. The compensation circuit is used to respond to the signal of the second gate drive signal terminal to connect the first node and the third node.

[0068] The initialization circuit is connected to the second electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the second electrode of the second capacitor;

[0069] The first reset circuit is connected to the second electrode of the second capacitor, and the first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the second electrode of the second capacitor using the first initial signal terminal.

[0070] In one exemplary embodiment of this disclosure, the second reset circuit includes:

[0071] The sixth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the first electrode of the second capacitor, and its gate connected to the second reset signal terminal.

[0072] The data writing circuit includes:

[0073] The seventh transistor has its first electrode connected to the data signal terminal, its second electrode connected to the second electrode of the second capacitor, and its gate connected to the first gate drive signal terminal.

[0074] The compensation circuit includes:

[0075] The tenth transistor has its first electrode connected to the first node, its second electrode connected to the third node, and its gate connected to the second gate drive signal terminal.

[0076] The second electrode of the fifth transistor is also connected to the second electrode of the second capacitor.

[0077] In one exemplary embodiment of this disclosure, the driving transistor is an N-type transistor, the driving transistor includes a main gate and an auxiliary gate, the main gate of the driving transistor is connected to the first node, and the auxiliary gate of the driving transistor is connected to the third node.

[0078] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0079] The second reset circuit is connected to the first node, the reference voltage terminal, and the second reset signal terminal. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the first node.

[0080] A data writing circuit is connected to the first node or the fourth node, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the first node or the fourth node.

[0081] The driving transistor and the second transistor are N-type transistors, and the first transistor and / or the fourth transistor are P-type transistors.

[0082] In one exemplary embodiment of this disclosure, the first enable signal terminal and the third enable signal terminal are connected to shift register units at different stages in the same gate drive circuit.

[0083] According to one aspect of this disclosure, a pixel driving circuit driving method is provided, wherein the pixel driving circuit driving method is used to drive the aforementioned pixel driving circuit, wherein the driving method includes:

[0084] During the first period of the reset phase, the first light-emitting control circuit is turned off, and the second light-emitting control circuit, the third light-emitting control circuit, and the first reset circuit are turned on, so as to transmit the signal from the first initial signal terminal to the third node and the fifth node.

[0085] During the second period of the reset phase, the first light-emitting control circuit and the third light-emitting control circuit are turned off, and the second light-emitting control circuit and the first reset circuit are turned on, so as to transmit the signal from the first initial signal terminal to the third node.

[0086] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes the pixel driving circuit described above.

[0087] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0088] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0089] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0090] Figure 1 A schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0091] Figure 2 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0092] Figure 3 for Figure 2 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0093] Figure 4 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0094] Figure 5 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0095] Figure 6 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0096] Figure 7 for Figure 6 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0097] Figure 8 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0098] Figure 9 for Figure 8 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0099] Figure 10 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0100] Figure 11 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0101] Figure 12 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0102] Figure 13This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0103] Figure 14 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0104] Figure 15 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0105] Figure 16 for Figure 15 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0106] Figure 17 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0107] Figure 18 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0108] Figure 19 for Figure 18 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0109] Figure 20 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0110] Figure 21 for Figure 20 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0111] Figure 22 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0112] Figure 23 for Figure 22 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0113] Figure 24 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0114] Figure 25 for Figure 24 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0115] Figure 26 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0116] Figure 27 for Figure 26The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0117] Figure 28 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0118] Figure 29 for Figure 28 The diagram shows the timing of each node in a driving method of the pixel driving circuit shown. Detailed Implementation

[0119] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0120] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0121] like Figure 1The diagram shown is a schematic representation of an exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit includes: a driving circuit 1, a first light-emitting control circuit 21, a second light-emitting control circuit 22, a third light-emitting control circuit 23, and a first reset circuit 31. The driving circuit 1 is connected to a first node N1, a second node N2, and a third node N3. The driving circuit 1 is used to generate a driving current between the second node N2 and the third node N3 based on the voltage of the first node N1. The first light-emitting control circuit 21 is connected to a first power supply terminal VDD, the second node N2, and a first enable signal terminal EM1. The first light-emitting control circuit 21 is used to respond to the signal from the first enable signal terminal EM1 to connect the first power supply terminal VDD and the second node N2. The second light-emitting control circuit 22 is connected to the third node N3, the second enable signal terminal EM2, and a fourth node N4. The second light-emitting control circuit 22 is used to respond to the signal from the second enable signal terminal EM2 to connect the third node N3 and the second node N4. The fourth node N4; the third light-emitting control circuit 23 is connected to the fourth node N4, the third enable signal terminal EM3, and the fifth node N5. The third light-emitting control circuit 23 is used to respond to the signal of the third enable signal terminal EM3 to connect the fourth node N4 and the fifth node N5. The fifth node N5 is used to connect the first electrode of the light-emitting unit L. The second electrode of the light-emitting unit L can be connected to the second power supply terminal VSS; the first reset circuit 31 is connected to the fourth node N4, the first initial signal terminal Vinit1, and the first reset signal terminal Re1. The first reset circuit 31 is used to respond to the signal of the first reset signal terminal Re1 to transmit the signal of the first initial signal terminal Vinit1 to the fourth node N4.

[0122] In this exemplary embodiment, the pixel driving circuit can, during the first period of the reset phase, turn off the first light-emitting control circuit 21 and turn on the second light-emitting control circuit 22, the third light-emitting control circuit 23, and the first reset circuit 31 to transmit the signal from the first initial signal terminal Vinit1 to the third node N3 and the fifth node N5; during the second period of the reset phase, it can turn off the first light-emitting control circuit 21 and the third light-emitting control circuit 23 and turn on the second light-emitting control circuit 22 and the first reset circuit 31 to transmit the signal from the first initial signal terminal Vinit1 to the third node N3. During the second period of the reset phase, the first initial signal terminal only provides an initial signal to the third node N3, thereby avoiding the influence of the light-emitting unit on the reset of the third node N3.

[0123] like Figure 1As shown, the driving circuit includes: a driving transistor T3, the first terminal of the driving transistor T3 is connected to the second node N2, the second terminal is connected to the third node N3, and the gate is connected to the first node N1; the first light-emitting control circuit 21 includes: a first transistor T1, the first terminal of the first transistor T1 is connected to the first power supply terminal VDD, the second terminal is connected to the second node N2, and the gate is connected to the first enable signal terminal EM1; the second light-emitting control circuit 22 includes: a second transistor T2, the first terminal of the second transistor T2 is connected to the third node N3, the second terminal is connected to the fourth node N4, and the gate is connected to the second enable signal terminal EM2; the third light-emitting control circuit 23 includes: a fourth transistor T4, the first terminal of the fourth transistor T4 is connected to the fourth node N4, the second terminal is connected to the fifth node N5, and the gate is connected to the third enable signal terminal EM3; the first reset circuit 31 includes: a fifth transistor T5, the first terminal of the fifth transistor T5 is connected to the first initial signal terminal Vinit1, the second terminal is connected to the fourth node N4, and the gate is connected to the first reset signal terminal Re1.

[0124] like Figure 2 The diagram shown is a schematic representation of another exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit further includes: a first capacitor C1, a second capacitor C2, and an initialization circuit 7. The first electrode of the first capacitor C1 is connected to a first node N1; the first electrode of the second capacitor C2 and the second electrode of the first capacitor C1 are connected to a third node N3; the initialization circuit 7 is connected to the second electrode of the second capacitor C2 and is used to provide an initial signal to the second electrode of the second capacitor C2.

[0125] In this exemplary embodiment, as Figure 2 As shown, the pixel driving circuit further includes: a second reset circuit 32 and a data writing circuit 4. The second reset circuit 32 is connected to the first node N1, the reference voltage terminal Vref, and the second reset signal terminal Re2. The second reset circuit 32 is used to respond to the signal of the second reset signal terminal Re2 to transmit the signal of the reference voltage terminal Vref to the first node N1. The data writing circuit 4 is connected to the first node N1, the data signal terminal Da, and the first gate driving signal terminal G1. The data writing circuit 4 is used to respond to the signal of the first gate driving signal terminal G1 to transmit the signal of the data signal terminal Da to the first node N1.

[0126] In this exemplary embodiment, as Figure 2As shown, the second reset circuit 32 includes a sixth transistor T6, whose first electrode is connected to the reference voltage terminal Vref, its second electrode is connected to the first node N1, and its gate is connected to the second reset signal terminal Re2. The data writing circuit 4 includes a seventh transistor T7, whose first electrode is connected to the data signal terminal Da, its second electrode is connected to the first node N1, and its gate is connected to the first gate drive signal terminal G1. The initialization circuit 7 may include a ninth transistor T9, whose first electrode is connected to the reference voltage terminal Vref, its second electrode is connected to the second electrode of the second capacitor C2, and its gate is connected to the first reset signal terminal Re1. In other exemplary embodiments, the first electrode of the ninth transistor T9 may also be connected to other signal terminals such as the first initial signal terminal Vinit1.

[0127] In this exemplary embodiment, as Figure 2 As shown, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 can all be N-type transistors. For example, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 can all be N-type oxide transistors. The channel region of the N-type oxide transistor can be made of indium gallium zinc oxide. The first power supply terminal VDD can be a high-level power supply terminal, and the second power supply terminal VSS can be a low-level power supply terminal.

[0128] like Figure 3 As shown, Figure 2 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit shown. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, and Re2 is the timing diagram for the signals at the second reset signal terminal.

[0129] The driving method of the pixel driving circuit may include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and an emission phase t4. The reset phase t1 may include a first time period t11 and a second time period t12.

[0130] During the first time period t11: the first enable signal terminal EM1 and the first gate drive signal terminal G1 output a low level, while the second enable signal terminal EM2, the third enable signal terminal EM3, and the first reset signal terminal Re1 output a high level. The fifth transistor T5, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are turned on. The first initial signal terminal Vinit1 inputs an initial signal to the third node N3 and the fifth node N5, and the reference voltage terminal Vref provides a reference voltage to the second electrode of the second capacitor C2.

[0131] During the second time period t12: the first enable signal terminal EM1, the first gate drive signal terminal G1, and the third enable signal terminal EM3 output a low level; the second enable signal terminal EM2, the second reset signal terminal Re2, and the first reset signal terminal Re1 output a high level. The first transistor T1 and the fourth transistor T4 are turned off; the fifth transistor T5 and the second transistor T2 are turned on; and the first initial signal terminal Vinit1 inputs an initial signal to the third node N3. It should be understood that in other exemplary embodiments, during the first time period t11, the second reset signal terminal Re2 may also output a high level.

[0132] During the threshold compensation phase t2: the first enable signal terminal EM1 and the second reset signal terminal Re2 output high levels, while the second enable signal terminal EM2 and the first gate drive signal terminal G1 output low levels. The first transistor T1 is turned on, and the first power supply terminal VDD inputs a compensation voltage Vdd-Vth to the third node N3, where Vdd is the voltage of the first power supply terminal and Vth is the threshold voltage of the driving transistor. The sixth transistor T6 is turned on, and the reference voltage terminal Vref inputs a reference voltage Vf to the second electrode of the first node N1 and the second capacitor C2.

[0133] During the data writing phase t3: the first gate drive signal terminal G1 and the first reset signal terminal Re1 output high levels, while the second reset signal terminal Re2 and the second enable signal terminal EM2 output low levels. The sixth transistor T6 and the second transistor T2 are turned off, and the seventh transistor T7 is turned on. The data signal terminal Da inputs a data signal to the first node N1, changing the voltage of the first node N1 from Vf to Vdata. Vdata is the voltage of the data signal. Under the voltage division effect of the first capacitor C1 and the second capacitor C2, the voltage of the third node N3 becomes Vdd - Vth + C1 / (C1 + C2)*(Vdata - Vf). The ninth transistor T9 remains on, and the reference voltage terminal Vref continuously inputs the reference voltage Vf to the second electrode of the second capacitor C2.

[0134] During the light-emitting phase t4: the first enable signal terminal EM1, the second enable signal terminal EM2, and the third enable signal terminal EM3 output high levels. The first gate drive signal terminal G1, the first reset signal terminal Re1, and the second reset signal terminal Re2 output low levels. The first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on. In the pixel driving circuit of this disclosure, the output current of the driving transistors is I = (μWCox / 2L)(Vgs-Vth). 2 =(μWCox / 2L)(Vdata-Vdd+Vth-C1 / (C1+C2)*(Vdata-Vf)-Vth) 2 Simultaneously, the first capacitor C1 couples the voltage change of the third node N3 to the first node N1, keeping Vgs constant. This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; and Vgs is the gate-source voltage difference of the driving transistor.

[0135] It should be understood that, in other exemplary embodiments, the gate of the ninth transistor T9 may also be connected to other control signal terminals, and the ninth transistor T9 may also be continuously turned on during the light-emitting phase.

[0136] like Figure 4 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 2 The pixel driving circuit shown is Figure 4 The pixel driving circuit shown reuses the first reset circuit 31 as the initialization circuit 7. The first reset circuit 31 is also connected to the second electrode of the second capacitor C2. The first reset circuit 31 is also used to respond to the signal of the first reset signal terminal Re1 to transmit the initialization signal of the first initial signal terminal Vinit1 to the second electrode of the second capacitor C2.

[0137] Figure 4 The driving method of the pixel driving circuit shown can be as follows: Figure 3 As shown, the driving method of the pixel driving circuit can also include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4. The reset phase t1 includes a first time period t11 and a second time period t12.

[0138] like Figure 5 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 4 The pixel driving circuit shown is Figure 5In the pixel driving circuit shown, the first transistor T1 and the fourth transistor T4 are P-type transistors. For example, the first transistor T1 and the fourth transistor T4 can be P-type polysilicon transistors. P-type polysilicon transistors have a higher response speed. This setting can improve the speed at which the first power supply terminal VDD writes the compensation voltage to the third node N3, and also improve the initialization speed of the first initial signal terminal Vinit1 to the fifth node N5. Other transistors can be N-type transistors. For example, other transistors can be N-type oxide transistors. N-type oxide transistors have a lower turn-off leakage current. This setting can reduce the leakage current from the first node N1 and the third node N3 to other signal terminals.

[0139] like Figure 6 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 4 The pixel driving circuit shown is Figure 6 The pixel driving circuit shown includes an additional connection circuit 6. Connection circuit 6 connects the second electrode of the second capacitor C2 and the fourth node N4. Connection circuit 6 is used to respond to a control signal to connect the second electrode of the second capacitor C2 and the fourth node N4. Connection circuit 6 can also be connected to a third gate driving signal terminal G3. Connection circuit 6 is used to respond to the signal from the third gate driving signal terminal G3 to connect the second electrode of the second capacitor C2 and the fourth node N4. Connection circuit 6 may include an eighth transistor T8. The first terminal of the eighth transistor T8 is connected to the second electrode of the second capacitor C2, the second terminal is connected to the fourth node N4, and the gate is connected to the third gate driving signal terminal G3.

[0140] like Figure 7 As shown, Figure 6 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, Re2 is the timing diagram for the signals at the second reset signal terminal, and G3 is the timing diagram for the signals at the third gate drive signal terminal. The driving method of this pixel driving circuit can also include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4. The reset phase t1 includes a first time period t11 and a second time period t12.

[0141] It should be understood that, in other exemplary embodiments, the gate of the eighth transistor T8 may also be connected to the first reset signal terminal Re1.

[0142] like Figure 8 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 4 The pixel driving circuit shown is Figure 8 In the pixel driving circuit shown, the second terminal of the fifth transistor T5 is connected to the fifth node N5. The second transistor T2 and the fourth transistor T4, connected in series, can reduce the leakage current of the third node N3.

[0143] like Figure 9 As shown, Figure 8 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit shown. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, and Re2 is the timing diagram for the signals at the second reset signal terminal.

[0144] The driving method of this pixel driving circuit may include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4. Figure 3 The pixel driving circuit shown differs in that, during the reset phase t1, both the second enable signal terminal EM2 and the third enable signal terminal EM3 output a high level, and the first initial signal terminal Vinit1 provides an initial signal to the fifth node N5. At the same time, the fifth node N5 provides an initial signal to the third node N3 through the fourth transistor T4 and the second transistor T2.

[0145] like Figure 10 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 8 In the pixel driving circuit shown, the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2 are connected to the fourth node N4. The driving method of this pixel driving circuit can be as follows: Figure 9 As shown, the driving method of this pixel driving circuit can also include: reset stage t1, threshold compensation stage t2, data writing stage t3, and light emission stage t4. Figure 10 The second transistor T2 in the pixel driving circuit shown can be turned off during the data writing stage, thereby preventing the driving transistor T3 from affecting the data writing, and thus enabling more complete and accurate data writing.

[0146] like Figure 11 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 4 The pixel driving circuit shown is Figure 11 The gate of the fourth transistor in the pixel driving circuit shown is connected to the second enable signal terminal EM2. Figure 11 The driving method of the pixel driving circuit shown can be as follows: Figure 9As shown, the driving method of this pixel driving circuit can also include: reset stage t1, threshold compensation stage t2, data writing stage t3, and light emission stage t4.

[0147] like Figure 12 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 8 The pixel driving circuit shown is Figure 12 The gate of the fourth transistor in the pixel driving circuit shown is connected to the second enable signal terminal EM2. Figure 12 The driving method of the pixel driving circuit shown can be as follows: Figure 9 As shown, the driving method of the pixel driving circuit may include: a reset stage t1, a threshold compensation stage t2, a data writing stage t3, and a light emission stage t4.

[0148] like Figure 13 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 10 The pixel driving circuit shown is Figure 12 The gate of the fourth transistor in the pixel driving circuit shown is connected to the second enable signal terminal EM2. Figure 13 The driving method of the pixel driving circuit shown can be as follows: Figure 9 As shown, the driving method of the pixel driving circuit may include: a reset stage t1, a threshold compensation stage t2, a data writing stage t3, and a light emission stage t4.

[0149] like Figure 1 , Figure 2 , Figures 4-6 , Figure 8 , Figures 10-13 In this embodiment, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 can be N-type transistors, such as N-type oxide transistors. It should be understood that in other exemplary embodiments, any one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 can also be P-type transistors. For example, any one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 can be P-type polysilicon transistors. Optionally, the first transistor T1 and / or the fourth transistor T4 can be P-type polysilicon transistors. For example, as... Figure 14 The diagram shown is a schematic representation of another exemplary embodiment of the pixel driving circuit of this disclosure, compared to... Figure 11 The pixel driving circuit shown is Figure 14The first transistor in the pixel driving circuit shown is a P-type polysilicon transistor.

[0150] In other exemplary embodiments, Figure 4 , 5 The pixel driving circuits shown in 6, 11, and 14 can also turn off the fourth transistor T4 during the data writing stage. This setting can avoid the influence of the capacitance of the light-emitting unit L itself on the voltage division of the first capacitor C1 and the second capacitor C2, thereby affecting the voltage of the third node N3.

[0151] like Figure 15 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 2 The pixel driving circuit shown is Figure 15 The pixel driving circuit shown connects the data writing circuit 4 to the second electrode of the second capacitor C2. In addition, the gate of the ninth transistor T9 is connected to the third reset signal terminal Re3. The first transistor T1 and the fourth transistor T4 are P-type transistors. For example, the first transistor T1 and the fourth transistor T4 can be P-type polysilicon transistors.

[0152] like Figure 16 As shown, Figure 15 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit shown. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, Re2 is the timing diagram for the signals at the second reset signal terminal, and Re3 is the timing diagram for the signals at the third reset signal terminal.

[0153] The driving method of the pixel driving circuit may include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and an emission phase t4. The reset phase t1 includes a first time period t11 and a second time period t12.

[0154] During the first time period t11: the first gate drive signal terminal G1, the third enable signal terminal EM3, and the second reset signal terminal Re2 output a low level, while the first enable signal terminal EM1, the second enable signal terminal EM2, and the first reset signal terminal Re1 output a high level. The fifth transistor T5, the second transistor T2, and the fourth transistor T4 are turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the third node N3 and the fifth node N5. It should be understood that in other exemplary embodiments, the second reset signal terminal Re2 may also output a high level during the first time period t11.

[0155] During the second time period t12: the first gate drive signal terminal G1 outputs a low level, and the first enable signal terminal EM1, the second enable signal terminal EM2, the third enable signal terminal EM3, the second reset signal terminal Re2, and the first reset signal terminal Re1 output a high level. The first transistor T1 and the fourth transistor T4 are turned off, and the fifth transistor T5 and the second transistor T2 are turned on. The first initial signal terminal Vinit1 inputs an initial signal to the third node N3.

[0156] During the threshold compensation phase t2: the third reset signal terminal Re3 and the second reset signal terminal Re2 output high levels, while the first enable signal terminal EM1, the second enable signal terminal EM2, and the first gate drive signal terminal G1 output low levels. The first transistor T1 is turned on, and the first power supply terminal VDD inputs the compensation voltage Vdd-Vth to the third node N3, where Vdd is the voltage of the first power supply terminal and Vth is the threshold voltage of the driving transistor. The sixth transistor T6 and the ninth transistor T9 are turned on, and the reference voltage terminal Vref inputs the reference voltage Vf to the second electrode of the first node N1 and the second capacitor C2.

[0157] During the data writing phase t3: the first gate drive signal terminal G1 and the second reset signal terminal Re2 output high levels, and the third reset signal terminal Re3 outputs a low level. The ninth transistor T9 is turned off, and the sixth transistor T6 and the seventh transistor T7 are turned on. The data signal terminal Da inputs a data signal to the second electrode of the second capacitor C2. The voltage at the second electrode of the second capacitor C2 changes from Vf to Vdata, where Vdata is the voltage of the data signal. The reference voltage terminal Vref continuously inputs the reference voltage Vf to the first node N1. Under the voltage division effect of the first capacitor C1 and the second capacitor C2, the voltage at the third node N3 becomes Vdd-Vth+C2 / (C1+C2)*(Vdata-Vf).

[0158] During the light-emitting phase t4: the second enable signal terminal EM2 outputs a high level, while the first enable signal terminal EM1 and the third enable signal terminal EM3 output low levels. The first gate drive signal terminal G1, the first reset signal terminal Re1, the second reset signal terminal Re2, and the third reset signal terminal Re3 output low levels. The first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on. In the pixel driving circuit of this disclosure, the output current of the driving transistors is I = (μWCox / 2L)(Vgs-Vth). 2 =(μWCox / 2L)(Vf-Vdd+Vth-C2 / (C1+C2)*(Vdata-Vf)-Vth) 2Simultaneously, the first capacitor C1 couples the voltage change of the third node N3 to the first node N1, keeping Vgs constant. This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; and Vgs is the gate-source voltage difference of the driving transistor.

[0159] like Figure 16 As shown, the signals on the third reset signal terminal Re3 and the second reset signal terminal Re2 are shift signals. The third reset signal terminal Re3 and the second reset signal terminal Re2 can be connected to shift register units at different stages in the same gate drive circuit.

[0160] like Figure 17 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 15 The pixel driving circuit shown is Figure 17 The pixel driving circuit shown reuses the first reset circuit 31 as an initialization circuit. The first reset circuit 31 is connected to the second electrode of the second capacitor C2. The first reset circuit 31 is used to respond to the signal of the first reset signal terminal Re1 to transmit the initial signal of the first initial signal terminal to the second electrode of the second capacitor. The driving method of this pixel driving circuit can be as follows: Figure 16 As shown, the driving method of the pixel driving circuit can also include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4. The reset phase t1 includes a first time period t11 and a second time period t12.

[0161] It should be understood that in other exemplary embodiments, Figure 15 , Figure 17 In the pixel driving circuit shown, any one or more of the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 can be P-type transistors. For example, any one or more of the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 can be P-type polysilicon transistors. The first transistor T1 and the fourth transistor T4 can also be N-type transistors. For example, the first transistor T1 and the fourth transistor T4 can be N-type oxide transistors.

[0162] like Figure 18The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. In this exemplary embodiment, the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2 are connected to the sixth node N6, and the second electrode of the second capacitor C2 is connected to the third node N3. The initialization circuit 7 is connected to the sixth node N6, and the initialization circuit 7 is used to provide an initial signal to the first electrode of the second capacitor C2. Figure 18 The transistors in the pixel driving circuit shown can all be N-type transistors, for example, Figure 18 The transistors in the pixel driving circuit shown can all be N-type oxide transistors.

[0163] like Figure 19 As shown, Figure 18 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit shown. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, Re2 is the timing diagram for the signals at the second reset signal terminal, and Re3 is the timing diagram for the signals at the third clock signal terminal.

[0164] The driving method of the pixel driving circuit may include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and an emission phase t4. The reset phase t1 includes a first time period t11 and a second time period t12.

[0165] During the first time period t11: the first enable signal terminal EM1 outputs a low level, while the second reset signal terminal Re2, the second enable signal terminal EM2, the third enable signal terminal EM3, and the first reset signal terminal Re1 output a high level. The fifth transistor T5, the second transistor T2, and the fourth transistor T4 are turned on. The first initial signal terminal Vinit1 inputs initial signals to the third node N3 and the fifth node N5, and the reference voltage terminal Vref inputs the reference voltage Vf to the first node N1.

[0166] During the second time period t12: the first enable signal terminal EM1 and the third enable signal terminal EM3 output low level, while the second enable signal terminal EM2, the second reset signal terminal Re2, the third reset signal terminal Re3, and the first reset signal terminal Re1 output high level. The first transistor T1 and the fourth transistor T4 are turned off, while the fifth transistor T5, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the ninth transistor T9 are turned on. The first initial signal terminal Vinit1 only inputs the initial signal to the third node N3. The reference voltage terminal Vref inputs the reference voltage Vf to the first node N1 and the sixth node N6.

[0167] During the threshold compensation phase t2: the first enable signal terminal EM1, the second reset signal terminal Re2, and the third reset signal terminal Re3 output high levels, while the second enable signal terminal EM2 and the first gate drive signal terminal G1 output low levels. The first transistor T1 is turned on, and the first power supply terminal VDD inputs the compensation voltage Vdd-Vth to the third node N3, where Vdd is the voltage of the first power supply terminal and Vth is the threshold voltage of the driving transistor. The sixth transistor T6 and the ninth transistor T9 are turned on, and the reference voltage terminal Vref continuously inputs the reference voltage Vf to the first node N1 and the sixth node N6.

[0168] During the data writing phase t3: the first gate drive signal terminal G1 and the third reset signal terminal Re3 output high levels, while the second reset signal terminal Re2 and the second enable signal terminal EM2 output low levels. The sixth transistor T6 and the second transistor T2 are turned off, the seventh transistor T7 is turned on, the data signal terminal Da inputs a data signal to the first node N1, and the voltage of the first node N1 changes from Vf to Vdata. The ninth transistor T9 remains on, and the reference voltage terminal Vref continuously inputs the reference voltage Vf to the sixth node N6. The voltage of the third node N3 remains Vdd-Vth.

[0169] During the light-emitting phase t4: the first enable signal terminal EM1, the second enable signal terminal EM2, and the third enable signal terminal EM3 output high levels. The first gate drive signal terminal G1, the first reset signal terminal Re1, and the second reset signal terminal Re2 output low levels. The first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on. In the pixel driving circuit of this disclosure, the output current of the driving transistors is I = (μWCox / 2L)(Vgs-Vth). 2 =(μWCox / 2L)(Vdata-Vdd+Vth-Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; and Vgs is the gate-source voltage difference of the driving transistor.

[0170] like Figure 20 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 18 The pixel driving circuit shown is Figure 20 The pixel driving circuit shown reuses the first reset circuit 31 as an initialization circuit 7. The first reset circuit 31 is connected to the sixth node N6. The first reset circuit 31 is also used to respond to the signal of the first reset signal terminal Re1 to transmit the signal of the first initial signal terminal Vinit1 to the first electrode of the second capacitor C2.

[0171] like Figure 21 As shown, Figure 20 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, and Re2 is the timing diagram for the signals at the second reset signal terminal. The driving method of this pixel driving circuit can also include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4. The reset phase t1 includes a first time period t11 and a second time period t12. Figure 19 The driving method shown is different, Figure 21 In the driving method, the first reset signal terminal Re1 needs to output a high level during the data writing phase t3.

[0172] like Figure 22 The diagram shown is a schematic representation of another exemplary embodiment of the pixel driving circuit of this disclosure. The second electrode of the first capacitor C1 and the first electrode of the second capacitor C2 are connected to the sixth node N6. The second reset circuit 32 is connected to the second electrode of the second capacitor C2, the reference voltage terminal, and the second reset signal terminal Re2. The second reset circuit 32 is used to transmit the signal of the reference voltage terminal Vref to the second electrode of the second capacitor C2 in response to the signal of the second reset signal terminal Re2. The data writing circuit 4 is connected to the second electrode of the second capacitor C2, the data signal terminal Da, and the first gate driving signal terminal G1. The data writing circuit 4 is used to transmit the signal of the data signal terminal Da to the second electrode of the second capacitor C2 in response to the signal of the first gate driving signal terminal G1. The initialization circuit 7 is connected to the first electrode of the second capacitor C2. The initialization circuit 7 is used to provide an initial signal to the first electrode of the second capacitor C2. The pixel driving circuit may further include: a compensation circuit 5, which is connected to the first node N1, the third node N3, and the second gate driving signal terminal G2. The compensation circuit 5 is used to connect the first node N1 and the third node N3 in response to the signal of the second gate driving signal terminal G2.

[0173] like Figure 22As shown, the second reset circuit 32 includes: a sixth transistor T6, the first terminal of which is connected to the reference voltage terminal, the second terminal of which is connected to the second electrode of the second capacitor C2, and the gate of which is connected to the second reset signal terminal Re2; the data writing circuit 4 includes: a seventh transistor T7, the first terminal of which is connected to the data signal terminal Da, the second terminal of which is connected to the second electrode of the second capacitor C2, and the gate of which is connected to the first gate drive signal terminal G1; the compensation circuit 5 includes: a tenth transistor T10, the first terminal of which is connected to the first node N1, the second terminal of which is connected to the third node N3, and the gate of which is connected to the second gate drive signal terminal G2. The initialization circuit 7 may include a ninth transistor T9, the first terminal of which is connected to the second initial signal terminal Vinit2, the second terminal of which is connected to the first electrode of the second capacitor C2, and the gate of which is connected to the third reset signal terminal Re3.

[0174] In this exemplary embodiment, as Figure 22 As shown, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be P-type transistors. For example, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be P-type polysilicon transistors. It should be understood that in other exemplary embodiments, one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can also be N-type transistors. For example, one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can also be N-type oxide transistors.

[0175] like Figure 23 As shown, Figure 22 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit shown. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, G2 is the timing diagram for the signals at the second gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, Re2 is the timing diagram for the signals at the second reset signal terminal, and Re3 is the timing diagram for the signals at the third reset signal terminal.

[0176] The driving method of the pixel driving circuit includes a reset phase t1, a threshold compensation phase t2, a data writing phase t3, a data coupling phase t4, and a light emission phase t5. The reset phase t1 may include a first time period t11 and a second time period t12.

[0177] During the first time period t11: the first enable signal terminal EM1 outputs a high level, while the second enable signal terminal EM2, the third enable signal terminal EM3, the first reset signal terminal Re1, the third reset signal terminal Re3, and the second gate drive signal terminal G2 output a low level. The fifth transistor T5, the second transistor T2, the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10 are turned on. The first initial signal terminal Vinit1 inputs initial signals to the third node N3, the fifth node N5, and the first node N1, while the second initial signal terminal Vinit2 provides an initial signal to the first electrode of the second capacitor C2.

[0178] During the second time period t12: the first enable signal terminal EM1 and the third enable signal terminal EM3 output high levels, while the second enable signal terminal EM2, the third reset signal terminal Re3, the second gate drive signal terminal G2, and the first reset signal terminal Re1 output low levels. The first transistor T1 and the fourth transistor T4 are turned off, while the fifth transistor T5, the second transistor T2, the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10 are turned on. The first initial signal terminal Vinit1 inputs initial signals to the third node N3, the fifth node N5, and the first node N1, while the second initial signal terminal Vinit2 provides an initial signal to the first electrode of the second capacitor C2.

[0179] During the threshold compensation phase t2: the first enable signal terminal EM1, the second reset signal terminal Re2, the third reset signal terminal Re3, and the second gate drive signal terminal G2 output low levels. The first transistor T1, the tenth transistor T10, the ninth transistor T9, and the sixth transistor T6 are turned on. The first power supply terminal VDD inputs the threshold compensation voltage Vdd+Vth to the first node N1, where Vdd is the voltage of the first power supply terminal VDD, and Vth is the threshold voltage of the driving transistor. Simultaneously, the reference power supply terminal Vref inputs the reference voltage Vf to the second electrode of the second capacitor C2, and the second initial signal terminal Vinit2 inputs the initial signal to the first electrode of the second capacitor C2.

[0180] During the data writing phase t3: the first gate drive signal terminal G1 and the third reset signal terminal Re3 output low level, while the second gate drive signal terminal G2, the second reset signal terminal Re2, and the first enable signal terminal EM1 output high level. The seventh transistor T7 and the ninth transistor T9 are turned on. The second initial signal terminal Vinit2 inputs an initial signal to the first electrode of the second capacitor C2, and the data signal terminal Da inputs a data signal to the second electrode of the second capacitor. The voltage of the data signal is Vdata.

[0181] During the data coupling phase t4: the second reset signal terminal Re2 outputs a low level, the first gate drive signal terminal G1, the third reset signal terminal Re3, the second gate drive signal terminal G2, and the second enable signal terminal EM2 output a high level, the second transistor T2, the tenth transistor T10, the ninth transistor T9, and the seventh transistor T7 are turned off, and the sixth transistor T6 is turned on. The reference voltage terminal Vref inputs the reference voltage Vf to the second electrode of the second capacitor C2, and the voltage of the second electrode of the second capacitor C2 jumps from Vdata to Vf. The voltage of the first node N1 jumps from Vdd+Vth to Vdd+Vth+K2(Vf-Vdata), where K2 is equal to K1*C1 / Cn1, K1 is equal to C2 / Cn6, C1 is the capacitance value of the first capacitor, C2 is the capacitance value of the second capacitor, Cn6 is the total capacitance of the sixth node N6, and Cn1 is the total capacitance of the first node.

[0182] During the light-emitting stage t5: the first enable signal terminal EM1, the second enable signal terminal EM2, and the third enable signal terminal EM3 output low-level signals, the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on, and the first light-emitting unit L1 emits light.

[0183] like Figure 24 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 22 The pixel driving circuit shown is Figure 24 The pixel driving circuit shown reuses the first reset circuit 31 as the initialization circuit 7. The first reset circuit 31 is also connected to the sixth node N6. The first reset circuit 31 is used to respond to the signal of the first reset signal terminal Re1 to transmit the signal of the first initial signal terminal to the sixth node.

[0184] like Figure 25 As shown, Figure 24 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, and Re2 is the timing diagram for the signals at the second reset signal terminal. The driving method of this pixel driving circuit may include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4. The reset phase t1 includes a first time period t11 and a second time period t12.

[0185] like Figure 26 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 22 Pixel driving circuit, Figure 26 The pixel driving circuit connects the second reset circuit 32 to the sixth node N6 and the initialization circuit 7 to the second electrode of the second capacitor C2.

[0186] like Figure 27 As shown, Figure 26 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, Re2 is the timing diagram for the signals at the second reset signal terminal, and Re3 is the timing diagram for the signals at the third reset signal terminal. The driving method of this pixel driving circuit may include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4. The reset phase t1 includes a first time period t11 and a second time period t12.

[0187] like Figure 28 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared to... Figure 26 Pixel driving circuit, Figure 28 The pixel driving circuit shown reuses the first reset circuit 31 as the initialization circuit 7. The first reset circuit 31 is also connected to the second electrode of the second capacitor C2. The first reset circuit 31 is used to respond to the signal of the first reset signal terminal Re1 to transmit the signal of the first initial signal terminal to the second electrode of the second capacitor C2.

[0188] like Figure 29 As shown, Figure 28 The diagram shows the timing diagrams of each node in a driving method of the pixel driving circuit. EM1 is the timing diagram for the signals at the first enable signal terminal, EM2 is the timing diagram for the signals at the second enable signal terminal, EM3 is the timing diagram for the signals at the third enable signal terminal, G1 is the timing diagram for the signals at the first gate drive signal terminal, Re1 is the timing diagram for the signals at the first reset signal terminal, and Re2 is the timing diagram for the signals at the second reset signal terminal. The driving method of this pixel driving circuit may include: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4. The reset phase t1 includes a first time period t11 and a second time period t12.

[0189] like Figure 24 , Figure 26 , Figure 28As shown, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be P-type transistors. For example, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be P-type polysilicon transistors. It should be understood that in other exemplary embodiments, one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can also be N-type transistors. For example, one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can also be N-type oxide transistors.

[0190] like Figure 1 , Figure 2 , Figures 4-6 , Figure 8 , Figures 10-13 , Figure 15 , Figure 17 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 As shown, the signals on the first enable signal terminal EM1 and the third enable signal terminal EM3 can be shift signals, and the first enable signal terminal EM1 and the third enable signal terminal EM3 can be connected to shift register units at different stages in the same gate drive circuit.

[0191] like Figure 1 , Figure 2 , Figures 4-6 , Figure 8 , Figures 10-13 , Figure 15 , Figure 17 , Figure 18 , Figure 20As shown, the driving transistor T3 may include a main gate and an auxiliary gate. The main gate of the driving transistor T3 is connected to the first node N1, and the auxiliary gate of the driving transistor T3 is connected to the third node N3. The auxiliary gate of the driving transistor T3 can regulate the subthreshold swing of the driving transistor to reduce the slope of the driving transistor's transfer characteristic curve, that is, to reduce the amplitude of the change in the driving transistor's output current with the gate-source voltage difference of the driving transistor, thereby enabling the driving transistor to stably output different currents. The main gate of the driving transistor T3 can be the top gate of the driving transistor, and the auxiliary gate of the driving transistor T3 can be the bottom gate of the driving transistor T3.

[0192] This exemplary embodiment also provides a display panel including the pixel driving circuit described above.

[0193] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, vehicle display, or other display device.

[0194] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0195] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A pixel driving circuit, wherein, The pixel driving circuit includes: A driving circuit is connected to a first node, a second node, and a third node. The driving circuit is used to generate a driving current between the second node and the third node based on the voltage of the first node. A first light-emitting control circuit is connected to a first power supply terminal, a second node, and a first enable signal terminal. The first light-emitting control circuit is used to respond to the signal of the first enable signal terminal to connect the first power supply terminal and the second node. The second light-emitting control circuit is connected to the third node, the second enable signal terminal, and the fourth node. The second light-emitting control circuit is used to respond to the signal of the second enable signal terminal to connect the third node and the fourth node. The third light-emitting control circuit is connected to the fourth node, the third enable signal terminal, and the fifth node. The third light-emitting control circuit is used to respond to the signal of the third enable signal terminal to connect the fourth node and the fifth node. The fifth node is used to connect the light-emitting unit. A first reset circuit is connected to the fourth node, a first initial signal terminal, and a first reset signal terminal. The first reset circuit is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initial signal terminal to the fourth node.

2. The pixel driving circuit according to claim 1, wherein, The driving circuit includes: A driving transistor, with its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the first node; The first light-emitting control circuit includes: The first transistor has a first terminal connected to the first power supply terminal, a second terminal connected to the second node, and a gate connected to the first enable signal terminal. The second light-emitting control circuit includes: The second transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the second enable signal terminal. The third light-emitting control circuit includes: The fourth transistor has its first terminal connected to the fourth node, its second terminal connected to the fifth node, and its gate connected to the third enable signal terminal. The first reset circuit includes: The fifth transistor has its first terminal connected to the first initial signal terminal, its second terminal connected to the fourth node, and its gate connected to the first reset signal terminal.

3. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit also includes: The first capacitor has its first electrode connected to the first node; The second capacitor has its first electrode connected to the second electrode of the first capacitor. An initialization circuit is connected to the first or second electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the first or second electrode of the second capacitor.

4. The pixel driving circuit according to claim 3, wherein, The first reset circuit is reused as the initialization circuit. The first reset circuit is also connected to the first electrode or the second electrode of the second capacitor. The first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the first electrode or the second electrode of the second capacitor using the first initial signal terminal.

5. The pixel driving circuit according to claim 4, wherein, The second electrode of the first capacitor and the first electrode of the second capacitor are connected to the third node; The pixel driving circuit also includes: The second reset circuit is connected to the first node, the reference voltage terminal, and the second reset signal terminal. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the first node. A data writing circuit is connected to the first node or the fourth node, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the first node or the fourth node. The initialization circuit is connected to the second electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the second electrode of the second capacitor; The second electrode of the second capacitor is also connected to the fourth node, and the first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the second electrode of the second capacitor using the first initial signal terminal.

6. The pixel driving circuit according to claim 5, wherein, The second reset circuit includes: The sixth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the first node, and its gate connected to the second reset signal terminal. The data writing circuit includes: The seventh transistor has its first terminal connected to the data signal terminal, its second terminal connected to the first node or the fourth node, and its gate connected to the first gate drive signal terminal.

7. The pixel driving circuit according to claim 5, wherein, The pixel driving circuit also includes: A connection circuit is provided to connect the second electrode and the fourth node of the second capacitor in response to a control signal.

8. The pixel driving circuit according to claim 7, wherein, The connection circuit is connected to the third gate drive signal terminal, and the connection circuit is used to respond to the signal of the third gate drive signal terminal to connect the second electrode of the second capacitor and the fourth node; The connection circuit includes: The eighth transistor has its first electrode connected to the second electrode of the second capacitor, its second electrode connected to the fourth node, and its gate connected to the third gate drive signal terminal.

9. The pixel driving circuit according to claim 4, wherein, The second electrode of the second capacitor is connected to the third node; The pixel driving circuit also includes: The second reset circuit is connected to the first node, the reference voltage terminal, and the second reset signal terminal. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the first node. A data writing circuit is connected to the first node, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the first node. The initialization circuit is connected to the first electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the first electrode of the second capacitor; The first reset circuit is connected to the first electrode of the second capacitor, and the first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the first electrode of the second capacitor using the first initial signal terminal.

10. The pixel driving circuit according to claim 9, wherein, The second reset circuit includes: The sixth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the first node, and its gate connected to the second reset signal terminal. The data writing circuit includes: The seventh transistor has its first terminal connected to the data signal terminal, its second terminal connected to the first node, and its gate connected to the first gate drive signal terminal.

11. The pixel driving circuit according to claim 4, wherein, The pixel driving circuit also includes: The second reset circuit is connected to the second electrode of the second capacitor, the reference voltage terminal, and the second reset signal terminal. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the second electrode of the second capacitor. A data writing circuit is provided, which is connected to the second electrode of the second capacitor, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the second electrode of the second capacitor. A compensation circuit is connected to the first node, the third node, and the second gate drive signal terminal. The compensation circuit is used to respond to the signal of the second gate drive signal terminal to connect the first node and the third node. The initialization circuit is connected to the first electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the first electrode of the second capacitor; The first reset circuit is connected to the first electrode of the second capacitor, and the first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the first electrode of the second capacitor using the first initial signal terminal.

12. The pixel driving circuit according to claim 11, wherein, The second reset circuit includes: The sixth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the second electrode of the second capacitor, and its gate connected to the second reset signal terminal. The data writing circuit includes: The seventh transistor has its first electrode connected to the data signal terminal, its second electrode connected to the second electrode of the second capacitor, and its gate connected to the first gate drive signal terminal. The compensation circuit includes: The tenth transistor has its first electrode connected to the first node, its second electrode connected to the third node, and its gate connected to the second gate drive signal terminal.

13. The pixel driving circuit according to claim 4, wherein, The pixel driving circuit also includes: The second reset circuit is connected to the first electrode, the reference voltage terminal, and the second reset signal terminal of the second capacitor. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the first electrode of the second capacitor. A data writing circuit is provided, which is connected to the second electrode of the second capacitor, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the second electrode of the second capacitor. A compensation circuit is connected to the first node, the third node, and the second gate drive signal terminal. The compensation circuit is used to respond to the signal of the second gate drive signal terminal to connect the first node and the third node. The initialization circuit is connected to the second electrode of the second capacitor, and the initialization circuit is used to provide an initial signal to the second electrode of the second capacitor; The first reset circuit is connected to the second electrode of the second capacitor, and the first reset circuit is also used to respond to the signal of the first reset signal terminal to provide an initial signal to the second electrode of the second capacitor using the first initial signal terminal.

14. The pixel driving circuit according to claim 13, wherein, The second reset circuit includes: The sixth transistor has its first terminal connected to the reference voltage terminal, its second terminal connected to the first electrode of the second capacitor, and its gate connected to the second reset signal terminal. The data writing circuit includes: The seventh transistor has its first electrode connected to the data signal terminal, its second electrode connected to the second electrode of the second capacitor, and its gate connected to the first gate drive signal terminal. The compensation circuit includes: The tenth transistor has its first electrode connected to the first node, its second electrode connected to the third node, and its gate connected to the second gate drive signal terminal.

15. The pixel driving circuit according to claim 2, wherein, The driving transistor is an N-type transistor, and the driving transistor includes a main gate and an auxiliary gate. The main gate of the driving transistor is connected to the first node, and the auxiliary gate of the driving transistor is connected to the third node.

16. The pixel driving circuit according to claim 2, wherein, The pixel driving circuit also includes: The second reset circuit is connected to the first node, the reference voltage terminal, and the second reset signal terminal. The second reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the reference voltage terminal to the first node. A data writing circuit is connected to the first node or the fourth node, a data signal terminal, and a first gate drive signal terminal. The data writing circuit is used to respond to the signal of the first gate drive signal terminal to transmit the signal of the data signal terminal to the first node or the fourth node. The driving transistor and the second transistor are N-type transistors, and the first transistor and / or the fourth transistor are P-type transistors.

17. The pixel driving circuit according to any one of claims 1-16, wherein, The first enable signal terminal and the third enable signal terminal are connected to shift register units at different stages in the same gate drive circuit.

18. A display panel, wherein, The display panel includes the pixel driving circuit according to any one of claims 1-17.

19. A display device, wherein, The display device includes the display panel as described in claim 18.

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