Display module and display device

Abstract

A display module and a display device, the display module comprising a display substrate having a display area and a frame area surrounding the display area. The frame area comprises a first drive circuit area and a second drive circuit area, the first drive circuit area comprising a plurality of gate drive circuits. The second drive circuit area comprises a first edge drive circuit, a second edge drive circuit and a plurality of middle drive circuits, the display substrate being provided with a first connection signal line and a second connection signal line, a control circuit board being provided with a signal transmission line, at least one of the first edge drive circuit and the second edge drive circuit being connected to at least one of the plurality of gate drive circuits through the first connection signal line, at least one of the plurality of middle drive circuits being connected to at least one of the plurality of gate drive circuits through the second connection signal line and the signal transmission line.

Description

Technical Field

[0001] This article relates to, but is not limited to, display technology, and in particular to a display module and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, display devices using OLEDs as light-emitting elements and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Utility Model Content

[0003] The following is an overview of the subject matter described in detail herein, and this overview is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a display module, including: a display substrate, a plurality of flexible circuit boards and a control circuit board, the display substrate having a display area and a border area surrounding the display area, the border area including: a first driving circuit area and a driving circuit area, the first driving circuit area being located on at least one of a first side and a second side of the display area, the second driving circuit area being located on a third side of the display area, the first side and the second side being disposed opposite to each other;

[0005] The first driving circuit region includes: a plurality of gate driving circuits; the second driving circuit region includes: a plurality of driving circuits arranged along a first direction; the plurality of driving circuits includes: an edge driving circuit and a plurality of center driving circuits; the edge driving circuit includes: a first edge driving circuit and a second edge driving circuit; the first edge driving circuit and the second edge driving circuit are respectively located at both ends of the plurality of center driving circuits along the first direction.

[0006] At least one of the first edge driving circuit and the second edge driving circuit and at least one of the plurality of middle driving circuits are electrically connected to the plurality of gate driving circuits, respectively; the plurality of flexible circuit boards are respectively connected to the plurality of driving circuits and the control circuit board.

[0007] The display substrate is provided with a first connection signal line and a second connection signal line, and the control circuit board is provided with a signal transmission line. At least one of the first edge driving circuit and the second edge driving circuit is connected to at least one of the plurality of gate driving circuits through the first connection signal line. At least one of the plurality of center driving circuits is connected to at least one of the plurality of gate driving circuits through the second connection signal line and the signal transmission line.

[0008] In an exemplary embodiment, the plurality of flexible circuit boards include: a first edge flexible circuit board, a second edge flexible circuit board, and a plurality of central flexible circuit boards. The first edge flexible circuit board is electrically connected to the first edge driving circuit, the second edge flexible circuit board is electrically connected to the second edge driving circuit, and the plurality of central flexible circuit boards correspond one-to-one with and are electrically connected to the plurality of central driving circuits.

[0009] The control circuit board is provided with multiple timing transmission lines and timing controller chips, and at least one timing transmission line is electrically connected to the timing controller chip and the multiple flexible circuit boards respectively.

[0010] In an exemplary embodiment, the display substrate further includes: a plurality of driving control signal lines located in the bezel region, at least one of the plurality of driving control signal lines extending at least partially along a second direction, the first direction and the second direction intersecting; the plurality of driving control signal lines being electrically connected to the plurality of gate driving circuits respectively; at least one of the first edge driving circuit and the second edge driving circuit and at least one of the plurality of center driving circuits being connected to at least one of the plurality of driving control signal lines respectively.

[0011] In an exemplary embodiment, the second connection signal line is located in the border area and includes: a plurality of first signal lines and a plurality of second signal lines;

[0012] The first signal line is connected to the target center drive circuit, the second signal line is electrically connected to at least one of the plurality of drive control signal lines, the first signal line is electrically connected to the second signal line through the signal transmission line, and the target center drive circuit is the center drive circuit connected to at least one of the plurality of drive control signal lines.

[0013] In an exemplary embodiment, one end of the first signal line is connected to the target center driving circuit, and the other end of the first signal line is connected to the target center flexible circuit board. One end of the signal transmission line is connected to the target center flexible circuit board, and the other end of the signal transmission line is connected to at least one flexible circuit board among the first edge flexible circuit board and the second edge flexible circuit board. One end of the second signal line is connected to at least one flexible circuit board among the first edge flexible circuit board and the second edge flexible circuit board, and the other end of the second signal line is connected to at least one of the plurality of drive control signal lines.

[0014] The target central flexible circuit board is the central flexible circuit board corresponding to the target central driving circuit.

[0015] In an exemplary embodiment, at least a portion of at least one of the plurality of signal transmission lines is located on the side of the flexible circuit board away from the display area.

[0016] In an exemplary embodiment, the other end of the signal transmission line is connected to the first edge flexible circuit board and the second edge flexible circuit board, respectively.

[0017] In an exemplary embodiment, the other end of the signal transmission line is connected to a flexible circuit board at the edge of the target.

[0018] The target edge flexible circuit board refers to the edge flexible circuit board that is closest to the central flexible circuit board connected to the signal transmission line along the first direction.

[0019] In an exemplary embodiment, at least a portion of at least one of the multiple drive control signal lines connected to the edge drive circuit is located on the side of at least one of the multiple drive control signal lines connected to the middle drive circuit that is closer to the display area.

[0020] In an exemplary embodiment, the display substrate is further provided with a plurality of third connection signal lines located in the frame area;

[0021] One end of the third connection signal line is connected to the target center driving circuit, and the other end of the third connection signal line is connected to at least one of the plurality of driving control signal lines. The target center driving circuit is the center driving circuit connected to at least one of the plurality of driving control signal lines.

[0022] In an exemplary embodiment, at least a portion of at least one of the multiple drive control signal lines connected to the edge drive circuit is located on the side of at least one of the multiple drive control signal lines connected to the center drive circuit that is away from the display area.

[0023] In an exemplary embodiment, the first connection signal line is located in the border area;

[0024] One end of the first connection signal line is connected to the target edge driving circuit, and the other end of the first connection signal line is connected to at least one of the plurality of driving control signal lines, wherein the target edge driving circuit is the edge driving circuit connected to at least one of the plurality of driving control signal lines.

[0025] In an exemplary embodiment, the display substrate further includes: a substrate and a plurality of pixel driving circuits and a plurality of data signal lines disposed on the substrate in the display area and a plurality of data fan-out lines in the border area, wherein the data signal lines and the data fan-out lines extend at least partially along the second direction;

[0026] At least one data signal line is connected to at least one column of pixel driving circuits and at least one data fan-out line, and at least one data fan-out line is also connected to at least one driving circuit.

[0027] When the display substrate includes multiple third connection signal lines, the orthographic projection of the third connection signal lines on the substrate does not overlap with the orthographic projection of the multiple data fan-out lines on the substrate.

[0028] In an exemplary embodiment, the display substrate further includes: a first power supply line and a second power supply line at least partially located in the border area; at least one of the first power supply line and the second power supply line at least partially overlaps between the orthographic projection on the substrate and the orthographic projection of at least one of the third connection signal lines.

[0029] In an exemplary embodiment, the at least one third connection signal line is located on the side of at least one of the first power supply line and the second power supply line away from the substrate.

[0030] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate further includes at least one gate metal layer and at least one source / drain metal layer sequentially disposed on the substrate; wherein, the data signal line is located in one of the at least one source / drain metal layers, the data fan-out line is located in at least one of the at least one gate metal layers, at least one of the first power supply line and the second power supply line is located in at least one of the at least one source / drain metal layers, and the third connection signal line is located in at least one of the at least one source / drain metal layers.

[0031] In an exemplary embodiment, the third connection signal line is located in the film layer that is furthest from the substrate in at least one source / drain metal layer.

[0032] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate further includes at least one source / drain metal layer and a touch layer sequentially disposed on the substrate, the touch layer including a first touch conductive layer and a second touch conductive layer sequentially disposed in a direction away from the substrate; the third connection signal line is located in at least one of the first touch conductive layer and the second touch conductive layer.

[0033] In an exemplary embodiment, the third connection signal line comprises a multilayer metal structure in a direction perpendicular to the display substrate, or the third connection signal line is a single-layer metal structure.

[0034] In an exemplary embodiment, a plurality of gate driving circuits within the first driving circuit region are arranged sequentially along the first direction; the display substrate includes two first driving circuit regions, which are respectively located on the first side and the second side of the display area; the display substrate has a symmetry line extending along the second direction, and the plurality of gate driving circuits within the two first driving circuit regions are symmetrically arranged with respect to the symmetry line axis.

[0035] In an exemplary embodiment, along the first direction, a plurality of drive circuits located on one side of the line of symmetry are configured to be connected to a plurality of drive control signal lines located on the same side of the line of symmetry; along the first direction, a plurality of drive circuits located on the other side of the line of symmetry are configured to be connected to a plurality of drive control signal lines located on the same side of the line of symmetry.

[0036] Secondly, embodiments of this disclosure provide a display device, including: a display module as described above.

[0037] Other advantages of this disclosure can be realized and obtained through the methods described in the specification and drawings.

[0038] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0039] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0040] Figure 1 This is a schematic diagram of the planar structure of a display module in one exemplary embodiment;

[0041] Figure 2 This is an equivalent circuit diagram of a pixel driving circuit in an exemplary embodiment.

[0042] Figure 3 This is a plan view of a display module in an exemplary embodiment of the present disclosure;

[0043] Figure 4 This is a plan view of the display module in yet another exemplary embodiment;

[0044] Figure 5 This is a top view of a plurality of gate drive circuits in the first drive circuit region in an exemplary embodiment;

[0045] Figure 6 This is a plan view of the display module in yet another exemplary embodiment;

[0046] Figure 7 This is a cross-sectional view of the display substrate in the display area according to an exemplary embodiment;

[0047] Figure 8 This is a top view of the first power line, the second power line, and the third connection signal line on the display substrate in an exemplary embodiment.

[0048] Figure 9 As an exemplary implementation Figure 7 A sectional view along direction AA;

[0049] Figure 10 This is a top view of the first power supply line, the second power supply line, and the third connection signal line on the display substrate in yet another exemplary embodiment.

[0050] Figure 11 This is a top view of the first power supply line, the second power supply line, and the third connection signal line on the display substrate in yet another exemplary embodiment. Detailed Implementation

[0051] This disclosure describes several embodiments, but these descriptions are exemplary and not restrictive, and many more embodiments and implementations are possible within the scope of the embodiments described herein, which will be apparent to those skilled in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with or in lieu of any other feature or element in any other embodiment.

[0052] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0053] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0054] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0055] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0056] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0057] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0058] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0059] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Electrical connection" includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0060] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0061] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0062] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0063] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0064] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0065] Figure 1 This is a schematic diagram of the planar structure of a display module in one exemplary embodiment. Figure 1 As shown, the display module may include a display substrate G, a control circuit board K, multiple driving circuits, and multiple flexible printed circuit boards (FPCs). The multiple driving circuits and multiple flexible printed circuit boards are electrically connected to each other and are respectively bonded to the display substrate G. The multiple flexible printed circuit boards are all electrically connected to the control circuit board K.

[0066] In an exemplary embodiment, the driving circuit can be an integrated circuit (IC).

[0067] like Figure 1As shown, the display substrate may include a display area AA and a border area BB surrounding the display area AA. The border area BB may include a first driving circuit area B1 and a second driving circuit area B2. Along the first direction X, the opposite sides of the display area AA are a first side and a second side, respectively. Along the second direction Y, the opposite sides of the display area AA are a third side and a fourth side, respectively. The first driving circuit area B1 may be disposed on at least one of the first side and the second side of the display area AA. The second driving circuit area B2 may be disposed on the third side or the fourth side of the display area AA; for example, the second driving circuit area B2 may be disposed on the third side of the display area AA. The first direction X and the second direction Y intersect each other; for example, the first direction X and the second direction Y may be perpendicular to each other. Multiple sub-pixels P are provided in the display area AA. Multiple sub-pixels P arranged along the first direction X can be referred to as a sub-pixel row, and multiple sub-pixels P arranged along the second direction Y can be referred to as a sub-pixel column. The multiple sub-pixels P on the display substrate are arranged in multiple rows and multiple columns. Each sub-pixel P may include a pixel driving circuit and a light-emitting element. The pixel driving circuit in sub-pixel P is connected to both the scan signal line Ls and the data signal line D. The pixel driving circuit is configured to receive the data voltage transmitted via the data signal line D under the control of the scan signal line Ls and output a corresponding current to the light-emitting element. The light-emitting element in sub-pixel P is connected to the pixel driving circuit of its respective sub-pixel P and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel P. Figure 1 As shown, each scan signal line Ls can be connected to multiple pixel driving circuits of a sub-pixel row, and each data signal line D can be connected to multiple pixel driving circuits of a sub-pixel column.

[0068] In an exemplary embodiment, multiple sub-pixels P may include a red sub-pixel (R) emitting red light, a blue sub-pixel (B) emitting blue light, and a green sub-pixel (G) emitting green light. One red sub-pixel, one blue sub-pixel, and one green sub-pixel can form a pixel unit, or one red sub-pixel, one blue sub-pixel, and two green sub-pixels can form a pixel unit. Multiple pixel units can be arranged in a matrix on the display substrate. In other embodiments, a pixel unit may include one red sub-pixel, one green sub-pixel, one blue sub-pixel, and one white sub-pixel emitting white (W) light. The shape of the sub-pixels can be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons, and other polygons. Three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, and four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, in a square, or in a diamond shape, etc. This disclosure does not limit the arrangement.

[0069] Figure 2This is a schematic diagram of the equivalent circuit of a pixel driving circuit in an exemplary embodiment. In this exemplary embodiment, the pixel driving circuit can be a structure such as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C. Figure 2 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit is connected to 6 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT and first power supply line VDD).

[0070] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0071] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the gate electrode of the third transistor T3.

[0072] The gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first terminal of the first transistor T1 is connected to the initial signal line INIT, and the second terminal of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initial voltage to the gate electrode of the third transistor T3 to initialize the charge on the gate electrode of the third transistor T3.

[0073] The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first terminal of the second transistor T2 is connected to the second node N2, and the second terminal of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode of the third transistor T3 to its second terminal.

[0074] The gate electrode of the third transistor T3 is connected to the second node N2, meaning the gate electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first terminal of the third transistor T3 is connected to the first node N1, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its gate electrode and its first terminal.

[0075] The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0076] The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting element EL to emit light.

[0077] The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element EL. When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits the initial voltage to the first electrode of the light-emitting element EL to initialize or release the accumulated charge in the first electrode of the light-emitting element EL.

[0078] In an exemplary embodiment, the light-emitting element EL can be an OLED, including a stacked first electrode, an organic light-emitting layer and a second electrode, or it can be a QLED, including a stacked first electrode, a quantum dot light-emitting layer and a second electrode. In this embodiment, the first electrode can be an anode and the second electrode can be a cathode. This disclosure does not limit this.

[0079] In an exemplary embodiment, the second electrode of the light-emitting element EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0080] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0081] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0082] exist Figure 1In the first driving circuit area B1, multiple gate driving circuits can be arranged sequentially along the first direction X away from the display area AA. Each gate driving circuit can be connected to a sub-pixel P in the display area AA to provide a corresponding driving signal to the sub-pixel P. Different gate driving circuits can provide different driving signals to the sub-pixels of the display area AA. These different driving signals can include: scan signals, compensation control signals, light emission control signals, and reset signals. Among them, the scan signal can be transmitted to the sub-pixel row through the scan signal line Ls, the compensation control signal is used to compensate the threshold voltage of the driving transistor in the pixel driving circuit, the light emission control signal is used to control the corresponding sub-pixel P to emit light, and the reset signal is used to eliminate the residual charge from the previous frame. The border area BB can be provided with multiple driving control signal lines Lz, at least one of the multiple driving control signal lines Lz extending at least partially along the second direction Y. The multiple driving control signal lines Lz are connected to the gate driving circuit and are configured to provide the necessary control signals to the gate driving circuit so that the gate driving circuit generates driving signals under the control of the control signals. Figure 1 The illustration uses an example where first driving circuit areas B1 are set on both the first and second sides of the display area AA. The multiple gate driving circuits set within the two first driving circuit areas B1 can be identical and can control different sub-pixel rows. The position of the first driving circuit area B1, the number of gate driving circuits it contains, and the driving signals provided by each gate driving circuit can be set as needed.

[0083] In an exemplary implementation, such as Figure 1 As shown, the display module may include n driving circuits, namely the first driving circuit IC1 to the nth driving circuit ICn from right to left along the first direction X. The n driving circuits can be arranged sequentially along the first direction X, where n is an integer greater than or equal to 3. The n driving circuits can be connected to multiple data signal lines D of the display area AA through multiple data fan-out lines Ld of the border area BB, thereby providing data signals to multiple sub-pixels P. For example, each data signal line D can be connected to one data fan-out line Ld, each data fan-out line Ld can be connected to at least one driving circuit, and each driving circuit can be connected to at least one sub-pixel column. Each data fan-out line Ld can be connected to the corresponding driving circuit through a data lead (not shown in the figure). The two driving circuits located at both ends along the first direction X can be called edge driving circuits, and the remaining driving circuits can be called middle driving circuits. Figure 1The first driving circuit IC1 can be called the first edge driving circuit, the nth driving circuit ICn can be called the second edge driving circuit, and the second driving circuit IC2 to the (n-1)th driving circuit ICn-1 are the middle driving circuits. The edge driving circuits can be connected to at least one of the multiple driving control signal lines Lz through multiple control signal transmission lines Lg to provide control signals to the gate driving circuit. The display module can include n flexible circuit boards, namely the first flexible circuit board FPC1 to the nth flexible circuit board FPCn from right to left along the first direction X, and the n flexible circuit boards can be arranged sequentially along the first direction X. The two flexible circuit boards located at both ends along the first direction X can be called edge flexible circuit boards, and the remaining flexible circuit boards can be called middle flexible circuit boards. Figure 1 The first flexible circuit board FPC1 can be called the first edge flexible circuit board, the nth flexible circuit board FPCn can be called the second edge flexible circuit board, and the second flexible circuit board FPC2 to the (n-1)th flexible circuit board FPCn-1 are the central flexible circuit boards. Multiple central driving circuits are correspondingly arranged and electrically connected to multiple flexible circuit boards. The flexible circuit boards can be located on the side of the corresponding driving circuit away from the display area AA. For example, the first driving circuit IC1 can be electrically connected to the first flexible circuit board FPC1, the i-th driving circuit ICi can be electrically connected to the i-th flexible circuit board FPCi, and the n-th driving circuit ICn can be electrically connected to the n-th flexible circuit board FPCn, where i is an integer greater than 1 and less than n. The display substrate G can be provided with multiple bonding pads (not shown in the figure) in the second driving circuit area B2. Multiple driving circuits and multiple flexible circuit boards can be bonded to the display substrate G through these bonding pads. The number of driving circuits and the number of flexible circuit boards can be set according to the requirements of the display module.

[0084] Figure 1 For clarity, the diagram simplifies the representation of the number of signal lines such as control signal transmission line Lg, drive control signal line Lz, and timing transmission line Lt. The number of these signal lines can be set as needed.

[0085] With the development of display technology, people have increasingly higher requirements for image display quality. For example, display devices need to support higher refresh rates while maintaining low power consumption at lower refresh rates. To achieve these requirements, improvements need to be made to the pixel driving circuit, for example, by... Figure 2 The 7T1C architecture was modified to a 10T2C architecture. The structure of pixel driving circuits is becoming increasingly complex, with an increasing number of gate driving circuits working in conjunction with them, and the types of signals that the gate driving circuits need to provide to the pixel driving circuits are also increasing. In this situation, the gate driving circuit needs to connect to more signal paths on the driving circuit. However, in... Figure 1 In the display module shown, the number of AC and DC signal channels that the edge driving circuit can provide is limited, and it cannot provide the signals required by the multiple gate driving circuits on the display substrate.

[0086] Therefore, this disclosure provides a display module and a display device.

[0087] The display module provided in this embodiment includes: a display substrate, a plurality of flexible circuit boards and a control circuit board. The display substrate has a display area and a border area surrounding the display area. The border area includes: a first driving circuit area and a second driving circuit area. The first driving circuit area is located on at least one of a first side and a second side of the display area, and the second driving circuit area is located on a third side of the display area. The first side and the second side are disposed opposite to each other.

[0088] The first driving circuit region includes a plurality of gate driving circuits, and the second driving circuit region includes a plurality of driving circuits arranged along a first direction. The plurality of driving circuits include an edge driving circuit and a plurality of center driving circuits. The edge driving circuit includes a first edge driving circuit and a second edge driving circuit. The first edge driving circuit and the second edge driving circuit are respectively located at both ends of the plurality of center driving circuits along the first direction.

[0089] Wherein, at least one of the first edge driving circuit and the second edge driving circuit and one of the plurality of middle driving circuits are electrically connected to the plurality of gate driving circuits respectively, and the plurality of flexible circuit boards are respectively connected to the plurality of driving circuits and the control circuit board.

[0090] The display substrate is provided with a first connection signal line and a second connection signal line, and the control circuit board is provided with a signal transmission line. At least one of the first edge driving circuit and the second edge driving circuit is connected to at least one of the plurality of gate driving circuits through the first connection signal line. At least one of the plurality of center driving circuits is connected to at least one of the plurality of gate driving circuits through the second connection signal line and the signal transmission line.

[0091] The display module provided in this disclosure provides control signals to multiple gate drive circuits by utilizing at least one of the first and second edge drive circuits and multiple center drive circuits. The center drive circuits can fully utilize their signal channels through signal lines located in the bezel area and the control circuit board. This not only satisfies the signal channel requirements of the drive circuits on the display module but also avoids the increased costs associated with developing new drive circuits.

[0092] In an exemplary embodiment, multiple flexible circuit boards are connected to a control circuit board K. The control circuit board K may house a timing controller (TCON) chip (TCON) and multiple timing transmission lines (Lt). The timing controller chip can be connected to the multiple flexible circuit boards via the timing transmission lines (Lt) on the control circuit board K. Timing signals emitted by the timing controller chip are transmitted to the flexible circuit boards via the timing transmission lines (Lt). The flexible circuit boards can then transmit the timing signals to the drive circuits connected to them. The drive circuits can provide control signals to the corresponding gate drive circuits based on the received timing signals. The control circuit board K can be, for example, a printed circuit board (PCB). The timing controller chip can also be integrated onto the flexible circuit board or into the processor of the display device; this disclosure does not limit this.

[0093] In an exemplary embodiment, the plurality of flexible circuit boards include: a first edge flexible circuit board, a second edge flexible circuit board, and a plurality of central flexible circuit boards. The first edge flexible circuit board is electrically connected to a first edge driving circuit, the second edge flexible circuit board is electrically connected to a second edge driving circuit, and the plurality of central flexible circuit boards correspond one-to-one with and are electrically connected to a plurality of central driving circuits.

[0094] Figure 3 This is a plan view of a display module in an exemplary embodiment of the present disclosure. Figure 3 The diagram also simplifies the representation of the number of various signal lines. For example... Figure 3 As shown, the display module includes a display substrate G and multiple driving circuits. The display area AA of the display substrate G is provided with multiple sub-pixels (not shown in the figure). The border area BB of the display substrate G includes a first driving circuit area B1 located on at least one of the first and second sides of the display area AA, and a second driving circuit area B2 located on the third side of the display area AA. Multiple driving circuits are bonded to the second driving circuit area B2. Multiple gate driving circuits are disposed within the first driving circuit area B1. The multiple driving circuits are arranged sequentially along a first direction X, including: edge driving circuits and multiple center driving circuits. The edge driving circuits include: a first edge driving circuit and a second edge driving circuit, which are respectively located at both ends of the multiple center driving circuits along the first direction X. Figure 3In this configuration, the first edge driving circuit is the first driving circuit IC1, the second edge driving circuit is the nth driving circuit ICn, and the middle driving circuit includes the second driving circuit IC2 to the (n-1)th driving circuit ICn-1. At least one circuit of the first driving circuit IC1 and the nth driving circuit ICn, and at least one circuit of the second driving circuit IC2 to the (n-1)th driving circuit ICn-1, are electrically connected to a plurality of gate driving circuits and configured to provide control signals to the plurality of gate driving circuits. The gate driving circuits are configured to generate driving signals under the control of the control signals, so that the sub-pixels emit light under the control of the driving signals. Figure 3 The dashed lines connecting each driving circuit and gate driving circuit represent electrical connections. By utilizing at least one edge driving circuit and multiple center driving circuits to provide control signals to multiple gate driving circuits, the signal channels of the center driving circuits can be fully utilized. This increases the number of signal channels provided to the gate driving circuits without changing the original display module layout, and avoids the increased costs associated with developing new driving circuits.

[0095] Figure 4 This is a plan view of the display module in yet another exemplary embodiment. Figure 4 The diagram also simplifies the representation of the number of various signal lines. For example... Figure 4 As shown, the second connection signal line is located in the frame area BB and includes multiple first signal lines Lx1 and multiple second signal lines Lx2. The control circuit board K includes multiple signal transmission lines Lk.

[0096] like Figure 4 As shown, the display substrate further includes: multiple drive control signal lines Lz located in the bezel area BB, at least one of the multiple drive control signal lines Lz extends at least partially along the second direction Y, the first direction X and the second direction Y intersect, and the drive control signal lines are electrically connected to the multiple gate drive circuits respectively.

[0097] In an exemplary embodiment, at least one of the first edge driving circuit and the second edge driving circuit, and a plurality of middle driving circuits, are respectively connected to at least one of the plurality of driving control signal lines Lz.

[0098] In an exemplary implementation, such as Figure 4 As shown, at least one first signal line Lx1 is connected to the target center drive circuit, and the second signal line Lx2 is electrically connected to at least one of the multiple drive control signal lines. The first signal line Lx1 is electrically connected to the second signal line Lx2 through the signal transmission line Lk. The target center drive circuit is a center drive circuit connected to at least one of the multiple drive control signal lines.

[0099] In an exemplary embodiment, one end of the first signal line Lx1 is connected to the target center driving circuit, and the other end of the first signal line Lx1 is connected to the target center flexible circuit board. One end of the signal transmission line Lk is connected to the target center flexible circuit board, and the other end of the signal transmission line Lk is connected to at least one of the first edge flexible circuit boards and the second edge flexible circuit board. One end of the second signal line Lx2 is connected to at least one of the first edge flexible circuit boards and the second edge flexible circuit board, and the other end of the second signal line Lx2 is connected to at least one of the multiple drive control signal lines Lz. The target center flexible circuit board is the center flexible circuit board corresponding to the target center driving circuit.

[0100] In this disclosure, the first signal line Lx1 is used to connect the target center driving circuit to the target center flexible circuit board corresponding to the target center driving circuit, the signal transmission line Lk is used to connect the target center flexible circuit board to at least one of the first edge flexible circuit board and the second edge flexible circuit board, and the second signal line Lx2 is used to connect at least one of the first edge flexible circuit board and the second edge flexible circuit board and at least one of the multiple drive control signal lines Lz. That is, the signal output from the target center driving circuit flows sequentially through the first signal line Lx1, the target center flexible circuit board corresponding to the target center driving circuit, the signal transmission line Lk, at least one of the first edge flexible circuit board and the second edge flexible circuit board, and the second signal line Lx2 to at least one of the multiple drive control signal lines Lz, so that the control signal output by the target center driving circuit can reach the corresponding gate driving circuit.

[0101] In an exemplary implementation, such as Figure 4 As shown, at least a portion of at least one of the multiple drive control signal lines Lz connected to the edge drive circuit is located on the side of at least one of the multiple drive control signal lines Lz connected to the middle drive circuit that is closer to the display area.

[0102] In an exemplary implementation, such as Figure 4 As shown, multiple signal transmission lines Lk can be located on the side of multiple flexible circuit boards away from multiple drive circuits.

[0103] In an exemplary implementation, such as Figure 4 As shown, the display substrate also has multiple first connection signal lines L1 in the bezel area BB. The target edge driving circuit can be directly connected to at least one of the multiple driving control signal lines Lz through the first connection signal lines L1 in order to provide control signals to the corresponding gate driving circuit. The target edge driving circuit refers to the edge driving circuit connected to at least one of the multiple driving control signal lines Lz.

[0104] In an exemplary embodiment, the multiple drive control signal lines Lz connected to the multiple first connection signal lines L1 can be referred to as first type signal lines, and the multiple drive control signal lines Lz connected to the multiple second signal lines Lx2 can be referred to as second type signal lines. At least one of the multiple first type signal lines is a different signal line from the second type signal line.

[0105] Compared to newly developed driver circuits with a larger number of channels, Figure 4 The display module shown uses the central driving circuit to provide control signals to the gate driving circuit. It does not require complex structural design, long development cycle and stability testing, and has lower cost. It also requires less structural modification to existing display modules and is easy to promote.

[0106] like Figure 4 As shown, the first driving circuit IC1 can be interconnected with the first flexible circuit board FPC1 via multiple first signal lines Lx1, the i-th driving circuit ICi can be interconnected with the i-th flexible circuit board FPCi via multiple first signal lines Lx1, and the n-th driving circuit ICn can be interconnected with the n-th flexible circuit board FPCn via multiple first signal lines Lx1. Each control signal from the central driving circuit can be transmitted via at least one first signal line Lx1. The multiple first signal lines Lx1 can be placed close to the edge of the connected central driving circuit, which not only reduces space occupation and facilitates wiring of the display substrate, but also helps to reduce the risk of overlapping with other signal traces on the display substrate, ensuring the stability of signal transmission.

[0107] In an exemplary embodiment, along the first direction X, the central flexible circuit board can be connected to the edge flexible circuit boards closer to it via a signal transmission line Lk. The edge flexible circuit board connected to this central flexible circuit board can be referred to as the target edge flexible circuit board. This proximity connection helps reduce the length of the signal transmission line Lk and facilitates routing on the control circuit board K, contributing to stable transmission of control signals. In other embodiments, the central flexible circuit board can be connected to two edge flexible circuit boards respectively via the signal transmission line Lk. In this case, the central drive circuit can provide control signals to the first flexible circuit board FPC1 and the nth flexible circuit board FPCn respectively. The connection relationship between a single central drive circuit and two edge flexible circuit boards can be configured as needed.

[0108] In an exemplary embodiment, Figure 4This example illustrates the concept of each central driving circuit providing a control signal. In other embodiments, any number of central driving circuits can provide control signals, while the remaining central driving circuits may not. For central driving circuits that do not provide control signals, the first signal line Lx1 and signal transmission line Lk may not be required, which helps reduce the number of traces in the display module. The number and location of central driving circuits providing control signals can be set as needed. The central driving circuit that provides control signals can be referred to as the target central driving circuit, and the corresponding central flexible circuit board can be referred to as the target central flexible circuit board.

[0109] In an exemplary embodiment, the display substrate may have a symmetry line O extending along the second direction Y. Multiple central flexible circuit boards located to the left of the symmetry line can be connected to the nth flexible circuit board FPCn via signal transmission line Lk, and multiple central flexible circuit boards located to the right of the symmetry line can be connected to the first flexible circuit board FPC1 via signal transmission line Lk, achieving proximity-based connection. When the symmetry line O passes through a certain central flexible circuit board, the connection between that central flexible circuit board and which edge flexible circuit board can be configured as needed, or the central flexible circuit board can be configured not to provide control signals. Multiple gate drive circuits disposed within the two first drive circuit areas B1 located on the first and second sides of the display area AA can be arranged symmetrically along the symmetry line O. This symmetry line O is a virtual concept; such a straight line does not exist in the actual product.

[0110] Figure 5 This is a top view of a plurality of gate drive circuits in the first drive circuit area in an exemplary embodiment, omitting the remaining structure of the display module. Figure 5 The diagram also simplifies the representation of the number of various signal lines. For example... Figure 5As shown, multiple gate driving circuits can be disposed in the first driving circuit area B1, and these multiple gate driving circuits can be arranged sequentially along the first direction X away from the display area AA. Each gate driving circuit can be connected to multiple driving control signal lines (not shown in the figure). These multiple gate driving circuits can include: a first gate driving circuit GOA1, a second gate driving circuit GOA2 to the m-th gate driving circuit GOAm. Different gate driving circuits can provide different driving signals to the sub-pixels P of the display area AA. For example, the first gate driving circuit GOA1 can be configured to provide a scan signal to the sub-pixel P, the second gate driving circuit GOA2 can be configured to provide a compensation control signal to the sub-pixel P to compensate the threshold voltage of the driving transistor in the pixel driving circuit, the third gate driving circuit GOA3 can be configured to provide a light emission control signal to the sub-pixel to make the corresponding sub-pixel emit light, and the m-th gate driving circuit GOAm can be configured to provide a reset signal to the sub-pixel P to eliminate the residual charge of the previous frame. Figure 5 The diagram illustrates the arrangement of multiple gate drive circuits in two first drive circuit regions B1 in an axially symmetrical configuration along the symmetry line O. The position of the first drive circuit region B1, the number of gate drive circuits it contains, and the drive signal provided by each gate drive circuit can be set as needed.

[0111] In an exemplary embodiment, each gate driving circuit may include multiple cascaded driving units Q, with the multi-stage driving units Q arranged sequentially in the second direction Y, and the output signal of the previous stage driving unit Q can be used as the input signal of the next stage driving unit Q. Figure 5 The arrows within each gate drive circuit indicate the signal transmission direction between the multi-stage drive units Q and the direction in which the drive unit Q transmits the drive signal to the sub-pixel row. Each drive unit Q is configured to transmit drive signals to one or more corresponding sub-pixel rows within the display area AA. Different gate drive circuits may include different numbers of drive units Q, and the number of drive units Q can be set according to the coordination between the drive signals transmitted by the gate drive circuit and the sub-pixels.

[0112] In an exemplary embodiment, multiple driving circuits can provide control signals to different gate driving circuits. For example, for the first driving circuit region B1 located to the left of the symmetry line O, the edge driving circuit located to the left of the symmetry line O can provide a control signal to the m-th gate driving circuit GOAm, and the multiple middle driving circuits located to the left of the symmetry line O can provide control signals to the remaining m-1 gate driving circuits. For the first driving circuit region B1 located to the right of the symmetry line O, the edge driving circuit located to the right of the symmetry line O can provide a control signal to the m-th gate driving circuit GOAm, and the multiple middle driving circuits located to the right of the symmetry line O can provide control signals to the remaining m-1 gate driving circuits. In other embodiments, each driving circuit can be configured to provide control signals to any number of gate driving circuits, and the location of each driving circuit can be configured as needed to facilitate wiring arrangement on the display substrate.

[0113] Figure 6 This is a plan view of the display module in yet another exemplary embodiment. Figure 6 The diagram also simplifies the representation of the number of various signal lines. Figure 6 and Figure 4 The difference lies in the routing method of the control signals provided by the middle drive circuit to the gate drive circuit. For the remaining details, please refer to the aforementioned section. Figure 4 The description will not be repeated here.

[0114] like Figure 6 As shown, the display substrate also includes multiple third connection signal lines L3, at least one of which is used to connect the target center driving circuit and at least one of the multiple driving control signal lines L2. The target center driving circuit can be connected to at least one gate driving circuit via at least one third connection signal line L3, reducing the need for wiring connections via first signal lines, second signal lines, and signal transmission lines on the flexible circuit board and control circuit board K. Figure 6 The display module shown simplifies the wiring design of the control circuit board.

[0115] In an exemplary implementation, such as Figure 6 As shown, at least a portion of at least one of the multiple drive control signal lines Lz connected to the edge drive circuit is located on the side of at least one of the multiple drive control signal lines Lz connected to the middle drive circuit that is away from the display area.

[0116] Figure 7 This is a cross-sectional view of a display substrate in the display area, illustrating the structure of three sub-pixels of the display substrate in an exemplary embodiment. Figure 7As shown, in a direction perpendicular to the display substrate, the display substrate may include a driving circuit layer 12 disposed on the substrate 10, a light-emitting element 13 disposed on the side of the driving circuit layer 12 away from the substrate 10, an encapsulation layer 14 disposed on the side of the light-emitting element 13 away from the substrate 10, and a touch layer 15 disposed on the side of the encapsulation layer 14 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as a light-shielding layer and a color filter layer, etc., which are not limited herein.

[0117] In some exemplary embodiments, the substrate 10 may be a flexible substrate or a rigid substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0118] In some exemplary embodiments, the driving circuit layer 12 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 7The illustration uses an example where each sub-pixel includes a driving transistor and a storage capacitor. In some possible implementations, the driving circuit layer 12 of each sub-pixel may include: a first insulating layer 21 disposed on a substrate; an active layer disposed on the first insulating layer 21; a second insulating layer 22 covering the active layer; a gate electrode and a first capacitor electrode disposed on the second insulating layer 202; a third insulating layer 23 covering the gate electrode and the first capacitor electrode; a second capacitor electrode disposed on the third insulating layer 23; a fourth insulating layer 24 covering the second capacitor electrode, with vias formed in the second insulating layer 22, the third insulating layer 23, and the fourth insulating layer 24, exposing the active layer; a source electrode and a drain electrode disposed on the fourth insulating layer 24, respectively connected to the active layer through vias; and a fifth insulating layer 25 covering the aforementioned structure, with vias formed in the fifth insulating layer 25, exposing the drain electrode. The driving circuit layer 12 may also include a first connecting electrode and a second connecting electrode, through which the anode 231 can be connected to the drain electrode of the driving transistor. The first connection electrode can be disposed on the fifth insulating layer 25 and connected to the drain electrode through a via formed in the fifth insulating layer 25. The sixth insulating layer 26 can cover the aforementioned structure and has a via formed in the sixth insulating layer 26, exposing the first connection electrode. The second connection electrode can be disposed on the sixth insulating layer 26 and connected to the first connection electrode through a via formed in the sixth insulating layer 26. The planarization layer 27 can cover the aforementioned structure and has a via formed in the planarization layer 27, exposing the second connection electrode. Subsequently, the anode 231 can be connected to the second connection electrode through the via formed in the planarization layer 27, thereby achieving connection with the drain electrode of the corresponding driving transistor. The active layer, gate electrode, source electrode, and drain electrode constitute the driving transistor 231, and the first capacitor electrode and the second capacitor electrode constitute the storage capacitor 232. In this embodiment, the film layer containing the gate electrode and the first capacitor electrode can be referred to as the first gate electrode layer, the film layer containing the second capacitor electrode can be referred to as the second gate electrode layer, the film layer containing the source electrode and the drain electrode can be referred to as the first source-drain electrode layer, the film layer containing the first connecting electrode can be referred to as the second source-drain electrode layer, and the film layer containing the second connecting electrode can be referred to as the third source-drain electrode layer. In an exemplary embodiment, the above-mentioned insulating layer can be formed using organic or inorganic materials, and a single insulating layer can be a single-layer structure or a multi-layer composite structure; this disclosure does not impose any limitations on this.

[0119] In some exemplary embodiments, the light-emitting element 13 may include an anode 31, a pixel definition layer 32, a light-emitting functional layer 33, and a cathode 34. The anode 31 is disposed on the planarization layer 25 and connected to the drain electrode of the driving transistor 231 through a via formed in the planarization layer 25; the pixel definition layer 32 is disposed on the anode 31 and the planarization layer 25, and the pixel definition layer 32 is provided with a pixel opening that exposes the anode 31; the light-emitting functional layer 33 is at least partially disposed within the pixel opening and is connected to the anode 31; the cathode 34 is disposed on the light-emitting functional layer 33 and is connected to the light-emitting functional layer 33; the light-emitting functional layer 33 emits light of a corresponding color under the drive of the anode 31 and the cathode 34.

[0120] In an exemplary embodiment, the anode 31 can be made of a transparent conductive material, which can be made of a single material or multiple materials stacked together, such as a three-layer composite structure of ITO / Ag / ITO. This disclosure does not limit this.

[0121] In some exemplary embodiments, the light-emitting functional layer of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltages of the anode and cathode, the light-emitting properties of the organic material are utilized to emit light at the required grayscale.

[0122] In some exemplary embodiments, the encapsulation layer 14 may include a first encapsulation layer 41, a second encapsulation layer 42, and a third encapsulation layer 43 stacked together. The first encapsulation layer 41 and the third encapsulation layer 43 may be made of inorganic materials to prevent the penetration of moisture, oxygen, etc. The second encapsulation layer 42 may be made of organic materials to improve the flatness of the encapsulation layer 14. The second encapsulation layer 42 is disposed between the first encapsulation layer 41 and the third encapsulation layer 43 to ensure that external moisture cannot enter the light-emitting element 13. In an exemplary embodiment, the encapsulation layer 14 may cover the display area AA.

[0123] In some exemplary embodiments, the touch layer 15 may include a touch base layer (TBL), a first touch conductive layer (TMA), a touch line definition layer (TLD), a second touch conductive layer (TMB), and a touch overcoat layer (TOC). Multiple touch electrodes may be disposed within the first and second touch conductive layers. In exemplary embodiments, combined with... Figure 6 As shown, the data fan-out line Ld can be disposed in at least one of the first gate metal layer and the second gate metal layer. The data signal line D can be disposed in at least one of the first source-drain electrode layer, the second source-drain electrode layer, and the third source-drain electrode layer. The first power line VDD and the second power line VSS can be disposed in, for example, the first power line VDD can adopt a stacked structure disposed in the first source-drain electrode layer and the second source-drain electrode layer, and the second power line VSS can adopt a stacked structure disposed in the first source-drain electrode layer and the second source-drain electrode layer, which helps to reduce impedance. The display substrate can include a first power supply line and a second power supply line located at least in the bezel area BB. The first power supply line can supply power to the first power line VDD, and the second power supply line can supply power to the second power line VSS. The first power supply line can be located in the same layer as the first power line VDD and have the same structure, and the second power supply line can be located in the same layer as the second power line VSS and have the same structure.

[0124] Figure 8 This is a top view of the first power supply line, the second power supply line, and the third connection signal line on the display substrate in an exemplary embodiment, omitting the rest of the display module structure. Figure 8 The diagram also simplifies the representation of the number of various signal lines. For example... Figure 8 As shown, multiple data fan-out lines Ld are connected to the data signal line D (not shown in the figure) within the display area AA, and each data fan-out line Ld is connected to the corresponding drive circuit through a data lead Lj. Figure 8 The diagram illustrates two data fan-out lines Ld connected to each driver circuit. Among the multiple data fan-out lines Ld connected to each driver circuit... Figure 8 The two data fan-out lines Ld shown can be the two outermost fan-out lines along the first direction X. The first power supply line 200 and the second power supply line 300 are both at least partially located in the bezel area BB. The first power supply line 200 and the second power supply line 300 can be connected to bonding pads on the display substrate, respectively. The second power supply line 300 can surround the display area AA. Figure 8 The first power line VDD and the second power line VSS are omitted from the diagram.

[0125] like Figure 8 As shown, the orthographic projection of at least one of the first power supply line 200 and the second power supply line 300 on the substrate 10 can overlap with the orthographic projection of the third connection signal line L3 on the substrate 10. Since the first power supply line 200 and the second power supply line 300 transmit constant DC signals, they will not interfere with the drive signal transmitted by the third connection signal line L3, and the probability of the third connection signal line L3 overlapping with other traces can be reduced, which helps to ensure the stability of the drive signal transmitted by the third connection signal line L3.

[0126] In an exemplary embodiment, at least one third connection signal line L3 may be located on the side of at least one of the first power supply line 200 and the second power supply line 300 away from the substrate 10.

[0127] In an exemplary embodiment, the orthographic projections of the multiple data fan-out lines Ld on the substrate 10 and the orthographic projections of the multiple third connection signal lines L3 on the substrate 10 do not overlap. By ensuring that the orthographic projections of the third connection signal lines L3 and the multiple data fan-out lines Ld on the substrate 10 do not overlap, the influence of the data signals transmitted by the data fan-out lines Ld on the control signals transmitted by the third connection signal lines L3 can be avoided, thus ensuring the stability of the drive signals transmitted by the third connection signal lines L3.

[0128] In an exemplary embodiment, multiple third connection signal lines L3 can be routed along the extension direction of the first power supply line 200, with the first power supply line 200 spaced between the third connection signal lines L3 and the data leads Lj located below them in their extension direction. The first power supply line 200 can shield the data leads Lj from the influence of the third connection signal lines L3, ensuring the stability of the drive signals transmitted by the third connection signal lines L3.

[0129] In an exemplary embodiment, the orthographic projections of the multiple third connection signal lines L3 on the substrate 10 do not overlap with the orthographic projections of the multiple data leads Lj connected to the same central drive circuit on the substrate 10. This design prevents interference between drive signals and data signals emitted from the same central drive circuit, helping to ensure the accuracy of transmitted signals.

[0130] Figure 9 As an exemplary implementation Figure 8 The cross-sectional view along direction AA omits the remaining film layers of the display substrate. Figure 7As shown, the first power supply line 200 may include a first power supply section 210 and a second power supply section 220 connected to each other. The first power supply section 210 may be located in the first source-drain electrode layer, and the second power supply section 220 may be located in the second source-drain electrode layer. Multiple third connection signal lines L3 may be disposed in the third source-drain electrode layer. The orthographic projections of the multiple third connection signal lines L3 on the substrate 10 may overlap with the orthographic projections of the first power supply line 200 on the substrate 10.

[0131] In an exemplary embodiment, Figure 8 The cross-sectional view at the second power supply line 300 can also be referred to. Figure 9 As shown. The second power supply line 300 may include a third power supply section (not shown) and a fourth power supply section (not shown) connected to each other. The third power supply section may be located in the first source-drain electrode layer, and the fourth power supply section may be located in the second source-drain electrode layer. Multiple third connection signal lines L3 may be disposed in the third source-drain electrode layer. The orthographic projections of the multiple third connection signal lines L3 on the substrate 10 may overlap with the orthographic projections of the second power supply line 300 on the substrate 10.

[0132] In an exemplary embodiment, combined with Figure 6 As shown, multiple third connection signal lines L3 can also be disposed in at least one of the first touch conductive layer TMA and the second touch conductive layer TMB. By disposing the third connection signal lines L3 in the touch layer 15 at a greater distance from the substrate 10, the probability of interference with other signal lines is reduced, thereby ensuring the stability of the drive signal transmitted by the third connection signal lines L3.

[0133] In an exemplary embodiment, multiple first signal lines Lx1 can be disposed in the third source / drain electrode layer, or can be disposed in at least one of the first touch conductive layer TMA and the second touch conductive layer TMB. Multiple second signal lines Lx2 can be disposed in the third source / drain electrode layer, or can be disposed in at least one of the first touch conductive layer TMA and the second touch conductive layer TMB. Multiple first connection signal lines L1 can be disposed in the third source / drain electrode layer, or can be disposed in at least one of the first touch conductive layer TMA and the second touch conductive layer TMB. The film layers containing the first signal lines Lx1, second signal lines Lx2, and first connection signal lines L1 can be configured as needed, and each signal line can adopt a single-layer or stacked structure.

[0134] In an exemplary embodiment, the third connection signal line L3 includes a multilayer metal structure in the direction perpendicular to the substrate 10, or the third connection signal line L3 is a single-layer metal structure.

[0135] In an exemplary embodiment, the third connection signal line L3 can be made of one or more of the following metals: titanium, aluminum, copper, molybdenum, niobium, nickel, and their alloys. The structure can be a single-layer or multi-layer metal structure, such as titanium-aluminum-titanium (Ti / Al / Ti) multilayer structure, molybdenum-aluminum (Mo / Al) multilayer structure, molybdenum-aluminum-molybdenum (Mo / Al / Mo) multilayer structure, molybdenum-niobium-titanium (MoNb / Ti) multilayer structure, molybdenum-niobium-titanium-copper (MoNb / Ti / Cu) multilayer structure, molybdenum-niobium-copper (MoNb / Cu) multilayer structure, and molybdenum-niobium... The structure may include one or a combination of the following: titanium-copper (MTD / Cu) stacked structure, molybdenum-niobium-copper-molybdenum-niobium-titanium (MoNb / Cu / MTD) stacked structure, molybdenum-niobium-titanium-copper-molybdenum-niobium-titanium (MTD / Cu / MTD) stacked structure, molybdenum-titanium-copper-molybdenum-niobium-titanium (MoTi / Cu / MTD) stacked structure, molybdenum-titanium-copper-molybdenum-titanium (MoTi / Cu / MoTi) stacked structure, molybdenum-neodymium-copper stacked structure, MoNb-copper-MoNb stacked structure, and AlNb-molybdenum-AlNd stacked structure.

[0136] Figure 10 This is a top view of the first power supply line, the second power supply line, and the third connection signal line on the display substrate in another exemplary embodiment, omitting the rest of the display module structure. Figure 10 The diagram also simplifies the representation of the number of various signal lines. Figure 10 and Figure 8 The difference lies in the overlapping relationship between the third connection signal line L3, the first power supply line 200, and the second power supply line 300.

[0137] like Figure 10 As shown, the third connection signal line L3 can be routed along the extension direction of the second power supply line 300. Compared to the overlap area between the third connection signal line L3 and the first power supply line 200, the overlap area between the third connection signal line L3 and the second power supply line 300 can be larger. The function of the second power supply line 300 overlapping with the third connection signal line L3 can be referred to the aforementioned... Figure 8 The description of the first power supply line 200 in the previous section will not be repeated here. Figure 10 The sectional view along the AA direction can be referenced. Figure 9 As shown, it can be Figure 9 The first power supply unit 210 is considered as the third power supply unit, and the second power supply unit 220 is considered as the fourth power supply unit. Further details will not be provided here.

[0138] Figure 11 This is a top view of the first power supply line, the second power supply line, and the third connection signal line on the display substrate in another exemplary embodiment, omitting the rest of the display module structure. Figure 10The diagram also simplifies the representation of the number of various signal lines. Figure 11 and Figure 8 The difference lies in the structure of the first power supply line; the rest can be found in the previous section. Figure 8 The description will not be repeated here.

[0139] like Figure 11 As shown, the first power supply line 200 may include a plurality of first power supply units 201, which may be arranged sequentially along a first direction X. Each first power supply unit 201 may provide an electrical signal to the first power supply line VDD. The third connection signal line L3 may overlap with at least one of the plurality of first power supply units 201, and the third connection signal line L3 may overlap with the second power supply line 300. The functions of the first power supply units 201 and the second power supply line 300 that overlap with the third connection signal line L3 are as described above. Figure 8 The description of the first power supply line 200 in the text, Figure 11 The sectional view along the AA direction can be referenced. Figure 9 As shown, it will not be elaborated further here.

[0140] This disclosure also provides a display device, including the display module described in any of the above embodiments. The display device can be any product or component with display function, such as an OLED display, QLED display, LED display, projector, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc., and this disclosure is not limited thereto.

[0141] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A display module, characterized in that, include: The display substrate comprises a display substrate, a plurality of flexible circuit boards, and a control circuit board. The display substrate has a display area and a border area surrounding the display area. The border area includes a first driving circuit area and a second driving circuit area. The first driving circuit area is located on at least one of a first side and a second side of the display area, and the second driving circuit area is located on a third side of the display area. The first side and the second side are disposed opposite to each other. The first driving circuit region includes: a plurality of gate driving circuits; the second driving circuit region includes: a plurality of driving circuits arranged along a first direction; the plurality of driving circuits includes: an edge driving circuit and a plurality of center driving circuits; the edge driving circuit includes: a first edge driving circuit and a second edge driving circuit; the first edge driving circuit and the second edge driving circuit are respectively located at both ends of the plurality of center driving circuits along the first direction. At least one of the first edge driving circuit and the second edge driving circuit and at least one of the plurality of middle driving circuits are electrically connected to the plurality of gate driving circuits, respectively; the plurality of flexible circuit boards are respectively connected to the plurality of driving circuits and the control circuit board. The display substrate is provided with a first connection signal line and a second connection signal line, and the control circuit board is provided with a signal transmission line. At least one of the first edge driving circuit and the second edge driving circuit is connected to at least one of the plurality of gate driving circuits through the first connection signal line. At least one of the plurality of center driving circuits is connected to at least one of the plurality of gate driving circuits through the second connection signal line and the signal transmission line.

2. The display module according to claim 1, characterized in that, The plurality of flexible circuit boards include: a first edge flexible circuit board, a second edge flexible circuit board, and a plurality of central flexible circuit boards. The first edge flexible circuit board is electrically connected to the first edge driving circuit, the second edge flexible circuit board is electrically connected to the second edge driving circuit, and the plurality of central flexible circuit boards correspond one-to-one with and are electrically connected to the plurality of central driving circuits. The control circuit board is also provided with multiple timing transmission lines and timing controller chips, and at least one timing transmission line is electrically connected to the timing controller chip and the multiple flexible circuit boards respectively.

3. The display module according to claim 2, characterized in that, The display substrate further includes: a plurality of driving control signal lines located in the frame area, wherein at least one of the plurality of driving control signal lines extends at least partially along a second direction, and the first direction and the second direction intersect; The plurality of drive control signal lines are electrically connected to the plurality of gate drive circuits respectively; At least one of the first edge driving circuit and the second edge driving circuit, and at least one of the plurality of middle driving circuits, are respectively connected to at least one of the plurality of driving control signal lines.

4. The display module according to claim 3, characterized in that, The second connection signal line is located in the frame area and includes: multiple first signal lines and multiple second signal lines; The first signal line is connected to the target center drive circuit, the second signal line is electrically connected to at least one of the plurality of drive control signal lines, the first signal line is electrically connected to the second signal line through the signal transmission line, and the target center drive circuit is the center drive circuit connected to at least one of the plurality of drive control signal lines.

5. The display module according to claim 4, characterized in that, One end of the first signal line is connected to the target center driving circuit, and the other end of the first signal line is connected to the target center flexible circuit board. One end of the signal transmission line is connected to the target center flexible circuit board, and the other end of the signal transmission line is connected to at least one of the first edge flexible circuit board and the second edge flexible circuit board. One end of the second signal line is connected to at least one of the first edge flexible circuit board and the second edge flexible circuit board, and the other end of the second signal line is connected to at least one of the plurality of driving control signal lines. The target central flexible circuit board is the central flexible circuit board corresponding to the target central driving circuit.

6. The display module according to claim 5, characterized in that, At least a portion of at least one of the multiple signal transmission lines is located on the side of the flexible circuit board away from the display area.

7. The display module according to claim 5, characterized in that, The other end of the signal transmission line is connected to the first edge flexible circuit board and the second edge flexible circuit board, respectively.

8. The display module according to claim 5, characterized in that, The other end of the signal transmission line is connected to the flexible circuit board at the edge of the target. The target edge flexible circuit board refers to the edge flexible circuit board that is closest to the central flexible circuit board connected to the signal transmission line along the first direction.

9. The display module according to claim 5, characterized in that, At least a portion of at least one of the multiple drive control signal lines connected to the edge drive circuit is located on the side of at least one of the multiple drive control signal lines connected to the middle drive circuit that is closer to the display area.

10. The display module according to claim 3, characterized in that, The display substrate is also provided with multiple third connection signal lines located in the frame area; One end of the third connection signal line is connected to the target center driving circuit, and the other end of the third connection signal line is connected to at least one of the plurality of driving control signal lines. The target center driving circuit is the center driving circuit connected to at least one of the plurality of driving control signal lines.

11. The display module according to claim 10, characterized in that, At least a portion of at least one of the multiple drive control signal lines connected to the edge drive circuit is located on the side of at least one of the multiple drive control signal lines connected to the middle drive circuit that is away from the display area.

12. The display module according to any one of claims 4 to 11, characterized in that, The first connection signal line is located in the border area; One end of the first connection signal line is connected to the target edge driving circuit, and the other end of the first connection signal line is connected to at least one of the plurality of driving control signal lines, wherein the target edge driving circuit is an edge driving circuit connected to at least one of the plurality of driving control signal lines.

13. The display module according to claim 12, characterized in that, The display substrate further includes: a substrate and multiple columns of pixel driving circuits and multiple data signal lines disposed on the substrate in the display area and multiple data fan-out lines in the frame area, wherein the data signal lines and the data fan-out lines extend at least partially along the second direction; At least one data signal line is connected to at least one column of pixel driving circuits and at least one data fan-out line, and at least one data fan-out line is also connected to at least one driving circuit. When the display substrate is provided with multiple third connection signal lines, the orthographic projection of the third connection signal lines on the substrate does not overlap with the orthographic projection of the multiple data fan-out lines on the substrate.

14. The display module according to claim 13, characterized in that, The display substrate is also provided with a first power supply line and a second power supply line that are at least partially located in the frame area. The orthographic projections of at least one of the first power supply line and the second power supply line on the substrate and the orthographic projections of at least one of the third connection signal lines at least partially overlap.

15. The display module according to claim 14, characterized in that, The at least one third connection signal line is located on the side of at least one of the first power supply line and the second power supply line away from the substrate.

16. The display module according to claim 15, characterized in that, In a direction perpendicular to the display substrate, the display substrate further includes at least one gate metal layer and at least one source / drain metal layer sequentially disposed on the substrate; Wherein, the data signal line is located in one of the at least one source / drain metal layers, the data fan-out line is located in at least one of the at least one gate metal layers, at least one of the first power supply line and the second power supply line is located in at least one of the at least one source / drain metal layers, and the third connection signal line is located in at least one of the at least one source / drain metal layers.

17. The display module according to claim 16, characterized in that, The third connection signal line is located in the film layer that is furthest from the substrate in at least one source / drain metal layer.

18. The display module according to claim 15, characterized in that, In a direction perpendicular to the display substrate, the display substrate further includes at least one source / drain metal layer and a touch layer sequentially disposed on the substrate, the touch layer including a first touch conductive layer and a second touch conductive layer sequentially disposed in a direction away from the substrate; The third connection signal line is located in at least one of the first touch conductive layer and the second touch conductive layer.

19. The display module according to claim 16 or 18, characterized in that, In a direction perpendicular to the display substrate, the third connection signal line includes a multi-layer metal structure, or the third connection signal line is a single-layer metal structure.

20. The display module according to claim 3, characterized in that, The plurality of gate driving circuits in the first driving circuit region are arranged sequentially along the first direction; The display substrate includes two first driving circuit regions, which are respectively located on the first side and the second side of the display area; the display substrate has a symmetry line extending along the second direction, and a plurality of gate driving circuits in the two first driving circuit regions are arranged symmetrically with respect to the symmetry line axis.

21. The display module according to claim 20, characterized in that, Along the first direction, a plurality of drive circuits located on one side of the line of symmetry are configured to be connected to a plurality of drive control signal lines located on the same side of the line of symmetry; Along the first direction, a plurality of drive circuits located on the other side of the line of symmetry are configured to be connected to a plurality of drive control signal lines located on the same side of the line of symmetry.

22. A display device, characterized in that, Includes the display module as described in any one of claims 1 to 21.

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