A monolithic laser bar

Abstract

The application provides a chip-on-substrate serial laser bar, comprising a substrate, at least two semiconductor laser units arranged on the substrate, and a chip-on-substrate electrical interconnection structure, wherein each semiconductor laser unit comprises at least one semiconductor heterojunction stack structure for generating laser, and the stack structure comprises a P-type semiconductor layer and an N-type semiconductor layer; each semiconductor laser unit comprises a first electrode contact region arranged on the P-type semiconductor layer and a second electrode contact region arranged on the N-type semiconductor layer; and the chip-on-substrate electrical interconnection structure is electrically connected with the second electrode contact region of the semiconductor laser unit and the first electrode contact region of an adjacent semiconductor laser unit to form a serial circuit. In this way, by arranging multiple laser units in series on a single substrate through a chip-on-substrate interconnection structure, a basic structure for high-voltage and low-current operation of the device is established.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor laser technology, and in particular to an on-chip tandem laser bar. Background Technology

[0002] Edge-emitting lasers (EELs), especially high-power laser bars, play a crucial role in industrial processing, medical applications, scientific research, and optical communications. A typical laser bar consists of multiple independent light-emitting units (also called "chip units" or "emitting areas") arranged in parallel on the same bar. In terms of circuit structure, these light-emitting units are usually connected in parallel, meaning that the P-type electrodes of all light-emitting units are connected to a common positive terminal, and all N-type electrodes are connected to a common negative terminal.

[0003] This traditional parallel operating mode has inherent technical bottlenecks. First, as the number of light-emitting units increases, the equivalent resistance of the overall circuit decreases sharply. According to Ohm's law, to drive the entire bar to its rated optical output power, a power supply system capable of providing extremely high operating current (e.g., tens or even hundreds of amperes) but low operating voltage (typically only a few volts) is required. This poses a severe challenge to the design and manufacturing cost of the driving power supply, requiring the use of large-size, high-cost electronic components and complex current management circuits. Second, due to the unavoidable slight non-uniformities in epitaxial growth and chip manufacturing processes, the internal resistance, threshold current, and other electrical characteristics of each light-emitting unit will have slight differences. In parallel mode, current will preferentially flow to units with lower resistance, resulting in uneven current distribution among the light-emitting units. This non-uniformity not only makes the emitted light power inconsistent across different light-emitting areas, affecting the uniformity of the overall beam quality, but may also cause some units to fail prematurely due to current overload, thereby reducing the reliability and lifespan of the entire laser bar.

[0004] Therefore, the industry urgently needs a new type of laser bar structure to overcome the problems of low voltage, high current, and uneven current distribution caused by traditional parallel structures, thereby reducing the requirements for the driving power supply, simplifying system design, and improving the overall performance and reliability of the device. Utility Model Content

[0005] Therefore, it is necessary to provide an on-chip tandem laser bar to solve at least one of the above-mentioned technical problems.

[0006] In a first aspect, this application provides an on-chip tandem laser bar, comprising:

[0007] Substrate;

[0008] At least two semiconductor laser units are disposed on a substrate, each semiconductor laser unit comprising at least one semiconductor heterojunction stacked structure for generating laser light, the stacked structure comprising a P-type semiconductor layer and an N-type semiconductor layer;

[0009] Each semiconductor laser unit includes a first electrode contact region disposed on a P-type semiconductor layer and a second electrode contact region disposed on an N-type semiconductor layer;

[0010] In addition, an on-chip electrical interconnect structure is provided, which electrically connects the second electrode contact area of ​​a semiconductor laser unit and the first electrode contact area of ​​an adjacent semiconductor laser unit to form a series circuit.

[0011] Thus, by connecting multiple laser units in series on a single substrate using an on-chip interconnect structure, the basic architecture for high-voltage, low-current operation of the device is established.

[0012] In one possible implementation, the semiconductor laser unit includes a P-electrode and an N-electrode, with the P-electrode disposed in a first electrode contact region and the N-electrode disposed in a second electrode contact region. Thus, by explicitly specifying that the P and N electrodes are respectively disposed on corresponding P-type and N-type semiconductor contact regions, the physical ports for current injection are defined.

[0013] In one possible implementation, the substrate is an insulating substrate, the N-type semiconductor layer is formed on the substrate, and the P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate. The on-chip electrical interconnect structure electrically connects the N-electrode of one semiconductor laser unit and the P-electrode of another adjacent semiconductor laser unit to form a series circuit. Thus, by defining the stacked structure with the N-type layer below and the P-type layer above, and the connection method from the N-electrode to the P-electrode, a specific and mainstream physical layout for series implementation is defined.

[0014] In one possible implementation, the substrate is an insulating substrate, the P-type semiconductor layer is formed on the substrate, and the N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate. The on-chip electrical interconnect structure electrically connects the P-electrode of one semiconductor laser unit and the N-electrode of another adjacent semiconductor laser unit to form a series circuit. Thus, by defining the stacked structure with the P-type layer below and the N-type layer above, and the connection method from P-electrode to N-electrode, another specific and mainstream series implementation physical layout is defined.

[0015] In one possible implementation, the peripheral and top sides of the semiconductor laser unit are covered with an insulating layer. The top insulating layer has an opening corresponding to the first electrode contact area. The P electrode is electrically connected to the first electrode contact area of ​​the P-type semiconductor layer through this opening. The lateral dimension of the N-type semiconductor layer is larger than that of the P-type semiconductor layer. The portion of the N-type semiconductor layer not covered by the P-type semiconductor layer facing the P electrode forms the second electrode contact area, and the N electrode is disposed in the second electrode contact area. Thus, by providing an insulating cover layer with an opening, passivation protection of the laser unit surface is achieved, and precise electrical contact of the P electrode is ensured. By designing the N-type layer to be wider than the P-type layer, the N-type contact area is cleverly exposed on the top of the chip, thereby achieving coplanar fabrication of the P and N electrodes.

[0016] In one possible implementation, the peripheral and top sides of the semiconductor laser unit are covered with an insulating layer. The top insulating layer has an opening corresponding to the first electrode contact area. The N-electrode is electrically connected to the first electrode contact area of ​​the N-type semiconductor layer through this opening. The lateral dimension of the P-type semiconductor layer is larger than that of the N-type semiconductor layer. The portion of the P-type semiconductor layer not covered by the N-type semiconductor layer facing the N-electrode forms the second electrode contact area, and the P-electrode is disposed in the second electrode contact area. Thus, by providing an insulating cover layer with an opening, passivation protection of the laser unit surface is achieved, and precise electrical contact of the N-electrode is ensured. By designing the P-type layer to be wider than the N-type layer, the P-type contact area is cleverly exposed on the top of the chip, thereby achieving coplanar fabrication of the P and N electrodes.

[0017] In one possible implementation, the on-chip electrical interconnect structure is a metal conductive strip that bridges and electrically connects the second top electrode contact area of ​​one semiconductor laser unit to the first top electrode contact area of ​​an adjacent semiconductor laser unit. Thus, by concretizing the on-chip interconnect structure as a bridging metal conductive strip, a direct and reliable physical connection for series connection between units is defined.

[0018] In one possible implementation, the substrate is a conductive substrate or a semi-insulating substrate. The semiconductor laser unit includes a first semiconductor laser unit and a second semiconductor laser unit, which are disposed adjacent to each other. In the first semiconductor laser unit, an N-type semiconductor layer is formed on the substrate, and a P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate. In the second semiconductor laser unit, a P-type semiconductor layer is formed on the substrate, and an N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate. The on-chip electrical interconnect structure is the portion of the substrate located between the first semiconductor laser unit and the second semiconductor laser unit. The on-chip electrical interconnect structure electrically connects the N-electrode of the first semiconductor laser unit and the P-electrode of the second semiconductor laser unit to form a series circuit. Thus, by alternately integrating semiconductor laser units with opposite PN polarities on a conductive or semi-insulating substrate, and utilizing the substrate itself as a conductive path connecting the N pole of one unit to the P pole of an adjacent unit, there is no need to fabricate surface metal interconnect structures, thereby simplifying the chip manufacturing process and helping to achieve a flatter device surface, which is beneficial for subsequent packaging and wiring, thus proposing an innovative on-chip integration scheme.

[0019] In one possible implementation, the substrate is a conductive substrate or a semi-insulating substrate. The semiconductor laser unit includes a first semiconductor laser unit and a second semiconductor laser unit, which are disposed adjacent to each other. In the first semiconductor laser unit, a P-type semiconductor layer is formed on the substrate, and an N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate. In the second semiconductor laser unit, an N-type semiconductor layer is formed on the substrate, and a P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate. The on-chip electrical interconnect structure is the portion of the substrate located between the first semiconductor laser unit and the second semiconductor laser unit. The on-chip electrical interconnect structure electrically connects the P-electrode of the first semiconductor laser unit and the N-electrode of the second semiconductor laser unit to form a series circuit. Thus, by alternately integrating semiconductor laser units with opposite PN polarities on a conductive or semi-insulating substrate, and utilizing the substrate itself as a conductive path connecting the N pole of one unit to the P pole of an adjacent unit, there is no need to fabricate surface metal interconnect structures, thereby simplifying the chip manufacturing process and helping to achieve a flatter device surface, which is beneficial for subsequent packaging and wiring, thus proposing another innovative on-chip integration scheme.

[0020] In one possible implementation, an isolation slot is provided between two adjacent semiconductor laser units to electrically isolate them from each other. Thus, by providing a physical isolation slot between adjacent laser units, the electrical independence between each unit is effectively guaranteed and potential crosstalk is suppressed. Attached Figure Description

[0021] The accompanying drawings are for illustrative purposes only and should not be construed as limiting this patent; the same reference numerals are used for components with the same structure and function. Wherein:

[0022] Figure 1 This is a schematic diagram of the current flow direction of an on-chip tandem laser bar according to an embodiment of this application;

[0023] Figure 2 This is a schematic cross-sectional view of the structure of an on-chip tandem laser bar according to an embodiment of this application;

[0024] Figure 3 This is a schematic cross-sectional view of the structure of the on-chip tandem laser bar according to another embodiment of this application;

[0025] Explanation of reference numerals in the attached figures:

[0026] 1-On-chip tandem laser bar;

[0027] 100-substrate;

[0028] 200 - Semiconductor laser unit; 210 - Semiconductor heterojunction stacked structure;

[0029] 211-N type semiconductor layer; 211a-N contact layer; 211b-N confinement layer; 211c-N waveguide layer;

[0030] 212-P type semiconductor layer; 212a-P contact layer; 212b-P confinement layer; 212c-P waveguide layer;

[0031] 213 - Active Layer;

[0032] 220 - First electrode contact area; 230 - Second electrode contact area;

[0033] 300-P electrode; 400-N electrode;

[0034] 500-chip on-chip electrical interconnect structure;

[0035] 600 - Isolation Groove;

[0036] 700 - Insulation layer; 710 - Opening. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0038] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features.

[0039] In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more.

[0040] This application provides an on-chip tandem laser bar 1. The core idea is to form at least two (usually more) physically separate but electrically connected semiconductor laser units 200 on a single substrate 100 through semiconductor micro-nano fabrication processes.

[0041] Please see Figure 1 and Figure 2 The on-chip series laser bar 1 functions by allowing current to enter from the overall positive terminal, flow sequentially through the first semiconductor laser unit 200, the second semiconductor laser unit 200, and so on, until the last semiconductor laser unit 200, and finally exit from the overall negative terminal. This serial path ensures that the current flowing through each unit 200 is strictly consistent.

[0042] Structurally, the bar mainly includes: a substrate 100 as a base; a plurality of semiconductor laser units 200 disposed on the substrate 100; and an on-chip electrical interconnect structure 500 for realizing series connection between the units.

[0043] A. Substrate

[0044] The substrate 100 serves as the mechanical support foundation for the entire device, supporting all the semiconductor laser units 200 and interconnect structures 500. The choice of substrate 100 significantly impacts the device's electrical isolation, heat dissipation performance, and manufacturing cost. In different embodiments of this application, the substrate 100 may be an insulating substrate, a semi-insulating substrate, or a conductive substrate.

[0045] Insulating substrates: These substrates are excellent insulators themselves and are typically used to grow material systems with significant lattice mismatches with the substrate, such as nitride semiconductors. Examples include sapphire (Al₂O₃), silicon carbide (SiC), and aluminum nitride (AlN), but are not limited to these. The selection of an insulating substrate requires comprehensive consideration of multiple factors, including the lattice matching of the epitaxial material system, the heat dissipation requirements of the device, the operating wavelength, and manufacturing costs.

[0046] Semi-insulating substrates: These substrates are identical to the material system of the epitaxially grown functional layers, thus possessing perfect lattice matching. They enable the growth of epitaxial layers with extremely low defect density and extremely high quality, making them the preferred choice for high-performance lasers. Their "semi-insulating" characteristic is not intrinsic to the material but is achieved through precise control of doping or intrinsic defects during crystal growth. Examples include semi-insulating gallium arsenide (SI-GaAs) and semi-insulating indium phosphide (SI-InP), but they are not limited to these. The selection of a semi-insulating substrate requires a comprehensive consideration of the trade-offs between the device's electrical performance, heat dissipation requirements, manufacturing process complexity, and final cost.

[0047] Conductive substrate: This refers to a substrate material with inherently good electrical conductivity, typically achieved through heavy doping of semiconductor single-crystal materials. Using conductive substrates is a very common technique in semiconductor laser manufacturing, especially suitable for device structures requiring vertical conduction. Examples include N+ type gallium arsenide (N+GaAs) substrates, N+ type indium phosphide (N+InP) substrates, N-type silicon carbide (N-SiC) or N-type gallium nitride (N-GaN) substrates, N-SiC substrates, and N-GaN substrates, but not limited to these. The selection of a conductive substrate requires comprehensive consideration of multiple factors, including material system compatibility, electrical properties, thermal characteristics, mechanical strength, and economic cost. First and foremost, the substrate material must achieve a high degree of lattice matching with the semiconductor epitaxial layer to be grown on it. This is fundamental to ensuring low defect density and excellent crystal quality in the epitaxial film, directly determining the laser's internal quantum efficiency and reliability. Secondly, its electrical properties are crucial. The substrate itself must have sufficiently low resistivity to serve as an efficient common electrode, minimizing parasitic voltage drop and Joule heat loss caused by bulk resistance, thereby improving the overall electro-optical conversion efficiency of the device. Simultaneously, the thermal conductivity of the substrate is a key parameter determining the heat dissipation capability of the laser. Especially for high-power devices, substrates with high thermal conductivity (such as silicon carbide) can more effectively dissipate waste heat generated in the active region, thereby suppressing temperature rise, ensuring the stability of output power and wavelength, and extending the device's lifespan. Finally, a trade-off must be made between its mechanical properties to withstand complex manufacturing and packaging processes, and its ultimate market cost and availability. The final choice often involves finding an optimal balance between these interrelated and even mutually restrictive performance indicators and commercial feasibility to meet the comprehensive performance and cost requirements of specific application scenarios.

[0048] B. Semiconductor laser unit

[0049] Each semiconductor laser unit 200 is an independent photoelectric conversion device, the core of which is a semiconductor heterojunction stacked structure 210, which can generate laser through stimulated emission when an external positive bias voltage is applied.

[0050] like Figure 2 As shown, a typical semiconductor laser unit 200 has a semiconductor heterojunction stacked structure 210 formed by bottom-up epitaxial growth. This structure includes:

[0051] N-type semiconductor layer 211: typically includes a heavily doped N-contact layer 211a for forming ohmic contacts, an N-confinement layer 211b for confining carriers and optical fields, and an N-waveguide layer 211c. These layers are made of lattice-matched semiconductor materials, such as AlGaAs materials of different compositions in gallium arsenide systems.

[0052] Active layer 213: Located between N-type semiconductor layer 211 and P-type semiconductor layer 212, it is the core region for light generation. Active layer 213 typically employs a quantum well or quantum dot structure, such as an InGaAs / GaAs quantum well, to achieve high carrier recombination efficiency and low threshold current.

[0053] P-type semiconductor layer 212: Arranged symmetrically with N-type semiconductor layer 211, typically including a P-waveguide layer 212c, a P-type confinement layer 212b, and a heavily doped P+ contact layer 212a for forming an ohmic contact.

[0054] In the process of manufacturing the semiconductor laser unit 200, a core step is to precisely etch the complete epitaxial wafer into multiple physically independent mesa structures through photolithography and etching processes, and each mesa structure constitutes a laser unit 200. These units are physically and electrically separated from each other by isolation trenches 600 formed by etching.

[0055] To achieve the on-chip cascading proposed in this application, the etching process here is particularly critical. Its purpose is not only to isolate the individual units, but also to cleverly create the necessary structural foundation for the subsequent cascading electrical connections. Specifically, the etching process is subject to precise depth control. It must completely penetrate the top P-type semiconductor layer 212 and the middle active layer 213, and finally stop firmly on the underlying N-type semiconductor layer 211, especially on the surface of its highly doped N-contact layer 211a.

[0056] More importantly, through careful design of the photolithography mask, the patterned area defining the P-type semiconductor layer 212 is smaller in lateral dimension than the area defining the entire unit base. The direct result is that, after etching, each laser unit 200 exhibits a unique "two-tiered" morphology: a narrower upper platform composed of the P-type semiconductor layer 212 sits on a wider lower base composed of the N-type semiconductor layer 211.

[0057] This unique geometry successfully exposes two electrode contact areas of different polarities simultaneously on the top surface of the chip: the top surface of the narrower upper mesa naturally forms the first electrode contact area 220 for depositing the P electrode. Crucially, the wider top surfaces of the lower N-type substrate, exposed due to size differences around the upper mesa, form a "platform" or "narrow edge," which is the second electrode contact area 230 for fabricating the N electrode. In this way, the contact areas of the P and N electrodes are placed side-by-side on the same side of the chip, providing structural convenience for on-chip serial wiring across cells.

[0058] C. Electrode and on-chip electrical interconnect structure

[0059] Electrodes: At the first electrode contact region 220, metal is deposited by means of evaporation or sputtering to form a P electrode 300 (e.g., Ti / Pt / Au). At the second electrode contact region 230, metal is deposited to form an N electrode 400 (e.g., AuGe / Ni / Au).

[0060] On-chip electrical interconnect structure 500: This structure electrically connects the N-electrode 400 of the preceding laser unit to the P-electrode 300 of the next adjacent laser unit. Fabricating this structure is one of the key challenges, as it requires addressing the complex surface topography. It must smoothly descend from one mesa (the platform containing the N-electrode) to the bottom of the isolation trench and then ascend to another higher mesa (the top surface containing the P-electrode), demanding excellent step coverage in the metal deposition process. Therefore, special processes are often required, such as thick photoresist-assisted air-bridge technology or planarization techniques involving dielectric filling and rewiring, to achieve reliable cross-connections. By alternately and repeatedly fabricating this interconnect structure, a complete, serpentine series current path is constructed across the entire laser bar, laying the physical foundation for the high voltage, low current, and uniform emission characteristics of this application.

[0061] In a complete on-chip tandem laser bar, the current path is as follows: Figure 1 As indicated by the middle arrow. Assume the P-electrode 300 of the leftmost unit in the bar is the overall positive electrode, and the N-electrode 400 of the rightmost unit is the overall negative electrode. When a driving voltage is applied by an external power supply, current is injected from the P-electrode 300 of the first unit at the leftmost end, flowing longitudinally through its P-type semiconductor layer 212, active layer 213, and N-type semiconductor layer 211, reaching its N-electrode 400. During this process, the unit is forward biased and emits light. Current flows into the second unit through the on-chip electrical interconnect structure 500 connecting the N-electrode 400 of the first unit and the P-electrode 300 of the second unit. The current repeats the same process in the second unit as in the first unit, and then flows into the third unit through the next interconnect structure. This process is repeated sequentially in all units until the current flows out from the N-electrode 400 of the last unit, returning to the negative terminal of the power supply. Since all units are on the same current path, the current flowing through each unit is strictly equal, and the operating voltage is the sum of the voltage drops of all units, achieving a high-voltage, low-current, uniform light emission operating mode.

[0062] The bar strip in this embodiment is manufactured through the following process steps:

[0063] Substrate selection: A (100) oriented semi-insulating gallium arsenide (SI-GaAs) substrate was selected as substrate 100. This substrate has a resistivity greater than 10^7 Ω·cm at room temperature, providing an excellent electrical isolation basis for the device.

[0064] Epitaxial growth: A semiconductor heterojunction stacked structure 210 was sequentially grown on substrate 100 using metal-organic chemical vapor deposition (MOCVD). The specific layer structure from bottom to top is as follows:

[0065] A 200 nm thick N-type doped (Si, 2 x 10^18 cm^-3) GaAs was used as the N-contact layer 211a.

[0066] A 1.5 μm thick N-type doped (Si, 1 x 10^18 cm^-3) Al0.3Ga0.7As was used as the N-confinement layer 211b.

[0067] A 200nm thick, lightly doped Al0.15Ga0.85As layer was used as the N-waveguide layer 211c.

[0068] An active layer 213 comprising one or more In0.2Ga0.8As / GaAs strained quantum wells with a total thickness of approximately 15 nm.

[0069] A 200nm thick, lightly doped Al0.15Ga0.85As layer was used as the P-waveguide layer 212c.

[0070] A 1.5 μm thick P-type doped (C, 1 x 10^18 cm^-3) Al0.3Ga0.7As was used as the P-confined layer 212b.

[0071] A 300 nm thick heavily doped P+ (C, >1 x 10^19 cm^-3) GaAs was used as the P-contact layer 212a.

[0072] Using standard photolithography, a striped photoresist pattern is formed on the P-contact layer 212a, defining the positions of all semiconductor laser units 200 and the shape of the P-layer mesa.

[0073] Etching: Chlorine-based inductively coupled plasma (ICP) dry etching is employed. The etching depth is precisely controlled, allowing the etching to penetrate the P-contact layer 212a, P-confining layer 212b, P-waveguide layer 212c, active layer 213, and N-waveguide layer 211c, finally stopping at the surface of either the N-confining layer 211b or the N-contact layer 211a. This forms multiple physically isolated Mesa structures, namely semiconductor laser units 200. Isolation trenches 600 are formed between adjacent units. The width of the P-layer mesa (e.g., 90 μm) is designed in the photolithographic mask to be smaller than the reserved width of the N-layer region (e.g., 120 μm). After etching, a surface of the N-contact layer 211a with a width of approximately 30 μm is exposed on one side of each P-layer mesa; this surface is the second electrode contact region 230. The top surface of the P-layer mesa is the first electrode contact region 220.

[0074] Insulation and passivation: A 200 nm thick silicon nitride (SiNx) layer is deposited as an insulating layer 700 on the entire wafer surface using plasma-enhanced chemical vapor deposition (PECVD). This insulating layer covers the top and sidewalls of the P-layer mesa, as well as the bottom and sidewalls of the isolation trench 600, serving to passivate the exposed semiconductor surface and prevent leakage.

[0075] Electrode window fabrication: Photolithography is performed again to form window patterns on the insulating layer 700 above the first electrode contact area 220 and the second electrode contact area 230 where electrodes are to be fabricated. SiNx within the windows is removed by reactive ion etching (RIE), exposing the underlying P-contact layer 212a and N-contact layer 211a. These openings 710 provide channels for subsequent contact between the metal electrode and the semiconductor layer.

[0076] Fabrication of P electrode: Using electron beam evaporation and lift-off processes, a Ti / Pt / Au (50nm / 50nm / 300nm) multilayer metal is deposited at the opening 710 of the first electrode contact region 220 to form P electrode 300.

[0077] Fabrication of the N electrode: Using a similar process, an AuGe / Ni / Au multilayer metal (e.g., 100nm / 30nm / 300nm) is deposited at the opening 710 of the second electrode contact region 230 to form the N electrode 400. After deposition, a rapid thermal annealing (RTA) treatment is performed to ensure good ohmic contact between the AuGe alloy and the N contact layer 211a.

[0078] Fabrication of the interconnect structure: In this embodiment, a dielectric-supported interconnect method is used to construct the on-chip electrical interconnect structure 500. After forming the P-electrode 300 and N-electrode 400, and after the entire chip surface is covered and passivated by an insulating layer 700 (e.g., silicon nitride), the interconnect structure is fabricated through subsequent photolithography and metal deposition processes. The specific steps are as follows: First, a layer of on-chip electrical interconnect structure 500 with sufficient thickness (e.g., 2-3 μm) is deposited through photolithography and lift-off or etching processes. Gold (Au), which has high electrical conductivity and chemical stability, is typically chosen. This metal layer is precisely patterned to form a wide metal conductive strip, which is the on-chip electrical interconnect structure 500. The path of this metal conductive strip is carefully designed to achieve a series function: it needs to physically cross the isolation trench 600 that separates the two semiconductor laser units 200. One end of it precisely covers the N-electrode 400 of the laser unit and forms a low-impedance electrical connection with it through the opening 710 below the electrode. At its other end, it extends to the top of the adjacent unit and covers the P electrode 300, forming a robust electrical connection. Because this interconnect structure needs to cover the significant height difference (step) from the platform where the N electrode 400 is located to the top of the mesa where the P electrode 300 is located, a high degree of step coverage is required in the metal deposition process to ensure that the metal does not thin or break at the step. The attached diagram clearly shows that the insulating layer 700 provides full physical support and electrical insulation for this bridging metal conductive strip 500, ensuring the mechanical strength and reliability of the structure and avoiding unnecessary electrical short circuits with the underlying semiconductor region. This dielectric-supported structure has good mechanical stability and heat dissipation performance. Ultimately, it forms as shown in the diagram. Figure 3 The structure shown is such that the P electrode 300 of the first unit and the N electrode 400 of the last unit of the entire bar bar serve as the overall input and output terminals of the bar bar.

[0079] In some embodiments, after epitaxial growth is completed, deep mesa etching may not be performed; instead, the partition can be achieved using the following process:

[0080] Shallow mesa etching: Only one shallow etching is performed to expose the N contact layer 211a as the second electrode contact area 230, and its depth is much smaller than that of the first embodiment.

[0081] Ion implantation: After defining the cell regions, photoresist or metal is used as a mask to protect the area of ​​each semiconductor laser cell 200. High-energy proton (H+) or oxygen ion (O+) implantation is performed on the exposed areas, i.e., the areas between cells. These implanted ions generate numerous defects and deep-level traps in the semiconductor lattice, significantly increasing the resistivity of this region (ion-implanted isolation region), making it semi-insulating, thereby achieving lateral electrical isolation between cells.

[0082] Subsequent processes: The subsequent processes of insulating layer deposition, electrode window opening, electrode fabrication, and interconnect structure fabrication are similar to those in the first or second embodiment. The metal conductive strip spans directly over the flat ion-implanted isolation region.

[0083] The advantage of this approach is that it can achieve a flatter chip surface, which is beneficial for subsequent photolithography and metal wiring processes and reduces the risk of open circuits that may be caused by step coverage issues.

[0084] Please see Figure 3 This embodiment demonstrates how to achieve series connection using a conductive substrate. In this embodiment, two adjacent semiconductor laser units have opposite PN layer stacking orders on the same conductive substrate. For example, the first semiconductor laser unit has a conventional "P layer on top, N layer on bottom" structure, while the adjacent second semiconductor laser unit has an inverted "N layer on top, P layer on bottom" structure. Since the substrate is conductive, after the current flows out of the bottom N layer of the first unit, it can directly enter the substrate, travel laterally a short distance, and then be injected into the bottom P layer of the second unit from below, thus cleverly forming a series connection of "N pole - substrate - P pole" without any surface metal interconnects.

[0085] For example, to achieve epitaxial structures with two different growth sequences, a selective area epitaxy (SAE) process can be used. The process steps are as follows:

[0086] Step 1: Substrate Selection and Preparation

[0087] An N-type doped gallium arsenide (n-GaAs) substrate with good conductivity is selected as the conductive substrate. This substrate can simultaneously serve as mechanical support, common electrode, and internal interconnect. A thin dielectric material mask, such as silicon nitride (SiNx), is deposited on the substrate surface using methods such as plasma-enhanced chemical vapor deposition (PECVD).

[0088] Step 2: First selective epitaxy (growth of type I units)

[0089] Windows are created on a SiNx mask using standard photolithography and reactive ion etching (RIE) techniques to expose the surface of the underlying substrate. These windows correspond to the regions where all the first semiconductor laser units (e.g., units 1, 3, 5...) will be grown. The processed wafer is then returned to a metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) apparatus. Since semiconductor materials only nucleate and grow on the exposed substrate surface and not on the SiNx mask, selective epitaxy is possible. Within the windows, the structures of the first semiconductor laser units are epitaxially grown sequentially: first an N-type semiconductor layer (e.g., N-AlGaAs), then the active layer, and finally a P-type semiconductor layer (e.g., P-AlGaAs).

[0090] Step 3: Second selective epitaxy (growth of type II units)

[0091] After the first epitaxy, the SiNx mask on the surface is removed by chemical etching or other methods. A new SiNx mask is then deposited over the entire wafer surface. New windows are then created on the mask through photolithography and etching. This time, the windows are positioned to correspond to the areas where all the second semiconductor laser units (e.g., units 2, 4, 6...) will be grown. The wafer is then fed back into the epitaxial wafer. Within these new windows, the structures of the second type of units are epitaxially grown sequentially, in the exact reverse order of the first type: first the P-type semiconductor layer, then the active layer, and finally the N-type semiconductor layer.

[0092] Step 4: Unit Definition and Electrode Fabrication

[0093] Through the two-step selective epitaxy process described above, two laser units with opposite polarities have been fabricated side-by-side on the substrate. At this point, a shallow mesa etching is required to clearly define the boundaries of each unit and improve electrical isolation.

[0094] For the first semiconductor laser unit (P layer on top): a P electrode is fabricated on the top P-type semiconductor layer. Its N electrode is actually the conductive substrate that is in direct contact with its bottom N-type layer.

[0095] For the second semiconductor laser unit (N layer on top): an N electrode is fabricated on the top N-type semiconductor layer. Its P electrode is a conductive substrate that is in direct contact with the bottom P-type layer.

[0096] Although this approach is more complex, it has advantages in certain applications that require the use of a substrate as a heat sink or for specific electrical connections.

[0097] Compared with the parallel laser bar in the prior art, the technical solution of this application brings significant progress and beneficial effects:

[0098] 1. A fundamental shift in operating mode has been achieved: the traditional high-current, low-voltage operating mode has been transformed into a low-current, high-voltage mode. This significantly reduces the requirements for the power supply drive system, making its design simpler, cheaper, and smaller.

[0099] 2. Provides perfect current uniformity: The series structure physically ensures that the current flowing through each light-emitting unit is completely equal, completely solving the problem of uneven current distribution caused by unit differences in the parallel structure. This makes the power, spectrum, and aging rate of all light-emitting points on the bar highly consistent, significantly improving the uniformity of beam quality and the overall reliability of the device.

[0100] 3. Improved system efficiency: Due to the significant reduction in operating current, I caused by line resistance and contact resistance is reduced. 2 The power loss of R is significantly reduced, thereby improving the overall conversion efficiency from electricity to light.

[0101] 4. High design flexibility and scalability: By adding or removing the number of series units on the chip, laser bars with different operating voltages and output power levels can be easily customized to meet diverse application requirements without redesigning complex power supply systems.

[0102] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims. The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A bar for an on-chip tandem laser, characterized in that, include: Substrate; At least two semiconductor laser units are disposed on the substrate, each semiconductor laser unit comprising at least one semiconductor heterojunction stacked structure for generating laser light, the stacked structure comprising a P-type semiconductor layer and an N-type semiconductor layer; Each of the semiconductor laser units includes a first electrode contact region disposed on the P-type semiconductor layer and a second electrode contact region disposed on the N-type semiconductor layer; In addition, an on-chip electrical interconnect structure is provided, wherein the on-chip electrical interconnect structure electrically connects the second electrode contact area of ​​the semiconductor laser unit and the first electrode contact area of ​​an adjacent semiconductor laser unit to form a series circuit.

2. The on-chip tandem laser bar according to claim 1, characterized in that, The semiconductor laser unit includes a P electrode and an N electrode, wherein the P electrode is disposed in the first electrode contact area and the N electrode is disposed in the second electrode contact area.

3. The on-chip tandem laser bar according to claim 2, characterized in that, The substrate is an insulating substrate, the N-type semiconductor layer is formed on the substrate, the P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate, and the on-chip electrical interconnect structure electrically connects the N electrode of the semiconductor laser unit and the P electrode of another adjacent semiconductor laser unit to form a series circuit.

4. The on-chip tandem laser bar according to claim 2, characterized in that, The substrate is an insulating substrate, the P-type semiconductor layer is formed on the substrate, the N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate, and the on-chip electrical interconnect structure electrically connects the P electrode of the semiconductor laser unit and the N electrode of another adjacent semiconductor laser unit to form a series circuit.

5. The on-chip tandem laser bar according to claim 3, characterized in that, The semiconductor laser unit is covered with an insulating layer on its periphery and top. The top insulating layer has an opening corresponding to the first electrode contact area. The P electrode is electrically connected to the first electrode contact area of ​​the P-type semiconductor layer through the opening. The lateral dimension of the N-type semiconductor layer is larger than that of the P-type semiconductor layer. The surface of the N-type semiconductor layer not covered by the P-type semiconductor layer facing the P electrode forms the second electrode contact area. The N electrode is disposed in the second electrode contact area.

6. The on-chip tandem laser bar according to claim 4, characterized in that, The semiconductor laser unit is covered with an insulating layer on its periphery and top. The top insulating layer has an opening corresponding to the first electrode contact area. The N electrode is electrically connected to the first electrode contact area of ​​the N-type semiconductor layer through the opening. The lateral dimension of the P-type semiconductor layer is larger than that of the N-type semiconductor layer. The surface of the P-type semiconductor layer not covered by the N-type semiconductor layer facing the N electrode constitutes the second electrode contact area. The P electrode is disposed in the second electrode contact area.

7. The on-chip tandem laser bar according to claim 1, characterized in that, The on-chip electrical interconnect structure is a metal conductive strip, which bridges and electrically connects the second top electrode contact area of ​​one of the semiconductor laser units and the first top electrode contact area of ​​another adjacent semiconductor laser unit.

8. The on-chip tandem laser bar according to claim 2, characterized in that, The substrate is a conductive substrate or a semi-insulating substrate. The semiconductor laser unit includes a first semiconductor laser unit and a second semiconductor laser unit, which are arranged adjacent to each other. In the first semiconductor laser unit, an N-type semiconductor layer is formed on the substrate, and a P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate. In the second semiconductor laser unit, a P-type semiconductor layer is formed on the substrate, and an N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate. The on-chip electrical interconnect structure is the portion of the substrate located between the first semiconductor laser unit and the second semiconductor laser unit. The on-chip electrical interconnect structure electrically connects the N-electrode of the first semiconductor laser unit and the P-electrode of the second semiconductor laser unit to form a series circuit.

9. The on-chip tandem laser bar according to claim 8, characterized in that, The substrate is a conductive substrate or a semi-insulating substrate. The semiconductor laser unit includes a first semiconductor laser unit and a second semiconductor laser unit, which are arranged adjacent to each other. In the first semiconductor laser unit, a P-type semiconductor layer is formed on the substrate, and an N-type semiconductor layer is formed on the P-type semiconductor layer in a direction away from the substrate. In the second semiconductor laser unit, an N-type semiconductor layer is formed on the substrate, and a P-type semiconductor layer is formed on the N-type semiconductor layer in a direction away from the substrate. The on-chip electrical interconnect structure is the portion of the substrate located between the first semiconductor laser unit and the second semiconductor laser unit. The on-chip electrical interconnect structure electrically connects the P-electrode of the first semiconductor laser unit and the N-electrode of the second semiconductor laser unit to form a series circuit.

10. The on-chip tandem laser bar according to claim 1, characterized in that, An isolation groove is provided between two adjacent semiconductor laser units to electrically isolate the adjacent semiconductor laser units from each other.

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