Class-d audio power amplifier pulse width modulation circuit
Patent Information
- Application Number
- CN202522540963.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-29
- Publication Date
- 2026-11-03
- Estimated Expiration
- 2035-11-29
AI Technical Summary
In existing Class D audio power amplifiers, two LC filters or ferrite bead filters are required in two-channel or multi-channel systems to filter out high-frequency carrier components, resulting in high system cost and large space occupation, which is not conducive to the miniaturization and low-cost design of the equipment.
A Class D audio power amplifier pulse width modulation circuit is adopted. Through the OUTP generation logic module and the OUTN generation logic module, only one filter is needed to meet the signal filtering requirements. The circuit includes a PWM_P conversion module, a PWM_N conversion module, an OUTP generation logic module, and an OUTN generation logic module. By using a combination of inverters and logic gates, the number of external inductors or ferrite beads at the OUTP terminal is reduced.
It reduces the number and cost of filters, saves board space, is suitable for medium and high power applications, improves the stability and compatibility of signal output, supports digital/analog audio input, and has a wide range of applications.
Smart Images
Figure CN224935651U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the technical field of analog audio input or digital audio input Class D audio power amplifier chips, specifically relating to a Class D audio power amplifier pulse width modulation circuit. Background Technology
[0002] In existing Class D audio power amplifier technologies, PWM modulation architectures mainly include four-state modulation, three-state modulation, and quasi-three-state modulation. Under these existing modulation architectures, both the audio differential pulse output signals OUTP and OUTN contain high-frequency carrier components (typically between 300kHz and 3MHz). To avoid interference from the high-frequency carrier and to suppress high-frequency switching noise and electromagnetic radiation, two LC filters or ferrite bead filters are required at the positive and negative terminals in front of each channel's speaker to filter out the high-frequency carrier components before the signal is input to the speaker.
[0003] However, in dual-channel or multi-channel Class D audio amplifier systems, especially in medium to high power applications, the configuration of two LC filters or ferrite bead filters leads to higher system costs and occupies a large amount of board space, which is not conducive to miniaturization and low-cost design. Therefore, there is an urgent need for a PWM modulation scheme that can reduce the number of filters, lower costs, and save space. Utility Model Content
[0004] The main purpose of this invention is to provide a pulse width modulation circuit for Class D audio power amplifiers, which can meet the signal filtering requirements with only one filter, thereby saving the cost of inductors or ferrite beads and reducing the board space occupied. It is especially suitable for dual-channel, multi-channel or medium-to-high power Class D audio power amplifier systems.
[0005] To achieve the above objectives, this utility model provides a Class D audio power amplifier pulse width modulation circuit, including a PWM_P conversion module, a PWM_N conversion module, an OUTP generation logic module, and an OUTN generation logic module, wherein: The input terminal of the PWM_P conversion module receives the differential signal PWM_P and the output terminal outputs the signal PWMO_P to the input terminal of the OUTP generation logic module. The input terminal of the PWM_N conversion module receives the differential signal PWM_N and the output terminal outputs the signal PWMO_N to the input terminal of the OUTN generation logic module. The OUTP generation logic module includes NOR gate L7 and NOR gate L8 (forming an RS flip-flop). The first input terminal of NOR gate L7 is connected to the signal PWMO_P. The second input terminal of NOR gate L7 is connected to the output terminal of NOR gate L8, and the output terminal of NOR gate L7 is connected to the first input terminal of NOR gate L8. The output terminal of NOR gate L8 outputs the signal OUT_P. The OUTN generation logic module includes NAND gate L9, OR gate L10, and AND gate L11. The signal PWMO_N is connected to the second input terminal of NAND gate L8 and the second input terminal of OR gate L10, respectively. The first input terminal of OR gate L10 and the first input terminal of NAND gate L9 are both connected to the output terminal of NAND gate L8. The second input terminal of NAND gate L9 is connected to the signal PWMO_P. The output terminal of NAND gate L9 is connected to the first input terminal of AND gate L11, and the output terminal of OR gate L10 is connected to the second input terminal of AND gate L11. The output terminal of AND gate L11 outputs the signal OUT_N.
[0006] As a further preferred embodiment of the above technical solution, the PWM_P conversion module includes an inverter L1, an inverter L2, and an AND gate L3. The input terminal of the inverter L1 receives the differential signal PWM_P, and the output terminal of the inverter L1 is connected to the input terminal of the inverter L2. The output terminal of the inverter L2 is connected to the first input terminal of the AND gate L3. The PWM_N conversion module includes an inverter L4, an inverter L5, and an AND gate L6. The input terminal of the inverter L4 receives the differential signal PWM_N, and the output terminal of the inverter L4 is connected to the input terminal of the inverter L5. The output terminal of the inverter L5 is connected to the first input terminal of the AND gate L6. The output of inverter L1 is also connected to the second input of AND gate L6, and the output of inverter L4 is also connected to the second input of AND gate L3.
[0007] As a further preferred technical solution to the above technical solution, it also includes an inverter L12, wherein the input terminal of the inverter L12 and the third input terminal of the NOR gate L8 are both input with RESET signals, and the output terminal of the inverter L12 is connected to the third input terminal of the AND gate L11.
[0008] As a further preferred technical solution of the above technical solution, the signal OUT_P is output as signal OUTP through the driver and power transistor U7, and the signal OUT_N is output as signal OUTN through the driver and power transistor U8.
[0009] As a further preferred technical solution to the above technical solution, the OUTP generation logic module further includes an XOR gate, which is used to erase the 11-level states of the signals PWMO_P and PWMO_N.
[0010] The beneficial effects of this utility model are as follows: 1. Cost reduction: By eliminating the LC filter or ferrite bead filter at the OUTP end, the cost savings of inductors / ferrite beads are significant in dual-channel and multi-channel systems, especially suitable for medium and high power applications.
[0011] 2. Space saving: Reducing the board space occupied by a filter facilitates the miniaturization of audio equipment and improves product integration.
[0012] 3. Performance optimization: By increasing the operating frequency of OUTN, the size of the external inductor of OUTN can be reduced, further compressing space; at the same time, the circuit structure of adding XOR gates can avoid the hidden dangers of level transition state and ensure the stability of signal output.
[0013] 4. Strong compatibility: It adapts to digital / analog audio input, supports various load architectures and logic timing designs, has a wide range of applications, and is easy to integrate into different types of Class D audio power amplifier chips. Attached Figure Description
[0014] Figure 1 Here is a schematic diagram of an existing four-state modulation waveform; Figure 2 This is a schematic diagram of an existing tri-state modulation waveform; Figure 3 This is a schematic diagram of the modulation waveform of the digital audio input (amplitude zero, OUTP=1) of this utility model. Figure 4 This is a schematic diagram of the modulation waveform of the digital audio input (amplitude is zero, OUTP=0) of this utility model; Figure 5 This is a schematic diagram of the analog audio input waveform based on four-state modulation according to this utility model; Figure 6 This is a schematic diagram of the analog audio input waveform based on tri-state modulation according to this utility model; Figure 7 This is a schematic diagram of the structure of the existing technology that requires two LC / magnetic bead filters; Figure 8 This is a schematic diagram of the structure of this utility model, which requires only one LC / magnetic bead filter (OUTN end); Figure 9 This is a schematic diagram of one of the analog Class D audio power amplifier PWM modulation structures of this utility model.
[0015] Figure 10 This is a schematic diagram of the second analog Class D audio power amplifier PWM modulation structure of this utility model. Detailed Implementation
[0016] The following description is intended to disclose the present invention so that those skilled in the art can implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the present invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.
[0017] This utility model discloses a pulse width modulation circuit for a Class D audio power amplifier. The specific embodiments of the utility model are further described below with reference to preferred embodiments.
[0018] In the embodiments of this utility model, those skilled in the art will note that the drivers and power transistors involved in this utility model can be considered as prior art.
[0019] Preferred embodiment.
[0020] Under all existing PWM modulation architectures, such as Figure 1-2 As shown, both the audio differential pulse output signals OUTP and OUTN contain high-frequency carrier components. Two LC filters or ferrite bead filters need to be configured in front of the speaker to filter out these high-frequency carrier components before the signals can be input to the speaker. Figure 7 As shown.
[0021] Figure 3-6 This utility model presents a PWM pulse width modulation scheme and its output waveform diagram. The overall design scheme is as follows: when the amplitude after differential audio output is positive, OUTP=1 (high level); when it is negative, OUTP=0 (low level). Furthermore, when OUTP=1, (OUTN duty cycle) = 1 - (required output duty cycle); when OUTP=0, (OUTN duty cycle) = (required output duty cycle). The resulting differential value (OUTP-OUTN) is the audio output pulse waveform. If the system is a digital audio input Class D amplifier, OUTP=1 can be designed when the audio input amplitude is zero. Figure 3 As shown, or designed with OUTP=0 as... Figure 4 As shown; if the system is an analog audio input Class D power amplifier, design OUTP=1 when the audio differential output pulse is positive, and design OUTP=0 when the audio differential output pulse is negative. Figure 5 The modulation scheme is based on four-state modulation, i.e. Figure 1 Design, Figure 6 The modulation scheme is based on tri-state modulation, i.e. Figure 2 To carry out the design.
[0022] Since the pulse frequency of the OUTP is approximately equal to the frequency at which the positive and negative amplitudes of the audio input alternate, meaning the OUTP frequency is within the audio range of 20~20kHz and does not include the high-frequency carrier frequency (typically 300kHz~3MHz), this design eliminates the need for an LC filter to remove high-frequency signal components at the OUTP output. Therefore, only a small-value filter capacitor needs to be connected to the OUTP output. Figure 8 As shown.
[0023] This utility model's PWM modulation scheme saves on external inductors or ferrite beads at the OUTP terminal, reducing system application costs and board space. By appropriately increasing the OUTN operating frequency (i.e., the PWM modulation frequency or sawtooth wave operating frequency), such as to 500kHz or even 3MHz, the inductance value and size of the external inductor at OUTN can be further reduced.
[0024] like Figure 9 As shown, this utility model discloses a pulse width modulation circuit for a Class D audio power amplifier, including a PWM_P conversion module, a PWM_N conversion module, an OUTP generation logic module, and an OUTN generation logic module, wherein: The input terminal of the PWM_P conversion module receives the differential signal PWM_P and the output terminal outputs the signal PWMO_P to the input terminal of the OUTP generation logic module. The input terminal of the PWM_N conversion module receives the differential signal PWM_N and the output terminal outputs the signal PWMO_N to the input terminal of the OUTN generation logic module. The OUTP generation logic module includes NOR gate L7 and NOR gate L8 (forming an RS flip-flop). The first input terminal of NOR gate L7 is connected to the signal PWMO_P. The second input terminal of NOR gate L7 is connected to the output terminal of NOR gate L8, and the output terminal of NOR gate L7 is connected to the first input terminal of NOR gate L8. The output terminal of NOR gate L8 outputs the signal OUT_P. The OUTN generation logic module includes NAND gate L9, OR gate L10, and AND gate L11. The signal PWMO_N is connected to the second input terminal of NAND gate L8 and the second input terminal of OR gate L10, respectively. The first input terminal of OR gate L10 and the first input terminal of NAND gate L9 are both connected to the output terminal of NAND gate L8. The second input terminal of NAND gate L9 is connected to the signal PWMO_P. The output terminal of NAND gate L9 is connected to the first input terminal of AND gate L11, and the output terminal of OR gate L10 is connected to the second input terminal of AND gate L11. The output terminal of AND gate L11 outputs the signal OUT_N.
[0025] Specifically, the PWM_P conversion module includes an inverter L1, an inverter L2, and an AND gate L3. The input terminal of the inverter L1 receives the differential signal PWM_P, and the output terminal of the inverter L1 is connected to the input terminal of the inverter L2. The output terminal of the inverter L2 is connected to the first input terminal of the AND gate L3. The PWM_N conversion module includes an inverter L4, an inverter L5, and an AND gate L6. The input terminal of the inverter L4 receives the differential signal PWM_N, and the output terminal of the inverter L4 is connected to the input terminal of the inverter L5. The output terminal of the inverter L5 is connected to the first input terminal of the AND gate L6. The output of inverter L1 is also connected to the second input of AND gate L6, and the output of inverter L4 is also connected to the second input of AND gate L3.
[0026] More specifically, it also includes an inverter L12, the input of which and the third input of the NOR gate L8 are both input with a RESET signal, and the output of the inverter L12 is connected to the third input of the AND gate L11.
[0027] Furthermore, the signal OUT_P is output as signal OUTP through the driver and power transistor U7, and the signal OUT_N is output as signal OUTN through the driver and power transistor U8.
[0028] In another embodiment, such as Figure 10 As shown, the OUTP generation logic module also includes an XOR gate L71, which is used to erase the 11-level states of the signals PWMO_P and PWMO_N. Figure 9 The PWM-to-pure tri-state logic circuit requires appropriate device timing to meet operational requirements. If the timing design is inappropriate, when the inputs simultaneously switch from level 11 to level 00, the outputs PWMO_P and PWMO_N may experience an undesirable level 11 transition state within a very short time, causing the subsequent OUTP generation logic to also generate an incorrect narrow pulse level signal. To avoid this potential problem, a second implementation structure is designed, see... Figure 10 . Figure 10 The OUTP generation logic circuit in the circuit uses an additional XOR gate to erase the possible 11-level states of its input signals PWMO_P and PWMO_N, thus eliminating this potential problem.
[0029] Regarding this utility model: Taking a Class D amplifier with analog audio input as an example, Figure 9 It is one of the system implementation structures, suitable for four-state or tri-state PWM pulse width modulation architectures.
[0030] After the audio signal is compared with the sawtooth wave (RAMP) signal by comparators U5 / U6, four-state or tri-state-like differential output signals PWM_P and PWM_N are generated respectively.
[0031] Figure 9 The function of the PWM to pure tri-state logic circuit is to convert the original four-state signals PWM_P and PWM_N into pure tri-state signals PWMO_P and PWMO_N. Specifically, it converts the PWM "11" level to the "00" level, so that the output becomes a pure tri-state PWM signal (i.e., there is no "11" state).
[0032] Figure 9 The processing of the OUTP generation logic circuit is as follows: when a positive pulse signal (i.e., the differential audio signal amplitude is positive) appears in PWMO_P, the RS flip-flop outputs OUT_P=1 and locks it. Unless a positive pulse signal (i.e., the differential audio signal amplitude is negative) appears in PWMO_N, the RS flip-flop outputs OUT_P=0 and locks it. This process repeats, meaning that when another positive pulse signal appears in PWMO_P, OUT_P changes to 1. Thus, the operating frequency of OUT_P is related to the frequency at which the audio input signal alternates between positive and negative values. Each time the audio input amplitude crosses zero, the OUTP level flips once, meaning it operates within the low-frequency range of 20~20kHz audio.
[0033] Figure 9 The processing of the logic circuit that generates OUTN is as follows: when OUT_P=1, OUT_N= / PWM_P, that is, the logic level of PWM_P is inverted; when OUT_P=0, OUT_N=PWM_N logic level.
[0034] Figure 9 The RESET logic triggers a reset operation under conditions such as system power-on startup, working mode switching, and fault protection activation. When RESET=1, a reset is performed, and OUT_P and OUT_N are reset to their initial state of 0.
[0035] This invention can be implemented in various ways, including but not limited to the methods described above. It can be modified based on any PWM modulation architecture, including other asynchronous or synchronous logic timing structures and even the addition of arbitration circuitry. For digital audio input Class-D amplifiers, corresponding OUTP and OUTN PWM output signals can be generated for the PWM driver output stage upon detecting a zero-crossing digital audio signal. For analog audio input Class-D amplifiers, in addition to the above implementation examples, an analog detection circuit can be used to detect whether the analog audio signal has crossed zero. Upon zero-crossing, a corresponding high or low level OUTP signal and an OUTN PWM signal containing audio amplitude information are generated based on the amplitude sign. Furthermore, regardless of whether it is a digital or analog input Class-D amplifier, a low-frequency pulse output can be generated at the OUTN terminal instead of the OUTP terminal, and a high-frequency PWM pulse signal containing audio amplitude information can be generated at the OUTP terminal. The signal definitions of OUTP and OUTN are interchangeable. The output architecture can be a BTL bridge load or a PBTL parallel bridge load. Specific implementation methods also include other improved methods and circuit structures derived from the PWM modulation concept of this invention and the aim of reducing the output inductance or ferrite bead at one end.
[0036] It is worth mentioning that the technical features such as the drive and power transistor involved in this utility model patent application should be regarded as prior art. The specific structure, working principle and possible control method and spatial arrangement of these technical features can be adopted by conventional choices in the field and should not be regarded as the inventive point of this utility model patent. This utility model patent will not be further elaborated in detail.
[0037] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A pulse width modulation circuit for a Class D audio power amplifier, characterized in that, It includes a PWM_P conversion module, a PWM_N conversion module, an OUTP generation logic module, and an OUTN generation logic module, wherein: The input terminal of the PWM_P conversion module receives the differential signal PWM_P and the output terminal outputs the signal PWMO_P to the input terminal of the OUTP generation logic module. The input terminal of the PWM_N conversion module receives the differential signal PWM_N and the output terminal outputs the signal PWMO_N to the input terminal of the OUTN generation logic module. The OUTP generation logic module includes NOR gate L7 and NOR gate L8. The first input terminal of NOR gate L7 is connected to the signal PWMO_P. The second input terminal of NOR gate L7 is connected to the output terminal of NOR gate L8, and the output terminal of NOR gate L7 is connected to the first input terminal of NOR gate L8. The output terminal of NOR gate L8 outputs the signal OUT_P. The OUTN generation logic module includes NAND gate L9, OR gate L10, and AND gate L11. The signal PWMO_N is connected to the second input terminal of NAND gate L8 and the second input terminal of OR gate L10, respectively. The first input terminal of OR gate L10 and the first input terminal of NAND gate L9 are both connected to the output terminal of NAND gate L8. The second input terminal of NAND gate L9 is connected to the signal PWMO_P. The output terminal of NAND gate L9 is connected to the first input terminal of AND gate L11, and the output terminal of OR gate L10 is connected to the second input terminal of AND gate L11. The output terminal of AND gate L11 outputs the signal OUT_N.
2. The Class D audio power amplifier pulse width modulation circuit according to claim 1, characterized in that, The PWM_P conversion module includes an inverter L1, an inverter L2, and an AND gate L3. The input terminal of the inverter L1 receives the differential signal PWM_P, and the output terminal of the inverter L1 is connected to the input terminal of the inverter L2. The output terminal of the inverter L2 is connected to the first input terminal of the AND gate L3. The PWM_N conversion module includes an inverter L4, an inverter L5, and an AND gate L6. The input terminal of the inverter L4 receives the differential signal PWM_N, and the output terminal of the inverter L4 is connected to the input terminal of the inverter L5. The output terminal of the inverter L5 is connected to the first input terminal of the AND gate L6. The output of inverter L1 is also connected to the second input of AND gate L6, and the output of inverter L4 is also connected to the second input of AND gate L3.
3. The pulse width modulation circuit for a Class D audio power amplifier according to claim 2, characterized in that, It also includes an inverter L12, the input terminal of which and the third input terminal of the NOR gate L8 are both input with RESET signals, and the output terminal of the inverter L12 is connected to the third input terminal of the AND gate L11.
4. The Class D audio power amplifier pulse width modulation circuit according to claim 3, characterized in that, The signal OUT_P is driven by the driver and power transistor U7 to output signal OUTP, and the signal OUT_N is driven by the driver and power transistor U8 to output signal OUTN.
5. The Class D audio power amplifier pulse width modulation circuit according to claim 4, characterized in that, The OUTP generation logic module also includes an XOR gate, which is used to erase the 11-level states of the signals PWMO_P and PWMO_N.