Novel storage device

Abstract

A method comprising: writing a plurality of data words, each containing a plurality of data bits, into respective bit cells of a storage device (100); in response to determining that not all data bits of the plurality of data words have been correctly written into the respective bit cells of the storage device (100), grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that have not been correctly written into the respective bit cells of the storage device (100), wherein the subset of data bits is contained in a respective of the plurality of data word sets.

Description

CROSS-REFERENCE TO A RELATED REGISTRATION GENERAL STATE OF THE ART Storage devices are commonly used in many types of electronic devices, such as computers, mobile phones, tablets, data loggers, and navigation equipment, to name just a few. Generally, write operations are used to store information, such as data bits, in such a storage device. In some cases, there may be multiple data words, each containing several data bits configured to be written to specific memory bit cells of the storage device. Occasionally, write operations may fail. One or more data bits from a plurality of data words may not be written correctly to the configured memory bit cells. Such data bits are typically called failed data bits. To remedy such failed data bits, techniques used in existing storage devices typically resort to one or more iterations of rewriting the failed data bits based on a single "word." For example, the failed data bits contained in a first word are rewritten to the respective configured memory bit cells, the failed data bits contained in a second word are rewritten to the respective configured memory bit cells, and so on, which is time-consuming and energy-intensive. Existing storage devices and methods for storing data bits are therefore not entirely satisfactory. The prior art relevant to the present invention is given by US 8,397,024 B2, US 9,110,829 B2, US 9,552,244 B2, and US 2016 / 0078946 A1.A method for a storage device that communicates with an external host device is known from the prior art. A data page from a page buffer is written back to a storage array. The host transmits user data, an initial write address, and a write command to the storage device. If the write attempt fails, the host sends a retry command with a new address, without transmitting the user data to the storage device again. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description with reference to the accompanying figures. It should be noted that various features are not necessarily drawn to scale. The dimensions of the various features may be arbitrarily enlarged or reduced for clarity of discussion. Fig. 1 illustrates an exemplary block diagram of a storage device in accordance with some embodiments. Fig. 2A illustrates an exemplary schematic diagram of a section of the storage device of Fig. 1 in accordance with some embodiments. Fig. 2B illustrates an exemplary schematic diagram of another section of the storage device of Fig. 1 in accordance with some embodiments. Fig. 3 illustrates a flowchart of an exemplary method for operating the storage device of Fig.1 in accordance with some embodiments. Fig. 4 illustrates a block diagram of a computer system for carrying out the method of Fig. 3 in accordance with some embodiments. DETAILED DESCRIPTION The present invention is defined by the subject matter of the independent claims. Particular embodiments are defined by the additional features of the dependent claims. The present disclosure provides various embodiments of a storage device comprising a control logic circuit configured to rewrite one or more failed data bits into respective configured memory bit cells based on a data word group unit. In some embodiments, the control logic circuits can initiate a grouping operation on a plurality of data words, each of which comprises a plurality of data bits, in response to the determination of the presence of one or more failed data bits within such plurality of data words. For example, the control logic circuit is configured to group the plurality of data words comprising a first number of data words into a plurality of data word sets comprising a second number of data word sets, the second number being less than the first number.According to some embodiments, the control logic circuit iteratively checks whether each of the data word sets contains any of the failed data bits, and if so, it rewrites the failed data bit(s) into the configured memory bit cells. In some embodiments, rewriting the failed data bit(s) based on the unit of a data word set, rather than on each individual word, can provide several advantages. Since, in general, the number of failed data bits is relatively low compared to the total number of data bits in each word (for example, approximately one part per million (ppm)), rewriting the failed data bits grouped within each data word set can be more efficient in terms of time and performance. Furthermore, due to the more efficient rewrite operation(s), a greater tolerance for errors during the initial write operation is permitted. The magnitude of an initial write signal applied to the memory bit cells of the disclosed storage device can therefore be significantly reduced, which can advantageously improve the respective endurance of the memory bit cells. Fig. 1 illustrates a block diagram of an exemplary storage device 100 in accordance with various embodiments of the present disclosure. As shown, the storage device 100 comprises a control logic circuit 102, a plurality of memory banks 104, 106, 108, and 110, and a buffer memory circuit 120. Although, as shown in the illustrated embodiment of Fig. 1, the storage device 100 has four memory banks 104 to 110, it is clear that the storage device 100 can have any desired number of memory banks while still remaining within the scope of protection of the present disclosure. In some embodiments, the control logic circuit 102, which is coupled to the memory banks 104 to 110, is configured to receive a plurality of data words, each containing a plurality of data bits, through a standardized interface (not shown), and to write such a plurality of data words into the respective memory bit cells of the memory banks 104 to 110. Upon receiving the plurality of data words, the control logic circuit 102 can also receive the respective logical addresses of the data bits of the plurality of data words. Based on these logical addresses, the control logic circuit 102 can write each of the data bits of the plurality of data words into the respective memory bit cell via the memory banks 104 to 110 (that is, write the data bits of the plurality of data words to their respective physical addresses).If one or more of the data bits are not correctly written to the respective memory bit cells at such configured addresses (referred to below as "failed data bits"), the control logic circuit 102 can perform a grouping operation to rewrite the failed data bit(s) to the respective memory bit cells using a data word group unit, as described in more detail below. In some embodiments, the buffer memory circuit 120, typically called cache memory, is coupled to the control logic circuit 102 and has a plurality of non-volatile memory cells, such as flash memory cells, chalcogenide random access memory (C-RAM) cells, programmable metallization cell random access memory (PMC-RAM or PMCm) cells, ovonic unified memory (OUM) cells, resistance random access memory (RRAM) cells, ferroelectric memory (FeRAM) cells, etc., or volatile memory cells, for example, static RAM (SRAM) cells, dynamic RAM (DRAM) cells, etc.Such memory cells of the buffer memory circuits 120 can be implemented as on-chip memory cells (i.e., formed on the same chip as memory banks 104 to 110) or off-chip memory cells (i.e., formed on a different chip than memory banks 104 to 110). In some embodiments, the control logic circuit 102 can store various types of data in the buffer memory circuit 120, for example, a representation of the failed data bits mentioned above, as discussed below. As mentioned above, each of the memory banks 104 to 110 has a plurality of memory bit cells. In some embodiments, the plurality of memory bit cells is arranged in a column-row configuration, with each memory bit cell located at the interface of a bit line (BL), which forms a column, and a word line (WL), which forms a row. Furthermore, each of the memory banks 104 to 110 has a row selection circuit, a column selection circuit, and a write driver. Figures 2A and 2B illustrate schematic diagrams of the memory banks 104 to 110 according to some embodiments. With reference to Fig. 2A, the schematic diagrams of memory banks 104 and 106 are shown. Memory bank 104 comprises memory bit cells 104-1, 104-2, 104-3, 104-4, 104-5, 104-6, 104-7, 104-8, 104-9, 104-10, 104-11, 104-12, 104-13, 104-14, 104-15 and 104-16, which are formed as an array 104A, a row selector circuit (typically called a row multiplexer circuit) 104RM, a column selector circuit (typically called a column multiplexer circuit) 104CM and a write driver circuit 104WD. As discussed below, each row selector circuit 104RM and column selector circuit 104CM has a plurality of components that are coupled to corresponding memory bit cells by respective BLs or WLs. Although in the illustrated embodiment of Fig.Since the memory bank 104 has 16 memory bit cells, the memory array 104A of the memory bank 104 can have any desired number of memory bit cells without leaving the scope of protection of the present disclosure. It is further understood that Fig. 2A illustrates only an exemplary embodiment, and that the memory bank 102 can employ other memory circuits according to the prior art, for example, sampling amplifiers, preload circuits, etc., without leaving the scope of protection of the present disclosure. As shown, memory bit cell 104-1 is arranged at an interface of BL 130, which is set up along a first column, and WL 138, which is set up along a first row; memory bit cell 104-2 is arranged at an interface of BL 132, which is set up along a second column, and BL 138, which is set up along the first row; memory bit cell 104-3 is arranged at an interface of BL 134, which is set up along a third column, and WL 138, which is set up along the first row; memory bit cell 104-4 is arranged at an interface of BL 136, which is set up along a fourth column, and WL 138, which is set up along the first row; memory bit cell 104-5 is arranged at an interface of BL 130, which is set up along the first column, and WL 140, which is set up along a second row.Memory bit cell 104-6 is arranged at an interface of BL 132, which is set up along the second column, and WL 140, which is set up along the second row; memory bit cell 104-7 is arranged at an interface of BL 134, which is set up along the third column, and WL 140, which is set up along the second row; memory bit cell 104-8 is arranged at an interface of BL 136, which is set up along the fourth column, and WL 140, which is set up along the second row; memory bit cell 104-9 is arranged at an interface of BL 130, which is set up along the first column, and WL 142, which is set up along the third row; memory bit cell 104-10 is arranged at an interface of BL 132, which is set up along the second column, and WL 142, which is set up along the third row.Memory bit cell 104-11 is arranged at an interface of BL 134, which is set up along the third column, and WL 142, which is set up along the third row; memory bit cell 104-12 is arranged at an interface of BL 136, which is set up along the fourth column, and WL 142, which is set up along the third row; memory bit cell 104-13 is arranged at an interface of BL 130, which is set up along the first column, and WL 144, which is set up along the fourth row; memory bit cell 104-14 is arranged at an interface of BL 132, which is set up along the second column, and WL 144, which is set up along the fourth row; memory bit cell 104-15 is arranged at an interface of BL 134, which is set up along the third column, and WL 144, which is set up along the fourth row.The memory bit cell 104-16 is located at an interface of BL 136, which is set up along the fourth column, and WL 144, which is set up along the fourth row. Along the first row of the memory array 104A, the memory bit cells 104-1 to 104-4 are coupled to a first component 104RM-1 of the row selection circuit 104RM by the WL 138; along the second row of the memory array 104A, the memory bit cells 104-5 to 104-8 are coupled to a second component 104RM-2 of the row selection circuit 104RM by the WL 140; along the third row of the memory array 104A, the memory bit cells 104-9 to 104-12 are coupled to a third component 104RM-3 of the row selection circuit 104RM by the WL 142; and along the fourth row of the memory array 104A, the memory bit cells 104-13 to 104-16 are coupled to a fourth component 104RM-4 of the row selection circuit 104RM by the WL 144.In some embodiments, each of the components 104RM-1 to 104RM-4 can be implemented by any of a variety of pass-gate transistors known from the prior art, configured to allow a signal to pass based on a control signal, such as a gated latch, a transfer gate, etc. Along the first column of the memory array 104A, the memory bit cells 104-1, 104-5, 104-9 and 104-13 are coupled to a first component 104CM-1 of the column selection circuit 104CM by BL 130; along the second column of the memory array 104A, the memory bit cells 104-2, 104-6, 104-10 and 104-14 are coupled to a second component 104CM-2 of the column selection circuit 104CM by BL 132; along the third column of the memory array 104A, the memory bit cells 104-3, 104-7, 104-11 and 104-15 are coupled to a third component 104CM-3 of the column selection circuit 104CM by BL 134; and along the fourth column of the memory array 104A, the memory bit cells 104-4, 104-8, 104-12 and 104-16 are coupled to a fourth component 104CM-4 of the column selection circuit 104CM by the BL 136.Similarly, in some embodiments, each of the components 104CM-1 to 104CM-4 can be implemented by any of a variety of pass-gate transistors configured to allow a signal to pass based on a control signal, such as a gated latch, a transfer gate, etc. Along the column direction, the memory bit cells are further coupled to the write driver circuit 104WD via the respective BL. For example, along the first column of the memory array 104A, memory bit cells 104-1, 104-5, 104-9, and 104-13 are coupled to the write driver circuit 104WD via BL 130; along the second column of the memory array 104A, memory bit cells 104-2, 104-6, 104-10, and 104-14 are coupled to the write driver circuit 104WD via BL 132; along the third column of the memory array 104A, memory bit cells 104-3, 104-7, 104-11, and 104-5 are coupled to the write driver circuit 104WD via BL 134; and along the fourth column of the memory array 104A, the memory bit cells 104-4, 104-8, 104-12 and 104-16 are coupled to the write driver circuit 104WD by the BL 136.In some embodiments, the write driver circuit 104WD can be implemented by a combination of several logic gates and / or transistors known from the prior art, configured to provide a write signal (for example, a voltage signal) to an acknowledged BL. Similar to the configuration of memory bank 102, memory bank 106 has memory bit cells 106-1, 106-2, 106-3, 106-4, 106-5, 106-6, 106-7, 106-8, 106-9, 106-10, 106-11, 106-12, 106-13, 106-14, 106-15 and 106-16, which are formed as an array 106A, each of which is arranged at an interface of a BL and a WL, for example at one of the BLs 146, 148, 150 and 152 and at one of the WLs 154, 146, 158 and 160, a row selector circuit 106RM, a column selector circuit 106CM and a write driver circuit 106WD. Furthermore, the row selection circuit 106RM also has four components 106RM-1, 106RM-2, 106RM-3 and 106RM-4, each of which is coupled to respective memory bit cells of the memory array 106A by a corresponding WL; and the column selection circuit 106CM also has four components 106CM-1, 106CM-2, 106CM-3 and 106CM-4, each of which is coupled to respective memory bit cells of the memory array 106A by a corresponding BL.The row selection circuit 106RM and the column selection circuit 106CM, as well as the write driver circuit 106WD, are essentially similar to the row selection circuit 104RM, column selection circuit 104CM and write driver circuit 104WD described above, so that descriptions of the row selection circuit 106RM, the column selection circuit 106CM and the write driver circuit 106WD are not repeated. Referring to Fig. 2B, memory banks 108 and 110 are essentially similar to memory banks 104 and 106 (Fig. 2A). Memory banks 108 and 110 are therefore briefly described as follows.Memory bank 108, for example, has memory bit cells 108-1, 108-2, 108-3, 108-4, 108-5, 108-6, 108-7, 108-8, 108-9, 108-10, 108-11, 108-12, 108-13, 108-14, 108-15 and 108-16, which are formed as an array 108A, each of which is arranged at an interface of a BL and a WL, for example one of the BLs 162, 164, 166 and 168 and one of the WLs 170, 172, 174 and 176, a row selection circuit 108RM, a column selection circuit 108CM and a write driver circuit 108WD; and the memory array 110 has memory bit cells 110-1, 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 110-8, 110-9, 110-10, 110-11, 110-12, 110-13, 110-14, 110-15 and 110-16, which are formed as an array 110A, each of which is arranged at an interface of a BL and a WL, for example one of the BLs 178, 180, 182 and 184 and one of the WLs 186, 188, 190 and 192.Furthermore, in memory bank 108, the row selector circuit 108RM also includes four components 108RM-1, 108RM-2, 108RM-3, and 108RM-4, each essentially similar to the components of the row selector circuit 104RM described above (Fig. 2A); and the column selector circuit 108CM also includes four components 108CM-1, 108CM-2, 108CM-3, and 108CM-4, each essentially similar to the components of the column selector circuit 104CM described above (Fig. 2A). In memory bank 110, the row selector circuit 110RM also includes four components 110RM-1, 110RM-2, 110RM-3, and 110RM-4, each essentially similar to the components of the row selector circuit 104RM described above (Fig. 2A). and the column selection circuit 110CM also has four components 110CM-1, 110CM-2, 110CM-3 and 110CM-4, each similar to the components of the column selection circuit 104CM described above ( Fig. 2A). As mentioned above, each component of the row selector circuits 104RM, 106RM, 108RM, and 110RM is configured to allow a signal to pass through based on a control signal, in accordance with certain embodiments. More specifically, each component of the row selector circuits 104RM, 106RM, 108RM, and 110RM is configured to acknowledge at least one of the coupled WLs by allowing the signal to pass through based on address information provided by the control signal supplied by the control logic circuit 102. Similarly, each component of the column selector circuits 104CM, 106CM, 108CM, and 110CM is configured to acknowledge at least one of the coupled BLs, also based on the address information mentioned above. In some embodiments, such address information can include which of the WLs 138 to 144, 154 to 160, 170 to 176 and 186 to 192 and which of the BLs 130 to 136, 146 to 152, 162 to 168 and 178 to 184 are to be acknowledged. Consequently, the row selection circuit 104RM can acknowledge one of the WLs 138 to 144 to allow access to the memory bit cells of the memory array 104A, which are arranged along the acknowledged WL (for example, to be read or written), by activating the corresponding component (for example, one of the components 104RM-1 to 104RM-4); The row selection circuit 106RM can acknowledge one of the WLs 154 to 160 to allow access (for example, to be read or written) to the memory bit cells of the memory array 106A, which are arranged along the acknowledged WL, by activating the corresponding component (for example, one of the components 106RM-1 to 106RM-4);The row selector circuit 108RM can acknowledge one of the WLs 170 to 176 to allow access (for example, reading or writing) to the memory bit cells of the memory array 108A that are arranged along the acknowledged WL; and the row selector circuit 110RM can acknowledge one of the WLs 186 to 192 to allow access (for example, reading or writing) to the memory bit cells of the memory array 110A that are arranged along the acknowledged WL by activating the corresponding component (for example, one of the components 110RM-1 to 110RM-4). And the column selection circuit 104CM can acknowledge one of the BLs 130 to 136 to allow access (for example, reading or writing) to the memory bit cells of the memory array 104A, which are arranged along the acknowledged WL, by activating the corresponding component (for example, one of the components 104CM-1 to 104CM-4); the column selection circuit 106CM can acknowledge one of the BLs 146 to 152 to allow access (for example, reading or writing) to the memory bit cells of the memory array 106A, which are arranged along the acknowledged BL, by accessing the corresponding component (for example, one of the components 106CM-1 to 106CM-4);The column selection circuit 108CM can acknowledge one of the BLs 162 to 168 to allow access (for example, reading or writing) to the memory bit cells of the memory array 108A arranged along the acknowledged BL by activating the corresponding component (for example, one of the components 108CM-1 to 108CM-4); and the column selection circuit 110RM can acknowledge one of the BLs 178 to 184 to allow access (for example, reading or writing) to the memory bit cells of the memory array 110A arranged along the acknowledged WL by activating the corresponding component (for example, one of the components 110CM-1 to 110CM-4). Fig. 3 illustrates a flowchart of an exemplary method for rewriting one or more failed data bits into respective configured memory bit cells based on a data word group unit in accordance with various embodiments. In various embodiments, the operations of method 300 are performed by the respective components illustrated in Figs. 1 to 2B. For the purpose of discussion, the following embodiment of method 300 is described in conjunction with Figs. 1 to 2B. The illustrated embodiment of method 300 is only an example. It must therefore be understood that any one of a variety of operations can be omitted, rearranged, and / or added without departing from the scope of protection of this disclosure. Method 300 begins with step 302, in which a first plurality of data words, each containing a plurality of data bits, are written into respective memory bit cells. In some embodiments, the respective number of data bits in the data words can be the same or different from each other. The control logic circuit 102 can, for example, receive 5 data words: 1st data word, 2nd data word, 3rd data word, 4th data word, and 5th data word, each of which contains a plurality of data bits (for example, 4 data bits for simplicity). Furthermore, as mentioned above, when the control logic circuit 102 receives the 5 data words, each of the data bits can be associated with a corresponding logical address that can be mapped to a physical address (i.e., at the interface of a BL and a WL) of one of the memory bit cells of the memory arrays 104A to 110A. The control logic circuit 102 then writes the data bits of the 5 data words into the memory bit cells using the respective logical addresses. More precisely, the 4 data bits of the 1st data word can each be configured to be written to the memory bit cells 104-1, 104-2, 104-3 and 104-4 of the memory array 104A (as shown in Fig. 2A); the 4 data bits of the 2nd data word can each be configured to be written to the bit memory cells 108-5, 108-6, 108-7 and 108-8 of the memory array 108A (as shown in Fig. 2B); the 4 data bits of the 3rd data word can each be configured to be written to the memory bit cells 108-9, 108-10, 108-11 and 108-12 of the memory array 108A (as shown in Fig. 2B); The 4 data bits of the 4th data word can each be configured to be written to memory bit cells 110-9, 110-10, 110-11 and 110-12 of memory array 110 (as shown in Fig. 2B); the 4 data bits of the 5th data word can each be configured to be written to bit memory cells 110-13, 110-14, 110-15 and 110-16 of memory array 100 (as shown in Fig.2B) to be written. The control logic circuit 102 can therefore cause the row selection circuit 104RM to activate the component 104RM-1 to confirm the WL 138 and cause the column selection circuit 104CM to activate the components 104CM-1 to 104CM-4 individually or collectively to confirm the BLs 130 to 136, so that the data bits of the 1st data word can be written into the memory bit cells 104-1 to 104-4. Similarly, the control logic circuit 102 can cause the column selection circuit 108RM to activate component 108RM-1 to acknowledge WL 172, and cause the column selection circuit 108CM to activate components 108CM-1 to 108CM-4 individually or collectively to acknowledge BLs 162 to 168, so that the data bits of the 2ndData words can be written into memory bit cells 108-5 to 108-8; the control logic circuit 102 can cause the row selection circuit 108RM to activate component 108RM-3 to confirm WL 174 and cause the column selection circuit 108CM to activate components 108CM-1 to 108CM-4 individually or collectively to confirm BLs 162 to 168, so that the data bits of the 3rd data word can be written into memory bit cells 108-9 to 108-12; The control logic circuit 102 can cause the row selection circuits 110RM to activate component 110RM-3 to acknowledge WL 190, and cause the column selection circuit 110CM to activate components 110CM-1 to 110CM-4 individually or collectively to acknowledge BLs 178 to 184, so that the data bits of the 4thThe data words can each be written into the memory bit cells 110-9 to 110-12; the control logic circuit 102 can cause the row selection circuit 110RM to activate the component 110RM-4 to confirm the WL 192, and cause the column selection circuit 110CM to activate the components 110CM-1 to 110CM-4 individually or collectively to confirm the BL 178 to 184, so that the data bits of the 5th data word can each be written into the bit memory cells 110-13 to 110-16. Procedure 300 continues at step 304 to determine whether all data bits of the first plurality of data words have been correctly written into the respective memory bit cells. Continuing with the example above, after writing all data bits of the 1st to 5th data words into the respective configured memory bit cells, the control logic circuit 102 can perform the same operations as above to confirm the respective WLs and BLs of the memory bit cells into which the 1st to 5th data words are being written, and use one or more coupled sampling amplifiers (not shown) to read out the written data bits. Furthermore, in some embodiments, the control logic circuit 102 can determine the respective logical states of the data bits of the 1st to 5th data words that the control logic circuit 102 intends to write into the memory bit cells (that is, the respective logical states of the data bits of the 1st to 5th data words).The data words received by the control logic circuit 102 during operation 302 are compared with the logical states read from the memory bit cells. In some embodiments, if all the read logical states of the data bits of the 1st to 5th data words correspond to the respective intended logical states (that is, that all data bits of the first plurality of data words have been correctly written into the respective memory bit cells), the procedure 300 continues to operation 306, in which the writing operation ends. On the other hand, if the read-out logical states of one or more of the data bits of the 1st to 5th data words do not correspond to the respective intended logical states, such data bits can be categorized by the control logic circuit 102 as failed data bits, as mentioned above. In this case (that is, if not all data bits of the first plurality of data words are correctly written to the respective memory bit cells), procedure 300 proceeds to operation 308, in which information about such failed data bits is recorded in a buffer memory circuit. In some embodiments, the aforementioned information about failed data bits may include which data word each failed data bit belongs to and a mapping of such failed data bits. The mapping may show where (that is, at which physical address) each of the failed data bits is configured to be written.Continuing with the example above, after executing the comparison in operation 304, the control logic circuit 102 can determine that the 3rd data bit of the 1st data word, the 3rd data bit of the 2nd data word, the 3rd data bit of the 3rd data word, and the 1st data bit of the 4th data word are failed data bits. In other words, every data word except the 5th data word has a failed data bit, and consequently, the control logic circuit 102 records information indicating which of the 5 data words has failed data bits in the buffer memory circuit 120. Subsequently, or simultaneously with identifying the failed data bits, the control logic circuit 102 can further record the respective physical addresses of the memory bit cells in the buffer memory circuit 120 into which the failed data bits were written. The control logic circuit 102 can, for example, record that the 3rd data bit of the 1stThe data word for the second data word was written to memory bit cell 104-3, which is located at the interface of the third column (BL 134) and the first row (WL 138) of memory array 104A; the third data bit of the second data word was written to memory bit cell 108-7 at the interface of the third column (BL 166) and the second row (WL 172) of memory array 108A; the third data bit of the third data word was written to memory bit cell 108-11 at the interface of the third column (BL 166) and the third row (WL 174) of memory array 108A; and the first data bit of the fourth data word was written to memory bit cell 110-9 at the interface of the first column (BL 178) and the third row (WL 190) of memory array 110A. Referring again to Fig. 3, procedure 300, after determining that not all of the data bits of the first plurality of data words were correctly written into the respective memory bit cells, and after recording the respective information of the failed data bits (operations 304 and 308), proceeds to operation 310, in which the first plurality of data words is grouped as a second plurality of data word sets. If the number of the first plurality of data words can be divided by the size without remainder, each data word set can contain an equally divided number of data words. Conversely, if the number of the first plurality of data words cannot be divided by the size without remainder, each data word set, with the exception of the last word set, can contain an equally divided number of data words.If the number of the first plurality of data words can be divided by the size without remainder, then each data word set can have an equally divided number of data words. Continuing with the example above, the control logic circuit 102 can determine the size of the data word set to be 2, which corresponds to the latter case discussed above. The control logic circuit 102 can therefore group the 1st and 2nd data words as a first data word set; the 3rd and 4th data words as a second data word set; and the 5th data word as a third data word set. In some embodiments, the control logic circuit 102 can rewrite the failed data bits in each data word set according to the respective sequences, that is, rewrite the first data word set, the second data word set, and the third data word set, which are described in more detail below. The third data word set can therefore be considered the last of the multiple data word sets.However, it is clear that the control logic circuit 102 may not follow the sequences for rewriting the failed data bits without leaving the scope of protection of the present disclosure. In some alternative embodiments, when determining the size of the data word set, the control logic circuit 102 can group the data words containing failed data bits into a single or first data word set and prioritize rewriting the failed data bits contained in such a first data word set. For example, where only the first and fourth data words contain failed data bits among the first five data words, the control logic circuit 102 can group the first and fourth data words as a first data word set; the second and third data words, which do not contain failed data bits, as a second data word set; and the fifth data word, which does not contain failed data bits, as a third data word set. Furthermore, the control logic circuit 102 can prioritize rewriting the failed data bits contained in the first data word set. Procedure 300 proceeds to process 312, in which a first data word set is selected. In some embodiments, after grouping the first plurality of data words, the control logic circuit 102 can select a first data word set according to its sequence, as mentioned above. In the example above, the control logic circuit 102 can select the first data word set containing the 1st and 2nd data words. Procedure 300 proceeds to operation 314 to determine whether the selected data word set contains any of the failed data bits. Continuing with the example above, the control logic circuit 102 can determine whether the selected data word set (for example, the first data word set, which contains the 1st and 2nd data words) contains any failed data bits by accessing the buffer memory circuit 120, since in operation 308 the control logic circuit 102 stores the information of all failed data bits in the buffer memory circuit 120. According to some embodiments, if the selected data word contains one or more of the failed data bits, the procedure 300 proceeds to procedure 316 during determination process 314, in which the failed data bit(s) contained in the selected data word are each rewritten into the respective configured memory bit cells, and then to procedure 318 to further determine whether the selected data word is the last data word of the second plurality of data words. If the selected data word is the last of the second plurality of data words, the procedure 300 proceeds again to procedure 304 to determine whether all data bits of the first plurality of data words are correctly written into the respective memory bit cells.Or, if the selected data word set is not the last of the second plurality of data word sets, procedure 300 continues to operation 320, in which a next data word set is selected, and then loops back to operation 314. If, on the other hand, the selected data word in determination process 314 does not contain any of the failed data bits, process 300 skips process 316 and proceeds directly to process 318 to further determine whether the selected data word is the last data word of the second plurality of data words. Similarly, if the selected data word is the last of the second plurality of data words, process 300 proceeds again to process 304 to determine whether all data bits of the first plurality of data words are correctly written into their respective memory bit cells. Or, if the selected data word is not the last of the second plurality of data words, process 300 proceeds to process 320, in which a next data word is selected, and then loops back to process 314. One or more iteration loops can therefore be formed when executing procedure 300, for example a first iteration loop that starts at operation 314, goes through operations 316, 318 and 320, and returns to operation 314, a second iteration loop that starts at operation 314, goes through operations 316, 318, 304, 308, 310 and 312, and returns to operation 314, a third iteration loop that starts at operation 314, goes through operations 318 and 320 and returns to operation 314, and a fourth iteration loop that starts at operation 314, goes through operations 318, 304, 308, 310 and 312, and returns to operation 314. Processes 316, 318 and 320 are described in more detail below. In the example above, where the first data word containing the first and second data words is selected (operation 312), since both the first and second data words contain at least one of the failed data bits (operation 314), the control logic circuit 102 can, in operation 316, simultaneously rewrite the failed data bits that were contained in the first and second data words, but are now grouped in the first data word, to their respective configured memory bit cells in accordance with some embodiments. More precisely, the first data word contains a failed data bit that was written to memory bit cell 104-3 of the memory array 104A, and the second data word contains a failed data bit that was written to memory bit cell 108-4 of the memory array 108.In some embodiments, the control logic circuit 102 can simultaneously confirm WL 138 by activating component 104RM-1 to allow access to memory bit cell 104-3, and WL 172 by activating component 108RM-2 to allow access to memory bit cell 108-7. Simultaneously or subsequently, the control logic circuit 102 confirms BL 134 by activating component 104CM-3 to cause the write driver circuit 104WD to rewrite the intended logical state of the 3rd data bit of the 1st data word to the memory bit cell 104-3, and BL 166 by activating component 108CM-3 to cause the write driver circuit 108WD to rewrite the intended logical state of the 3rd data bit of the 3rd data word to the memory bit cell 108-7. In step 318, the control logic circuit 102 checks whether the selected first data word, containing the 1st and 2nd data words, is the last of a plurality of data word sets. In the current example, the last data word should be the third data word, containing the 5th data word, so the procedure 300 proceeds to step 320 to select the next data word, which is the second data word, containing the 3rd and 4th data words. The procedure 300 loops back to step 314 to determine whether the second data word contains one of the failed data bits. Since both the 3rd and 4th data words contain at least one of the failed data bits (as described above), the control logic circuit 102 can follow the concept described above, namely to simultaneously check the failed data bits that are present in the 3rd and 4th data words, respectively.The data words contained in the first data word, which are now grouped in the second data word set, are to be rewritten to the respective configured memory bit cells 108-11 and 110-9, and it is checked whether the selected second data word set, which contains the 3rd and 4th data words, is the last of the multiple data word sets. In the current example, the second data word set is still not the last data word set, which is why procedure 300 continues to operation 320 to select the next data word set, namely the third data word set, which contains the 5th data word, and then loops back to operation 314. Since the third data word set does not contain a failed data bit, procedure 300 continues directly to operation 318, and since the third data word set is the last data word set (as determined in operation 318), procedure 300 then continues to operation 304 to determine whether all data bits of the 1st to 5th data words are valid.The data words have been correctly written to their respective configured memory bit cells. Similarly, if all data bits of the 1st to 5th data words have been correctly written to their respective configured memory bit cells, the write operation (operation 306) ends; and if one or more failed data bits still remain, such failed data bits are rewritten selectively following operations 308 to 312, following the iteration loop of operations 314, 316, 318, 320 and 314, the iteration loop of operations 314, 318, 320 and 314, or the iteration loop of operations 314, 316, 318, 304, 308, 310, 312 and 314. Fig. 4 is a block diagram of a computer system 400 according to some embodiments. In some embodiments, one or more of the circuits and / or machines and / or systems and / or processes described with reference to Fig. 1, Fig. 2 to Fig. 3 are implemented by one or more computer systems 400 of Fig. 4. The system 400 comprises at least one processor 401, one memory 402, one network interface (I / F) 406, one input / output (I / O) device 408, and one storage device 410, which are coupled for communication via a bus 404 or another interconnected communication mechanism. In some embodiments, the memory 402 comprises random access memory (RAM) and / or another dynamic storage device and / or read-only memory (ROM) and / or another static storage device, coupled to the bus 404 for storing data and / or instructions to be executed by the processor 401. The memory 402 may further comprise a userspace 412, a core 414, sections of the core and / or the userspace, and components thereof. In some embodiments, the memory 402 is also used to store temporary variables or other intermediate information during the execution of instructions to be executed by the processor 401. In various embodiments, the memory 402 may be contained within a single integrated circuit or comprise a plurality of separate storage devices that are operationally coupled together. In some embodiments, a storage device 410, such as a magnetic disk or optical disk, is coupled to the bus 404 for storing data and / or instructions. The I / O device 408 comprises an input device, an output device, and / or a combined input / output device to enable user interaction with the system 400. An input device includes, for example, a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction arrows for transmitting information and commands to the processor 401. An output device includes, for example, a display, printer, speech synthesizer, etc., for transmitting information to a user. In some embodiments, one or more operations and / or functionalities of the circuits and / or machines and / or systems described with reference to Figures 1, 2 to 3 are executed by the processor 401, which is programmed to perform such operations and / or functionalities. In some embodiments, the processor 401 is configured as specifically configured hardware (for example, one or more application-specific integrated circuits (ASICs)). In accordance with various embodiments, the processor 401 can be implemented within a single integrated circuit (IC) or as multiple interconnected ICs and / or separate circuits. It is clear that the processor 401 can be implemented in accordance with various known technologies.In one embodiment, the processor 401 comprises one or more circuits or units that are configurable to execute one or more functions or processes described herein by carrying out instructions stored, for example, in an associated memory. In other embodiments, the processor 401 can be implemented as firmware (for example, separate logic components) configured to execute one or more functions or processes described herein.In accordance with various embodiments, the processor 401 may, for example, comprise one or more control devices, microprocessors, microcontrollers, application-specific integrated circuits (ASICs), digital signal processors, programmable logic devices, field-programmable gate arrays, or any combination of these devices or structures, or other known devices and structures, to perform the functions described herein. One or more of the memory 402, I / F 406, storage 410, I / O device 408 and bus 404 is / are operable to receive instructions, data, design constraints, design rules, netlists, layouts, models and / or other parameters for processing by the processor 401. In some embodiments, the operations and / or functionality are executed as functions of a program stored in a non-volatile, computer-readable recording medium. In at least one embodiment, the operations and / or functionality are executed as functions of a program, such as a set of executable instructions, stored in memory 402. In at least one embodiment, an IC design is stored in a non-volatile, computer-readable recording medium for access by one or more operations as described herein.Examples of non-volatile, computer-readable recording media include, but are not limited to, an external / removable and / or internal / built-in storage unit, such as one or more optical discs, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. In one embodiment, a method comprises: writing a plurality of data words, each comprising a plurality of data bits, into respective bit cells of a storage device; in response to the determination that not all data bits of the plurality of data words have been correctly written into the respective bit cells of the storage device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that have not been correctly written into the respective bit cells of the storage device, wherein the subset of data bits is contained in a respective of the plurality of data word sets. In another embodiment, a method comprises the following: writing a plurality of data words, each containing a plurality of data bits, into respective bit cells of a storage device; checking whether all data bits of the plurality of data words are correctly written into the respective bit cells of the storage device; in response to the presence of one or more data bits of the plurality of data words that are not correctly written into the respective bit cells of the storage device, grouping the plurality of data words into a plurality of data word sets; and iteratively rewriting at least one of the one or more data bits contained in each of the plurality of data word sets into the respective bit cell of the storage device until it has been verified that all data bits of the plurality of data words have been correctly written into the respective bit cells of the storage device. In yet another embodiment, a storage device comprises: a plurality of memory bit cells; and a control logic circuit coupled to the plurality of memory bit cells.The control logic circuit is configured to: write a plurality of data words, each containing a plurality of data bits, into the respective plurality of memory bit cells; check whether all data bits of the plurality of data words are correctly written into the respective memory bit cells; in response to the presence of one or more data bits of the plurality of data words that are not correctly written into the respective memory bit cells, group the plurality of data words into a plurality of data word sets; and iteratively rewrite at least one of the one or more data bits contained in each of the plurality of data word sets into the respective memory bit cell until it has been verified that all data bits of the plurality of data words are correctly written into the respective memory bit cells.

Claims

A method comprising: writing a plurality of data words, each containing a plurality of data bits, into respective bit cells of a storage device (100); in response to determining that not all data bits of the plurality of data words have been correctly written into the respective bit cells of the storage device (100), grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that have not been correctly written into the respective bit cells of the storage device (100), wherein the subset of data bits is contained in a respective of the plurality of data word sets. Method according to claim 1, wherein at least one subset of the plurality of data word sets has a common number of data words. Method according to claim 1 or 2, wherein at least one subset of the plurality of data word sets has a different number of data words. A method according to any of the preceding claims, further comprising: storing the respective addresses associated with the data bits that were not correctly written into the respective bit cells of the storage device (100) in one or more buffer memories (120) of the storage device (100). The method of claim 4, further comprising: accessing the one or more buffer memories (120) to determine whether a first of the plurality of data word sets has any of the data bits that were not correctly written into the respective bit cells of the storage device (100). The method of claim 5, further comprising: in response to the fact that the first of the plurality of data word sets has a first subset of data bits that were not correctly written into the respective bit cells of the storage device (100), rewriting the first subset of data bits into the respective bit cell of the storage device (100) and then determining whether the first of the plurality of data word sets is a last of the plurality of data word sets; and in response to the fact that the first of the plurality of data word sets does not have any of the data bits that were not correctly written into the respective bit cells of the storage device (100), determining whether the first of the plurality of data word sets is the last of the plurality of data word sets. The method of claim 6, further comprising: in response to the fact that the first of the plurality of data word sets is not the last of the plurality of data word sets, determining whether a second of a plurality of data word sets contains any of the data bits that have not been correctly written into the respective bit cells of the storage device (100), and in response selectively rewriting a second subset of the data bits contained in the second of the plurality of data word sets into the respective bit cells of the storage device (100); and in response to the fact that the first of the plurality of data word sets is the last of the plurality of data word sets, checking whether all data bits of the plurality of data word sets have been correctly written into the respective bit cells of the storage device (100). A method comprising: writing a plurality of data words, each containing a plurality of data bits, into respective bit cells of a storage device (100); verifying that all data bits of the plurality of data words are correctly written into the respective bit cells of the storage device (100); in response to the presence of one or more data bits of the plurality of data words that are not correctly written into the respective bit cells of the storage device (100), grouping the plurality of data words into a plurality of data word sets; and unditeratively rewriting at least one of the one or more data bits contained in each of the plurality of data word sets into the respective bit cell of the storage device (100) until it has been verified that all data bits of the plurality of data words are correctly written into the respective bit cells of the storage device (100). Method according to claim 8, wherein at least one subset of the plurality of data word sets has a common number of data words. Method according to claim 8 or 9, wherein at least one subset of the plurality of data word sets has a different number of data words. Method according to any one of claims 8 to 10 above, further comprising: storing the respective addresses associated with the one or more data bits that were not correctly written into the respective bit cells of the storage device (100) in one or more buffer memories (120) of the storage device (100). The method of claim 11, further comprising: accessing the one or more buffer memories (120) to determine whether a first of the plurality of data word sets has any one or more data bits that were not correctly written into the respective bit cells of the memory device (100). The method of claim 12, further comprising: if the first of the plurality of data word sets has at least one first of the one or more data bits that were not correctly written into the respective bit cells of the storage device (100), rewriting the at least first of the one or more data bits into the respective bit cells of the storage device (100); and determining whether the first of the plurality of data word sets is the last of the plurality of data word sets. The method of claim 13, further comprising: if the first of the plurality of data word sets is not the last of the plurality of data word sets, iteratively determining whether a next of the plurality of data word sets contains any one of the one or more data bits that have not been correctly written into the respective bit cells of the storage device (100), and in response selectively rewriting at least one of the one or more data bits contained in the next of the plurality of data word sets into the respective bit cell of the storage device (100), until the next of the plurality of data word sets is the last of the plurality of data word sets; and rechecking whether all data bits of the plurality of data words have been correctly written into the respective bit cells of the storage device (100). A method according to any one of claims 12 to 14 above, further comprising: if the first of the plurality of data word sets does not contain one or more data bits that have not been correctly written into the respective bit cells of the storage device (100), determining whether the first of the plurality of data word sets is a last of the plurality of data word sets; rechecking whether all data bits of the plurality of data words have been correctly written into the respective bit cells of the storage device (100). Storage device (100) comprising: a plurality of memory bit cells; and a control logic circuit (102) coupled to the plurality of memory bit cells and configured to: write a plurality of data words, each containing a plurality of data bits, into respective memory bit cells; check that all data bits of the plurality of data words are correctly written into the respective memory bit cells; group the plurality of data words into a plurality of data word sets in response to the presence of one or more data bits of the plurality of data words that are not correctly written into the respective memory bit cells;to rewrite at least one of the one or more data bits contained in each of the plurality of data word sets into the respective memory bit cell in an unditerative manner until it has been verified that all data bits of the plurality of data words have been correctly written into the respective memory bit cells. Storage device (100) according to claim 16, wherein the control logic circuit (102) is further configured to: determine whether a first of the plurality of data word sets has any one of the one or more data bits that are not correctly written into the respective memory bit cells. Storage device (100) according to claim 17, wherein, if the first of the plurality of data word sets has at least one first of the one or more data bits that were not correctly written into the respective memory bit cells, the control logic circuit (102) is further configured to: rewrite the at least first of the one or more data bits into the respective memory bit cell; and to determine whether the first of the plurality of data word sets is a last of the plurality of data word sets. Storage device (100) according to claim 18, wherein, if the first of the plurality of storage word sets is not the last of the plurality of storage word sets, the control logic circuit (102) is further configured to: iteratively determine whether a next of the plurality of data word sets contains any one of the one or more data bits that have not been correctly written into the respective storage bit cells, and in response, selectively rewrite at least one of the one or more data bits contained in the next of the plurality of data word sets into the respective storage bit cells, until the next of the plurality of data word sets is the last of the plurality of data word sets; and recheck whether all data bits of the plurality of data words have been correctly written into the respective storage bit cells. Storage device (100) according to any one of the preceding claims 17 to 19, wherein, if the first of the plurality of data word sets does not contain any of the one or more data bits that were not correctly written into the respective memory bit cells, the control logic is further configured to: determine whether the first of the plurality of data word sets is a last of the plurality of data word sets; if the first of the plurality of data word sets is not the last of the plurality of data word sets, iteratively determine whether a next of the plurality of data word sets contains any one of the one or more data bits that were not correctly written into the respective memory bit cells; and, as a response, selectively rewrite at least one of the one or more data bits contained in the next of the plurality of data word sets into the respective memory bit cells.until the next of the plurality of data word sets is the last of the plurality of data word sets, and to check again whether all data bits of the plurality of data words are correctly written into the respective memory bit cells.

Images