OLED display panel and associated OLED display device

Abstract

OLED display panel, which includes the following: an active area (AA) containing data lines (139), sampling lines (149) that cross the data lines, and subpixels arranged at each crossing; and a stage of a GIP drive circuit which is distributed and arranged in several unit pixel areas which are driven by m (where m is a natural number greater than 1) sampling lines (149) in the active area (AA) to supply sampling pulses to the corresponding sampling lines (149), wherein the active area (AA) further includes m GIP-internal connecting line parts (32) each adjacent to the m scanning lines (149).

Description

[0001] This application claims priority over Korean patent application No. 10-2017-0159650, filed on November 27, 2017. BACKGROUND OF THE INVENTION Area of ​​the invention

[0002] The present invention relates to an OLED display panel and an OLED display device provided therewith, wherein the OLED display panel comprises stages of a GIP drive circuit arranged in a pixel array and signal connection lines for forming the GIP drive circuit. Discussion of the state of the art

[0003] With the development of the information society and various portable electronic devices such as mobile communication devices and notebook computers, the need for flat panel display devices applicable to these electronic devices has increased.

[0004] A liquid crystal display (LCD) and a display device with an organic light-emitting diode (OLED display device) that uses an OLED are used as such flat display devices.

[0005] Such a flat display device consists of a display panel containing several gate lines and several data lines to display images, and a control circuit to control the display panel.

[0006] Among the aforementioned display devices, an LCD display panel includes a thin-film transistor array substrate comprising a thin-film transistor array formed on a glass substrate, a color filter array substrate comprising a color filter array formed on a glass substrate, and a liquid crystal layer inserted between the thin-film transistor array substrate and the color filter array substrate.

[0007] The thin-film transistor array substrate contains multiple gate lines GL extending in a first direction and multiple data lines DL extending in a second direction perpendicular to the first direction. A subpixel region (pixel: P) is defined by each gate line and each data line. A thin-film transistor and a pixel electrode are formed within the subpixel region P.

[0008] The LCD display panel shows an image by applying a voltage to electrodes to generate an electric field (a pixel electrode and a common electrode) to create an electric field in the liquid crystal layer, and adjusting the arrangement state of liquid crystal molecules of the liquid crystal layer through the electric field to control the polarization of incident light.

[0009] In addition, among the aforementioned display devices, a display panel of the OLED display device contains subpixels defined according to the intersection of several gate lines and several data lines, and each subpixel contains an OLED composed of an anode, a cathode and an organic emission layer inserted between the cathode and the anode, and a pixel circuit for independently driving the OLED.

[0010] The pixel circuit is configured in various ways and contains at least one switching TFT, one capacitor, and one driver TFT.

[0011] At least one switching TFT charges a data voltage into the capacitor in response to a sampling pulse. The driver TFT controls the amount of current supplied to the OLED in response to the data voltage applied to the capacitor, in order to adjust the amount of light emitted by the OLED.

[0012] Such a display panel for display devices is defined by an active area (AA) through which an image is displayed for a user, and an inactive area (NA) which is a peripheral area of ​​the active area AA.

[0013] Additionally, the control circuit for controlling the display panel includes a gate control circuit for sequentially supplying gate pulses (or sampling pulses) to the multiple gate lines (sampling lines), a data control circuit for supplying a data voltage to the multiple data lines, and a timing control unit for supplying image data and various control signals to the gate control circuit and the data control circuit.

[0014] Although the gate drive circuit can consist of at least one gate drive IC, the gate drive circuit can be formed in a process to create the multiple signal lines (gate lines and data lines) and subpixels of the display board simultaneously on the inactive area of ​​the display board.

[0015] This means that a gate-in-panel (GIP) method is used to integrate the gate control circuit into the display panel.

[0016] The aforementioned gate drive circuit contains a greater number of stages than the number of gate lines in order to sequentially feed sampling pulses to the gate lines. Each stage consists of an oxide semiconductor TFT to improve the drive characteristics.

[0017] This means that the gate drive circuit contains several cascaded stages. Additionally, each stage includes an output unit connected to each gate line (sampling line). Each stage receives a clock signal, a gate start signal, a gate high voltage, and a gate low voltage from the timing unit and generates a transmit pulse and a sample pulse.

[0018] Fig. Figure 1 is a block diagram showing the drive circuits of a conventional OLED display device and a relationship between the drive circuits.

[0019] Referring to Fig. 1 includes an OLED display device 1000, an OLED display panel PNL and control circuits for supplying input image data to a pixel array 110 of the OLED display panel PNL.

[0020] The OLED display panel PNL contains several gate lines 149 and several data lines 139 arranged in an intersecting manner, and the pixel array 110 in which subpixels defined by the several gate lines 149 and the several data lines 139 are arranged as a matrix.

[0021] Each subpixel contains an OLED consisting of an anode, a cathode and an organic emission layer inserted between the anode and the cathode, and a pixel circuit for independently controlling the OLED.

[0022] The pixel circuit can be configured in various ways and contains at least one switching TFT, one capacitor and one driver TFT.

[0023] The control circuits for controlling the OLED display panel PNL include a data control circuit 130, which is formed in an inactive area and supplies a data voltage to the several data lines 130, a GIP control circuit 140, which is formed in the inactive area and sequentially supplies a gate (sampling) signal, which is synchronized with the data voltage, to the several gate lines 149, and a timing control unit (TCON) 120.

[0024] The timing unit 120 is mounted on a printed circuit board (PCB), synchronizes input image data received from an external host system, and feeds the synchronized input image data to the data control circuit 130. Additionally, the timing unit 120 receives timing signals, such as a vertical synchronization signal, a horizontal synchronization signal, a data activation signal, and a dot clock signal, synchronized with the input image from the external host system and generates control signals (a data driver control signal DDC and a gate driver control signal GDC) to control the operating time of the data control circuit 130 and the GIP control circuit 140.

[0025] The data control circuit 130 receives the input image data and the data driver control signal DDC from the timing control unit 120 and converts the input image data into a gamma-compensated voltage to generate a data voltage, and outputs the data voltage to the multiple data lines 139.

[0026] The data control circuit 130 contains several integrated source control circuits (source control ICs), each configured in the form of a chip-on-film (COF) and each connected between a contact point part of the circuit board on which the time control unit 120 is mounted and a contact point part of the display panel PNL.

[0027] The GIP control circuit 140 can be located on one edge or on both wheels of the PNL display panel, depending on the control method. The in Fig. 1 Gate drive circuit 140 shown is a networked GIP drive circuit and includes a first GIP drive circuit 140L, which is located on the left side of the PNL display panel, and a second GIP drive circuit 140R, which is located on the right side of the PNL display panel.

[0028] Although the GIP drive circuit 140 can consist of at least one gate drive IC, the GIP drive circuit 140 can be formed simultaneously with the multiple signal lines (gate lines and data lines) and subpixels that form the pixel array 110 of the OLED display panel PNL in the inactive area of ​​the display panel by a process for forming the signal lines and subpixels.

[0029] This means that the gate-in-panel (GIP) method is used to integrate the gate control circuit into the display panel.

[0030] The GIP control circuit 140 sequentially feeds a gate (sampling) signal to the gate lines 149 in response to the control signal GDC sent by the timing control unit 120.

[0031] The aforementioned GIP drive circuit 140 contains a larger number of stages (hereinafter referred to as "GIP") than the number of gate lines in order to sequentially feed a sampling pulse to the gate lines, and uses oxide semiconductor thin-film transistors to improve the drive characteristics.

[0032] This means that the GIP drive circuit contains several cascaded GIP stages. Additionally, each GIP stage includes an output unit connected to each gate line. Each GIP stage receives a clock signal, a gate start signal, a gate high voltage, and a gate low voltage supplied by the timing unit and generates a transmit pulse and a sample pulse.

[0033] Fig. Figure 2 is a block diagram of a normal nth GIP stage.

[0034] As in Fig. As shown in Figure 2, each GIP stage contains a node control unit 100, which is set by a start pulse or a transmit pulse SET issued by the previous GIP stage and reset by a transmit pulse RST issued by the next GIP stage, to control voltages of the first and second nodes Q and Qb, and an output unit 200, which receives one of several clock signals SCCLKs for a sample pulse output and one of several clock signals CRCLKs for a transmit pulse output and outputs a sample pulse So(n) and a transmit pulse Co(n) in response to voltage levels of the first and second nodes Q and Qb.

[0035] In the case of a GIP stage driven by a 6-phase clock signal, the node control unit 100 is set by a transmission pulse (n-3) issued from the third preceding GIP stage and is reset by a transmission pulse (n+3) issued from the third next GIP stage to control the voltages of the first and second nodes Q and Qb.

[0036] Although not shown in the figure, the output unit 200 of the GIP stage contains a transmit pulse output unit and a sample pulse output unit.

[0037] The transfer pulse output unit contains a first pull-up transistor and a first pull-down transistor connected in series between a transfer pulse output clock signal terminal, to which one of the several clock signals for the transfer pulse output is applied, and a first gate low-voltage terminal VGL1.

[0038] The first pull-up transistor is switched on / off in response to the voltage level of the first node Q, and the first pull-down transistor is switched on / off in response to the voltage level of the second node Qb, in order to output the input transfer pulse output clock signal as a transfer pulse Co(n).

[0039] The sampling pulse output unit includes a second pull-up transistor and a second pull-down transistor connected in series between a sampling pulse output clock signal terminal, to which one of the multiple clock signals for sampling pulse output is applied, and a second gate low-voltage terminal VGL2, and a bootstrap capacitor connected between the gate electrode and the source electrode of the second pull-up transistor.

[0040] The second pull-up transistor is switched on / off in response to the voltage level of the first node Q, and the second pull-down transistor is switched on / off in response to the voltage level of the second node Qb, in order to output the input sample pulse output clock signal as a transfer pulse So(n).

[0041] Fig. 3 is a waveform diagram that illustrates the operation of the in Fig. Figure 2 shows the nth GIP stage.

[0042] Fig. Figure 3 shows that the node control unit 100 is set by the transmission pulse Co(n-3) output from the third preceding GIP stage and reset by the transmission pulse Co(n+3) output from the third next GIP stage to control the voltages of the first and second nodes Q and Qb.

[0043] The nth GIP stage(s) is set by the transfer pulse Co(n-3) output from the third preceding GIP stage to charge the first node Q with a gate high voltage VGH and discharge the second node Qb to a gate low voltage VGL. Accordingly, the first pull-up transistor of the transfer pulse output unit and the second pull-up transistor of the sampling pulse output unit are turned on, and the first pull-down transistor of the transfer pulse output unit and the second pull-down transistor of the sampling pulse output unit are turned off.

[0044] Additionally, the clock signals CRCLK and SCCLK, which have the same phase, are applied to the drain electrode of the first pull-up transistor of the transmission pulse output unit and the drain electrode of the second pull-up transistor of the sampling pulse output unit.

[0045] When the clock signals CRCLK and SCCLK, which correspond to a high level, are applied to the drain electrode of the first pull-up transistor and the drain electrode of the second pull-up transistor, the voltage of the floating first node Q is pulled up by the bootstrap capacitor, so that it increases by 2VGH.

[0046] In a state where the first node Q is pulled in this way, the transmit pulse output unit and the sample pulse output unit, respectively, output the input clock signals CRCLK and SCCLK as a transmit pulse Co(n) and a sample pulse So(n).

[0047] Additionally, the stage is reset by the transfer pulse Co(n+3) output from the third-next GIP stage, thus setting the first node to a low state and the second node Qb to a high state. Accordingly, the first pull-up transistor of the transfer pulse output unit and the second pull-up transistor of the sampling pulse output unit are turned off, and the first pull-down transistor of the transfer pulse output unit and the second pull-down transistor of the sampling pulse output unit are turned on to output the gate low voltage VGL as the transfer pulse Co(n) and the sampling pulse So(n).

[0048] However, the GIP driver circuit is integrated into the inactive area of ​​the display panel in the conventional OLED display panel, as described above, and thus it is difficult to construct a display device with a narrow bezel.

[0049] EP 3 321 920 A2 describes a display field and an OLED display device that uses it, wherein the display field comprises an active area with intersecting data and gate lines, matrix-arranged pixels, and a shift register distributed in the active area that supplies gate pulses to the gate lines.

[0050] US 2015 / 0 293 546 A1 describes a technique for the rapid control of gate lines on an active matrix substrate by integrated gate drivers with switching elements in the pixel area, wherein control signals are transmitted via separate lines from an external control circuit to the gate drivers in order to reduce the image frame area.

[0051] KR 10 2016 086 436 A describes a gate shift register to avoid multiple outputs on one gate line and to increase reliability, whereby node voltages are controlled and gate signals are selectively output depending on the clock. SUMMARY OF THE INVENTION

[0052] One object of the present invention, which was conceived to solve the aforementioned problem, is to create an OLED display panel and an OLED display device for arranging the signal connection lines for a GIP drive circuit in an active area and for minimizing the number of signal connection lines in order to minimize the size of a bezel.

[0053] To solve the above problem, an OLED display panel according to the present invention comprises: an active area containing data lines, scanning lines crossing the data lines, and subpixels arranged at each crossing; and a stage of a GIP driver circuit distributed and arranged in several unit pixel areas driven by m (where m is a natural number greater than 1) scanning lines in the active area to supply scanning pulses to the corresponding scanning lines, wherein the active area further comprises m GIP internal interconnection line parts adjacent to each of the m scanning lines, and several internal interconnection lines for connecting elements forming each stage may be distributed and arranged in the m GIP internal interconnection line parts.

[0054] Here, each stage contains: a logic unit for controlling the voltage levels of a first node and a second node using a transfer pulse from the preceding stage and a transfer pulse from the next stage; a transfer pulse output unit for outputting an input transfer pulse output clock signal as a transfer pulse in response to the voltage levels of the first and second nodes; and m sample pulse output units for outputting input sample pulse output clock signals to the m sample lines as sample pulses in response to the voltage levels of the first and second nodes.

[0055] To solve the above problem, an OLED display device according to the invention comprises an OLED display panel which in turn comprises: an active area containing data lines, scanning lines that cross the data lines, and subpixels arranged at each intersection; and a stage of a GIP driver circuit which is distributed and arranged in several unit pixel areas which are driven by m (where m is a natural number greater than one) scanning lines in the active area to supply scanning pulses to the corresponding scanning lines, wherein the active area further comprises m GIP-internal interconnection line parts each adjacent to the m scanning lines, and several internal interconnection lines for connecting elements that form each stage may be distributed and arranged in the m GIP-internal interconnection line parts.In a preferred embodiment, each of the unit pixel areas can contain at least three subpixels, a GIP part in which an element forming each stage of the GIP control circuit is arranged, and the multiple internal connecting lines arranged in the m GIP internal connecting line parts extend to the GIP part and are electrically connected to the elements forming each stage.

[0056] In a preferred embodiment, the m GIP-internal connecting line parts are contained in areas adjacent to the m scanning lines, and a node Q, a node Qb, a node Qh, a transmission pulse output terminal of the preceding stage, and a transmission pulse output terminal of the next stage for connecting the unit elements that form each stage are distributed and arranged in the m GIP-internal connecting line parts.

[0057] In a preferred embodiment, an OLED display panel comprises: an active area containing data lines, scanning lines that cross the data lines, and subpixels arranged at each intersection; and a stage of a GIP driver circuit distributed and arranged in several unit pixel areas driven by five scanning lines in the active area to supply scanning pulses to the corresponding scanning lines.

[0058] Preferably, each stage can include: a logic unit for controlling the voltage levels of a first node and a second node using a transfer pulse from the preceding stage and a transfer pulse from the next stage; a transfer pulse output unit for outputting an input transfer pulse output clock signal as a transfer pulse in response to the voltage levels of the first and second nodes; and first to fifth sample pulse output units for outputting first to fifth input sample pulse output clock signals to the five sample lines as sample pulses in response to the voltage levels of the first and second nodes.

[0059] In a preferred embodiment, five GIP internal interconnection line parts can be contained in areas adjacent to the five scanning lines, and a node Q, a node Qb, a node Qh, a preceding stage transmit pulse output terminal, and a next stage transmit pulse output terminal for connecting the unit elements that form each stage are distributed and arranged in each GIP internal interconnection line part.

[0060] In a preferred embodiment, each of the unit pixel areas can contain at least three subpixels and a GIP part in which an element forming each stage of the GIP control circuit is arranged, and the node Q, the node Qb, the node Qh, the transmission pulse output terminal of the preceding stage and the transmission pulse output terminal of the next stage, which are arranged in the five GIP-internal connecting line parts, extend to the GIP part and are electrically connected to the unit elements forming each stage.

[0061] In a preferred embodiment, an OLED display panel can comprise an active area containing data lines, sample lines crossing the data lines, and subpixels arranged at each crossing; and a stage of a GIP driver circuit distributed and arranged in multiple unit pixel areas driven by two sample lines in the active area to supply sample pulses to the corresponding sample lines, each stage comprising: a logic unit for controlling voltage levels of a first node and a second node using a transfer pulse from the preceding stage and a transfer pulse from the next stage; a transfer pulse output unit for outputting an input transfer pulse output clock signal as a transfer pulse in response to the voltage levels of the first node and the second node;and first and second sample pulse output units for the respective output of the first and second input sample pulse output clock signals to the two sample lines as sample pulses in response to the voltage levels of the first node and the second node.

[0062] In a preferred embodiment, the active area can further include two GIP-internal connecting line parts, each adjacent to the m scanning lines, with a node Q, a node Qb, a node Qh, a transmission pulse output terminal of the preceding stage and a transmission pulse output terminal of the next stage for connecting unit elements that form each stage distributed and arranged in the two GIP-internal connecting line parts.

[0063] In a preferred embodiment, an OLED display panel can comprise an active area containing data lines, sample lines crossing the data lines, and subpixels arranged at each crossing; and a stage of a GIP driver circuit distributed and arranged in multiple unit pixel areas driven by three sample lines in the active area to supply sample pulses to the corresponding sample lines; wherein the stage comprises: a logic unit for controlling voltage levels of a first node and a second node using a transfer pulse from the preceding stage and a transfer pulse from the next stage; a transfer pulse output unit for outputting an input transfer pulse output clock signal as a transfer pulse in response to the voltage levels of the first node and the second node;and first to third sampling pulse output units for the respective output of the first to third input sampling pulse output clock signals to the three sampling lines as sampling pulses in response to the voltage levels of the first node and the second node.

[0064] In a preferred aspect, an OLED display device may include an OLED display panel according to one of the embodiments described above.

[0065] Each of the unit pixel areas can contain at least three subpixels, a GIP part in which an element forming each stage of the GIP control circuit is arranged, and the multiple internal connecting lines arranged in the m GIP internal connecting line parts can extend to the GIP part and be electrically connected to the elements forming each stage.

[0066] The OLED display panel, which has the aforementioned properties according to the present invention, has the following advantages.

[0067] This means that, according to a first embodiment of the present invention, the internal connecting lines in the GIP internal connecting line parts of an OLED display panel can be arranged in the active area.

[0068] Furthermore, according to a second embodiment of the present invention, an OLED display panel can reduce the number of internal interconnect lines arranged in GIP internal interconnect line parts because an output buffer contains multiple sample pulse output units, GIP elements are distributed and arranged in unit pixels driven by as many sample lines as the number of sample pulse output units, and internal interconnect lines (the node Q, the node Qb, the node Qh, interconnect lines connected to the transmit pulse output terminal of the preceding stage and the transmit pulse output terminal of the next stage) are distributed and arranged in GIP internal interconnect line parts adjacent to the sample lines.

[0069] Accordingly, the size of the frame of the OLED display panel according to the first embodiment of the present invention can be reduced.

[0070] Accordingly, the aperture ratio of the OLED display panel according to the second embodiment of the present invention can increase, and the area occupied by the GIP internal connecting line parts can be reduced, thus providing a high-resolution display panel. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram showing the drive circuits of a conventional OLED display device and a relationship between the drive circuits. Fig. Figure 2 is a block diagram of a normal nth GIP stage. Fig. 3 is a waveform diagram that illustrates the operation of the in Fig. Figure 2 shows the nth GIP stage. Fig. Figure 4 is a circuit diagram of a subpixel in the OLED display panel according to an embodiment of the present invention. Fig. Figure 5 is a circuit diagram of a k-th stage of a GIP control circuit according to an embodiment of the present invention. Fig. Figure 6 is a diagram showing a configuration of an active area of ​​an OLED display panel according to a first embodiment of the present invention. Fig. Figure 7 is a diagram showing a detailed configuration of two adjacent unit pixel areas located in the active area of ​​the OLED display panel. Fig. 6 are arranged. Fig. Figure 8 is a diagram for describing internal connecting lines arranged in a GIP internal connecting line part according to the first embodiment of the present invention. Fig. Figure 9 is a block diagram of an nth GIP stage according to a second embodiment of the present invention. Fig. Figure 10 is a diagram for describing internal connecting lines arranged in a GIP internal connecting line part, according to the second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0071] The applicant applied the technology to distribute and arrange GIP control circuits in an active area of ​​a scoreboard in order to reduce the size of a scoreboard bezel (Korean patent application no. 10-2018-0095895).

[0072] The invention described in the Korean patent application (10-2018-0095895) is briefly described below.

[0073] Fig. Figure 4 is a circuit diagram of a subpixel in the OLED display panel according to the present invention, and Fig. Figure 5 is a circuit diagram of a k-th stage of a GIP control circuit according to an embodiment of the present invention.

[0074] As in Fig. As shown in Figure 4, each subpixel of the OLED display panel according to an embodiment of the present invention contains an OLED and a pixel circuit for controlling the OLED.

[0075] The pixel circuit contains a first and a second switching TFT T1 and T2, a storage capacitor Cst and a driver TFT DT.

[0076] The first switching TFT, T1, changes a data voltage DATA in the storage capacitor Cst in response to a sampling pulse signal. The driver TFT DT controls the amount of current supplied to the OLED according to the data voltage charged into the storage capacitor Cst, in order to adjust the amount of light emitted by the OLED. The second switching TFT, T2, detects the threshold voltage and mobility of the driver TFT DT in response to a detection signal.

[0077] The OLED can consist of a first electrode (e.g. anode or cathode), an organic emission layer and a second electrode (e.g. cathode or anode).

[0078] The storage capacitor Cst is electrically connected between the gate and the source of the driver TFT DT to maintain a data voltage, which corresponds to an image signal voltage or a voltage equivalent to it, for a frame time interval.

[0079] Although Fig. Figure 4 shows a 3T1C subpixel configuration consisting of three TFTs T1, T2 and DT and a storage capacitor Cst, the present invention is not limited thereto, and each subpixel of the OLED display panel according to the present invention can have a 4T1C, 4T2C, 5T1C or 5T2C subpixel configuration.

[0080] Meanwhile, as in Fig. Figure 5 shows that the circuit of the k-th stage of the GIP drive circuit according to an embodiment of the present invention comprises: a first and a second waiting-time node control unit 21 and 26, which include the transistors TA, TB, T3qA, T1B, T1C, T5A and T5B and a capacitor C1, selectively store a setting signal CP(k) according to a line selection pulse (LSP), charge a first node Q of the corresponding stage with a first constant voltage GVDD and discharge a second node Qb to a second constant voltage GVSS2 according to a vertical real-time signal (VRT signal) in a waiting time;a first to third drive-time node control unit 23 and 25, containing T1, T1A, T3n, T3nA, T3q, T3, T3A and T5, charging the first node Q of the corresponding stage with the voltage of the transfer pulse CP(k-3) of the third preceding stage according to the transfer pulse CP(k-3), discharging the first node Q and the third node Qh to a second constant voltage GVSS2 according to the transfer pulse CP(k+3) of the third next stage and charging the third node Qh with the first constant voltage GVDD according to the voltage of the first node in a drive time; an inverter 24, containing the transistors T4, T4l, T4q and T5q and a capacitor C2, inverting the voltage of the first node Q and applying the inverted voltage to the second node Qb;an output buffer 27, which contains the pull-up transistors T6cr and T6, the pull-down transistors T7cr and T7 and a bootstrapping capacitor C3, receives a clock signal CRCLK(k) from several clock signals for the transmit pulse output and a clock signal SCCLK(k) from several clock signals for the sample pulse output and outputs a transmit pulse CP(k) and a sample pulse SP(k) according to the voltages of the first node Q and the second node Qb; and a reset unit 22, which contains the transistors T3nB and T3nC and discharges the first node to the second constant voltage GVSS2 according to a reset signal RST that is output from the timing unit during the waiting period.

[0081] The transistors TB, TA and T3q in the first and second waiting-time node control units 21 and 26 are switched on to store the setting signal CP(k) in the capacitor C1 when the LSP is at a high level.

[0082] Additionally, transistors T1C and T5B are switched on to charge the first node Q with the first constant voltage GVDD and discharge the second node Qb to the second constant voltage GVSS2 when the VRT signal is at a high level during the waiting period.

[0083] Transistors T1, T1A, and T5 in the first to third drive-time node control unit 23 and 25 are switched on to charge the first node Q with the transfer pulse CP(k-3) of the third preceding stage and to discharge the second node Qb to the second constant voltage GVSS2 when the transfer pulse CP(k-3) of the third preceding stage is a high level in the drive time. When the first node Q is charged and the second node Qb is discharged in this way, transistor T3q is switched on to charge the third node Qh with the first constant voltage GVDD.

[0084] When the transfer pulse CP(k+3) of the third next stage is at a high level, transistors T3n and T3nA are switched on to discharge the first node Q and the third node Qh to the second constant voltage GVSS2.

[0085] Inverter 24 inverts the voltage of the first node Q and applies the inverted voltage to the second node Qb.

[0086] In output buffer 27, the pull-up transistor T6cr is turned on and the pull-down transistor T7cr is turned off to output a clock signal CRCLK(k) from the multiple clock signals for the transfer pulse output as a transfer pulse CP(k) when the first node Q is at a high level and the second node Qb is at a low level. Furthermore, the pull-up transistor T6 is turned on and the pull-down transistor T7 is turned off to output a clock signal SCCLK(k) from the multiple clock signals for the sample pulse output as a sample pulse SP(k) when the first node Q is at a high level and the second node Qb is at a low level.

[0087] Here, when the clock signal SCCLK(k) for the sample pulse output is applied at a high level, the bootstrapping capacitor C3 of the output buffer 27 pulls the first node Q (couples it), and thus the first node Q has a higher potential.

[0088] In this way, the output buffer 27 outputs the clock signal CRCLK(k) for the transmit pulse output and the clock signal SCCLK(k) for the sample pulse output, which are input into it, as a transmit pulse CL(k) and a sample pulse SP(k) in a state in which the first node Q is being pulled, and thus an output loss can be avoided.

[0089] In the reset unit 22, transistors T3nB and T3nC are switched on to discharge the first node Q to the second constant voltage GVSS2 when the reset signal RST, which is output from the timing unit, is at a high level during the waiting period.

[0090] Although Fig. Figure 5 shows a stage of the GIP control circuit which is driven by 6 phases, the present invention is not limited thereto, and stages of the GIP control circuit can be configured in various ways.

[0091] As in Fig. As shown in Figure 5, each stage of the GIP drive circuit contains 25 transistors and 3 capacitors.

[0092] Accordingly, if an element (transistor or capacitor) that forms the stage of the GIP drive circuit is distributed and arranged in a unit pixel area, the circuit of a stage for driving a gate line (sampling line) can be arranged.

[0093] Fig. Figure 6 is a diagram showing a configuration of the active area of ​​the OLED display panel according to a first embodiment of the present invention, and Fig. Figure 7 is a diagram showing a detailed configuration of two adjacent unit pixels located in the active area of ​​the Fig. The 6 OLED display panels shown are arranged.

[0094] As in the Fig. 6 and Fig. As shown in Figure 7, in the arrangement of the GIP control circuit in the active area of ​​the OLED display panel, a unit pixel area of ​​the active area is subdivided into at least three subpixels R, G, B and W, a GIP part 31 and a GIP-internal interconnection line part 32.

[0095] The at least three subpixels (R, G, B and W) 33 are configured in such a way that several data lines DL1 to DL8, several reference voltage lines Vref and first and second constant voltage lines EVDD and EVSS are arranged in the vertical direction and several gate lines (scan lines) SCAN are arranged in the horizontal direction.

[0096] GIP part 31 corresponds to at least one element (transistor(s) or capacitor(s)) of a stage of the GIP drive circuit. That is, the at least one element (transistor or capacitor) that forms the stage of the GIP drive circuit is distributed and arranged in a unit pixel area consisting of red, green, blue, and white subpixels R, G, B, and W.

[0097] This means that at least one stage ST of the GIP control circuit for controlling a gate line (sampling line) is distributed and arranged in several unit pixel areas that are controlled by a gate line (sampling line).

[0098] The GIP internal interconnection line section 32 is an area in which interconnection lines (a node Q, a node QB, a node Qh, a transmission pulse output terminal of the preceding stage, a transmission pulse output terminal of the next stage, etc.) are arranged for connecting elements in a stage of the GIP control circuit.

[0099] As described above, since the GIP drive circuit is located in the active area, the multiple data lines DL1 to DL8 and the reference voltage lines Vref for driving the subpixels R, G, B and W are arranged in the vertical direction, as shown in Fig. 7 is shown.

[0100] Additionally, since GIP part 31 corresponds to at least one element (transistor or capacitor) that forms a stage of the GIP drive circuit, one of the signals LSP, VRT, GVDD, GVSS0, GVSS1, GVSS2, VST, CRCLK and SCCLK, which are in Fig. 5 are shown, attached to GIP part 31.

[0101] Furthermore, in the OLED display panel according to the first embodiment of the present invention, the circuit of a stage for driving a gate line (scanning line) is distributed and arranged in unit pixel areas driven by the gate line (scanning line), and thus all connecting lines (the node Q, the node Qb, the node Qh, the transmission pulse output terminal of the preceding stage, the transmission pulse output terminal of the next stage, connecting lines between elements, etc.) for connecting elements in the stage of the GIP drive circuit must be arranged in the GIP-internal connecting line part 32, which corresponds to the gate line (scanning line).

[0102] Fig. Figure 8 shows internal connecting lines arranged in the GIP internal connecting line part 32, according to the first embodiment of the present invention.

[0103] In Fig. 5 is, for example, a signal line CP(k+3) to which the transmission pulse output from the third next stage is applied, connected to the gate electrode of transistor T3n, node Q is connected to the source electrode of transistor T3n, and node Qh is connected to the drain electrode of transistor T3n.

[0104] Accordingly, if it is assumed that the transistor T3n, which is in Fig. 5 is shown, in a GIP part 31, at least the signal line CP(k+3), to which the transmission pulse output from the third next stage is applied, the node Q and the node Qb are arranged in the GIP-internal connection line part 32.

[0105] In this way, in the OLED display panel according to the first embodiment of the present invention, the circuit of a stage for driving a gate line (scanning line) in unit pixel areas driven by the gate line (scanning line) is arranged, and thus a maximum of four GIP-internal interconnection lines (the node Q, the node Qb, the node Qh, the transmit pulse output terminal of the preceding stage, the transmit pulse output terminal of the next stage, interconnection lines between elements, etc.) are arranged in the GIP-internal interconnection line part 32 of each line. For example, an interconnection line between elements corresponds to an interconnection line between the gate electrode of transistor T4 and the drain electrode of transistor T4l in Fig. 5.

[0106] Accordingly, the aperture ratio of the OLED display panel according to the first embodiment of the present invention decreases, and the area occupied by the GIP internal connecting line parts 32 increases, and thus the OLED display panel is not suitable for high resolution.

[0107] To solve this problem, in an OLED display panel and an OLED display device according to a second embodiment of the present invention, the stages of the GIP drive circuit are arranged in the pixel array to increase the aperture ratio of the OLED display panel while providing a narrow bezel, and to reduce the area occupied by the GIP internal connecting line parts, thus achieving high resolution.

[0108] Fig. Figure 9 is a block diagram of the nth GIP stage according to the second embodiment of the present invention.

[0109] In the OLED display panel according to the second embodiment of the present invention, the stages of the GIP drive circuit are arranged in the pixel array in such a way that a stage containing multiple sampling pulse output units is configured for unit pixels that are driven by multiple sampling lines.

[0110] That is, the circuit of the k-th stage of the GIP control circuit according to an embodiment of the present invention includes the first and second waiting time node control units 21 and 26, the first to third drive time node control units 23 and 25, the inverter 24, the output buffer 27 and the reset unit 22, as described above with reference to Fig. 5 is described.

[0111] However, the OLED display panel according to the second embodiment of the present invention has the stages of the GIP drive circuit arranged in the pixel array, wherein the first and second wait-time node control units 21 and 26, the first to third drive-time node control units 23 and 25, the inverter 24 and the reset unit 22, which were described above with reference to Fig. 5 are described, and the output buffer 27, which contains a transmit pulse output unit and several sample pulse output units, is arranged in unit pixels that are driven by several sample lines, as in Fig. 9 is shown.

[0112] In Fig. 9 are the first and second waiting time node control units 21 and 26, the first to third drive time node control units 23 and 25, the inverter 24 and the reset unit 22, which are described above with reference to Fig. 5 are described, represented by a logic unit S / R1.

[0113] The logic unit S / R1 controls the voltage levels of the first node Q and the second node Qb using the line selection signal LSP, the setting signal CP(k), the vertical real-time signal VRT, the transfer pulse CP(k-3) of the m-th preceding stage, the transfer pulse CP(k+3) of the m-th next stage, and the reset signal RST, as shown in Fig. 5 is described.

[0114] Additionally, the output buffer 27 contains a transmission pulse output unit and several sampling pulse output units.

[0115] That is, the output buffer 27 contains: a transfer pulse output unit consisting of a pull-up transistor T6cr and a pull-down transistor T7cr and is configured such that the pull-up transistor T6cr is turned on and the pull-down transistor T7cr is turned off to output a clock signal CRCLK1 from the multiple transfer pulse output clock signals as a transfer pulse CP(1) when the first node Q is at a high level and the second node Qb is at a low level;a first sample pulse output unit consisting of a first pull-up transistor T6-1, a first pull-down transistor T7-1 and a first bootstrapping capacitor Cq1 and configured such that the first pull-up transistor T6-1 is turned on and the first pull-down transistor T7-1 is turned off to output a clock signal SCCLK(1) from the multiple sample pulse output clock signals as a sample pulse SP(1) when the first node Q is at a high level and the second node Qb is at a low level;a second sample pulse output unit consisting of a second pull-up transistor T6-2, a second pull-down transistor T7-2 and a second bootstrapping capacitor Cq2, configured such that the second pull-up transistor T6-2 is turned on and the second pull-down transistor T7-2 is turned off to output a clock signal SCCLK(2) from the multiple sample pulse output clock signals as a sample pulse SP(2) when the first node Q is a high level and the second node Qb is a low level;a third sample pulse output unit, consisting of a third pull-up transistor T6-3, a third pull-down transistor T7-3 and a third bootstrapping capacitor Cq3, configured such that the first pull-up transistor T6-3 is turned on and the first pull-down transistor T7-3 is turned off to output a clock signal SCCLK(3) from the multiple sample pulse output clock signals as a sample pulse SP(3) when the first node Q is at a high level and the second node Qb is at a low level;a fourth sample pulse output unit, consisting of a fourth pull-up transistor T6-4, a fourth pull-down transistor T7-4 and a fourth bootstrapping capacitor Cq4, configured such that the fourth pull-up transistor T6-4 is turned on and the fourth pull-down transistor T7-4 is turned off to output a clock signal SCCLK(4) from the multiple sample pulse output clock signals as a sample pulse SP(4) when the first node Q is at a high level and the second node Qb is at a low level;and a fifth sample pulse output unit, consisting of a fifth pull-up transistor T6-5, a fifth pull-down transistor T7-5 and a fifth bootstrapping capacitor Cq5, configured such that the fifth pull-up transistor T6-5 is turned on and the fifth pull-down transistor T7-5 is turned off to output a clock signal SCCLK(5) from the multiple sample pulse output clock signals as a single sample pulse SP(5) when the first node Q is at a high level and the second node Qb is at a low level.

[0116] If the output buffer 27 contains one transmit pulse output unit and five sample pulse output units, as in Fig. As shown in Figure 9, the OLED display panel according to the second embodiment of the present invention contains elements that form the stage comprising the logic unit S / R1 and the output buffer 27, which are shown in Figure 9. Fig. 9 are shown, distributed and arranged in unit pixels, which are controlled by five scanning lines.

[0117] Although the output buffer 27 contains one transmit pulse output unit and five sample pulse output units in Fig. 9 contains, the present invention is not limited thereto, and the output buffer 27 can contain a transmission pulse output unit and at least two sampling pulse output units.

[0118] If the output buffer 27 contains a transmission pulse output unit and two sampling pulse output units, the elements forming the stage comprising the logic unit S / R1 and the output buffer 27 in the OLED display panel according to the second embodiment of the present invention are Fig. 9 are shown, distributed and arranged in unit pixels, which are controlled by two scanning lines.

[0119] Furthermore, in the OLED display panel according to the second embodiment of the present invention, when the output buffer 27 contains a transmission pulse output unit and three sampling pulse output units, the elements that form the stage comprising the logic unit S / R1 and the output buffer 27 are Fig. 9 are shown, distributed and arranged in unit pixels, which are controlled by three scanning lines.

[0120] That is, in the OLED display panel according to the second embodiment of the present invention, the elements that form the stage comprising the logic unit S / R1 and the output buffer 27, which are in Fig. 9 are shown, distributed and arranged in unit pixels, which are controlled by as many sampling lines as the number of sampling pulse output units.

[0121] The routing of the GIP internal connection line parts, when the stage having the aforementioned configuration is located in the relevant area, is described below.

[0122] Fig. Figure 10 is a diagram for describing internal connecting lines arranged in the GIP internal connecting line parts according to the second embodiment of the present invention.

[0123] Fig. 10 represents internal connection lines when the output buffer 27 contains one transmit pulse output unit and five sample pulse output units, as in Fig. 9 is shown.

[0124] That is, the elements that form the stage containing the logic unit S / R1 and the output buffer 27, which are in Fig. The units shown in 9 are distributed and arranged in arbitrary unit pixels among the unit pixels that are controlled by the first to fifth scanning lines SCAN1 to SCAN5.

[0125] Additionally, one of the internal connecting lines (the node Q, the node Qb, the node Qh, the transmission pulse output terminal of the preceding stage, the transmission pulse output terminal of the next stage, connecting lines between elements, etc.) is arranged in each GIP internal connecting line part 32 adjacent to each scanning line SCAN1 to SCAN5.

[0126] That is, node Q is located in the GIP-internal connection line part 32 adjacent to the first scanning line SCAN1, node Qb is located in the GIP-internal connection line part 32 adjacent to the second scanning line SCAN2, the connection line CP(K+3), which is connected to the transmission pulse output terminal of the next stage, is located in the GIP-internal connection line part 32 adjacent to the third scanning line SCAN3, node Qb is located in the GIP-internal connection line part 32 adjacent to the fourth scanning line SCAN4, and the connection line CP(k-3), which is connected to the transmission pulse output terminal of the preceding stage, is located in the GIP-internal connection line part 32 adjacent to the fifth scanning line SCAN5.

[0127] Additionally, the elements that form the stage containing the logic unit S / R1 and the output buffer 27 are located in Fig. 9 are shown, distributed and arranged in any unit pixels among the unit pixels that are driven by the first to fifth scanning lines SCAN1 to SCAN5, as described above.

[0128] For example, the signal line CP(k+3), to which the transmission pulse output from the third next stage is applied, is connected to the gate electrode of transistor T3n (see Fig. 5) among the elements that form the stage which includes the logic unit S / R1 and the output buffer 27, which are in Fig. 9 are shown, connected, node Q is connected to the source electrode of transistor T3n, and node Qh is connected to the drain electrode of transistor T3n.

[0129] Accordingly, if the in Fig. 5 transistor T3n is arranged in the GIP part 31, node Q, which is arranged in the GIP-internal connecting line part 32 adjacent to the first scanning line SCAN1, the connecting line CP(k+3), which is connected to the transmission pulse output terminal of the next stage, which is arranged in the GIP-internal connecting line part 32 adjacent to the third scanning line SCNA3, and node Qh, which is arranged in the GIP-internal connecting line part 32 adjacent to the fourth scanning line SCAN4, is connected to transistor T3n as shown in Fig. 10 is shown.

[0130] Additionally, the signal line CP(k-3), to which the transmission pulse output from the third preceding stage is applied, is connected to the gate electrode and the source electrode of transistor T1 (see Fig. 5) among the elements that form the stage which includes the logic unit S / R1 and the output buffer 27, which are in Fig. 9 are shown, connected, and node Qh is connected to the source electrode of transistor T1.

[0131] Accordingly, if the in Fig. 5 transistor T1 is arranged in the GIP part 31, node Qh, which is arranged in the GIP-internal connecting line part 32 adjacent to the fourth scanning line SCAN4, and the connecting line CP(k-3), which is connected to the transmit pulse output terminal of the preceding stage, which is arranged in the GIP-internal connecting line part 32 adjacent to the fifth scanning line SCAN4, is connected to transistor T1, as shown in Fig. 10 is shown.

[0132] Since the elements that form the stage, which includes the logic unit S / R1 and the output buffer 27, which are in Fig. As shown in Figure 9, in any unit pixels among the unit pixels controlled by the first to fifth scanning lines SCAN1 to SCAN5, distributed and arranged as described above, GIP elements are not located in the GIP parts 31 of all unit pixels. Accordingly, signal lines extending to the GIP parts 31 and located in the GIP-internal connecting line parts 32 can be connected to the GIP elements.

[0133] Although Fig. 10 shows that the unit elements that form the stage, which includes the logic unit S / R1 and the output buffer 27, which are in Fig. The present invention is not limited to the unit elements that form the stage being distributed and arranged in any unit pixels among the unit pixels controlled by the first to fifth scanning lines SCAN1 to SCAN5, as shown in Figure 9.

[0134] If the in Fig. The output buffer 27 shown in Figure 9 contains a transmission pulse output unit and two sampling pulse output units. In the OLED display panel according to the second embodiment of the present invention, these elements form the stage comprising the logic unit S / R1 and the output buffer 2, which are shown in Figure 9. Fig. Figure 9 shows the units distributed and arranged in unit pixels controlled by the first and second scanning lines SCAN1 and SCAN2. Additionally, the internal interconnection lines (node ​​Q, node Qb, node Qh, the transmission pulse output terminal of the preceding stage, the transmission pulse output terminal of the next stage, interconnection lines between elements, etc.) are distributed and arranged in two GIP internal interconnection line sections 32 adjacent to the first and second scanning lines SCAN1 to SCAN2.

[0135] If the in Fig. The output buffer 27 shown in Figure 9 contains a transmission pulse output unit and three sampling pulse output units. In the OLED display panel according to the second embodiment of the present invention, these elements form the stage comprising the logic unit S / R1 and the output buffer 27, which are shown in Figure 9. Fig. Figure 9 shows the units distributed and arranged in unit pixels controlled by the first to third scanning lines SCAN1 to SCAN3. Additionally, the internal interconnection lines (node ​​Q, node Qb, node Qh, the transmission pulse output terminal of the preceding stage, the transmission pulse output terminal of the next stage, interconnection lines between elements, etc.) are distributed and arranged in three GIP internal interconnection line sections 32 adjacent to the first to third scanning lines SCAN1 to SCAN3.

[0136] That is, in the OLED display panel according to the second embodiment of the present invention, the elements that form the stage comprising the logic unit S / R1 and the output buffer 27, which are in Fig. 9 are shown, distributed and arranged in unit pixels driven by as many sampling lines as the number of sampling pulse output units contained in the output buffer 27, and the internal interconnect lines (the node Q, the node Qb, the node Qh, the transmit pulse output terminal of the preceding stage, the transmit pulse output terminal of the next stage, interconnect lines between elements, etc.) are distributed and arranged in GIP internal interconnect line parts 32 adjacent to the corresponding sampling lines.

[0137] As described above, in the OLED display panel according to the second embodiment of the present invention, the Fig.9. Output buffers are shown. Several sample pulse output units. GIP elements are distributed and arranged in unit pixels, which are driven by as many sample lines as the number of sample pulse output units. The internal interconnect lines (the node Q, the node Qb, the node Qh, the transmit pulse output terminal of the preceding stage, the transmit pulse output terminal of the next stage, interconnect lines between elements, etc.) are distributed and arranged in GIP internal interconnect line parts 32 adjacent to the corresponding sample lines. Thus, the number of internal interconnect lines arranged in the GIP internal interconnect line parts 32 can be reduced.

[0138] Accordingly, the aperture ratio of the OLED display panel according to the second embodiment of the present invention can increase, and the area occupied by the GIP internal connecting lines 32 can be reduced, and thus a high-resolution display panel can be realized.

[0139] Experts will recognize that various modifications and variations can be made to the present invention without altering the scope of protection of the present invention as defined by the foregoing description. Accordingly, the scope of protection of the invention should be determined by the appended claims and their legal equivalents, and not by the foregoing description.

Claims

[1] OLED display panel comprising the following: an active area (AA) containing data lines (139), sampling lines (149) that cross the data lines, and subpixels arranged at each crossing; and a stage of a GIP drive circuit which is distributed and arranged in several unit pixel areas which are driven by m (where m is a natural number greater than 1) sampling lines (149) in the active area (AA) to supply sampling pulses to the corresponding sampling lines (149), wherein the active area (AA) further includes m GIP-internal connecting line parts (32) each adjacent to the m scanning lines (149). [2] OLED display panel according to claim 1, wherein an internal GIP interconnection part (32) contains several internal interconnection lines (Q, Qb; CP(k+3), Qh, CP(k-3)) for connecting elements (31) that form each stage, wherein the several internal interconnection lines (Q, Qb; CP(k+3), Qh, CP(k-3)) are distributed and arranged in the m GIP internal interconnection parts (32). [3] OLED display panel according to claim 1 or 2, wherein each stage contains: a logic unit (S / R1) for controlling voltage levels of a first node (Q) and a second node (Qb) using a transfer pulse of the preceding stage (CP(k-3)) and a transfer pulse of the next stage (CP(k+3)) and an output buffer (27). [4] OLED display panel according to claim 3, wherein the output buffer (27) includes a transmission pulse output unit for outputting an input transmission pulse output clock signal as a transmission pulse in response to the voltage levels of the first node (Q) and the second node (Qb); and m sampling pulse output units for outputting input sampling pulse output clock signals to the m sampling lines as sampling pulses in response to the voltage levels of the first node and the second node. [5] OLED display panel according to one of claims 1-4, wherein each of the unit pixel areas contains at least three subpixels (33) and a GIP part (31) in which at least one element forming each stage of the GIP control circuit is arranged, and the multiple internal connecting lines (Q, Qb; CP(k+3), Qh, CP(k-3)) arranged in the m GIP internal connecting line parts (32) extend to the GIP part (31) and are electrically connected to the elements forming each stage. [6] OLED display panel according to one of the preceding claims, wherein m GIP-internal connecting line parts (32) are arranged adjacent to the m scanning lines and a node Q, a node Qb, a node Qh, a transmission pulse output terminal of the preceding stage and a transmission pulse output terminal of the next stage for connecting the elements that form each stage are distributed and arranged in the m GIP-internal connecting line parts. [7] OLED display panel according to one of the preceding claims, wherein a GIP internal connecting line part (32) contains m internal connecting lines, while one of the m internal connecting lines is arranged parallel to a scanning line from the m scanning lines. [8] OLED display panel comprising the following: an active area (AA) containing data lines (139), sampling lines (149) that cross the data lines, and subpixels arranged at each crossing; and a stage of a GIP drive circuit, which is distributed and arranged in several unit pixel areas, which are driven by five scanning lines (SCAN1-SCAN5) in the active area (AA) to supply scanning pulses to the corresponding scanning lines, wherein each stage contains: a logic unit (S / R1) for controlling voltage levels of a first node (Q) and a second node (Qb) using a transmission pulse from the preceding stage and a transmission pulse from the next stage; a transmission pulse output unit for outputting an input transmission pulse output clock signal (CRCLK1) as a transmission pulse in response to the voltage levels of the first node (Q) and the second node (Qb); and First to fifth sampling pulse output units for the respective output of first to fifth input sampling pulse output clock signals (SCCLK1-SCCLK5) to the five sampling lines (SCAN1-SCAN5) as sampling pulses in response to the voltage levels of the first node (Q) and the second node (Qb). [9] OLED display panel according to claim 8, wherein five GIP internal interconnection line parts are included in areas adjacent to the m scanning lines, and a node Q, a node Qb, a node Qh, a preceding stage transmit pulse output terminal and a next stage transmit pulse output terminal for connecting the elements (31) that form each stage are distributed and arranged in each GIP internal interconnection line part (32). [10] OLED display panel comprising the following: an active area (AA) containing data lines (139), sampling lines (149) that cross the data lines, and subpixels arranged at each crossing; and a stage of a GIP drive circuit, which is distributed and arranged in several unit pixel areas, which are driven by two scanning lines (SCAN1, SCAN2) in the active area (AA) to supply scanning pulses to the corresponding scanning lines, wherein each stage contains: a logic unit (S / R1) for controlling voltage levels of a first node (Q) and a second node (Qb) using a transmission pulse from the preceding stage and a transmission pulse from the next stage; a transmission pulse output unit for outputting an input transmission pulse output clock signal (CRCLK1) as a transmission pulse in response to the voltage levels of the first node and the second node; and First and second sampling pulse output units for the respective output of first and second input sampling pulse output clock signals (SCCLK1-SCCLK2) to the two sampling lines (SCAN1, SCAN2) as sampling pulses in response to the voltage levels of the first node (Q) and the second node (Qb). [11] OLED display panel according to claim 10, wherein the active area (AA) further comprises two GIP-internal connecting line parts (32) each adjacent to the two scanning lines (SCAN1, SCAN2), a node Q, a node Qb, a node Qh, a transmission pulse output terminal of the preceding stage and a transmission pulse output terminal of the next stage for connecting elements forming each stage, distributed and arranged in the two GIP-internal connecting line parts (32). [12] OLED display panel comprising the following: an active area (AA) containing data lines (139), sampling lines (149) that cross the data lines, and subpixels arranged at each crossing; and a stage of a GIP drive circuit, which is distributed and arranged in several unit pixel areas, which are driven by three scanning lines (SCAN1, SCAN2, SCAN3) in the active area (AA) to supply scanning pulses to the corresponding scanning lines, wherein the stage contains: a logic unit (S / R1) for controlling voltage levels of a first node (Q) and a second node (Qb) using a transmission pulse from the preceding stage and a transmission pulse from the next stage; a transmission pulse output unit for outputting an input transmission pulse output clock signal (CRCLK1) as a transmission pulse in response to the voltage levels of the first node (Q) and the second node (Qb); and First to third sampling pulse output units for the respective output of first to third input sampling pulse output clock signals (SCCLK1-SCCLK3) to the three sampling lines (SCAN1, SCAN2, SCAN3) as sampling pulses in response to the voltage levels of the first node (Q) and the second node (Qb). [13] OLED display device comprising an OLED display panel according to any one of claims 1-12.

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