FLEXIBLE HIGH AVAILABILITY COMPUTING WITH PARALLEL CONFIGURABLE FABRICS

Abstract

A composable computing platform (100) comprising the following: a first parallel interconnection layer (260, 262, 264), comprising a first plurality of switching structure branches (270, 273, 275) which provide parallel connections via the first parallel interconnection layer (260, 262, 264); and a second parallel interconnection structure layer (260, 262, 264) comprising a second plurality of switching structure branches (271, 274, 276) providing parallel connections via the second parallel interconnection structure layer (260, 262, 264); where: a first switching structure branch of the first plurality of switching structure branches (270, 273, 275) and a first switching structure branch of the second plurality of switching structure branches (271, 274, 276) are communicatively connected to each other and comprise a first switching structure, a second switching structure branch of the first plurality of switching structure branches (270, 273, 275) and a second switching structure branch of the second plurality of switching structure branches (271, 274, 276) are communicatively connected to each other and comprise a second switching structure, and The first switching structure and the second switching structure are isolated from each other and provide independent paths for routing packets.

Description

BACKGROUND

[0001] Current custom configuration techniques typically involve selecting which components (e.g., processor, memory, input / output interfaces, storage devices) are connected within a physical enclosure. The connection can be made, for example, via a PCI-compliant (Peripheral Component Interconnect) bus to which the components can be attached. PCI standards are available from the PCI Special Interest Group (PCI-SIG) in Beaverton, Oregon, USA. By providing a standard interface, various components can be interconnected to achieve the desired system configuration. However, these architectures are not optimally configured in terms of efficient use of computing functions, resource utilization, and / or fault tolerance.US 2004 / 0 095 927 A1 describes a method for dynamically updating routing information within a multi-stage network switch fabric without requiring conventional handshake protocols. US 2020 / 0 341 919 A1 describes a system for dynamically configuring communication paths between multiple processors and peripheral devices in a server. US 2004 / 0 010 600 A1 describes a system for registering components within a Storage Area Network (SAN). US 2010 / 0 165 984 A1 describes a modular and scalable architecture for building large, multi-stage network switches that can be expanded over time with minimal or no downtime. An object of the invention is to propose modular computing platforms for flexible, highly available computing with parallel, configurable structures.This problem is solved by a composable computing platform according to claim 1, a composable computing platform according to claim 10 and a composable computing platform according to claim 19. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Embodiments of the invention are shown by way of example and without limitation in the figures of the accompanying drawings, in which the same reference numerals refer to similar elements. Fig. Figure 1 is a block diagram of an embodiment of a composable computer environment with a single parallel interconnect structure. Fig. Figure 2 is a block diagram of an embodiment of a composable computer environment with stacked connection structures. Fig. Figure 3 is a logical representation of an embodiment of an architecture that can provide flexible, configurable systems using parallel interconnection structures. Fig. Figure 4 is a conceptual diagram of an embodiment of an infrastructure resource pool that provides composable resources from which resource instances or complete devices can be assembled and configured to create logical servers that operate like traditional servers. Fig. Figure 5 is a block diagram of an embodiment of a trusted composable computing architecture consisting of trusted composable infrastructure resources with intelligent modules, simple modules, and parallel interconnect fabrics from which server modules can extend their IO capabilities or create logical servers. Fig. Figure 6 is a block diagram of an embodiment of an infrastructure resource pool that provides composable infrastructure resources in a hardened, secure environment where logical server resource bindings are cryptographically linked via the parallel link structure. Fig. Figure 7 is an example of a packet frame header of a parallel link structure that can be used with the composable architecture described here for a parallel PCIe link structure built with standard PCIe switches. Fig. Figure 8 is a flowchart of an implementation of a technique for configuring a computing infrastructure resource in an environment that provides composable resources. Fig. Figure 9 is a flowchart of an embodiment of a technique for configuring a computing resource in an environment that provides composable resources. Fig. Figure 10 is a conceptual diagram of an embodiment of an infrastructure resource pool that provides composable infrastructure resources configured as a set of logical servers. Fig. Figure 11 is a conceptual diagram of logical servers configured to use peer-to-peer communication over the parallel interconnect networks of the composable architecture. DETAILED DESCRIPTION

[0003] The following description includes numerous specific details. However, embodiments of the invention can also be carried out without these specific details. In other cases, known structures and techniques have not been described in detail so as not to impair the understanding of this description.

[0004] As described in more detail below, an efficient and configurable computing environment, referred to as a composable infrastructure architecture, can be provided that is modular, extensible, and highly available. This composable infrastructure architecture is not limited by distance and utilizes parallel interconnect structures that can provide both parallel connections and enhanced fault tolerance.

[0005] In various embodiments, the composable architecture described here can provide the functionality to logically connect simple components, e.g., a computing module (e.g., processor(s), memory), with I / O modules (e.g., Peripheral Component Interconnect Express or "PCIe", graphics processing units or "GPUs", network interface cards or "NICs", memory controllers, expansion memory, Non-Volatile Memory Express or "NVMe") via a carrier switching fabric (e.g., PCIe, InfiniBand or "IB", Generation Z or "GenZ"), so that the logically connected components function (partially or completely) as an equivalent PC server (a logical server).

[0006] As described in more detail below, this functionality can be provided through a single interface, such as an environment application programming interface (API). This allows the environment functionality (e.g., composition, binding, enforcement of software license agreements (SLAs)) to be controlled through a single interface and facilitates the use of resource adapters (RAs) that provide interfaces to individual modules within the computational environment. Thus, the composable environment can be functionally treated as a single configurable device accessible through a single interface.

[0007] In some embodiments, multiple parallel interconnect fabrics can be used to create a single integrated structure that can provide greater fault tolerance, redundancy, and / or parallelism than the individual parallel interconnect fabrics. The individual physical connections can be managed by their own managers and protocols and be fully addressable, so that each RA can be reached by other RAs. Thus, the RAs can be considered "multi-homed" to each of the parallel interconnect fabrics, providing an interface to each interconnect fabric. In this way, the physical interconnect fabrics can be managed by their own managers and protocols, and the RAs can be reached by any other RA in the environment, providing hardware failover functionality.In some implementations, individual physical connection managers can be grouped into clusters to provide a single interface to the integrated structure.

[0008] As described in more detail below, RAs can communicate with each other and connect using the appropriate addressing scheme for the underlying physical structure (e.g., Ethernet can use MAC addresses, PCIe can utilize bus device functions). The unified management structure (and the corresponding interface) can be used to communicate with different RAs about how they should connect within the composable environment.

[0009] These mechanisms and structures allow a system administrator (or other entity) to describe the desired functionality at a relatively high level using the API, and the underlying management units and supporting hardware within the environment can then provide that functionality. Furthermore, the environment's configuration can be updated / modified via the API if conditions or requirements change.

[0010] In various embodiments, the composable architecture described here can provide the functionality to logically connect simple components, e.g., a computing module (e.g., processor(s), memory), with I / O modules (e.g., Peripheral Component Interconnect Express or "PCIe", graphics processing units or "GPUs", network interface cards or "NICs", memory controllers, expansion memory, Non-Volatile Memory Express or "NVMe") via a carrier switching fabric (e.g., PCIe, InfiniBand or "IB", Generation Z or "GenZ"), so that the logically connected components (partially or completely) function, for example, as an equivalent PC server (a logical server).

[0011] In various embodiments described here, a parallel interconnect architecture based on Peripheral Component Interconnect (PCI)-compatible interfaces can provide configurable, fault-tolerant connections between multiple resources and compute nodes. Subsequent PCI standards can also be used. For example, related standards such as Compute Express Link (CXL) can be used with the techniques and architectures described here. CXL is an open standard for high-speed processor-to-device and processor-to-memory interconnects, provided by the Compute Express Link Consortium in Beaverton, Oregon. Similarly, Gen Z interconnect standards can also be supported. The Gen Z standards are provided by the Gen Z Consortium.

[0012] In the described embodiments, the improved functionality can be achieved through the use of one or more resource adapters (RAs – e.g., an application-specific integrated circuit or an ASIC module). In one embodiment, RAs can be configured in one of three modes: 1) Compute-RA (C-RA); 2) Target-RA (T-RA); and 3) Stacking-RA (S-RA). Compute-RAs (e.g., adapters for compute resources) or Target-RAs (e.g., target I / O resource adapters) can provide hardware protocol connections that bridge the gap between the local module connection (e.g., PCIe, CXL) and the carrier switching fabric (e.g., PCIe, IB, GenZ).

[0013] In the various embodiments described here, each RA provides a single control surface (i.e., a programming interface) that extends the capability of the carrier switching fabric, e.g., using PCIe switches, to a hardware-resistant (e.g., hardware failover, meaning no higher-level management software is required to orchestrate failover) fabric across multiple isolated and independent paths to provide a parallel connectivity fabric. Furthermore, RAs can enhance the capability of the carrier switching fabric by providing end-to-end quality of service (QoS), e.g., through cryptographic isolation between bindings and logically bound resources, such as logical servers, which can be connected to an external cryptographic key management service.

[0014] In other implementations, the connections can also be extended to standard intelligent infrastructure resources such as conventional PC servers or storage arrays, enabling flexible I / O expansion or peer-to-peer communication over this parallel connection structure. For example, each isolated fabric can be managed independently of its own fabric managers, but work together as a cluster to provide a unified interface and experience.

[0015] Due to fabric independence, the fabric type or fabric latency need not be identical. Consequently, in parallel fabrics, only the fabric nodes need to be addressable (e.g., for the RAs) to be reachable on the fabric. In some implementations, a stacking RA (S-RA) can be used as a bridge between the two parallel fabric domains as parallel interconnect fabrics grow or are extended to provide scalability. This means, for example, that a fabric branch in Parallel Interconnect Fabric A is connected to a fabric branch in Parallel Interconnect Fabric B using an S-RA to resolve address resolution and quality of service (QoS) considerations within the target parallel fabric domain.

[0016] In some configurations, all parallel fabric domains with the same fabric node addressability for the RA domain can be designated as an infrastructure resource pool, independent of the number of parallel fabrics. Using programmatic bindings, all resources can be managed in real time and on demand, supporting modern intelligent applications that require binding new resources (computing resources) or creating new compute resources and logical server nodes. Furthermore, unused resources from intelligent applications can be returned to the free pool for reassignment.

[0017] The described modularity can be achieved, for example, by not restricting input / output components to the physical device they support, by allowing compute nodes, resources, switches, and routers to be dynamically added to the architecture, and by enabling the various components to be interconnected over any distance (e.g., chip-to-chip, board-to-board, via copper cables, fiber optic cables, or the internet). In various implementations, an application-transparent alternative path partitioning can ensure independence and fault isolation. Furthermore, a single management footprint can be provided.

[0018] Conceptually, the architecture can be viewed as PCI-based middle management of I / O devices, including, for example, NVMe storage devices and / or PCIe storage devices. Furthermore, the architecture described here can provide fault tolerance for non-fault-tolerant devices and redundancy for PCIe-based systems (or other interconnect architectures that do not offer native redundancy). That is, the architecture described here provides I / O resilience in systems that do not inherently support fault tolerance and I / O resilience.

[0019] PCIe, for example, is based on a point-to-point topology with separate serial links connecting each device to the hosts. However, the PCIe standards do not offer native support for fault tolerance in the event of a link failure. Furthermore, providing fault tolerance through redundant links leads to inefficient resource utilization. Therefore, the techniques and mechanisms described here allow mature, widely adopted technologies like PCIe to be used to deliver improved, more efficient, and more advanced architectures.

[0020] In some embodiments, a first switch fabric routes packets between compute resources and I / O resources. Each compute resource has a compute resource adapter (C-RA) to configure a packet header with a destination identifier (with a corresponding first frame identifier) ​​and a source identifier (with a corresponding second frame identifier). Each I / O resource has a destination resource adapter (T-RA) to manage the packet based on the header. A second switch fabric also routes packets between the compute resources and the I / O resources.

[0021] One or more fabric managers can be coupled to the first and second switch fabrics to route packets in parallel across both fabrics when packet transmission errors are below a predefined error rate, and to dynamically reconfigure packet routing across both fabrics when packet transmission errors exceed the predefined error rate. The fabric manager(s) can also be used to enable more sophisticated resource allocation by supporting and managing a composable computing environment.

[0022] Fig. Figure 1 is a block diagram of an embodiment of a composable computer environment with a single parallel interconnect structure. The example in Fig. 1 configures one or more logical servers from resources of the composable computing environment; however, this is only one example of the types of configurations that can be supported.

[0023] In the example of Fig. 1. The composable resource manager 120 (which may be a cluster of composable resource managers) can provide management connectivity for controlling the parallel connection structure(s) 110 as well as for the compute module(s) 150 and the target module(s) 160. In some implementations, the composable resource manager 120 may also have management connectivity (e.g., 154, 164) to the resource adapters (RAs) in the compute and target modules (e.g., 152, 162), but in the example of Fig. 1. The RAs 152 and 162 are controlled via the Parallel Interconnect Fabric (PIF) 110 using APIs from fabric management modules (e.g., 130, 135, 138). The Parallel Interconnect Fabric 110 can comprise any number of fabric structures (e.g., 112, 114, 116) with fabric management modules (e.g., 130, 135, 138).

[0024] In the example of Fig. 1. The user interface is represented by API / GUI / Script 125 to the Composable Resource Manager. In one embodiment, the interface between the Composable Resource Manager and the API / GUI / Script can provide the connected compute and target modules (e.g., 150, 160) with information, status, and control over the entire topology of the parallel interconnect structure 110. In one embodiment, the Composable Resource Manager API 125 contains information, health status, and control of the PIF 110 and can contain information, health status, and control of each RA connected to the PIF 110, as in the example of Fig. 1 is the case.

[0025] In one embodiment, the composable resource manager 120 manages the RA modules (e.g., 152, 162) directly via one or more APIs specific to the information, health status, and control of the various RAs. In another embodiment, the composable resource manager 120 is also able to associate each RA with either a compute module (e.g., 150) or a target module (e.g., 160). In the example of Fig. 1. The Composable Resource Manager 120 has a management connection to the compute module 150 and the target module 160, and the API of these connections provides information about the module identity, the inventory of the module including the identity of the Fabric RA and other resources within the module.

[0026] An example of a management unit that can provide information, status information, and control in the compute module 150 or the target module 160 is a Baseboard Management Controller (BMC). In one embodiment, the Composable Resource Manager 120 can discover the parallel connection structure(s) 110 via management connections (e.g., 122, 126, 128) to the Fabric Managers (e.g., 130, 135, 138), which, for example, contain the complete connection topology to all RAs.

[0027] The Composable Resource Manager discovers the connection of each resource adapter to the Parallel Interconnect Fabric and the hosting compute or target module either through the Fabric Manager(s) or through the management connection to each compute or target module management API. In one embodiment, the Composable Resource Manager can also discover resources within each compute or target module to create a complete inventory of the resources and the Parallel Interconnect Fabric topology, and can store this information in the database, in memory, or a combination thereof.

[0028] In one embodiment, the user interface 125 of the Composable Resource Manager 120 can query information and the health status of the entire topology or request a change to the resource(s) for any computation module. The Composable Resource Manager 120 can respond to a requested addition or subtraction of resources by identifying resources that can be reconfigured on the parallel link structure to fulfill the request and complete the reconfiguration, or by responding that the request cannot be fulfilled or that an error occurred during the operation.

[0029] In the example of Fig. One or more logical servers (170) can be configured as described above. The example for configuring the logical server in Fig. 1 is a PCIe-based configuration; however, as described above, various other protocols can also be supported. Each logical server can contain one or more processing resources 172 (from one or more processor modules 150), one PCIe logical switch 175 (from the parallel link structure 110), and any number of PCIe logical devices 180, 184, 188 (from one or more target modules 160).

[0030] Fig. Figure 2 is a block diagram of an implementation of a composable computing environment with stacked interconnect fabrics. The example in Fig. 2 configures one or more logical servers from resources of the composable computing environment; however, this is only one example of the types of configurations that can be supported.

[0031] The composable computing architecture of Fig. Section 2 comprises three types of Resource Adapters (described in more detail below): Compute Resource Adapter (C-RA), Target Resource Adapter (T-RA), and Stacking Resource Adapter (S-RA). In addition to the different types of resource adapters, one or more Fabric modules and corresponding Fabric Managers can provide composable interconnectivity.

[0032] At a high level, the architecture of Fig. 2. In one embodiment, use end-to-end credit-based flow control (e.g., between one or more compute resources and one or more target resources). The embodiment in Fig. Section 2 provides three example types of parallel connection structures: 1) parallel connection structure 1 (260), which establishes connections between one or more computing resources and another parallel connection structure; 2) parallel connection structure 2 (262), which establishes connections between other parallel connection structures; and 3) parallel connection structure 3, which establishes connections between one or more target resources and another parallel connection structure. Any number of these types of parallel connection structures can be used. The in Fig. The stacked architecture shown in Figure 2 offers more features and more flexibility than the unstacked architecture of [reference missing]. Fig. 1.

[0033] Different distances can be supported by providing connections at the chip-to-chip level, board-to-board level, copper or fiber optic cables, or any combination thereof. This allows for the dynamic addition and removal of end nodes, switches, and / or routers.

[0034] In various embodiments, stacking connections (e.g., 202, 204, 206, 208) can be any type of connecting line, e.g., copper, fiber optic, which can be used between S-RAs (e.g., 253, 254, 255, 256, 265, 266). That is, the stacking connections can be a different type of connection than the connections of the interconnect structure.

[0035] In the example of Fig. 2. The Composable Resource Manager 215 can be a cluster of Composable Resource Managers and have management connectivity to control the parallel interconnect fabrics 260, 262, and 264, as well as the depicted compute modules 250 and intelligent target modules 260 (e.g., 280, 281, 282, 283, 284, 285, 288, 289). In some implementations, the Composable Resource Manager 215 can also have management connectivity to the RAs in the compute modules 250 (e.g., 252) and the target modules 260 (e.g., 262), but in this example, the RAs are controlled via parallel interconnect fabrics 260, 262, 264 through APIs of fabric management modules.

[0036] In one embodiment, the user interface 210 can be an API / GUI / script interface to the Composable Resource Manager 215. In one embodiment, the API / GUI / script interface of the Composable Resource Manager provides all connected compute modules 250 and target modules 260 with information, status, and control of the topology of any number of parallel link structures (e.g., 260, 262, 264). In one embodiment, the API of the Composable Resource Manager can provide the manager(s) of the parallel link structure with information, health, and control of that structure, as well as information, health, and control of each RA connected to that structure.

[0037] In one embodiment, the Composable Resource Manager 215 can directly manage RA modules (e.g., 250, 260), using an API specific to the information, health status, and control of the various RAs. In another embodiment, the Composable Resource Manager 215 can be used to assign each RA to either a compute module or a target module.

[0038] In this example, the Composable Resource Manager 215 can have a management connection to the compute modules 250 and the target modules 260, and the API of these connections can be used to provide information such as the module identity, the module's inventory including the Fabric RA identity, and other resources within the module. An example of a management entity that can provide information, status, and control of a compute module or target module is a Baseboard Management Controller (BMC).

[0039] In one embodiment, the Composable Resource Manager 215 can operate such that it discovers the parallel interconnect fabrics (e.g., 260, 262, 264) via management connections (e.g., 280 to 285) to the Fabric Managers 290, 292, 294, 295, 297, 298, including the complete connection topology to all RAs. In another embodiment, the Composable Resource Manager 215 discovers the mapping of each RA to the parallel interconnect fabrics 260, 262, 264 and the host compute modules or target modules either via the Fabric Manager(s) or via the management connection to each Compute Module or Target Module Management API.

[0040] In one embodiment, the Composable Resource Manager 215 also identifies the resources in each compute module or target module to create a complete inventory of the resources and topology of the parallel interconnect structure, and can store this information in the database 220, in memory, or a combination thereof. In one embodiment, the user interface 210 to the Composable Resource Manager 215 can, for example, query information and the status of the entire topology or request a change to the resource(s) for any compute module.In one embodiment, the Composable Resource Manager 215 can respond to a requested addition or subtraction of resources by identifying resources that can be reconfigured on the parallel link structures 260, 262, 264 to satisfy the request and successfully complete the reconfiguration, or by responding that the request cannot be satisfied or that an error occurred during the operation.

[0041] In various embodiments, each RA (i.e., C-RA or T-RA) is assigned to its own address domain within the connection structure. Each S-RA bridges transactions between the address ranges of the connection structure and is therefore a member of two address ranges within the connection structure.

[0042] Multiple resource modules can be interconnected via interconnection networks. In various embodiments, resource modules can have multiple RAs, which can provide different types of resources to the computing modules. The example in Fig. 2 can, for example, include intelligent I / O modules with multifunction devices, intelligent I / O modules with multi-host devices, I / O modules with interfaces for pluggable resources, or memory modules. Other embodiments may support other types and / or a different number of resources.

[0043] The example architecture from Fig. Architecture 2 can offer several advantages over current architectural strategies. At a high level, the architectures described here utilize a composable structure that allows for the partitioning of the platform to facilitate modular compute resources and modular I / O resources that can be dynamically configured to meet different requirements. In this way, I / O scaling can be implemented to meet changing compute resource demands. Furthermore, I / O utilization can be more efficient because I / O resources can be shared sequentially or concurrently between compute resources. In some implementations, peer-to-peer connections between resource modules are possible, enabling more efficient use of compute node resources.

[0044] In example implementations, I / O modules can contain one or more dual-port NVMe devices that can be coupled with two RAs. This allows the dual-port functionality of NVMe devices to be utilized within composable computing architectures. Various implementations and configurations that use NVMe devices are described in more detail below.

[0045] In various embodiments, the fabric managers can control the traffic flow through the interconnection fabrics so that, when capacity is sufficient, parallel paths are used as much as possible, and reroute traffic with less parallelism if one or more connections are unavailable. In some embodiments, the functionality provided by the fabric managers is supported by encapsulation and additional information provided by the various resource adapters. In this embodiment, each frame type comprises one or more interconnection fabrics with corresponding fabric managers.

[0046] The architecture described here can provide hardware failover for PCIe cards and NVMe drives across the link structure. Furthermore, the architecture can provide Quality of Service (QoS) controls for fabric bandwidth and throughput. The example architecture defines QoS as a "consumption unit" for a shared resource, which is used either concurrently or sequentially as part of a logical server. For the link structure, sharing occurs concurrently, with the consumption unit based on the use of credits for end-to-end flow control of the link structure.In one embodiment, the use of end-to-end flow control balances prevents each RA from injecting new transactions or network packets into the interconnection structure until available balances for pending transactions or network packets previously injected into the network have been accumulated (confirmed packets).

[0047] In one embodiment, the QoS “consumption unit” for T-RAs also includes the target I / O resource device, either as a sequential representation of a complete target I / O device (e.g., PCIe device (all PF physical functions of the PCIe devices)), within a PCIe adapter device, within a PCIe GPU device, or within a PCIe NVMe device. In addition to sequentially allocating the target device, the T-RA can also allocate target I / O resources concurrently, i.e., fabric bindings within a portion of the I / O resource / device (e.g., a PCIe PF physical function within a PCIe multifunction device, or a PCIe PF virtual function within a PCIe device that supports many VFs within its PF(s)).

[0048] In some embodiments, the I / O target for all T-RAs is either bound to a C-RA that creates a logical server, or to a different T-RA for peer-to-peer transactions if the same target resources are also bound to the same logical C-RA server. In one embodiment, a logical server hosting a hypervisor software stack can simply allocate the processor I / O memory management unit (IOMMU) to the C-RA to group the C-RA's T-RA bindings so that they are hardware-isolated between VM instances within the same logical server. Furthermore, each RA can be assigned QoS based on the logical server type, class, and support for I / O target resource bindings for peer-to-peer transactions, including transactions (network packets) flowing through S-RA stack nodes. Additionally, the architecture can provide a certifiable infrastructure for enhanced security.

[0049] In various implementations, RAs provide a physical interface between a resource (e.g., computing power, storage module, NVMe device) and a PCIe-based interconnect structure. Besides providing encapsulation services (and potentially other data formatting services), RAs may include a state machine that supports flow control and failover functions by further encapsulating PCI-based traffic. Similarly, compute resource adapters (C-RAs) provide RA functionality for compute resources such as a processor core.

[0050] In some embodiments, multiple parallel connection fabrics can be provided. These fabrics can provide parallel connectivity when fully functional and offer fault tolerance when some of them fail. That is, when fully functional, multiple parallel paths can be provided between compute modules and resources, but if part of one of the fabrics fails, the overall connection configuration can be dynamically reconfigured to compensate for the failure without using a primary backup mechanism.

[0051] Fig. Figure 3 is a logical representation of an implementation of an architecture that can provide flexible, configurable systems using parallel interconnect structures. The example in Fig. 3 comprises a small number of components; however, more complex systems with any number of components can also be supported. The example in Fig. 3 can be a PCI-based system, in which, for example, PCIe components are used.

[0052] In the example of Fig. 3. Node 312 comprises input / output (I / O) target resource devices (e.g., 320, 321) and compute resource nodes (e.g., 323, 324, 325) connected to switch 322. I / O devices can be, for example, storage devices, memory systems, or user interfaces, and compute nodes can be one or more processors (or processor cores) providing processing functions. Switch 322 connects I / O devices 320 and 321 and compute devices 323, 324, and 325. In some embodiments, these components can be arranged together as node 312; however, in other embodiments, these components can be geographically distributed.

[0053] Node 314 is similarly configured with a switch 335 that connects I / O devices (e.g., 330, 331, 332) and computing devices (e.g., 333, 334). Node 318 is an I / O node with several I / O devices 360, 361, 362, 363, 364 connected via a switch 365. Node 316 is a control node comprising a controller 352 and storage media 353 used to control the architecture of Fig. 3. Switches 322, 335, and 365 of different nodes can establish a connection and, furthermore, be interconnected by several parallel interconnection networks (e.g., 342, 344). In various embodiments, switches 322, 335, and 365 and interconnection networks 342 and 344 are PCIe-based connections, as described in more detail below. In alternative embodiments, CXL- or Gen-Z-based connections can also be used.

[0054] Under normal operation, connection structures 342 and 344 can provide parallel paths between the various nodes to ensure maximum available bandwidth. If some or all connection structures fail, the overall connection between the nodes can be reconfigured to compensate for the failure. This means that the multiple parallel connection fabrics are not configured as a primary fabric and a backup / standby fabric, but are controlled and configured by one or more fabric managers to provide optimal connection bandwidth. This functionality is described in more detail below.

[0055] The in Fig. The modular and composable architecture shown in Figure 3 offers modularity in that I / O resources need not be restricted to a specific physical system. Furthermore, it allows for the consolidation of, for example, storage, cluster traffic, and / or I / O devices. This exemplary modular and composable architecture also provides high availability, as it enables application-transparent alternative pathing, partitioning for independence, fault isolation, and a single management footprint.

[0056] Fig. Figure 4 is a conceptual diagram of an embodiment of an infrastructure resource pool that provides composable resources from which resource instances or complete devices can be assembled and configured to create logical servers that operate like traditional servers. Fig. Figure 4 shows an exemplary use case for mapping physical and virtual functions provided by compute modules and target modules to achieve a logical server architecture. This figure illustrates both the physical infrastructure with parallel fabrics and the logical infrastructure, where the parallel fabrics are not visible and only the allocated resources for a server are shown.

[0057] Infrastructure resource pool 400 comprises the various physical infrastructure modules, as described in Fig. 2 described. In the exemplary embodiment of Fig. These include 410 computing modules, each with one or more computing cores 412 and corresponding C-RAs 414. The computing cores 412 can be connected to the C-RAs 414 via CXL or PCIe protocols, for example. The computing cores 412 can be any type of processing resource, such as a central processing unit (CPU), a graphics processing unit (GPU), etc.

[0058] The infrastructure resource pool 400 also includes target modules 430, each of which has one or more target / IO resources 434 that provide a physical function (PF) and corresponding T-RAs 432. The resources 434 can be connected to the T-RAs 414 via CXL or PCIe protocols, for example. The compute cores 412 can be any type of resource that can be used to support the compute cores 412, such as memory modules, intelligent I / O modules, etc.

[0059] The Interconnection Fabrics 421 and 425, with their associated Fabric Managers 420 and 426 respectively, can provide configurable connections between C-RAs 414 and T-RAs 432, enabling connections between the Computing Modules 410 and the Target Modules 430. In some embodiments, the interconnection components are PCIe-based. In other embodiments, the interconnection structures are CXL- or Gen-Z-based.

[0060] In various embodiments, different computer architectures can be assembled using Fabrics 421 and 425 with Fabric Managers 420 and 426, the modules of the Infrastructure Resource Pool 400. The example in Fig. Figure 4 shows a series of logical servers (e.g., 450, 452, 454). The in Fig. Although the configuration shown corresponds to the same logical device type (i.e., logical servers), the described functionality is not limited to multiple logical devices of the same type. Thus, in alternative implementations, many different logical device types can be configured simultaneously.

[0061] In the example configuration of Fig. Each logical server contains at least one processor resource 460, which consists of some or all of the compute modules 410 (i.e., processor 412 and corresponding C-RA 414) from the infrastructure resource pool 400. Some or all of the interconnection fabrics 421 and 425 can be configured (via Fabric Manager 420 and 426) to provide logical PCIe switches 465. In alternative embodiments, such as those based on CXL or Gen-Z, the logical switch would be based on the corresponding protocol.

[0062] Furthermore, each logical server contains at least one logical resource 470, 474, or 478, which is some or all of the target modules 430 (i.e., resources 434 and corresponding T-RA 432) from infrastructure resource pool 400. Once configured, logical servers 452, 453, and 454 can provide server functionality with the allocated resources. If conditions change, one or more of the logical servers 450, 452, and 454 can be reconfigured or deconfigured as logical servers with different resource allocations or as other logical device types, with the resources being reassigned to infrastructure resource pool 400.

[0063] Fig. Figure 5 is a block diagram of an implementation of a trusted composable computing architecture consisting of trusted composable infrastructure resources with intelligent modules (e.g., a server, a storage array), simple modules (e.g., a CPU, a PCIe adapter, an NVMe drive), and parallel interconnects from which conventional server modules (intelligent modules) can extend their I / O capabilities or create logical servers. The architecture of Fig. 5 can be a fully displayable infrastructure and provide complete encryption and key management isolation services. The in Fig. The architecture shown in section 5 can also provide fabric state monitoring and report generation, as well as compliance and security services and modes.

[0064] The example in Fig. Figure 5 illustrates how the system can be extended for compliance and security at each of the management endpoints, such as the Composable Resource Manager, the Fabric Manager(s), the Resource Adapter(s), and the Baseboard Management Controller(s). This compliance and security is represented by a "fly" icon at each endpoint. This "fly" indicates that the endpoint provides authentication, attestation, and encryption key management services.

[0065] The in Fig. The architecture shown in Figure 5 uses expansion fabrics 505 and 508, which function as described above. Expansion fabrics 505 and 508 can be PCIe-based or, alternatively, CXL- or Gen-Z-based. Fabric managers 512 and 518 can configure connections within expansion fabrics 505 and 508, respectively, to provide the composable functionality described here. Resource managers 510 and 516 can provide functions for managing resource configuration for one or more compute resources and / or one or more target resources. In alternative embodiments, any number of expansion fabrics, fabric managers, and resource managers can be supported. In some embodiments, fabric managers 512 and 518 can provide identity, enumeration, and discovery services, as well as resource pool authentication services. Fig. 5 can provide high availability management via the resource managers.

[0066] The in Fig. The architecture shown in Figure 5 can utilize compute resources (e.g., 540) that include processor resources 542 and C-RA(s) 546. In some embodiments, C-RA(s) 546 can provide identity and / or consumption unit authentication services. In some embodiments, one or more intelligent compute resources 520 can be included. Intelligent compute resources include at least one application 522 that provides a degree of intelligence to the intelligent compute resource 520 compared to the compute resource 540. In addition to the application 522, the intelligent compute resource 520 can include one or more processor resources 524 and one or more corresponding C-RAs 526. The intelligent compute resource 520 can also include an authentication agent 528 that provides authentication services for the identity and / or consumption units of the intelligent compute resource 520.

[0067] Various implementations of a composable computing architecture, as in Fig. As shown in Figure 5, simple expansion resources 580 can include expansion resources 582 and T-RA 584. Expansion resources can include, for example, SmartIO modules, NVMe modules, etc. In some embodiments, C-RA(s) 584 can provide identity and / or consumption unit authentication services. In some embodiments, one or more intelligent expansion resources 560 can be included. Intelligent expansion resources include at least one processing element 568, which provides a level of intelligence to the intelligent expansion resource 560 compared to the simple expansion resource 580. In addition to the processing element 568, the intelligent expansion resource 560 can include one or more expansion resources 564 and one or more corresponding T-RAs 562.The intelligent expansion resource 560 can also include an authentication agent 566 to provide identity and / or consumption unit authentication services for the intelligent expansion resource 560.

[0068] The architecture in Fig. Section 5 illustrates in general terms how layers of security and attestation functions can be provided for composable architecture modules. These additional functions can support enumeration and discovery functions, such as interconnect traversal (e.g., link-by-link in a PCIe variant). Furthermore, resource bindings, such as RA fabric bindings (host-to-destination, destination-to-destination) and I / O destination bindings (e.g., logical storage areas, logical NVMe devices, dual-path NVMe devices to a single host, physical PCIe adapters), can be supported.

[0069] The architecture in Fig. The five provided authentication functions enable secure management and control with mutual authentication and a fully encrypted data path, providing cryptographic isolation between connections / logical servers. Furthermore, hardware failover for a trigger event or software control (e.g., a scheduled event) can be supported. Controller failover can be software-controlled, validating the path and clearing any fault conditions.

[0070] Fig. Figure 6 is a block diagram of an implementation of an infrastructure resource pool that provides composable infrastructure resources in a hardened, secure environment where logical server resource bindings are cryptographically connected via the parallel link structure. In the example of Fig. 6. The infrastructure resource 600 can include any number of compute modules 610, link modules 640, and destination modules 660.

[0071] As with the configurations described above, the compute module(s) 610 can contain one or more processors 612 and corresponding C-RAs 614. The interconnect module 640 can contain one, two, or more interconnect fabrics 642 and corresponding fabric managers 645. The example target module(s) 660 from Fig. 6 can include one or more T-RAs 662 and corresponding switches 664 to provide access to various PCI slots 666. Other target module configurations offering different functions can also be supported.

[0072] In the Fig. In the architecture shown in Figure 6, the C-RAs 614 and T-RAs 662 ensure compliance with PCIe host packets as well as encapsulation / decapsulation functions. In various embodiments, the C-RAs 614 receive logical server PCIe packets 620 into encapsulated packets 650. The encapsulated packets 650 are then transmitted via the link module 640 to the T-RAs 662, which also provide compliance and decapsulation functions. Traffic can also flow in the reverse direction, using the same procedures and protocols.

[0073] In one embodiment, the encapsulated packets 650 contain the end 652, the payload 654 (e.g., a PCIe packet 620), and the message header 656. In one embodiment, the message header 656 contains a provider ID, a request ID (e.g., compute RA ID, destination RA ID), a destination ID, flow control balances, and transaction order requests. In alternative embodiments, different configurations of the message headers can be used.

[0074] The combination of the various elements that are in the Fig. Figures 1-6 are shown, and the corresponding description forms a compatible computer framework with various security levels, encryption, cryptographic isolation of logical server connections, attestation, etc.

[0075] Fig. Figure 7 is an example of a packet frame header for a parallel connection structure that can be used with the composable architecture described here for a parallel PCIe connection structure built with standard PCIe switches. The example in Fig. 7 is a PCIe Transaction Layer Packet (TLP) header that uses the bytes reserved by the manufacturer to support the Composable Fabrics and Composable Computing architectures described here; however, other protocols may use different header formats.

[0076] In the example format of Fig. 7. Bytes 0 to 11 of the TLP header (815) can be defined as in the PCIe standards. In various implementations, bytes 12 to 15 of the header (825) can be used to support the composable architecture described here, since bytes 12 to 15 are reserved for manufacturer use in the current standards. As the standards evolve, the exact header configuration may change, but the functionality can be maintained by using the portions reserved for manufacturer use.

[0077] In various embodiments, the information in bytes 12 to 15 of the TLP header can be used by one or more of the RAs within the composable architecture. In one embodiment, bytes 12 and 13 of the header are used for a destination identifier (840) and a frame identifier (845). Similarly, bytes 14 and 15 of the header are used for a source identifier (850) and a frame identifier (855). Other header structures can be used to provide similar functionality.

[0078] In various implementations, transactions traversing address ranges of the link structure are updated by the S-RA with a new S-RA ID (header bytes 6 and 7...request ID) and a new destination ID (header bytes 10 and 11...bus and device number), allowing frames to flow independently between different address ranges of the link structure. When the bus and device number (bytes 10 and 11) matches the destination ID (bytes 14 and 15), the packet has reached its final destination, a C-RA or a T-RA connected to the address domain of the destination link structure.

[0079] In various embodiments, each network can have a corresponding subnet, and the frame ID (e.g., 745, 755) can be used to identify the frames and thus the corresponding address ranges. In some embodiments, the frame ID can be used for routing packets with reusable device IDs. In some embodiments, routing tables and / or address translation tables can be used for traffic between frames.

[0080] Fig. Figure 8 is a flowchart of an implementation of a technique for configuring a computing infrastructure resource in an environment that provides composable resources. The flowchart in Fig. Section 8 describes one embodiment of how a composable resource manager (e.g., 215 in Fig. 2) one or more fabric managers (e.g., 290, 292, 294, 295, 297, 298 in Fig. 2) for example, it can be controlled based on an API to provide computing power tailored to the API requirements using the composable Fabric.

[0081] In one embodiment, the environment provides (or includes) an API that supports the creation of new compute resources, which may include, for example, processor(s), memory, storage, network, and / or accelerator resources. This can be considered a "server profile." In alternative embodiments, additional and / or different resources may be supported. In one embodiment, one or more compute specifications are received via the API in block 800.

[0082] In one embodiment, a system manager (or another component, such as one or more fabric managers) can assess the environment and determine whether a compute resource is available that meets the requested requirements (block 810). If the compute resource is available, the system manager (or another component) can allocate the compute resource from the resource pool in block 870 in block 810. Once the compute resource has been allocated in block 870, a response can be provided via the system API in block 880. In one embodiment, the response indicates that the requested compute resource was successfully allocated. In alternative embodiments, additional information can also be provided.

[0083] If the compute resource is unavailable, the system manager (or another component) can determine in block 810 whether the requested resources can be met by configuring available resources from the resource pool in block 820. If not, an error message can be returned via the API in block 890. If the requested resources can be met using the resource pool, a Fabric API and / or Fabric Manager can connect the desired resources (e.g., processor(s), memory, storage, network) using the RAs and other elements as described here in block 830.

[0084] If the Fabric manager(s) successfully connect to the desired resources, a response can be provided in block 840 via the Fabric API, indicating that the compute resources in block 850 have been allocated. If the Fabric manager(s) fail to connect to the desired resources, an error response can be provided in block 840 via the Fabric API, indicating that the compute resources in block 855 have not been allocated.

[0085] After receiving a response via the Fabric API, the system manager can determine in block 860 whether the resource connection was successful. If not, an error message can be returned via the API in block 890. If the resource connection was successful in block 860, a response can be provided via the system API in block 880. In one embodiment, the response indicates that the requested compute resource was successfully allocated. In alternative embodiments, additional information can also be provided.

[0086] Fig. Figure 9 is a flowchart of an implementation of a technique for configuring a computing resource in an environment that provides composable resources. The process in Fig. 9 presents an exemplary alternative to the procedure in Fig. 8 represents. In the example of Fig. 9 can be one or more resource managers (e.g., 510 and 516 in Fig. 5) one or more fabric managers (e.g., 512 and 518 in Fig. 5) Control based on, for example, an API to provide computing power tailored to the API requirements using the Composable Fabric. In this example, the resource managers communicate with other Fabric Switches as well as with C-RAs and T-RAs to provide the desired configurations.

[0087] In one embodiment, the environment provides (or includes) a resource API that supports the creation of new compute resources, which may include, for example, processor(s), memory, storage, network, and / or accelerator resources. Alternative embodiments may support additional and / or other resources. In one embodiment, block 900 receives one or more compute specifications via the resource API.

[0088] In one embodiment, a resource manager (or another component, such as one or more fabric managers) can assess the environment and determine whether a compute resource is available that meets the requested requirements (block 910). If the compute resource is available, the resource manager (or another component) can allocate the compute resource from the resource pool in block 950 in block 910. Once the compute resource has been allocated in block 950, a response can be provided via the resource API in block 960. In one embodiment, the response indicates that the requested compute resource was successfully allocated. In alternative embodiments, additional information can also be provided.

[0089] If the computing resource is unavailable, the resource manager (or another component) can determine in block 910 whether the requested resources can be met by configuring available resources from the resource pool in block 920. If not, an error message can be issued via the resource API in block 970. If the requested resources can be met using the resource pool, the resource manager can connect the desired resources (e.g., processor(s), memory, storage, network) using the resource allocation rules (RAs) and other elements as described here in block 930.

[0090] Fig. Figure 10 is a conceptual diagram of an embodiment of an infrastructure resource pool that provides composable infrastructure resources configured as a set of logical servers. Fig. Figure 10 shows an exemplary use case for mapping physical and virtual functions provided by compute modules and target modules to achieve a logical server architecture. The example in Fig. 10 is a more complex and flexible example than the example in Fig. 3.

[0091] Infrastructure resource pool 1000 comprises the various physical infrastructure modules, such as compute resource modules 1010 and 1020, and target resource modules 1040, 1050, and 1060. Any number of compute modules and target modules can be supported. In the example implementation of Fig. This includes the Computing Resource Module 1010 with at least one Processing Core 1011 and a corresponding C-RA 1012 (designated RA-1), and the Computing Resource Module 1020 with Processing Cores 1022 and 1024 and corresponding C-RAs 1026 and 1028 (designated RA-4 and RA-5, respectively). The processing cores can be connected to the C-RAs via CXL or PCIe protocols, for example.

[0092] Infrastructure resource pool 1000 also includes target resource modules 1040, 1050, and 1060, each containing one or more resources 1045, 1055, and 1065, respectively. These resources can be connected to T-RAs via CXL or PCIe protocols, for example. In the example of Fig. Target Resource Module 1040 comprises a single T-RA 1041 (designated RA-2), a PCIe switch 1042, and several PCIe slots 1045 connected to the switch 1042. Similarly, Target Module 1060 comprises a single T-RA 1061 (designated RA-7), a PCIe multi-function device 1064, represented as a smart resource 1065. Target Module 1050 comprises two T-RAs 1051 and 1052 (designated RA-3 and RA-6, respectively), which can be used to access dual-port NVMe devices 1055 via switches 1053 and 1054.

[0093] The Interconnection Fabrics 1031 and 1035, with their associated Fabric Managers 1030 and 1036 respectively, can provide configurable connections between the various RAs, enabling connections between the Compute Resource Modules 1010 and 1020 and the Target Resource Modules 1040, 1050, and 1060. In some embodiments, the interconnection components are PCIe-based. In alternative embodiments, the interconnection structures are CXL- or Gen-Z-based.

[0094] In various embodiments, different computer architectures can be assembled using the Fabric connections 1031 and 1035 with the Fabric managers 1030 and 1036, the modules of the infrastructure resource pool 1000. The example in Fig. 10 indicates a pair of logical servers (e.g., 1070, 1080). Other configurations may also be supported.

[0095] In the Fig. In the example configuration shown in Figure 10, logical server 1070 can contain processing core(s) 1011, and logical server 1080 can contain processing cores 1022 and 1024. C-RA 1012 (RA-1) is configured to provide the functionality of logical PCIe switch 1072.

[0096] Parts of T-RA 1041 (RA-2) can be configured to provide the functionality of the PCIe logical switch 1073, which can act as an interface to some or all of the PCIe slots 1045 (designated as PCIe device 1076). Parts of the interconnect structure 1031 and parts of the interconnect structure 1035 and T-RA 1051 (RA-3) can be configured to provide the functionality of the PCIe logical switch 1074, which can act as an interface to some or all of the NVMe devices 1055 (designated as NVMe device 1077). Parts of the interconnect structure 1031 and parts of the interconnect structure 1035 and the T-RA 1061 (RA-7) can be configured to provide the functionality of the logical PCIe switch 1075, which can act as an interface to the multifunction PCIe device 1064 (referred to as multifunction device 1078).

[0097] In the Fig. In the example configuration shown in Figure 10, the logical server 1080 can include the processor cores 1022 and 1024. C-RA 1026 (RA-4), C-RA 1028 (RA-5), parts of the link structure 1031, and parts of the link structure 1035 can be configured to provide the functionality of the logical PCIe switch 1083 and the logical PCIe switch 1084.

[0098] Parts of the 1031 interconnect structure and parts of the 1035 interconnect structure and T-RA 1041 (RA-2) can be configured to provide the functionality of the 1085 logical PCIe switch, which can act as an interface to some or all of the 1045 PCIe slots (referred to as the 1090 PCIe device). Parts of the 1031 interconnect structure and parts of the 1035 interconnect structure and T-RA 1061 (RA-7) can be configured to provide the functionality of the 1086 logical PCIe switch, which can act as an interface to some or all of the 1064 multifunction devices (referred to as the 1091 multifunction device).

[0099] Parts of the 1031 interconnect and parts of the 1035 interconnect and T-RA 1041 (RA-2) can be configured to provide the functionality of the 1087 PCIe logical switch, which can act as an interface to 1045 PCIe slots (referred to as PCIe device 1092). Parts of the 1031 interconnect and parts of the 1035 interconnect, T-RA 1051 (RA-3) and T-RA 1052 (RA-6) can be configured to provide the functionality of the 1089 PCIe logical switch, which can act as an interface to some or all of the 1055 NVMe devices (referred to as NVMe devices 1093 and 1094).

[0100] Fig. Figure 11 is a conceptual diagram of logical servers configured to use peer-to-peer communication over the parallel link structures of the composable architecture. Fig. Figure 11 shows an exemplary use case for mapping physical and virtual functions provided by compute modules and target modules to achieve a logical server architecture with an internal peer-to-peer connection. The example in Fig. 11 is more complex and flexible than the example in Fig. 10.

[0101] Infrastructure resource pool 1100 comprises the various physical infrastructure modules, such as compute resource modules 1110 and 1120, and target resource modules 1140, 1150, 1160, and 1165. Any number of compute modules and target modules can be supported. In the example implementation of Fig. This includes the computing module 1110 with a computing core 1111 and the corresponding C-RA 1112 (designated RA-1), and the computing module 1120 with computing cores 1122 and 1124 and the corresponding C-RAs 1126 and 1128 (designated RA-4 and RA-5, respectively). The computing cores can be connected to the C-RAs via CXL or PCIe protocols, for example.

[0102] Infrastructure resource pool 1100 also includes target modules 1140, 1150, 1160, and 1165, each with one or more resources 1145, 1155, 1164, and 1168. These resources can be connected to the T-RAs via CXL or PCIe protocols, for example. In the example of Fig. Target module 1140 comprises a single T-RA 1141 (designated RA-2), a PCIe switch 1142, and several PCIe slots 1145 connected to the switch 1142. Target module 1150 comprises two T-RAs 1151 and 1152 (designated RA-3 and RA-6, respectively), which can be used to access dual-port NVMe devices 1155 via switches 1153 and 1154.

[0103] Similarly, the target module 1160 comprises a single T-RA 1161 (designated RA-7), a PCIe multi-function device 1162, represented as an intelligent resource 1164. The target module 1165 comprises a T-RA 1166 (designated RA-8), a CXL memory controller 1167, and one or more memory modules 1168.

[0104] The Fabric Managers 1130 and 1136 can provide configurable connections between the various RAs, enabling connections between the Computing Modules 1110 and 1120 and the Target Modules 1140, 1150, 1160, and 1165. In some embodiments, the connection structures are PCIe-based. In alternative embodiments, the connection structures are CXL- or Gen-Z-based.

[0105] In various embodiments, different computer architectures can be assembled using Fabrics 1131 and 1135 with Fabric Managers 1130 and 1136, the modules of the Infrastructure Resource Pool 1100. The example in Fig. Figure 11 shows the logical server 1170 with internal peer-to-peer functionality 1169. Other configurations may also be supported.

[0106] In the Fig. In the example configuration shown in Figure 11, the logical server 1170 can contain the compute cores 1122 and 1124. C-RA 1126 (RA-4), C-RA 1128 (RA-5), parts of the link structure 1131 and parts of the link structure 1135 can be configured to provide the functionality of the logical PCIe switch 1183 and the logical PCIe switch 1184.

[0107] Parts of Interconnection Fabric 1131 and parts of Interconnection Fabric 1135 and T-RA 1141 (RA-2) can be configured to provide the functionality of the logical PCIe switch 1185, which can act as an interface to some or all of the PCIe slots 1145 (designated as PCIe device 1190). Parts of Interconnection Fabric 1131 and parts of Interconnection Fabric 1135 and T-RA 1161 (RA-7) can be configured to provide the functionality of the logical PCIe switch 1186, which can act as an interface to some or all of the multifunction devices 1164 (designated as multifunction device 1191).

[0108] Parts of connection structure 1131 and parts of connection structure 1135 and T-RA 1141 (RA-2) can be configured to provide the functionality of logical PCIe switch 1187, which can act as an interface to PCIe device 1145 (referred to as PCIe device 1192). Parts of connection structure 1131 and parts of connection structure 1135, T-RA 1151 (RA-3) and T-RA 1152 (RA-6) can be configured to provide the functionality of logical PCIe switch 1189, which can act as an interface to some or all NVMe devices 1155 (referred to as NVMe devices 1193 and 1194).

[0109] Parts of Interconnection Fabric 1131 and parts of Interconnection Fabric 1135 and T-RA 1141 (RA-2) can be configured to provide the functionality of the logical PCIe switch 1185, which can act as an interface to some or all of the PCIe slots 1145 (designated as PCIe device 1190). Parts of Interconnection Fabric 1131 and parts of Interconnection Fabric 1135 and T-RA 1161 (RA-7) can be configured to provide the functionality of the logical PCIe switch 1186, which can act as an interface to some or all of the multifunction devices 1164 (designated as multifunction device 1191).

[0110] Parts of connection structure 1131 and parts of connection structure 1135 and T-RA 1141 (RA-2) can be configured to provide the functionality of logical PCIe switch 1187, which can act as an interface to PCIe device 1145 (referred to as PCIe device 1192). Parts of connection structure 1131 and parts of connection structure 1135, T-RA 1151 (RA-3) and T-RA 1152 (RA-6) can be configured to provide the functionality of logical PCIe switch 1189, which can act as an interface to some or all NVMe devices 1155 (referred to as NVMe devices 1193 and 1194).

[0111] In some embodiments, in addition to the configurable processor resource connections, peer-to-peer connections within the logical server 1170 can also be supported. For example, the resource manager 1136 can provide a path through the connection structure 1135 between the multifunction device 1119 and the storage device 1198 via the PCIe logical switches 1186 and 1183 and the storage controller 1167. This functionality can be supported by the processor 1122. A similar configuration (in Fig. (11 not explicitly shown) can be provided for the processor 1124 (to the storage device 1199) using the logical PCIe switches 1186 and 1184 and the memory controller 1167.

[0112] When the description refers to "an embodiment" or "an embodiment," this means that a particular feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the invention. The phrase "in an embodiment" appearing at different points in the description does not necessarily refer to the same embodiment.

[0113] While the invention has been described with reference to several embodiments, those skilled in the art will recognize that the invention is not limited to the described embodiments, but can be carried out with modifications and changes within the scope and intent of the appended claims. The description should therefore be considered illustrative and not limiting.

Claims

[1] A composable computing platform (100) comprising the following: a first parallel interconnection layer (260, 262, 264), comprising a first plurality of switching structure branches (270, 273, 275) which provide parallel connections via the first parallel interconnection layer (260, 262, 264); and a second parallel interconnection structure layer (260, 262, 264) comprising a second plurality of switching structure branches (271, 274, 276) providing parallel connections via the second parallel interconnection structure layer (260, 262, 264); where: a first switching structure branch of the first plurality of switching structure branches (270, 273, 275) and a first switching structure branch of the second plurality of switching structure branches (271, 274, 276) are communicatively connected to each other and comprise a first switching structure, a second switching structure branch of the first plurality of switching structure branches (270, 273, 275) and a second switching structure branch of the second plurality of switching structure branches (271, 274, 276) are communicatively connected to each other and comprise a second switching structure, and The first switching structure and the second switching structure are isolated from each other and provide independent paths for routing packets. [2] Composable computing platform (100) according to claim 1, further comprising: a computing resource (520, 540) comprising a computing resource adapter, C-RA (526, 546), which communicatively connects the computing resource (520, 540) to the first plurality of switching structure branches (270, 273, 275) of the first parallel interconnection structure layer (260, 262, 264). [3] Composable computing platform (100) according to claim 1, further comprising: an input / output (I / O) resource comprising an I / O resource adapter (I / O-RA) that communicatively connects the I / O resource to the first plurality of switching structure branches (270, 273, 275) of the first parallel interconnect structure layer (260, 262, 264). [4] Composable computing platform (100) according to claim 1, wherein: the first parallel interconnect layer (260, 262, 264) further comprises a first plurality of switching structure resource adapters, S-Ras (253, 254, 255, 256, 265, 266); the first switching structure branch of the first plurality of switching structure branches (270, 273, 275) is communicatively connected to a first S-RA of the first plurality of S-RAs (253, 254, 255, 256, 265, 266); and the first S-RA of the first multitude of S-RAs (253, 254, 255, 256, 265, 266) is communicatively connected to a first S-RA of the second parallel connection structure layer (260, 262, 264). [5] Composable computing platform (100) according to claim 4, wherein: the second parallel interconnect layer (260, 262, 264) further comprises a second plurality of S-RAs (253, 254, 255, 256, 265, 266), including the first S-RA of the second parallel interconnect layer (260, 262, 264); and the first switching structure branch of the second plurality of switching structure branches (271, 274, 276) is in communication connection with the first S-RA of the second plurality of S-RAs (253, 254, 255, 256, 265, 266), so that the first switching structure branch of the second plurality of switching structure branches (271, 274, 276) is in communication connection with the first switching structure branch of the first plurality of switching structure branches (270, 273, 275). [6] Composable computing platform (100) according to claim 1, wherein: the first parallel interconnection structure layer (260, 262, 264) further comprises a first plurality of structure managers (130, 135, 138) which are connected to the first plurality of switching structure branches (270, 273, 275); and the second parallel interconnection structure layer (260, 262, 264) further comprises a second plurality of structure managers (130, 135, 138) which are connected to the second plurality of switching structure branches (271, 274, 276). [7] Composable computing platform (100) according to claim 6, further comprising: a composable resource controller (120, 215) that manages the first and second set of structure managers (130, 135, 138). [8] Composable computing platform (100) according to claim 7, which further comprises a user interface that is communicatively connected to the composable resource controller (120, 215). [9] Composable computing platform (100) according to claim 7, wherein the composable resource controller (120, 215) is configured such that it: receives an I / O or memory resource request for a compute workload for a host device; and Allocates I / O resources to individual computing resources (520, 540) based on the received requests; where the first and second parallel interconnection layer (260, 262, 264) provide communicative links between the I / O resources and the compute resources (520, 540). [10] A composable computing platform (100), comprising: a parallel interconnect layer (260, 262, 264) comprising a plurality of switching branch structures (270, 271, 273, 274, 275, 276) that provide parallel connections via the parallel interconnect layer (260, 262, 264); where: a first branch of the circuit structure of the multitude of Switch structure branches (270, 271, 273, 274, 275, 276) comprise a first switching structure, and a second switching structure branch of the plurality of switching structure branches (270, 271, 273, 274, 275, 276) comprises a second switching structure, and the first switching structure and the second switching structure are isolated from each other and provide independent paths for routing packets; and a second parallel interconnection structure layer (260, 262, 264) comprising a second plurality of switching structure branches (270, 271, 273, 274, 275, 276) providing parallel connections via the second parallel interconnection structure layer (260, 262, 264); where: a first switching structure branch of the second plurality of switching structure branches (270, 271, 273, 274, 275, 276) includes the first switching structure and a second switching structure branch of the second plurality of switching structure branches (270, 271, 273, 274, 275, 276) includes the second switching structure. [11] Composable computing platform (100) according to claim 10, wherein: the first switching structure branch of the plurality of switching structure branches (270, 273, 275) is communicatively connected with the first switching structure branch of the second plurality of switching structure branches (271, 274, 276); and the second switching structure branch of the multitude of switching structure branches (270, 273, 275) is communicatively connected with the second switching structure branch of the second multitude of switching structure branches (271, 274, 276). [12] Composable computing platform (100) according to claim 11, wherein: the first parallel interconnect structure layer (260, 262, 264) further comprises a first plurality of S-RAs (253, 254, 255, 256, 265, 266); the first switching structure branch of the plurality of switching structure branches (270, 273, 275) is communicatively connected to a first S-RA of the first plurality of S-RAs (253, 254, 255, 256, 265, 266); and the first S-RA of the first multitude of S-RAs (253, 254, 255, 256, 265, 266) is communicatively connected to a first S-RA of the second parallel connection structure layer (260, 262, 264). [13] Composable computing platform (100) according to claim 12, wherein: the second parallel compound layer (260, 262, 264) further comprises a second plurality of S-RAS (253, 254, 255, 256, 265, 266) which contain the first S-RA of the second parallel compound layer (260, 262, 264); and the first switching structure branch of the second plurality of switching structure branches (271, 274, 276) is connected to the first S-RA of the second plurality of S-RAs (253, 254, 255, 256, 265, 266), so that the first switching structure branch of the second plurality of switching structure branches (271, 274, 276) is connected to the first switching structure branch of the first plurality of switching structure branches (270, 273, 275). [14] Composable computing platform (100) according to claim 10, wherein: the parallel interconnection structure layer further comprises a multitude of structure managers (130, 135, 138) which are connected to the multitude of switching structure branches (270, 271, 273, 274, 275, 276). [15] Composable computing platform (100) according to claim 14, further comprising: a composable resource controller (120, 215) that manages the multitude of structure managers (130, 135, 138). [16] The composable computing platform (100) according to claim 15, wherein the composable resource controller (120, 215) is configured to: to receive an I / O or memory resource request for a compute workload for a host device; and Allocate I / O resources to individual computing resources (520, 540) based on the received requests; where the parallel interconnect layer between the I / O resources and the computing resources (520, 540) is provided. [17] Composable computing platform (100) according to claim 10, wherein the first and second switching structure branches of the plurality of switching structures are communicatively separated. [18] Composable computing platform (100) according to claim 10, wherein the first switching structure branch comprises a network of multiple switches. [19] Composable computing platform (100) comprising the following: a composable resource controller (120, 215) that manages a parallel interconnection structure layer; and the parallel interconnection structure layer comprises a multitude of switching structure branches (270, 271, 273, 274, 275, 276) that provide parallel connections via the parallel interconnection structure layer; where: a first switching structure branch of the plurality of switching structures comprises a first switching structure and a second switching structure branch of the plurality of switching structure branches (270, 271, 273, 274, 275, 276) comprises a second switching structure and the first switching structure and the second switching structure are isolated from each other and provide independent paths for routing packets; and a second parallel interconnection structure layer (260, 262, 264) comprising a second plurality of switching structure branches (271, 274, 276) providing parallel connections via the second parallel interconnection structure layer (260, 262, 264); where: a first switching structure branch of the second plurality of switching structure branches (271, 274, 276) comprises the first switching structure and a second switching structure branch of the second plurality of switching structure branches (271, 274, 276) comprises the second switching structure.

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