METHOD AND DATA PROCESSING DEVICE FOR RESTRUCTURING INPUT DATA TO BE STORED IN A MULTI-LEVEL NAND FLASH MEMORY

Abstract

A method and a data processing device for restructuring input data to be stored in a NAND flash memory with a plurality of multi-level flash memory cells are provided. The method comprises: restructuring the segmented input data, based on a defined page structure according to which the input data is segmented into multiple logical input pages, to obtain corresponding output data segmented into logical output pages, each output page having one or more associated target data pages for storing the content of the output page therein; and outputting the segmented output data for storage in the flash memory in accordance with the mappings between the output pages and their respective target data pages.The restructuring process involves assigning a corresponding input page to each output page and selecting the respective input page for assignment to the respective output page based on: the level of the one or more target data pages associated with the output page, the content of the input page, and a memory reliability optimization goal defined as a function of the level of the one or more target data pages associated with the output page. The input page is selected such that it, or a reversibly transformed version thereof, satisfies the memory reliability optimization goal associated with the target data page associated with the output page, and the content of the output page is defined accordingly as that of the input page or its reversibly transformed version.

Description

[0001] The present invention relates to the field of flash memory technology. Specifically, it is directed to a Method and apparatus for restructuring, i.e. reordering or modifying or both, input data stored in a NAND flash memory having a plurality of multi-level flash memory cells arranged in arranged in several physical pages, each of which has a defined number N > 1 of data pages, which correspond to the different levels of multi-level flash memory. In particular, NAND flash memory can or multiple flash memory components, such as semiconductor-based memory chips.

[0002] Flash memory, especially NAND flash memory, is one of the most popular Data storage solutions that are used in almost all modern electronic devices requiring storage, from portable devices to enterprise servers, is playing an increasingly important role. The constantly increasing cost efficiency, the non-volatile, growing capacity, good performance and mechanical shock resistance of flash memory are the The main reasons for this popularity are: Flash memory manufacturers have mainly developed NAND flash cells in smaller Semiconductor technology nodes scaled to meet increasing demands for capacity, performance and reduce the cost of flash memory. NAND flash technology is inherently error-prone Technology, and its reliability must therefore be constantly monitored, corrected and optimized. With increasing Flash density, NAND flash memory cells generally become more susceptible to various types of errors and noise on circuit level, which affects their reliability and endurance. For example, the write-erase Cycles (writeerase - HOW) usually cause gradual, permanent damage to the NAND flash cells, which reduces their reliability over time and limit the lifetime of the NAND flash memory (i.e. the so-called endurance).

[0003] In a NAND flash cell, the stored data is represented by the amount of electrical charge that stored in a memory transistor, ie a floating-gate (FG) or charge-trap (CT) transistor. Originally NAND flash cells, so-called single-level cells (SLC), could only store one data bit per cell. To increase storage density, flash manufacturers have switched to using multi-level cells (MLC), which can store several data bits per cell and thus multiply the storage capacity (e.g. double, triple or quadruple) while using the same physical flash memory device, such as a semiconductor chip. Nowadays, single-level cell (SLC), dual-level cell or triple-level cell (TLC) NAND flash memory is commonly used Each type has unique properties and applications, as described below in conjunction with Fig. 1 is explained in more detail.

[0004] While it is common practice in the electronics industry to use cells with two levels - slightly different from the above, more general definition of MLC - as ´´multiple-level cells´´ or ´´multi-level cells´´, we adopt here the above, more general definition, according to which the terms ´´multiple-level cell´´, ´´multi-level cell´´ and ´´MLC´´ refers to cells of a NAND flash memory that stores multiple data bits per cell and not only a single bit like SLC.

[0005] Due to the programming technique and the nature of the charge discharge immediately after programming, different charges represent the same stored logical data. Therefore, in MLC memory cells, the stored logical data is represented by a threshold voltage range (Vth) that represents the minimum voltage required to power the transistor (ie the memory cell) based on the stored charge of the threshold voltage of the cell, as explained in more detail below in connection with Fig. 1. The However, the threshold voltage range used to represent each logical value is still smaller, which increases the error rates for determining the correct logical representation in the cell (ie the Probability that the stored data is read correctly decreases).

[0006] Conventional NAND flash memories have a planar (2D) architecture in which the entire The memory cell array is arranged laterally in a single plane. The increasing demand for non-volatile However, high-density storage devices have prompted flash manufacturers to switch to a 3D flash structure instead of to switch to a planar flash structure.

[0007] Today, planar NAND flash memories typically use a technology node of 20 nm to 15 nm, and future generations will likely use even smaller nodes. Further shrinking of the flash Cell while maintaining consistent reliability was a major challenge for flash manufacturers. The 3D NAND flash Memory was introduced to solve the problems mentioned above. Unlike planar NAND flash, 3D NAND flash memory uses vertically stacked Flash cells are used in a 3D structure, as explained in more detail in Fig. 2. This in turn enables the Flash manufacturers to increase storage density while simultaneously using larger technology nodes than planar NAND flash storage and thus ensure high reliability of the flash memory. circuitry and structural changes brought about by 3D NAND flash memory technology, However, there are numerous sources of error that affect reliability. For example, new Reliability risks are critical, such as layer-to-layer variations and cell-to-cell interference, which generally lead to particularly relevant error sources of 3D NAND flash.

[0008] Various phenomena affect the reliability of NAND flash, disrupt the stored data and shorten the lifespan of flash memory devices. NAND flash is inherently error-prone because the stored charge is altered for various reasons. This can lead to reliability threats, such as such as data retention, cell disruption, and cell degradation. These threats usually occur simultaneously which can significantly reduce the reliability of the NAND flash if no countermeasures are taken. Therefore, correction mechanisms (e.g. error correction code (ECC)) are always required to To ensure the reliability and security of the stored data. The correction options are provided by the algorithm used, and extending these capabilities is very costly. To improve correction options at acceptable costs, advanced correction mechanisms will be However, modern storage devices use advanced mitigation mechanisms to Reduce the impact of reliability threats and keep error rates at an acceptable level and maintain reliability.

[0009] Although the introduction of 3D NAND flash memory has improved reliability compared to planar 2D NAND flash Although storage has generally improved, it has brought with it new reliability risks. Today, it is still a Challenge of ensuring the reliability of high-density NAND flash memory while to achieve a long service life. Although reliability threats are usually simultaneous phenomena, they usually have similar effects and roots. The stored charge (ie the Data) is the most important factor affecting the reliability and lifetime of the NAND flash cell. It can mitigate or exacerbate certain reliability problems to a certain extent. For example, a good Distribution of charges between neighboring cells can reduce cell-to-cell interference. In addition, it is important for Reliability of the cells and the extension of their lifespan, which also depends on the stored charge, crucial to keep the cells under good conditions and minimize internal degradation.

[0010] An object of the present invention is to improve the achievable reliability and / or lifetime of flash to further improve memory devices, especially 3D NAND flash memory devices.

[0011] A solution to this problem is provided by the teaching of the independent claims. Various preferred embodiments of the present solution are provided by the teachings of the dependent claims.

[0012] A first aspect of the present solution relates to a method which is in particular a computer- implemented method for restructuring input data stored in a NAND flash memory to which has a plurality of multi-level flash memory cells (ie MLC cells) arranged in several physical pages, each of which has a defined number N > 1 of data pages that represent the correspond to different levels of multi-level flash memory.

[0013] The method, which is carried out in particular by a flash memory controller can, indicates: a) based on a defined page structure, according to which the input data is divided into several logical Input pages are segmented, restructuring the segmented input data to provide appropriate To obtain output data that is segmented into logical output pages, where each output page contains a or multiple associated target data pages for storing the contents of the output page therein; and b) Outputting the segmented output data for storage in the flash memory according to the Mappings between the output pages and their respective target data pages.

[0014] The restructuring includes assigning a corresponding input page to each output page and Selecting the respective input page for assignment to the respective output page based on: (i) the level of one or more target data pages associated with the output page, (ii) the content of the input side and (iii) a memory reliability optimization objective defined as a function of the level of the one or more Target data pages assigned to the output page are defined.

[0015] The input side is selected so that it or a reversibly transformed version of it meets the optimization objective for storage reliability that is assigned to the target data page associated with the output page, and the content the output side is defined accordingly as that of the input side or its reversibly transformed version.

[0016] The term ´´flash memory device´´ or ´´memory device´´ used in this document refers refers to a physical device that has flash memory. In particular, a flash memory component such as a flash memory chip, a more highly integrated system such as a flash memory stick or a flash memory card or a SSD storage in a computer are all examples of flash storage devices.

[0017] The term ´´physical side´´ used here refers to a physical realization of a Data storage unit in a flash memory device that is the smallest amount of data that can be independently written or read into the flash memory device, in particular into a flash Memory component. The size of a physical page can vary depending on the type and manufacturer of the flash memory device vary. Currently, the size is typically in the range of kilobytes (KB) to several hundred kilobytes (KB). A physical page consists of a fixed number of bytes, ranging from 128 bytes in some small flash memories to several megabytes (MB) or even more in larger memories. The number of physical pages in a Flash memory is usually defined by the size of the device and the capacity of the memory cells it contains Each page in a flash memory usually has its own unique address, which is used to page within the device. The addresses are usually assigned consecutively, with each page having a has a unique address that increases as more pages are added to the device. In a typical NAND flash Memory design, all flash memory cells belonging to the same physical page share a common Word line that is connected to the control gates of these memory cells and thus connects them together.

[0018] The term ´´data page´´ used in this document refers to a smaller data storage unit within a larger physical page in a multi-level flash memory cell. In other words, a data page is a subset a page that contains a section of the total data stored on the physical page. The size of a Data page may vary depending on the type and manufacturer of the flash memory, but is usually in the order of Hundreds of bytes up to several kilobytes (KB). The concept of data pages is used in Multi-Level Cell (MLC) Flash Storage is used to increase storage density. In MLC flash memory, each physical page can store data on multiple levels, ie on multiple data pages, where the levels correspond to the different bit levels of the memory cells in the physical page. For example, in a TLC flash memory device with three Storage levels (L0-L2) each physical page stores data from each of these three levels. These levels correspond to three Bit levels, which are usually referred to as the most significant bit (MSB), the center significant bit (Cbit) CSB) or least significant bit (LSB), as described below in conjunction with Fig. 3 will be explained in more detail. Similarly, the data pages of a TLC flash, which correspond to the three bit levels, commonly referred to as most significant page (MSP), middle significant page (CSP), and least significant page (LSP).

[0019] The term ´´target data page´´ used in this document refers to a data page that is used as a target for the Storing at least part of the contents of an output page associated with that data page is selected. Likewise, the term ´´target page´´ used in this document refers to a physical page to which the target data page heard.

[0020] The term ´´page structure´´ as used in this document refers to a defined physical or logical structure according to which a data record is structured into several data segments, which in particular have the same size For a physical structure, a page structure can, for example, be a physical arrangement of Memory cells into which the data to be structured is loaded and in which either the rows or the Columns of the array define the segments so that all data elements of the same row (or column) belong to a same segment. In contrast, data elements from different rows (or columns) belong to according to different segments. In another example, in the case of a logical structure, a Page structure must be defined so that a data record organized according to a linear address range can be logically divided into segments, each having the same defined page size m (ie m bits per page), so that in the Area every m bits a new page begins.

[0021] The term ´´logical page´´ as used herein refers to a data storage unit that is accessible by the user or the application and is not determined by the physical structure of the storage device. Logical pages can be larger than the physical pages of the flash memory and usually range from a few kilobytes to several megabytes (MB). A logical page usually consists of a contiguous block of data that located on one or more physical pages, especially on data pages of the same level, in the flash memory The number of physical pages required to store a logical page can vary depending on the type and Flash memory manufacturers and specific application or user requirements vary.

[0022] The term ´´logical input page´´ or ´´input page´´ used in this document refers to a logical page (e.g., a data segment of a larger data set) provided as part of the input data, the are to be processed according to the procedure in order to prepare the logical page for later storage in a flash memory to prepare, e.g. on a same physical page or in particular on a same data page thereof.

[0023] The term ´´logical output´´ or ´´output´´ used in this document refers to a logical Page (e.g. a data segment of a larger data set) that results from performing the procedure and which is a flash memory, e.g., on the same physical page, in particular on the same Data page.

[0024] The terms ´´optimization objective for storage reliability´´ or ´´optimization objective´´ for short, as used in this font, can be used interchangeably and refer to one or more defined Conditions whose fulfillment correlates positively with the reliability of the flash memory, in particular with a Reducing degradation (usually caused by the gradual degradation of the memory cells) or to an extension of the lifetime. An optimization goal for storage reliability can be particularly The basis of a flash memory allocation scheme must be defined, according to which different logical Data representations of the flash memory cells with different threshold voltages of the flash memory cells of the Flash memory. The optimization goals for memory reliability can therefore be determined by the specific type of flash memory with respect to which the method is performed. The one or more Conditions can be defined in a quantifiable manner, so that a degree of fulfilment below or above a threshold value at which the condition is fulfilled. For example, if single condition the condition is defined so that it is fulfilled when a number of bits with the (logical) value ´´1´´ (one) in a bit pattern is higher than a threshold value k, then for a particular bit pattern, e.g. Input side, the corresponding degree of fulfillment of the condition as a mathematical difference between the actual number n of bits with the value ´´1´´ in the bit pattern and the threshold value k are defined, ie as nk. In the following the term ´´optimization constraint´´ is used to denote those threshold values ​​k which are used to define the Optimization objectives can be used (see optimization constraints O and Z ). TH TH

[0025] The terms ´´first´´, ´´second´´, ´´third´´ and the like in the description and in the claims are to distinguish between similar elements and not necessarily to describe a sequential or chronological order. It is understood that the terms used in this way may, under appropriate circumstances, are interchangeable and that the embodiments of the present solution described herein are designed to operate in other sequences than those described or illustrated herein.

[0026] Unless the context requires otherwise, the term ´´having´´ or ´´including´ or a Variation of how ´´having´´ or ´´comprise´´ or ´´include´´ in the present description and the claims does not exclude other elements or steps and is to be interpreted in an open, inclusive sense, i.e. as ´´including, but not limited to´´.

[0027] If an indefinite or definite article is used when it refers to a singular noun, e.g. ´´ein´´ or ´´eine´´, ´´der / die / das´´, this includes a plural of this noun, unless explicitly stated otherwise. unless otherwise stated.

[0028] The appearance of the terms ´´in some embodiments´´, ´´in one embodiment´´ or ´´in an Embodiment'' in the description does not necessarily refer to the same embodiment. In addition, the certain features, structures or characteristics in any suitable manner in one or more embodiments can be combined.

[0029] Furthermore, unless expressly stated to the contrary, ´´or´´ refers to an inclusive or and not on an exclusive or. For example, a condition A or B by any of the following: A is true (or present) and B is false (or absent), A is false (or not present) and B is true (or present) and both A and B are true (or present).

[0030] The terms ´´configured´´ or ´´arranged´´ to perform a particular function (and corresponding variations thereof) as used in this document, it is to be understood that a relevant Device or component is already in a configuration or setting in which it performs the function can, or at least it is adjustable (ie configurable) so that it can perform the function after appropriate setting In this context, the configuration can be carried out, for example, by setting of parameters of a process flow or of hardware (HW) or software (SW) or combined HW / SW switches or similar to activate or deactivate functionalities or settings. In particular, the Device may have a variety of predefined configurations or operating modes, so that the configuration can be determined by the Selecting one of these configurations or operating modes can be performed.

[0031] Accordingly, the method of the first aspect can be used to process the input data, namely their input pages, before storing them in the flash memory in a data-aware manner, i.e. re- to arrange and / or transform so that, based on the respective content of the input pages, an optimized Assignment of input pages to output pages and thus to the target data pages assigned to the output pages in With regard to the associated optimization objective for storage reliability, Based on the restructuring, a better match between the content of the input pages and the physical constraints of the data pages as defined in the respective optimization goal for the Memory reliability is achieved, thus reducing the load on the flash memory. For example, a certain first data page may be less resilient if it is loaded with a bit pattern that has a majority of bits with the bit value ´´1´´ than if it is loaded with a bit pattern that has a majority of bits with the bit value "0" (also the position of the "1" or "0" values ​​within the bit pattern can play a role in this respect), while the opposite is true for the second side of the data.

[0032] Then, according to the method, a given input page can be assigned a majority of bits with the bit value ,, 0" can be advantageously assigned to an output page that corresponds to the second data page and not to the first data page In this way, the stress level for the flash memory cells can be mitigated and the lifetime of the Flash memory can be extended.

[0033] Typically, due to the physical structure of flash memory cells, the bit representations that according to the corresponding allocation scheme of the flash memory, higher charges for their storage and thus longer require longer write times and higher threshold voltages for reading from the flash memory, more susceptible to high stress, especially for the tunnel oxides of the affected memory cells, than bit representations that require correspondingly lower voltages. Accordingly, the method can be used as an optimization method be considered, the appropriate allocated for given input pages (via assignment to output pages) data pages for storage, whereby the selection is based on the content of the input pages, the technology of the flash memory (especially its allocation scheme) and the type of data page (i.e., its level). The method attempts to restructure the input data in such a way that the charge states of the flash cells used for Low voltage side of the Vth distribution, ie the lower Vth states, as far as possible for the storage while avoiding higher Vth states as much as possible.

[0034] Therefore, the method can be used in particular to suppress the constantly increasing error rates and to Longevity of multi-level NAND flash memories, such as TLC 3D NAND flash memories, without limitations improve.

[0035] Preferred embodiments of the method of the first aspect are described below, which may be can be combined with each other or with other aspects of the present solution, provided that such Combination is not expressly excluded or technically impossible.

[0036] In some embodiments, the selection of the respective input page for assignment to the respective Output page consists of selecting a specific input page and selecting from the target subpages that do not yet have input page has been assigned to search for a suitable one, and in other embodiments or vice versa a to select a specific available target data page and to choose a suitable one from the input pages not yet assigned. to meet the goal of optimizing storage reliability.

[0037] In some embodiments, selecting the respective input page for each output page comprises determining a respective assigned indicator that characterizes the input side. Furthermore, selecting the input side includes for allocation to the output side: (i) comparing the assigned respective indicators of several Input pages with the memory reliability optimization objective that extends to the level of one or more target data pages associated with the output page, and (ii) determining an input page among the plurality of Input pages that themselves or their reversibly transformed version meet the optimization objective for memory reliability than the selected input page. In this way, the matching of input pages and suitable Output pages are based on a single indicator and therefore with high efficiency. The indicator is preferably a number and the optimization objective for memory reliability is defined as a mathematical condition defined so that the comparison can be easily carried out as a mathematical calculation. This can determine the achievable Further increase efficiency.

[0038] The indicator associated with an input side may in particular be a function of the number of bits within the Input side with the same given bit value, e.g. "1". In particular, the function can be the identity function , ie the indicator can be equal to the number of bits that have the same given bit value. Counting the occurrences of a particular bit value within a particular bit pattern is an operation that is Usually involves little effort, the achievable efficiency in determining the indicator(s) be further increased.

[0039] In some embodiments, the input data is randomized and the input pages are randomized before Restructuring based on the randomized input data. The randomization of the data is particularly helpful to mitigate cell-to-cell (C2C) interference and thus increase the reliability of the flash memory improve.

[0040] In some embodiments, the respective memory reliability optimization objective assigned to a assigned to a given target data page, as a function of the level of the target data page as one of the following targets selected: (i) Maximize the number of ´´0´´ bit values ​​to be stored on the destination data page; (ii) Maximize the Number of '1' bit values ​​to be stored on the target data page; (iii) Optimize a balance between '0'- bit values ​​and ´´1´´-bit values ​​to be stored on the target data side, ie reaching or at least approaching an equal number of occurrences of both bit values.

[0041] In some embodiments, the flash memory is a 3D NAND flash memory in which the physical pages are distributed across a multitude of stacked layers of flash memory. In this case, the optimization objective for the memory reliability applied to a target data page as a function of both the level of target data page and the layer to which the physical page with the target data page belongs. To further optimize the restructuring of the input data, this definition takes into account that the physical properties of the memory cells of a 3D NAND flash memory usually vary from layer to layer. Specifically, In many 3D NAND flash technologies, the memory cells closer to one end of the stack are slightly different dimensions, e.g., in terms of the thickness of their tunnel oxide, than the memory cells located closer to the opposite end of the stack. Accordingly, the stress resistance of the memory cells, e.g. of their tunnel oxides. The same can and usually is true for their associated error bit counts (Error Bit Counts (EBC), which generally correlate positively with the stress resistance of the memory cells.

[0042] Similarly to what has been generally described above, in the specific case of a 3D NAND flash Memory the respective memory reliability optimization goal associated with a given target data page is a function of both the level of the target data page and the layer to which the physical page with the target data page belongs to, selected as one of the following objectives: (i) Maximize the number of ´´0´´ bit values ​​that can be are to be stored; (ii) Maximize the number of "1" bit values ​​to be stored on the target data page; (iii) Optimize a balance between ´´0´´ bit values ​​and ´´1´´ bit values ​​to be stored on the target data side, ie Achieve or at least approach an equal number of occurrences of both bit values.

[0043] In both cases mentioned above, ie in the more general case (which also applies in particular to 2D NAND flash memory) and in the case of 3D NAND flash memory, one or more of the following definitions may be applied are: (i) Maximizing the number of ´´0´´ bit values ​​is defined as satisfying the condition that the number of bits in an input side or a reversibly transformed version thereof, which has a bit value of one, is less than a defined upper threshold; (ii) Maximizing the number of "1" bit values ​​is defined as satisfying the condition, that the number of bits in an input page or a reversibly transformed version thereof that has a bit value of one, is greater than a defined lower threshold; and / or (iii) optimising a balance between ´´0´´-bit values ​​and ´´1´´-bit values ​​is defined as meeting the condition that the number of bits in an input side or a reversibly transformed version thereof, which have a bit value of one, greater than a defined lower threshold and less than a defined upper threshold. These definitions have the advantage of not requiring absolute maximum of the number of "0" bit values ​​or the number of "0" bit values ​​or an exact balance thereof but rather more relaxed requirements that can be achieved more easily and with less effort (e.g. with fewer iterations to find a good match between input pages and output pages) and thus more efficiently fulfills can be.

[0044] In some embodiments, when multiple input pages or their reversibly transformed versions Satisfy the memory reliability optimization objective associated with the one or more target data pages, assigned to a given output page, an input page among these multiple input pages is used to Allocation to the output side selected for which a degree that meets the optimization objective for the Storage reliability quantified, such as the respective size of any overfulfillment, among the several Input pages are maximized. This allows a selection of a suitable input page that contains both simple (and therefore efficient) and at the same time very effective (with regard to the desired high Storage reliability).

[0045] In some embodiments, selecting the respective input page for association with the respective Output page further (i) selecting an input page from the not yet assigned input pages and transforming this input side according to a reversible transformation scheme determined as a function of this input side, to obtain the reversibly transformed version of that input page; and (ii) storing Transformation information on the basis of which the transformation can be undone in a retrievable manner to restore the non-transformed input page from its transformed version. Transformation scheme is based on the not yet transformed input page and the optimization goal for the Memory reliability defined that of the one or more target data pages associated with the output page is assigned to display in the input page one or more data representations, the corresponding first Threshold voltages of the flash memory are assigned, reversibly by a corresponding number of to replace data representations associated with corresponding second threshold voltages of the flash memory, which are lower than the corresponding first threshold voltages to obtain the transformed version of the input side obtain.

[0046] Accordingly, these embodiments provide a way in which the restructuring of the input data via the reordering according to the above-described way of defining the allocation of output pages to suitable Input pages also an optimization of the content of one or more input pages through the transformation(s) to avoid the use of high Vth states as much as possible. The storage of the Transformation information required for the inversion of the corresponding transformation(s) contributes to helps to recover the entropy of the stored data when reading back and allows the flash memory to intended to function, ie to restore the input data from the data stored in the flash memory.

[0047] The transformation can be carried out in particular when (ie if or only if) in the course of the Restructuring determines that for a given output page there is no unassigned input page can be found that satisfies the storage reliability optimization objective assigned to the one or more target data pages assigned to the output page. Accordingly, the transformation in some of these Embodiments are only used when a restructuring that involves a mere rearrangement of the input data is not sufficient to achieve the optimization goal for storage reliability, while otherwise a This way, the transformation, which usually requires more effort, can be than a mere rearrangement, effectively limited to those situations in which it is required, to achieve the optimization goal for memory reliability. In this way, the method can be more effective be designed more effectively than without this option, while maintaining a high level of efficiency.

[0048] In some embodiments, the one input side is selected to be among the not yet assigned Input sides before transformation minimized to a degree that reduces the size of the remaining gap of the respective input side with regard to the fulfillment of the optimization objective for storage reliability, which is assigned to the one or the multiple target data pages assigned to the output page. Accordingly Accordingly, this particular selection of one input page requires only a minimal change in its content (i.e. minimal in Compared to the required changes for the other input pages considered) to achieve the optimization goal for the This is particularly advantageous because it prevents over-optimization, which can have a negative impact on reliability of the storage is safely avoided.

[0049] In some embodiments, transforming the one input side comprises inverting at least one Subset of the data representations associated with the respective first threshold voltages. This approach is very efficient because inverting (ie reversing bits) is a simple and very efficient bit operation. In addition, the entropy of the input data can be effectively protected.

[0050] Inverting at least a subset of the data representations that represent the respective first threshold voltages are assigned, applying a masking operation to each of the Data representations individually or together. The masking operation can combine the input side mathematically with at least one mask that has a specific bit pattern, so that the masking operation leads to an inversion of the data representation to be inverted. The combination can in particular be a Boolean XOR Operation and one or more masks that have only bit values ​​of 1. Using a variety of different masks, a corresponding variety of different transformation results can be obtained from the Pre-transformation input page is retained and a suitable result from this multitude of results can then be selected as the transformed version of the input page. The other results can be discarded. become.

[0051] Specifically, the input side for the masking operations can be divided into several frames with the same frame size in bits be divided, where the size of the masks in bits is equal to or a multiple of the frame size, while different Masks can have the same or different sizes. Using this frame-based approach enables a particularly simple implementation of the masking operations and above all supports the goal of effectively minimize the necessary changes to the input page in order to achieve the applicable optimization goal for the to meet storage reliability requirements.

[0052] As already indicated above, the masking operation can be repeated several times per input page with different masks. Among the various results that can be achieved in this way, A result can be selected as a transformed version of the input page that has one of the multiple results Fulfillment level maximizes the respective size of the overfulfillment of the optimization objective for storage reliability quantified that the one or more target data pages assigned to the output page by the various results are assigned.

[0053] If several results have the same maximum degree of fulfillment, that result can be considered as transformed version of the input page that differs least from the corresponding untransformed input side in terms of the number of bits that were inverted during the corresponding transformation.

[0054] Specifically, the selection of one result can be performed using a greedy algorithm. For example, the series of masking operations with the different masks can be defined so that the size of the masks with increases over time. Using a greedy algorithm, the series can be terminated as soon as the greedy Algorithm finds a result that meets the optimization goal for memory reliability, but has a lower degree of fulfillment than the previous result. The result that is the most significant of all the results achieved so far has the best degree of fulfillment can then be selected as the one that serves as the transformed version of the input page is selected.

[0055] In some embodiments, the input data is stored in a cache memory other than the multi-level flash memory, such as SLC flash memory or SRAM memory, and the Restructuring of the input data is performed with respect to the input data stored in the cache memory in order to to obtain the output data. In this way, the advantages of caching, such as caching an incoming data stream providing the input data and restructuring according to the procedure effectively combined, and the multi-level flash memory itself does not need to be used for the restructuring process This helps to avoid unnecessary damage to the multi-level flash memory and thus to to maintain lifespan.

[0056] In some embodiments, the respective memory reliability optimization goals assigned to one or the multiple target data pages are assigned, each defined as a function of a calibration parameter that common reliability range of the optimization objectives for storage reliability. The optimization goals for storage reliability can also be defined as Function of the target data pages to which they belong, e.g., as a function of the layer in a 3D NAND flash in which the data pages are located. While the calibration parameter serves to provide the possibility to Fine-tune or otherwise calibrate storage reliability optimization goals to achieve an applicable Defining a reliability margin can reduce the dependence of the storage reliability optimization goals on the Target data pages are used to identify the physical differences between the physical pages to which the target data pages to ensure optimal definition of storage reliability optimization objectives for Optimize the reliability of flash memory.

[0057] A second aspect of the present solution relates to a data processing device, such as a flash memory Control device configured to perform the method of the first aspect.

[0058] In some embodiments, the data processing device comprises one or more processors and has Access to a program memory containing one or more programs which, when executed on one or the plurality of processors cause the data processing device to carry out the method according to the first aspect to carry out.

[0059] Finally, a third aspect of the present solution is directed to a computer program or a computer program product that has instructions to cause the data processing device to to carry out the procedure according to the first aspect of the solution. Specifically, the instructions can be defined in such a way that when executed on one or more processors of the data processing device, it enables the data processing device to cause the procedure to be carried out according to the first aspect of the solution.

[0060] The data processing device of the second aspect may accordingly comprise a program memory in which the computer program is stored. Alternatively, the data processing device can also be set up to access a Computer program that is available externally, for example on one or more servers or other Data processing units, via a communication connection, in particular in order to process data used during the course of execution of the computer program or outputs of the computer program.

[0061] The features and advantages explained with reference to the first aspect of the solution apply accordingly to the other aspects of the solution.

[0062] Further advantages, features and applications of the present solution are described in the following detailed Description and the accompanying figures, where: Fig. 1 schematically shows different flash technologies with a different number of levels illustrated; Fig. 2 schematically illustrates an example 3D NAND flash memory block; Fig. 3 in the subfigure (a) Models of the states of TLC flash cells and their 3-bit binary data representation (coding), in subfigures (b) and (c) examples of the threshold voltage distribution of two different Flash technologies and in sub-figure (d) a diagram showing an exemplary typical Dependence of the required voltage and time for programming flash cells on different states illustrated; Fig. 4A and Fig. 4B show a total of six different synthetic data pattern distributions for a TLC NAND Flash memory; in particular, these figures each show a different byte distribution of a data sequence within a page with three data pages corresponding to the three levels of TLC flash memory; Fig. 5 shows a histogram of the synthetic data patterns from Fig. 4A and Fig. 4B, with the density on the Size of the page is standardized in bytes, e.g. 18336 bytes; Fig. 6 an example EBC of the data retention of DP pages, normalized to the maximum EBC of DP2 For illustration purposes, the EBC is chosen as the maximum EBC of the three sides, ie EBC = MaxEBC (LSP, CSP, MSP); Fig. 7 shows example page content areas with three different optimization conditions / goals; Fig. 8 shows an example masking method for inverting frames (i.e. sections) of the page; Fig. 9 shows in pseudocode an exemplary first embodiment of a method for restructuring Input data to be stored in a multi-level NAND flash memory according to the present solution shows; Fig. 10 shows an example process flow for restructuring input data stored in a multi-level NAND Flash memory to are to be stored, in accordance with the present solution and an examination of the results of a shows the optimization achieved through restructuring; and Fig. 11 Example results for the EBC of (a) data-unaware (DU) and (b) data-aware (DA) scenarios under the W / E cycles = 1000 of the three-side types, EBC-normalized to shows the maximum value of (a) obtained using the method of Fig. 10 in combination with the Methods from Fig. 9 for data-aware (DA) optimization were obtained; and Fig. 12 schematically shows an exemplary data processing device for carrying out the method in the form of a Illustrates storage control within a storage system.

[0063] Fig. 1 schematically illustrates different flash technologies with a different number of Levels, namely Single-Level Cell Flash (SLC), Dual-Level Cell Flash (often referred to as ´´MLC´´, although this term is used in This document, as described above, is broader and covers all types of multi-level cell flash technologies , ie those with two or more bits per cell (C)); and Triple-Level Cell Flash (TLC). In addition to TLC Flash, Flash technologies with more than three levels (ie bits / cell) are possible, such as Quad-Level-Cell (QLC) or Penta-Level- Cell (PLC) with four or five levels.

[0064] Depending on the number k of different bit patterns that can be stored and distinguished per cell C, k-1 threshold voltages V are defined, which are required to distinguish different charge states TH of the flash memory cells, which in turn correspond to a stored bit value (in the case of SLC) or a stored Bit patterns (in multi-level flash) correspond, especially for reading the stored data. In the example in Fig. 1 shows seven threshold voltages V ,..., V for the TLC flash memory. TH0 TH6

[0065] Typically, a smaller number of levels of flash memory is more advantageous in terms of high Reliability and high performance, while a higher number of levels is more advantageous in terms of high density and low production costs.

[0066] Fig. 2 schematically illustrates an exemplary 3D NAND flash memory block. A 3D NAND flash memory is a type of non-volatile memory that stores data in a three-dimensional (3D) structure. The structure of a 3D NAND flash consists of several layers of interconnected transistors and capacitors that are stacked on top of each other stacked to increase storage density. The bottom layer of the 3D NAND flash is the substrate, which typically made of silicon. This layer forms the basis for the entire structure and serves as an electrical path for the signals.

[0067] A thin oxide layer, the so-called tunnel oxide, is deposited on the substrate and serves as Tunnel barrier. This layer helps control the flow of electrons through the flash memory cells. The flash memory cells are located in the next higher or higher layers. These cells consist of a series of Transistors and capacitors connected together to store data. Each cell can store multiple bits of data (MLC) arranged in a grid-like pattern within each cell-bearing layer.

[0068] Above the flash memory cells there is an inspection gate that acts as a barrier and prevents Electrons escape during the reading process. This gate also contributes to the reading speed and to improve the accuracy of the flash memory. A selective gate is an additional layer that connects the flash memory cells from the control circuits. It allows a control circuit to selectively switch the cells on or off, to access the stored data. The control circuit is located at the top of the 3D NAND flash structure. include the gate drivers, sense amplifiers and other components used to read and write data to the flash Memory cells are necessary.

[0069] The different layers in the 3D NAND flash are connected to each other by a complex network of connections These connections allow the control circuits to communicate with the flash memory cells and read or write data as needed. Multiple insulation layers are used throughout the structure, to insulate the different layers and prevent electrical short circuits between them. Top and bottom in The 3D NAND flash structure contains electrodes that provide a path for electrons through the memory cells.

[0070] The exemplary block B (Fig. 2) of the 3D NAND flash structure has (as part of the overall flash described above) Structure) has a plurality of flash memory cells arranged in layers, each of several layers (Levels) L , ..., L has a subset of the memory cells C and the layers L , ..., L are stacked. The number M 0 M 0 M of layers in current technologies already has more than M=100 layers and the industry is constantly trying to achieve even higher values ​​for M in order to increase storage density and to further reduce costs. The 3D NAND flash memory block B has several columns in which the different memory cells C are located at the intersection points of the columns and layers in block B. Each row of cells C in a particular layer and along a dimension within the layers defines a physical Side P of block B, such as the exemplary sides P and P . Accordingly, a number of 0 N #P of pages arranged laterally and sequentially along the other dimension within each layer.

[0071] By stacking these layers on top of each other, the storage density in 3D NAND flash can be increased compared to compared to conventional 2D flash storage. This allows more data to be stored in a smaller area making them an attractive option for use in high-density devices such as smartphones and laptops.

[0072] Fig. 3 shows in sub-figure (a) models of the states of TLC flash cells and their 3-bit binary data representation (coding), in sub-figures (b) and (c) examples of the threshold voltage distribution of two different flash Technologies and in sub-figure (d) a diagram showing an exemplary typical dependency of the required Shows voltage and time for programming flash cells of different states. NAND flash memory

[0073] As discussed above, NAND flash is organized into blocks and pages. MLC pages are divided into a variety of of data pages (one per level) that share the same physical cells. In 3D NAND flash memory, The physical pages are stacked on several layers. The physical pages are arranged from lower to upper layer organized, see Fig. 3. When writing to TLC, for example, three bits are stored per cell, and therefore the Data is mapped to three logical pages, which we call ´´data pages´´ in this document: least significant bit (LSB) and Least significant side (LSP), middle significant bit (CSB) and middle significant side (CSP) and most significant bit (MSB) and most significant page (MSP), see Fig. 3. The basic NAND flash operations are reading, writing (programming) and delete. These operations are supported with different granularities. For example, reading and Writing at the level of a physical page, while erasing can only occur at the level of a block. However, the nature of the NAND flash cell does not support in-place updates. To update a physical page To write / update, the block containing the physical page must first be deleted.

[0074] Write-erase cycle: On the one hand, writing into a flash memory cell works by storing the representative charge amounts of the corresponding data bits, as shown in Fig. 2. This is achieved by applying the correct programming voltage and timing to ensure that the required amount of charge is correctly applied to the cell can be transferred. The stored charge determines the respective threshold voltage V of the flash cell, i.e. TH i.e., the minimum voltage required to turn on the cell / transistor when reading data. On the other hand, During the NAND flash erase operation, the stored charge is removed from the cells. Erasing requires a high voltage is applied to the gate of the cell. The high programming / erase voltage stresses the flash cell and can cause unwanted shocks. Specifically, the stress on MLC flash memory is typically more pronounced than with SLC flash memory. Each write-erase (W / E) cycle causes permanent internal damage to the flash Cell due to the injection of hot charge carriers and the degradation of the tunnel oxide, such as the generation of Traps. This in turn leads to a gradual (ie incremental) degradation, which reduces the lifetime of the flash memory. The NAND flash endurance determines the maximum number of W / E cycles that the flash cells while still being able to store charges correctly. For example, the 3D TLC NAND flash used to generate the results discussed below with reference to Figures 10 to 15 was up to 3000 W / E cycles as nominal endurance rate.

[0075] Caching: Storage devices (e.g., Solid State Drive (SSD)) typically store data upon arrival. However, writing to flash memory is an atomic operation in which all data is copied to the flash memory before programming the corresponding pages. For example, with 3D TLC NAND Flash, the three Data pages (LSP, CSP and MSP) must be available and transferred to the flash device before programming. However, a caching mechanism is mandatory if there is not enough data available or direct writing is not It even helps improve write throughput in MLC flash, as writing to the cache is much faster than writing to the MLC flash. After that, data migration is important, where the cached data is Flash pages are copied. It should be noted that this process is completely hidden from the host and normally does not affect write throughput. In addition, the host (e.g., a computer that uses flash memory for data storage) does not specify the physical location of the data, which is entirely determined by the storage device itself is managed.

[0076] Interference: In NAND flash memory, neighboring cells influence each other, causing the stored logical values. As already mentioned, the stored charge amount represents the logical value (data) stored in a flash cell. Due to the coupling capacitance between the flash cells, the V TH of a flash cell while the neighboring cells are being programmed, as charge is transferred from one cell to another Cell-to-cell (C2C) interference is a phenomenon in which the threshold voltage of a flash cell, the programmed, unintentionally changes the neighboring victim cell(s). This changes the logical value of the victim cell incorrect, which causes the data to be corrupted when reading the data back.

[0077] Even if the cells have been programmed correctly, the stored charge can change over time from a cell to another and change the stored logical value of the victim cells, which affects the Data retention in the flash. Data retention defines the time in which the cells can retain enough charge to to read data correctly. The state of the neighboring cell can particularly affect the victim cell. The large Similarity of charges (states) within the neighborhood is very destructive and leads to stronger disturbances. On the other hand, the higher the charge of the neighboring cell, the smaller the threshold voltage shift. Randomness of the data therefore compromises the effects mentioned above and mitigates the disturbances of the programming. Therefore, the use of a random generator in the memory device generally helps to to avoid the most unfavorable neighborhood charges.

[0078] Correction: NAND flash loses charge over time, making it inherently susceptible to errors. Therefore stored binary data can be misinterpreted due to bit inversions. Thus, the stored Data corrupted while reading.

[0079] Flash memory devices use sophisticated mechanisms to detect and correct errors, such as such as error correction codes (ECC). ECC is commonly used in NAND flash devices to correct bit errors. detect and correct. However, the number of corrections per data unit is limited with ECC. Data dependency

[0080] The impact of data on the reliability of NAND flash can be very large. As already mentioned, With each W / E cycle, the internal degradation of the flash cells gradually increases. The level of degradation is directly proportional to the load level and load time (i.e. voltage level and time) acting on the cell. The load is therefore determined by the applied voltage when writing (programming) and erasing as well as by the writing time The present solution only takes into account the degradation caused by writing, which - up to a certain to some extent - can be mitigated if the data is organized in a reliability-conscious manner and be tailored as explained in more detail below.

[0081] Each data representation has a certain amount of charge that should be stored in the cell. The larger the stored charge (ie V ), the higher the load (ie higher voltage and longer time, see Fig. 3 (d) TH ), which in turn increases the internal degradation of the flash cell and vice versa. Therefore, the level of flash Degradation depends on the data. The higher the V, the lower the reliability due to the high electrical TH field above the tunnel oxide.

[0082] Fig. 3(a) shows the TLC flash cell states S, which are defined as S (i.e., erase) and the states S to S, ER AG where each state has a unique data representation.

[0083] Figures 3(b) and (c) show the distributions of the threshold voltage V and the data plots for each Vth for TH two Flash technologies. As shown, the technologies have different representations of V (ie TH different amounts of charge) and states.

[0084] Fig. 3(d) shows the programming voltage required for each V (ie each state) and the corresponding TH Programming time. As shown, the higher the V , the higher the required voltage and the longer the TH programming time, and vice versa. Therefore, the states on the right side in Fig. 3(a) - 3(c) are more likely to be a cause of the Degradation of the flash cells than on the left side. For example, state S leads to a stronger degradation than G the state S . However, this should be compared with the technology, since the states when considering the A actual data may have different logical representations. Data-aware characterization

[0085] NAND flash vendors generally recommend randomizing the stored data on each page. in turn helps to reduce C2C interference and thus improve reliability. Therefore, the Reliability of the NAND flash is data dependent, which also affects the content of the cells and the neighborhood affects.

[0086] In developing this solution, various synthetic data patterns (about 20 data sets) for 3D TLC NAND flash to characterize the dependence between reliability and data. Data patterns were synthetically tailored to cover all possible use cases in consciousness and Cover the unawareness of flash technology (e.g., 3D structure and W / E degradation (Fig. 3)).

[0087] Fig. 4A and Fig. 4B together show a subset of the above-mentioned data sets, which consists of six different synthetic data patterns (DP) for the two TLC NAND flash technologies from Fig. 3(b) and Fig. 3(c). Specifically, Fig. 4A and Fig. 4B each show a different byte distribution of a data sequence within a physical page with three associated data pages corresponding to the three levels of TLC flash memory.

[0088] (DP1): The data are trimmed to cover the sequence of all unique TLC values ​​(ie, three Bits of eight states to form three bytes (3x8) for LSB, CSB and MSB, based on the coding in Fig. 3(c)), and then applied everywhere, taking into account similar patterns of neighboring cells and the 3D structure of the flash be moved to avoid similarity in the neighborhood.

[0089] (DP2): The data is generated randomly for the entire block, using the 3D structure of the NAND Flash is taken into account (ie the number of layers is the seed for the random generator).

[0090] (DP3): The data is generated randomly for the entire block, using the 3D structure of the NAND Flash is taken into account. The data is only distorted for LSP to include more binary zero values.

[0091] (DP4): The data is generated randomly for the entire block, using the 3D structure of the NAND Flash is taken into account. The data is only distorted for LSP to contain more binary ones.

[0092] (DP5): The data is generated randomly for the entire block, using the 3D structure of the NAND Flash is taken into account. The data is only distorted for MSP to include more binary zero values.

[0093] (DP6): The data is generated randomly for the entire block, using the 3D structure of the NAND Flash is taken into account. The data is only distorted for MSP to contain more binary ones.

[0094] Fig. 4A and Fig. 4B show the data order (ie the byte-wise distribution) within the three data pages (d (i.e., LSP, CSP, and MSP) of the DPs mentioned above. As can be seen, the data values ​​in all DPs except DP1 fully randomized.

[0095] Fig. 5 shows a state (ie, a 3-bit) histogram of the synthetic data patterns (DP) from Fig. 4A and Fig. 4B for a TLC flash, where the density is normalized to the page size in bytes, e.g., 18336 bytes. As can be seen, DP1 has histogram-wise (not bitwise) almost similar contents to DP2, whereby the logical states in both cases are almost balanced. In addition, the DPs with random data still have different histograms, such as DP3-DP6 are generated by shifting the states for a particular technology to the left, as shown in Fig. 3, which increases the occurrence of ones or zeros on certain pages. This in turn increases the probability of certain conditions occurring by distorting data content. As shown in Fig. 3(b) and (c) show, the distorted data increase / decrease the density (i.e., the occurrence) of the states (i.e., V ). DP3 TH and DP6 are used for the coding in Fig. 3(b), while DP4 and DP5 are used for the coding in Fig. 3(c) Applying DP with the other technology results in very high W / E over W / E cycles, which increases the load of the cells is increased because a higher Vth is used for programming. For example, from Fig. 3(b) it can be seen that an increasing number of ones on the MSP (ie DP6) or increasing zeros on the LSP (DP3) the V - TH occurrence on the left side. This in turn may suppress the W / E cycle-induced Degradation.

[0096] To quantify the reliability degradation caused by each DP in combination with W / E The reliability of the test flash memories described above was investigated. Each DP was used to load a block for W / E = 1000 cycles. The reliability of the block was then tested ten minutes after Programming is being examined. The reliability indicator in this area is the error bit count (EBC), which refers to the number of bit revolutions in of a page without using ECC for corrections. Please note that this section only covers the EBC results under W / E are shown to exclude other reliability risks. Below are also the reliability under W / E, the data retention and the variations between the layers were examined, as they are latest 3D flash memories pose the greatest reliability risks.

[0097] Fig. 6 shows the results of these tests for two different technologies. Specifically, Fig. 6 shows the normalized EBC of the DP relative to the maximum EBC of DP2 as the initial value. For illustrative purposes, the EBC of a DP is chosen as the maximum EBC of the three sides sharing the same physical cells (i.e. EBC = Max EBC (LSP, CSP, MSP)). It should be noted that the maximum EBC was chosen because it represents the worst-case scenario and thus the required correction capability of each NAND flash controller. Variations between the EBC of the different Page types are still noticeable and will be taken into account in later optimization.

[0098] The results show that different DPs have different EBC, which is directly related to the internal Degradation at each W / E cycle and slight C2C perturbations, since no data retention is used. Although the data in the DP1 sequence appears to be bit-unique, the EBC of DP1 is very high (about 600× of DP2), since the neighborhood has a similar level of loadings, which violates the random constraints and program disruption and C2C interference are significantly worsened. This underlines the importance of Random generator as in DP2. DP2 uses a modern random generator based on the manufacturers' recommendations However, DP2 shows a higher maximum EBC compared to the distorted DP. This is expected since DP3- DP6 are designed to suppress degradation with a predominantly significant reduction of EBC.

[0099] It is important to note that there is no single optimal DP for the entire range of pages and different technologies. DP3 and DP6, for example, reduce the EBC over pages using the technology shown in Fig. 3(b), while they significantly increase the EBC on the technology in Fig. 3(c). Therefore, a compromise must be found by using more as a DP to maximize profits and optimality considering the underlying technology. Since DP2 also describes the typical form of data stored in flash storage devices, optimizing DP2 for synthetic patterns is apparently the only way to achieve data-aware flash reliability. It is noteworthy that the EBC decreases towards higher pages for all DPs, as the uppermost layers are generally more tolerant to degradation, as they are affected by the manufacturing process tend to be larger cells.

[0100] In summary, the results of the characterization described above indicate indicate that the Flash content is not suitable for the above-defined objective of ensuring the reliability and durability of the Flash memory can be optimized by increasing the density of states on the left side (in Fig. 2) of the data (states with low V , e.g. S - S ) are maximized and the states on the right side are reduced. The TH ER E means that each page type (i.e. the type of data page) should have a different optimization goal and the variations between cells are considered advisable. The optimization must be data-aware and should be systematic without wiping out the entropy of the stored data. However, the optimization must be conditionally reversible, so that the entropy of the data is preserved when read back and the storage device functions as intended.

[0101] The method of the present solution, which due to its dependence on the data to be stored is also known as ´´data-aware reliability optimization technique´´ will now be illustrated by means of exemplary Embodiments described in more detail.

[0102] The technique is based on optimizing the data before it is written to the flash memory. Since the host (who can provide the data to be stored and / or request the reading of data already stored) the does not know the actual physical location of the stored data in the flash memory, the storage device the privilege to organize and modify the data based on the management technology it uses. The proposed technique is intended to be generic (i.e. applicable to any NAND flash technology), which is important given the variety of flash technologies with different representations of the stored charge and the fact that the Data representation can differ from one Flash provider to another, is a desirable further goal. Based on the characteristics of Flash technology, the technique can therefore be used as a post-optimization of the input data, such as such as the output of a random generator.

[0103] The technique can be used particularly in conjunction with input data that has already been randomized and are cached or when they arrive (e.g. at the memory controller that executes the technology) so Specifically, the data can be collected in the SRAM cache to complete three pages (ie as with TLC), and then randomized and written to flash memory. In many cases, SLC cache Pages instead of expensive SRAM. Therefore, in these cases, the data is already read back from the SLC cache randomized. It should be noted that the technique works with a data migration, which typically occurs when there are enough pages in the cache. However, the technique can also be used in cache-free storage devices, that write directly to the flash memory before the data is written to the flash memory, which write throughput. Data-aware Flash Reliability Optimization aims to to suppress internal degradation caused by each W / E cycle, reduce the EBC and / or extend the lifetime to extend the memory. Data-aware reliability modeling

[0104] As the characterization described above shows, each data page type should have a unique data pattern to enable data-aware flash reliability. For example, an LSP requires more logical Zeros as ones. The technique helps to increase the probability of the desired patterns occurring and while preserving the randomness of the data. This can especially support fast runtime decisions and requires fewer resources.

[0105] The content of a page, in particular an input page, can be quantified by a suitable indicator, such as the sum of logical ones and / or zeros (ie bits with the value '1' or '0') on the (input) Page. Equations (1) and (2) provided below are examples of this approach: PageZeros=(∑b=0mbi t(!b)) / m>Zeros PageOnes=(∑b=0mbit(b)) / m>Ones where m is the number of bits per page, Page and Page Zeros ones Indicators are defined as the sum of logical zeros and ones on the page, and ´´Ones´´ and ´´Zeros´´ threshold constants (e.g. 60%). Accordingly, a side that meets the condition from Eq. (1) more ´´0´´ bit values ​​on the page than the threshold constant zeros, and a page that satisfies the condition from Eq. (2) satisfies, has more '1' bit values ​​on the page than the threshold constant ones.

[0106] Randomized data should not be altered to preserve randomization when reading back the data Otherwise, the changes would have to be tracked. Therefore, the technology only takes into account minimal changes, by inverting only parts of the input side (ie reversing logical bits 0 → 1 and 1 → 0) that are negligible overhead, as will be explained later. The technique can be described as optimization algorithm that rank the locations of pages based on their content, Flash technology and page types and (optionally) optimizes the page content. The technology attempts to optimize the input data restructure so that the threshold voltages V of the flash cells are as far as possible on the left side of the V - TH TH distribution, i.e., at lower V states, while maintaining the randomness of the data. TH

[0107] The optimization objectives for the exemplary embodiment of the technique may be as defined in the following equations described: Page[i](l)={MaxZeros,∑b=0mBit(b)<Zth(l)MaxOnes,∑b=0mBit(b)> Other Balance, Zth(l)<∑b=0mBit(b) <oth(l) wobei page die ausgewählte seite ist, l="1" schichtanzahl der (z. b. für schicht l1 ) for 3D Flash, the index i represents a page type (e.g. LSP or CSP), m is the number of bits in a page, Z and O th th Optimization constraints are as defined in Eq. (4) and Eq. (5) below. The page Page with the Page type index i is selected, e.g., using the greedy method, if it meets the optimization goal (Storage reliability optimization objective) based on the available metadata.

[0108] The optimization itself can be implemented in particular as a multi-objective optimization process that attempts to To maximize profit with a minimum number of changes to the input data using the greedy method. This way, the randomness of the data is maintained with minimal overhead for reading performance. that any generic multi-objective algorithm can be used for the technique under given optimization objectives. The (memory reliability) optimization objectives (for a logical page P[i]) can be defined in particular according to Eq. (3) in in abbreviated form as follows: - MaxZeros: Maximizing the number of zeros (Eq. (1)) - MaxOnes: Maximizing the number of ones (Eq. (2)) - Balance: Balanced content, ie number of ones ≈ number of zeros

[0109] To take into account the variations of the layer process, where different optimization levels may be required, and to make the technique more general, the model categorizes the content of the pages into three Levels / regions based on defined constraints, as shown in Fig. 7 and Eq. (3). The thresholds may in particular be defined on the basis of an experimental study and defined for each layer, and can even be adjusted at runtime. Using a single optimization level for all layers is still possible, although this usually leads to significant EBC differences between the different layers.

[0110] The optimization constraints Z and O can be defined as in Eq. (4) and Eq. (5) below for the number of th th zeros and ones, respectively, taking into account the differences between the layers. Zth(l)=ez[l]-αr; Oth(l)=ez[l]+α MaskPage=Page[i]⊕Im[j]

[0111] Here, ε is an experimental ´´zeros´´ threshold matrix, ε is an experimental ´´ones´´- z0 Threshold matrix, α a calibration constant (which can be used to obtain a layer-independent Variation variant of the boundary conditions in Fig. 7), MaskPage the masked page and I a matrix m different inversion masks (i.e. vectors of logical ones for bit inversion). I is generated by converting the page into m a certain number n of frames F is divided, for example into the frames F , F , ..., F , and then all 0 1 n Inversion combinations between these segments are found. Such optimization aims to Greedy method to select pages with content that maximizes the optimization goals (profit).

[0112] This is done by inverting parts of the page content (see Eq. (6)). Therefore, the exemplary Optimization algorithm (Algorithm 1), which will be discussed in more detail below, the input side in different frames, evaluates all optimization scenarios (ie inverts frames), as shown in Fig. 8, and selects Then, using the greedy method, select the solution that maximizes the profit with minimal changes. The mask set M can have masks of different sizes, for example, masks (M , M ) the size of a frame and masks (M ) of 1 2 x larger size, e.g., the size of several frames, up to a mask (M ) the size of the entire page. n In this example, the masks are completely filled with ones, so that the linking of the content of the input page with the mask by a Boolean exclusive-or (XOR) operation results in a reversal of the bits in the page that is the mask. Obviously, an XOR operation is per se a reversible operation, because if you If the result is combined with the same mask a second time, the original page is obtained. Therefore, the resulting transformation scheme of the input side, which is determined by the mask with respect to the above-mentioned with the The solution selected by the greedy method is defined as a reversible transformation. Accordingly, the Apply the selected transformation to the input page to a transformed version that has an optimized Content to reduce degradation and increase the lifespan of the flash memory. Algorithm for data-aware reliability optimization

[0113] Fig. 9 shows in pseudocode an exemplary first embodiment of a method for restructuring Input data to be stored in a multi-level NAND flash memory according to the present solution;

[0114] The method of the exemplary technique is summarized in Algorithm 1 provided in Figure 9. This algorithm first quantifies the page contents by counting the number of ones in all cached Input pages (´´Pages´´ stored in a page array P) are counted and the results are displayed in a arr Result table T stores as shown in row 1 and row 2.

[0115] To take the underlying flash technology into account, the algorithm then reads the metadata MD of the Flash technology (i.e. V distributions, page size m, page types, data encoding, etc.) and then defines the TH Optimization objectives G (e.g. per (data) page type (line 3), e.g. according to Eq. (3).

[0116] Then the algorithm restructures the input pages by applying a data-aware Flash reliability optimization, where the content of the pages is selected to ensure that it Optimization conditions (see Eq. (3)) are met to achieve the results obtained from the stored To suppress damage caused by data (line 5 to line 17). The optimization works individually for each page type P (line 5) and then finds the layer I of the current physical target page D (line 6) to determine the optimization goal G as type P Function of this layer / to select.

[0117] Then the algorithm examines all available solutions (input pages) that satisfy the optimization objectives and selects the optimal solution that maximizes profit using the greedy method (lines 7 to 9). The algorithm also optimizes the available pages directly for the desired memory locations to ensure the write order of the flash pages in a block (ie between LSB / CSB / MSB pages and between layers). Only the three available pages in the TLC case and optimized taking into account page type and layer. If not If enough data is available, a memory controller can generate random data, which can also be optimized must.

[0118] It should be noted that the data pages should preferably be randomized to minimize the dependence of the To minimize the error rate of the data values. Good randomization aims to randomly select an equal number of distributed zeros and ones to have a similar degree of degradation across W / E, so that little There is room for optimization. Therefore, the algorithm optimizes the content of the input page to reduce the number of zeros and To change ones if no solution is found.

[0119] The algorithm continues to search for pages that satisfy the desired optimization goals G (line 7). This is done by examining the number of ones or zeros according to the page type and the number of layers.

[0120] (Only) if there is no solution, the algorithm selects the best candidate page for optimization, ie the Page with the highest probability of quickly fulfilling the optimization conditions and no solution candidate (line 11). It is assumed that the best candidate page is the one that has a minimum number of ones or zeros, depending on the optimization goal G.

[0121] Then the algorithm examines all predefined inversion masks M in I to find the one mask M, m whose application fulfills the objective G (line 13).

[0122] The final masking can be formed from a combination of several images F with corresponding masks M where each mask M is represented as an inverting binary vector that represents the inversion of the corresponding image It should be noted that the smaller the mask, the better the solution and therefore the reliability, However, this comes at the expense of performance and the overhead of the administrative data. It is important to note that over-optimization can lead to insufficient reliability. Over-optimization means that the data exceeds a certain limit where a high level of neighborhood similarity is observed, thus reducing the work of the random generator is largely eliminated. Therefore, the algorithm applies a conservative selection by it makes only minimal changes (ie, minimal masking) to satisfy the optimization objective G.

[0123] The algorithm then updates the result table T with all required administrative data (line 15), e.g. B. Page content, inversion vector, etc. The algorithm optimizes all cached pages, provided that enough pages are available. Otherwise, the remaining data will wait for the next iteration, or random data is written. It is important that the technique is generic and can be used with all available data for Optimization works. At the same time, it is a multi-objective optimization method.

[0124] Fig. 10 shows an example process flow for restructuring input data stored in a multi-level NAND flash memory according to the present solution and an investigation of the results of a the optimization achieved through restructuring.

[0125] A data generator, such as a host computer, generates and provides input data stored in the flash memory (Flash). During the optimization process, the input data is first randomized and then further processed by the data-aware restructuring (optimization) process of the present solution, the Flash Technology Data with details on the technology of the flash memory and other relevant information for the Restructuring process (see Fig. 9) as further inputs from a data store.

[0126] The data-aware restructuring (optimization) process results in, for each input page in the input data a corresponding output page in the process output data as a result of the optimization. The output data are sent to the flash memory and stored there (write data).

[0127] Figure 10 also shows a test procedure used to test the effectiveness of the restructuring process. For this purpose, both the Both the randomized input data and the output data resulting from the optimization are stored in the flash memory and also provided to an error estimation process configured to estimate the error rates (e.g., normalized EBC) contained in the stored randomized input data and in the corresponding stored optimized output data after a given number of W / E cycles These error rates can then be compared to determine the effectiveness of the optimization process. Example evaluation results

[0128] Fig. 11 shows exemplary results for the EBC of (a) data-unaware (DU) and (b) data-aware (DA) scenarios under the W / E cycles = 1000 of the three-side types, EBC-normalized to the Maximum value of (a). The results were obtained using the method shown in Fig. 10 in combination with the Method from Fig. 9 for data-aware (DA) optimization.

[0129] A set of blocks with DU and DA scenarios was tested. The sides of the first and last 12 layers for DA have been optimized (restructured) by increasing the optimization constraints and at the same time making Restrictions for internal layers were used. In addition, the data retention time was extended to ensure the EBC to further highlight the results of the upper layers. Figure 11 shows the EBC of the two scenarios (i.e., DU and DA), normalized to the maximum EBC in DU.

[0130] Fig. 11(a) shows the typical scenario, and as can be seen, the EBC in the lower and upper layers is Compared to the inner layers, the EBC of the upper and lower layers is over 50% higher than all other layers. This can be explained by several aspects: (1) The lower layers are smaller than the other layers due to the manufacturing process, which worsens the effects of internal damage. (2) The top layers are subject to a higher quenching voltage than other layers, which which in turn increases the damage to the internal cell via W / E. (3) Larger cells in the upper layers are more affected by C2C because the cells are closer together than in the lower layers.

[0131] Due to the high EBC, endurance and durability of the NAND memory can be limited to the upper and lower Layers may be limited. At the same time, many pages are still in good condition.

[0132] However, Fig. 11(b) shows how DU suppresses these fluctuations under the same operating conditions and thus can improve the reliability and lifetime of the device. Therefore, DA can be used in spatial applications of be of great benefit to optimize the desired layers and mitigate process variations (e.g. L2L). Storage system with data processing device

[0133] Fig. 12 shows an exemplary memory system 1 comprising a memory controller 2 and a NAND flash Storage device 3, e.g., of the 3D NAND TLC type. The storage system 1 is connected to a host 4, such as a Computer to which the memory system 1 belongs, via a set of address lines A1, a set of data lines D1 and a set of control lines C1. The memory controller 2 has a processing unit 2a and an internal memory 2b, typically of the embedded type, and is connected to the flash memory 3 via a Address bus A2, a data bus D2 and a control bus C2. Accordingly, the host has 4 indirect read and / or write access to the memory 3 via its connections A1, D1 and C1 to the memory controller 2, which can in turn access memory 3 directly via buses A2, D2 and C2. Each of the set of lines or Buses A1, B1, C1, A2, B2 and C2 can be implemented by one or more individual communication lines.

[0134] The memory controller 2 is configured as a data processing device adapted to Method of the present solution, in particular as described below with reference to Figs. 7 to 9 For this purpose, the memory controller 2 can store a computer program in its internal memory 2b which is configured to carry out the method when it is on the processing unit 2a of the Memory Controller 2. Alternatively, the program may, for example, be located wholly or partly in the memory 3 or in an additional program memory (not shown) or even by a hard-wired circuit be implemented.

[0135] While at least one exemplary embodiment of the present solution has been described above, It should be noted that a large number of variations exist. Furthermore, it is understood that the described exemplary embodiments illustrate only non-limiting examples of how the present solution can be implemented and that it is not intended to limit the scope, application or configuration of the devices and methods described herein. Rather, the foregoing Description to the person skilled in the art constructions for implementing at least one exemplary embodiment of the present solution, it being understood that various changes in functionality and arrangement of the elements of the exemplary embodiment can be made without departing from the scope of the invention provided by the attached Claims and their legal equivalents defined subject matter. LIST OF REFERENCE SYMBOLS 1 storage system 2 Memory control, including coding device 2a Processing unit 2b Embedded memory of the memory controller 3 Non-volatile memory, especially flash memory 4 Host A1 address line(s) D1 Data line(s) C1 Control line(s) A2 address bus D2 data bus C2 control bus B Flash memory block C Flash memory cell CD cell degradation D probability density DP data pattern x D Number of (physical) landing pages p EBC error bit counting F, F frames x G (Memory Reliability) Optimization Objective i Index for page type I Frame mask set M m L layers x m page size, in number of bits M, M (frame) masks x MD Flash metadata Ones Number of bit values ​​´´1´´ O (Upper) optimization constraint TH Z (Lower) optimization constraint TH P side, especially input side P Page arrangement, saving and defining the page structure of input pages arr P Number of pages per shift I P Data page type, e.g., MSP, CSP, or LSP in the case of TLC flash Type Pages[ ] Arrangement of output pages Page input page α Reliability margin parameter P physical page number 0 0 P physical page number N N #P Page numbering S, S states of a memory cell, e.g. a TLC cell x T Results table T Programming time P V programming voltage P V threshold voltage THx V voltage Zeros Number of bit values ​​"0" ⊕ Boolean XOR operation

Claims

1. A method for restructuring input data to be stored in a NAND flash memory having a plurality of of multi-level flash memory cells arranged in multiple physical pages, each of which has a defined number N > 1 of data pages corresponding to the different levels of the multi-level flash memory wherein the method comprises: based on a defined page structure, according to which the input data is segmented into several logical input pages are, restructuring the segmented input data to obtain corresponding output data, which is divided into logical Output pages are segmented, with each output page having one or more associated target data pages for storing of the content of the output page therein; and Output the segmented output data to Storage in flash memory in accordance with the mappings between the output pages and their respective Target data pages; restructuring includes: Assigning a respective input page to each output page, and wherein selecting the respective input page for Assignment to the respective output page is based on the following: the level of the one or more target data pages associated with the output page, the content of the input page and a storage reliability optimization objective that is defined as a function of the level of the one or more Target data pages are defined that are assigned to the output page, where the input side is selected such that it or a reversibly transformed version thereof meets the optimization objective for storage reliability that the one or more target data pages associated with the output page and the content of the output page is correspondingly considered to be that of the input page or its reversibly transformed version is defined.

2. The method of claim 1, wherein selecting the respective corresponding input page for each output page Determining, for each of the input pages, a respective associated indicator comprising the input page characterized; and Selecting the input page to assign to the output page includes: Comparing the assigned respective indicators of several input pages with the optimization goal for the Memory reliability, which refers to the level of the one or more target data pages that are assigned to the output page are assigned, and Determining an input page among the multiple input pages that is itself or its reversibly transformed version satisfies the memory reliability optimization objective than the selected input page.

3. The method of claim 2, wherein the associated indicator of an input side is a function of the number of bits within the input side with the same given bit value.

4. Method according to one of the preceding claims, wherein: the input data is randomized, and the input pages are defined before restructuring based on the randomized input data.

5. Method according to one of the preceding claims, wherein the respective optimization objective for the Memory reliability associated with a particular target data page as a function of the level of the target data page as one of the following is selected: Maximize the number of '0' bit values ​​stored on the destination data page; Maximize the number of 1-bit values ​​to be stored on the destination data page; Optimize a balance between 0-bit values ​​and 1-bit values ​​to be stored on the destination data page.

6. The method according to any one of claims 1 to 4, wherein: the flash memory is a 3D NAND flash memory in which the physical pages are stacked over a multitude of Layers of flash memory are distributed, and the memory reliability optimization objective applied to a target data page as a function of both the level of the target data page and the layer to which the physical page containing the target data page belongs.

7. The method according to claim 6, wherein the respective optimization objective for the memory reliability corresponding to a specific Target data page is assigned as a function of both the level of the target data page and the layer to which the physical page containing the target data page is selected as one of the following: Maximize the number of '0' bit values ​​to be stored on the destination data page; Maximize the number of 1-bit values ​​to be stored on the destination data page; Optimize a balance between 0-bit values ​​and 1-bit values ​​to be stored on the destination data page.

8. The method according to claim 5 or 7, wherein: Maximizing the number of ´´0´´ bit values ​​is defined as fulfilling the condition that the number of bits in a input side or a reversibly transformed version thereof, which have a bit value of one, less than a defined upper threshold; Maximizing the number of 1-bit values ​​is defined as fulfilling the condition that the number of bits in a input side or a reversibly transformed version thereof, which have a bit value of one, greater than a defined lower threshold; and / or optimizing a balance between ´´0´´ bit values ​​and ´´1´´ bit values ​​is defined as fulfilling the condition, that the number of bits in an input page or a reversibly transformed version thereof that has a bit value of one, is greater than a defined lower threshold and less than a defined upper threshold.

9. Method according to one of the preceding claims, wherein, if several input pages or their reversibly transformed versions meet the optimization goal for storage reliability that is assigned to one or the multiple target data pages associated with a given output page, an input page among these multiple input pages is selected for assignment to the output page for which a degree that represents the Fulfillment of the optimization objective for memory reliability quantified, maximized among the multiple input pages is.

10. Method according to one of the preceding claims, wherein the selection of the respective input page for assignment to the respective output page further selecting an input page from the input pages not yet assigned and Transforming this input side according to a reversible transformation scheme that is defined as a function of this input side is determined to obtain the reversibly transformed version of that input page; and storing Transformation information on the basis of which the transformation can be undone in a retrievable manner can be used to restore the non-transformed input page from its transformed version; where the Transformation scheme based on the not yet transformed input page and the optimization goal for the Memory reliability is defined that of the one or more target data pages associated with the output page is assigned to display in the input page one or more data representations, the corresponding first Threshold voltages of the flash memory are assigned, reversibly by a corresponding number of to replace data representations associated with corresponding second threshold voltages of the flash memory, which are lower than the corresponding first threshold voltages to obtain the transformed version of the input side obtain.

11. The method according to claim 10, wherein the transformation is carried out when, in the course of the restructuring it is determined that no unassigned input page can be found for a given output page, that satisfies the memory reliability optimization objective assigned to one or more of the output side assigned target data pages.

12. The method according to claim 10 or 11, wherein the one input page is selected such that it is among the not yet assigned input sides before transformation minimizes a degree that reduces the size of the remaining gap of the respective input side with regard to the fulfillment of the optimization objective for storage reliability, which which is assigned to one or more target data pages associated with the output page.

13. The method according to any one of claims 10 to 12, wherein transforming the one input side comprises inverting, within this input page, of at least a subset of the data representations that represent the respective first threshold voltages are assigned.

14. The method of claim 13, wherein inverting at least a subset of the data representations comprising the respective first threshold voltages, applying a masking operation to each of the inverting data representations individually or jointly, where the masking operation is mathematical Combining the input side with at least one mask with a defined bit pattern so that the Masking operation leads to an inversion of the data representation to be inverted.

15. The method according to claim 14, wherein the input side for the masking operations is divided into several frames with the same Frame size is divided into bits, where the size of the masks in bits is equal to or a multiple of the frame size, while different masks can have the same or different sizes.

16. The method according to claim 14 or 15, wherein: the masking operation is performed multiple times per input page with different masks; and among the several results thus obtained, one result as a transformed version of the Input page is selected that maximizes a degree of fulfillment among the multiple results that the respective size the over-fulfillment of the storage reliability optimization objective assigned to one or more of the Output page assigned target data pages through the various results.

17. The method according to claim 16, wherein, if several results have the same maximum degree of fulfillment, the result selected as the transformed version of the input page is the one that differs the least from the corresponding untransformed input side in terms of the number of bits that are used in the corresponding transformation were inverted.

18. The method according to claim 16 or 17, wherein the selection of the one result is performed using a greedy algorithm is performed.

19. Method according to one of the preceding claims, wherein the input data is stored in a cache memory other than the Multi-level flash memory and the restructuring of the input data with respect to the input data stored in the cache memory to obtain the output data.

20. Method according to one of the preceding claims, wherein the respective optimization objectives for the Storage reliability associated with the one or more target data pages, each as a function of a calibration parameter that provides a common reliability range of the optimization objectives for the Storage reliability defined.

21. Data processing device configured to carry out the method according to any one of the preceding claims to carry out.

22. Data processing device according to claim 21, comprising one or more processors and having access to a Program memory containing one or more programs which, when executed on one or more several processors cause the data processing device to carry out the method according to one of claims 1 to 20 to carry out.

23. Computer program or computer program product comprising instructions to operate the data processing device according to Claim 21 or 22 to carry out the method according to one of claims 1 to 20.