ERROR CORRECTION DEVICE AND STORAGE DEVICE WITH THE SAME

Abstract

A storage device comprises a memory core with a plurality of cell blocks grouped into a plurality of cell groups, each cell group comprising adjacent cell blocks arranged in a row direction and sharing sub-word drivers with adjacent cell groups; and an error correction circuit configured to correct an error of principal data in units of symbols during a read operation by calculating the principal data and an error correction code read from the memory core with a check matrix, each unit of symbols comprising data output by a cell group or data output by cell blocks arranged at both ends of two adjacent cell groups, based on a sub-word driver shared between the two adjacent cell groups.

Description

BACKGROUND 1st field Various embodiments of the present disclosure relate to a semiconductor design technology and, in particular, a storage device that performs an error correction operation. 2. Description of the state of the art In the early days of the semiconductor memory industry, a large number of initially good chips without defective memory cells were distributed onto a wafer within a memory chip that had undergone a semiconductor manufacturing process. However, as memory capacity gradually increases, it has become difficult to manufacture a memory chip without defective memory cells. Currently, it is unlikely that such a memory chip can be produced. To overcome this situation, a method for repairing defective memory cells in a memory chip with redundant memory cells is used. Another possibility is to use a method for error correction of data from memory cells using an error correction circuit embedded in a memory device and / or a memory controller. SUMMARY Embodiments of the present disclosure are directed to a storage device that is capable of extending an error correction capability according to a tendency of errors to occur. According to one embodiment of the present disclosure, a storage device comprises a storage core with a plurality of cell blocks grouped into a plurality of cell groups, each cell group comprising adjacent cell blocks arranged in a row direction and sharing sub-word line drivers with adjacent cell groups.these share; and an error correction circuit configured to correct an error of principal data in units of symbols during a read operation by calculating the principal data and an error correction code read from the memory kernel using a check matrix, wherein each unit of symbols comprises data output by a cell group, or data output by cell blocks arranged at both ends of two adjacent cell groups, based on a subword line driver shared by the two adjacent cell groups. According to one embodiment of the present disclosure, a storage device comprises a lower chip; and one or more upper chips stacked above the lower chip, each of the upper chips comprising: a memory core comprising a plurality of cell blocks grouped into a plurality of cell groups, each cell group comprising adjacent cell blocks arranged in a row direction; and an error correction circuit configured during a read operation to correct an error of principal data in units of symbols by calculating the principal data and an error correction code read from the memory core with a check matrix, each unit of symbols comprising data output by a cell group or data output by cell blocks arranged at both ends of two adjacent cell groups. According to one embodiment of the present disclosure, an error correction device comprises a syndrome comparison circuit configured to generate a plurality of subsyndromes by calculating a first syndrome specifying an error pattern and a check matrix, and to generate a plurality of syndrome comparison signals corresponding to each from a plurality of cell blocks by comparing the plurality of subsyndromes and a second syndrome specifying a location of a symbol containing an error;a fault location detector configured to generate, based on the plurality of syndrome comparison signals, a fault location signal indicating a fault location in units of symbols, wherein the unit of symbols comprises data output by a cell group from a plurality of cell groups in which adjacent cell blocks are grouped, or data output by cell blocks located at both ends of two adjacent cell groups; and a fault correction device configured to correct an error in a codeword output by the plurality of cell groups according to the fault location signal. According to one embodiment of the present disclosure, a storage device comprises a storage core; and an error correction circuit configured during a read operation to correct an error in principal data in units of symbols by calculating the principal data and an error correction code read from the storage core with a check matrix, wherein the check matrix comprises: data matrices corresponding to the principal data, each data matrix comprising an upper section in which two unit matrices are arranged in a first diagonal direction, and a lower section in which two identical Tk companion matrices are arranged in the first diagonal direction, wherein k values ​​of the Tk companion matrices are distinct positive integers that differ from each data matrix;and parity matrices corresponding to the error correction code, each parity matrix comprising an upper section in which two unit matrices are arranged in the first diagonal direction and a lower section in which two unit matrices or two zero matrices are arranged in the first diagonal direction. According to embodiments of the present disclosure, in a storage device that corrects an error in read data in units of symbols, the storage device can extend the error-correcting capability by correcting not only an error occurring in a single symbol, but also an error occurring at both ends of two adjacent symbols. According to embodiments of the present disclosure, the storage device can provide optimized reliability, accessibility, and serviceability (RAS) by increasing the error-correcting capability of the storage controller. These and other features and advantages of the embodiments of the present disclosure will be apparent to a person skilled in the art from the following detailed description in conjunction with the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a block diagram representing a storage device according to an embodiment of the present disclosure. Fig. 2 shows a detailed configuration diagram representing a storage core from Fig. 1 according to an embodiment of the present disclosure. Fig. 3 shows a diagram describing the occurrence of a fault due to a failure of a sub-line driver in the storage core of Fig. 2 according to an embodiment of the present disclosure. Figs. 4A and 4B show diagrams describing a symbol configuration according to an embodiment of the present disclosure. Figs. 5A to 6B show diagrams describing a configuration of a check matrix used by an ECC engine according to an embodiment of the present disclosure. Figs. 7A to 7C show diagrams describing a configuration of a check matrix according to an embodiment of the present disclosure.Figure 8 shows a block diagram representing a fault correction circuit according to an embodiment of the present disclosure. Figure 9 shows a diagram describing a first and a second syndrome generated in a syndrome generation circuit of Figure 8 according to an embodiment of the present disclosure. Figure 10 shows a detailed block diagram representing a first multiplier of Figure 8 according to an embodiment of the present disclosure. Figure 11 shows a detailed circuit diagram representing a syndrome comparator of Figure 8 according to an embodiment of the present disclosure. Figure 12 shows a detailed circuit diagram representing a fault location detector of Figure 8 according to an embodiment of the present disclosure. Figure 13 shows a detailed circuit diagram representing the fault detector of Figure 12 according to an embodiment of the present disclosure.Figure 14 shows a table describing a configuration of a test matrix according to an operation of a fault location detector of Figure 12 according to an embodiment of the present disclosure. Figures 15A and 15B show diagrams illustrating a fault correction operation according to an embodiment of the present disclosure. Figure 16 shows a block diagram illustrating a storage system with a storage module according to an embodiment of the present disclosure. Figure 17 shows a block diagram illustrating a storage system with a stacked storage device according to an embodiment of the present disclosure. Figure 18 shows a block diagram illustrating a mobile system with a storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION Various embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. However, the embodiments of the present disclosure can take various forms and should not be understood as being limited to those presented here. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete and fully conveys the scope of the present disclosure to a person skilled in the art. In this disclosure, identical reference numerals refer to identical parts in the various figures and embodiments of the present disclosure. It is understood that when an element is described as "coupled" or "connected" to another element, this may mean that the two are directly coupled or electrically connected, with another circuit or element interposed. It is further understood that the terms "have," "comprising," "have," etc., when used in this patent specification, indicate the presence of listed features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In this disclosure, singular forms are intended to include plural forms unless the context clearly indicates otherwise. Fig. 1 shows a block diagram representing a storage device 100 according to an embodiment of the present disclosure. Fig. 1 shows only parts of the storage device 100 that relate directly to data storage and data error correction. Referring to Fig. 1, the storage device 100 can comprise a storage core 110 and an error correction code (ECC) engine 150. The memory core 110 can refer to an area within the storage device 100 where data is stored and can comprise a memory cell array with a plurality of memory cells for storing data. The plurality of memory cells can be coupled between a plurality of word lines and a plurality of bit lines arranged in an array. The memory core 110 can further comprise a row control circuit coupled to the memory cell array via the plurality of word lines to perform row control of the memory cell array, and a column control circuit coupled to the memory cell array via the plurality of bit lines to perform column control of the memory cell array. During a write operation, memory core 110 can receive and store data (DATA) and an error correction code (ECC) from the ECC engine 150. During a read operation, memory core 110 can transfer stored data (DATA) and the stored error correction code (ECC) to the ECC engine 150. The data (DATA) can be referred to as user data. The error correction code (ECC) can be referred to as parity data. The ECC engine 150 can generate the error correction code ECC using the DATA' data input from an external device (e.g., a storage device) during a write operation and can provide the main DATA' and the error correction code ECC to the memory core 110. The ECC engine 150 can correct an error in the main DATA' data read from the memory core 110 using the error correction code ECC read from the memory core 110 during a read operation and output the error-corrected DATA to the memory controller. In one embodiment, the ECC engine 150 can have the capability to correct an error occurring in the main DATA' data in units of symbols. That is, the ECC engine 150 can correct an error in a symbol regardless of the number of error bits. A Reed-Solomon (RS) algorithm can be used for error correction in units of symbols.The ECC Engine 150 can perform an RS encoding operation, which generates an error correction code (ECC) using a parity check matrix (hereinafter referred to as the "check matrix"), and an RS decoding operation, which corrects an error using the error correction code (ECC). In one embodiment, a symbol can comprise data with a specific number of bits as a basic unit for RS encoding and RS decoding operations. For example, a symbol can comprise 8-bit or 16-bit data. The ECC engine 150 can include an ECC generation circuit 152 and an error correction circuit 154. The ECC generation circuit 152 can generate the error correction code ECC using the DATA data input by the memory controller during a write operation, i.e., during a coding operation of the ECC engine 150. The ECC generation circuit 152 can generate the error correction code ECC by calculating the DATA data using a check matrix. Since the error correction code ECC is generated and the error correction operation is not performed during the write operation, the DATA data input to the ECC generation circuit 152 can be the same as the main DATA data output by the ECC generation circuit 152 during the write operation. For reference, the check matrix, which will be described later, can be composed of H-matrices in units of symbols. The error correction circuit 154 can correct an error in the main data DATA' using the error correction code ECC read from the memory core 110 during a read operation, i.e., a decoding operation of the ECC engine 150. The error correction circuit 154 can calculate the error in the main data DATA' and the error correction code ECC read from the memory core 110 using a check matrix and correct the error in the main data DATA' in units of symbols. Correcting an error here can mean detecting the error in the main data DATA' and correcting the error when the error is detected. Depending on the embodiment, the ECC engine 150 can be located at any point along a path over which data is transferred during write and read operations. During a write operation, write data can be transferred from the memory controller to the memory core 100, and during a read operation, read data can be transferred from the memory core 100 to the memory controller. The ECC engine 150 can be located at any point along a path over which the write and read data are transferred. For example, the ECC engine 150 can be located within the memory controller or within the memory device 100. Alternatively, the ECC engine 150 can be located within a buffer chip that buffers data between the memory controller and the memory device 100. Fig. 2 shows a detailed configuration diagram in which the memory core 110 of Fig. 1 is depicted according to an embodiment of the present disclosure. With reference to Fig. 2, a memory cell arrangement of the memory core 110 is shown. The memory cell arrangement can comprise a plurality of memory cells MC, which are coupled between a plurality of word lines WL or a plurality of bit lines BL and arranged in an array. The plurality of word lines WL can extend in a first direction X1 (e.g., a row direction) and can be arranged consecutively perpendicular to the row direction in a second direction Y1 (e.g., a column direction). The plurality of bit lines BL can extend in the column direction Y1 and can be arranged consecutively in the row direction X1. The memory cell arrangement can be subdivided into a plurality of memory blocks (hereinafter referred to as "cell blocks"), each comprising a plurality of memory cells MC. For example, a plurality of cell blocks can comprise cell blocks MB0 to MB37, the first through thirty-eighth. Figure 2 shows only cell blocks MB0 to MB37 arranged in the row direction X1, but the cell blocks can be arranged in an array-type configuration in both the row direction X1 and the column direction Y1. In one embodiment, a cell block can be defined as a set of memory cells that share the word lines WL and the bit lines BL and are arranged in the same configuration. The multitude of cell blocks MB0 to MB37, arranged in the row direction X1, can be subdivided into a multitude of cell groups MG0 to MG18. A predetermined number (e.g., two) of adjacent cell blocks among the first to thirty-eighth cell blocks MB0 to MB37 can form a single cell group. For example, the first and second cell blocks MB0 and MB1 form a first cell group MG0, and the third and fourth cell blocks MB2 and MB3 form a second cell group MG1, and in this way, the thirty-seventh and thirty-eighth cell blocks MB36 and MB37 can form a nineteenth cell group MG18. A multitude of sub-word drivers (SWD) can be arranged between the cell groups MG0 to MG18, which are arranged in the row direction X1. Lines extending to the left and right of the sub-word drivers (SWD) can represent word lines (WL) (or sub-word lines). In reality, there are many more sub-word drivers and word lines, but only a subset is shown here to illustrate the basic structure. Each of the cell groups MG0 to MG18 can contain odd-numbered word lines (hereinafter referred to as "first word lines WLO") and even-numbered word lines (hereinafter referred to as "second word lines WLE") that extend in the row direction X1 and alternate in the column direction Y1. In odd-numbered cell groups, the first word lines WLO can share sub-word line drivers SWD with an adjacent cell group in the row direction X1, and the second word lines WLE can share sub-word line drivers SWD with an adjacent cell group in a direction X2 opposite to the row direction X1. Conversely, in even-numbered cell groups, the second word lines WLE can share sub-word line drivers SWD with an adjacent cell group in the row direction X1, and the first word lines WLO can share sub-word line drivers SWD with an adjacent cell group in the direction X2. As a reference, a plurality of bit line read amplifiers can be arranged between a plurality of cell blocks arranged in the column direction Y1. That is, two cell blocks adjacent to each other in the column direction Y1 can share the bit line read amplifiers. During a read or write operation, each cell block can input or output 8-bit data. During a read or write operation, a cell group can input or output 16-bit data, and 16-bit data output by a cell group can form a symbol. The ECC Engine 150 has the capability to correct an error occurring in a symbol. In the memory cell arrangement of Fig. 2, the first through seventeenth cell groups MG0 to MG16 of the plurality of cell groups MG0 to MG18 can store the main data 'DATA', and the eighteenth and nineteenth cell groups MG0 to MG16 can store the error correction code ECC. As a result, 17 symbols form the 272-bit main data 'DATA', and two symbols form the 32-bit error correction code 'ECC', and during a read or write operation a 304-bit codeword can be output containing the 272-bit main data 'DATA' and the 32-bit error correction code 'ECC'. Since two cell groups adjacent to each other in the row direction X1 share the sub-word drivers SWD, one sub-word driver SWD can be responsible for four cell blocks in the row direction X1. In this case, if a fault occurs in the shared sub-word driver SWD, there is a tendency for a multitude of faults to occur in cell blocks that are far from the sub-word driver SWD. For example, if a fault occurs in a sub-word driver shared by the first to fourth cell blocks MB0 to MB3, as shown in Fig. 3, the probability of a fault occurring in the first cell block MB0 and the fourth cell block MB3, which are located at opposite ends, is higher than the probability of a fault occurring in the second cell block MB1 and the third cell block MB2.In this case, if errors occur in the first cell block MB0 and in the fourth cell block MB3, an error correction operation exceeds the error correction capability of the ECC engine 150, which performs the error correction operation in units of symbols, and thus an uncorrectable error (UE) occurs. In one embodiment of the present disclosure, data output from a cell group can be implemented as a single symbol, or, based on a shared sub-line driver, data output from cell blocks located at both ends of two adjacent cell groups can be implemented as a single symbol. For example, as shown in Fig. 4A, a 16-bit data output from the second cell group MG1 can be implemented as a single symbol (①). Alternatively, as shown in Fig. 4B, data output from the first cell block MB0 and the fourth cell block MB3, located at both ends of two adjacent cell groups, can be implemented as a single symbol.h) The first cell group MG0 and the second cell group MG1 can be executed as a single symbol (②) based on the shared sub-word driver between them, or data output from the third cell block MB2 and the sixth cell block MB5, located at either end of two adjacent cell groups, i.e., the second cell group MG1 and the third cell group MG2, can be executed as a single symbol (③) based on the shared sub-word driver between them. The ECC Engine 150 can extend its error correction capability by performing an error correction operation in units of symbols (①) from Fig. 4A or symbols (② or ③) from Fig. 4B. A detailed configuration of the ECC engine 150 is described below according to one embodiment of the present disclosure. Before describing the configuration of the ECC engine 150, a test matrix used in one embodiment of the present disclosure is described. Figures 5A to 6B show diagrams describing a configuration of a test matrix used by an ECC engine according to an embodiment of the present disclosure. Referring to Fig. 5A, the check matrix can be a matrix of (number of bits of the error correction code) * (number of bits of data + number of bits of the error correction code). Since the error correction code (ECC) consists of 32 bits and the data of 272 bits, the check matrix can be a matrix of 32 * 304. Each component of the check matrix can have a value of 1 or 0. The check matrix can consist of the first through nineteenth H-matrices, H0 through H18, corresponding to each symbol. Each H-matrix can consist of a row corresponding to the bits (i.e., 32 bits) of the error correction code (ECC) and a column corresponding to the bits (i.e., 16 bits) of the corresponding symbol. Each H-matrix can include an upper matrix consisting of (symbol size)*(symbol size), i.e., a 16x16 square matrix, and a lower matrix of the same size as the upper matrix. Each upper matrix of the first through nineteenth H-matrices, H0 through H18, can consist of a 16x16 identity matrix. Each lower matrix of the first through seventeenth H-matrices, H0 through H16, corresponding to the data matrices (DATA), can consist of a companion matrix of 16x16, for example, T1, T2, T3, ..., T17.The lower matrix of the eighteenth H-matrix H17, which corresponds to the lower bits of the error correction code ECC, can consist of a zero matrix 0 of 16 * 16, and the lower matrix of the nineteenth H-matrix H18, which corresponds to the upper bits of the error correction code ECC, can consist of a unity matrix I of 16 * 16. As shown in Fig. 5B, in the identity matrix I of 16 * 16, components of i * i, where i is an integer from 1 to 16, can be set to a value of 1 in a diagonal direction XY1 among the 16 row components and 16 column components, and the remaining components can be set to a value of 0. As shown in Fig. 5C, in the zero matrix 0 of 16 * 16, all column components and row components can be set to a value of 0. Before the configuration of the H-matrix is ​​described, a Galois field, a primitive element, a primitive polynomial and a companion matrix are described. The Galois field: A Galois field (GF) refers to a field with a finite number of elements, and a Galois field with size X has a finite number of X elements from 0 to (X-1). For example, a Galois field with a finite number of 16 (=24) elements from 0 to 15 can be expressed as GF(16) or GF(24). The primitive element: All elements except 0 in the Galois field (GF) can be expressed as the square of an element α, and this element is called the primitive element. If a particular Galois field is expressed as GF(2n), then 2 can be used as the primitive element. For example, the elements of GF(23) are as follows: GF(23) = {0, α1, α2, α3, α4, α5, α6, α7 (=1=α0)}. The last element α7 of the Galois field is also expressed as 1 or α0. The primitive polynomial: When a Galois field is generated, a primitive polynomial is used to determine which of the quadratic forms of α corresponds to each element in the Galois field. Even for Galois fields of the same size, a corresponding form can vary depending on the primitive polynomial chosen. If GF(23) is generated using a primitive polynomial p(x) = x³ + x + 1 and α = 2, a result shown in Fig. 6A can be obtained. The following rules, such as (1) and (2), can be used to determine α. (1) Since αie is a value obtained by multiplying αi-1 with α (=2), αium is shifted by 1 bit. (2) If at position x3 of p(x) is generated due to the shift 1, an XOR operation is performed on the result of (1) and a term other than x3 to replace 1 with the term other than x3. Referring to Fig. 6A, α2 can be generated from α1 by applying rule (1). That is, α2 can be (0, 0, 1) by shifting 1 bit of (0, 1, 0) from α1. α3 can be generated from α2 by applying rules (1) and (2). First, rule (1) can be applied so that (0, 0, 1) is changed to (0, 0, 0), and then rule (2) can be applied, i.e., an XOR operation is performed on (0, 0, 0) and (1, 1, 0) to obtain (1, 1, 0). α4 can be generated from α3 by applying rule (1), i.e., it can be (0, 1, 1) by shifting it from (1, 1, 0). α5 can be generated as (0, 0, 1) from α4 by applying rule (1), and then rule (2) can be applied, i.e., an XOR operation is performed on (0, 0, 1) and (1, 1, 0) to obtain (1, 1, 1). α6 and α7 can also be generated by applying the same rules. The companion matrix: The companion matrix can refer to a matrix that contains column vectors of α1. For example, a companion matrix Tj with size y*y can be a matrix containing column vectors of αj, αj+1, αj+2, ..., αj+y-1. Similarly, a companion matrix T1 can be a matrix containing column vectors of α1, α2, α3, ..., αy. Referring to Fig. 6B, companion matrices of size 16*16 each are generated using elements of GF(α16) generated by a primitive polynomial p(x)=x16+x12+x3+x1+1 and α=2. The companion matrix T1 can comprise a plurality of column vectors of α1, α2, α3, ..., and α16. α1 can have a column vector of (0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), and α2 can have a column vector of (0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) shifted by α1 by 1 bit. α3 can have a column vector (0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) shifted by 1 bit from α2. α15 can have a column vector of (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1), and α16 can have a column vector of (1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0) generated by shifting α15 by 1 bit and using the primitive polynomial p(x) = x16 + x12 + x3 + x1 + 1. In one embodiment of the present disclosure, a test matrix modified from the test matrix described in Fig. 5A can be used to perform an error correction operation in units of symbols from Fig. 4A or symbols from Fig. 4B. Figures 7A to 7C show diagrams describing a configuration of a test matrix according to an embodiment of the present disclosure. Referring to Fig. 7A, the check matrix can be a matrix consisting of (number of bits of the error correction code) * (number of bits of the data + number of bits of the error correction code). The check matrix can consist of the first through nineteenth H-matrices, H0 through H18, corresponding to each symbol. Each H-matrix can consist of a row corresponding to the bits (i.e., 32 bits) of the error correction code ECC and a column corresponding to the bits (i.e., 16 bits) of the corresponding symbol. In the following, among the first to nineteenth H matrices H0 to H18, the first to seventeenth H matrices H0 to H16, which correspond to the first to seventeenth cell groups MG0 to MG16 that store the data DATA, are referred to as data matrices, and the eighteenth and nineteenth matrices H17 and H18, which correspond to the eighteenth and nineteenth cell groups MG17 and MG18 that store the error correction code ECC, are referred to as parity matrices. Each of the data matrices H0 to H16 can comprise an upper section in which two unit matrices I are arranged in a diagonal direction XY1, and a lower section in which two identical companion matrices Tk, where k is an integer greater than or equal to 1, are arranged in the diagonal direction XY1. The diagonal direction XY1 can be a direction in which a row direction X1 and a column direction Y1 intersect. Each of the parity matrices H17 and H18 can comprise an upper section in which two unit matrices I are arranged in the diagonal direction XY1, and a lower section in which either two unit matrices I are arranged in the diagonal direction XY1 or two zero matrices 0 are arranged in the diagonal direction XY1.For example, the parity matrix H17 can include an upper section in which two unit matrices I are arranged in the diagonal direction XY1, and a lower section in which two zero matrices 0 are arranged in the diagonal direction XY1, and the parity matrix H18 can include an upper section and a lower section in which two unit matrices I are arranged in the diagonal direction XY1. Each H-matrix can be subdivided into two submatrices. The first to nineteenth H-matrix, H0 to H18, can each correspond to the first to nineteenth cell groups, MG0 to MG18, and the first to thirty-eighth submatrix, H0_L to H18_H, can each correspond to the first to thirty-eighth cell blocks, MB0 to MB37. Each submatrix can comprise an upper section consisting of two square matrices of (symbol size / 2)*(symbol size / 2), i.e., 8*8, and a lower section consisting of two square matrices of the same size. That is, two unit matrices I can be arranged diagonally XY1 on an upper section of two submatrices encompassed in a data matrix, and two identical companion matrices Tk can be arranged diagonally XY1 on a lower section of two submatrices encompassed in a data matrix.Furthermore, two unit matrices I can be arranged in the diagonal direction XY1 on an upper section of two submatrices encompassed in a parity matrix, and two unit matrices I or two zero matrices 0 can be arranged in the diagonal direction XY1 on a lower section of two submatrices encompassed in a parity matrix. Each of the identity matrix I, the zero matrix 0 and the companion matrix Tk can consist of a square matrix with a size of 8 * 8. As shown in Fig. 7B, in the identity matrix I of 8 * 8 components of j * j, where j is an integer from 1 to 8, in the diagonal direction XY1, 8 row components and 8 column components can be set to a value of 1, and the remaining components can be set to a value of 0. In the zero matrix 0, all column components and row components can be set to a value of 0. Each of the companion matrices Tk can be formed by a matrix comprising a plurality of column vectors from αk to αk+m-1, where m is the number of bits of data output by a cell block. The companion matrix of 8*8 can be generated using elements of GF(28) generated by a primitive polynomial p(x) = x8 + x7 + x6 + x1 + 1, α = 2. For example, as shown in Fig. 7C, the companion matrix T1 can comprise a plurality of column vectors of α1, α2, α3, ..., and α8. α1 can have a column vector of (0, 1, 0, 0, 0, 0, 0, 0), and α2 can have a column vector of (0, 0, 1, 0, 0, 0, 0, 0) shifted by 1 bit from α1. α3 can also have a column vector of (0, 0, 0, 1, 0, 0, 0, 0, 0) shifted by 1 bit from α2.α7 can have a column vector of (0, 0, 0, 0, 0, 0, 0, 1), and α8 can have a column vector of (1, 1, 0, 0, 0, 0, 1, 1) generated by shifting α7 by 1 bit and using the primitive polynomial p(x) = x8 + x7 + x6 + x1 + 1. The k values ​​of the companion matrices Tk can be set to be positive integers that are different from each data matrix. Although the k values ​​of the companion matrices Tk increment by 1 in Fig. 7A, the embodiments are not limited to this, and the k values ​​of the companion matrices can be set to different values. Preferably, the k values ​​of the companion matrices can be set to different values ​​that do not overlap. In one embodiment, the ECC generation circuit 152 can generate an error correction code ECC<0:31> by calculating data DATA<0:271> and a check matrix described in Fig. 7A during a write operation. The ECC generation circuit 152 can generate upper bits ECC<16:31> of the error correction code ECC<0:31> by performing a matrix multiplication on a matrix of a vector expression of the data DATA<0:271> and a matrix of 272 * 16, which is the lower section of the data matrices H0 to H16. Furthermore, the ECC generation circuit 152 can generate a 16-bit code by performing a matrix multiplication on the matrix of the vector expression of the data DATA<0:271> and a matrix of 272 *16, which is the upper section of the data matrices H0 to H16, and generate lower bits ECC<0:15> of the error correction code ECC<0:31> by performing a logical XOR operation on the 16-bit code and the upper bits ECC<16:31> of the error correction code ECC<0:31>.As a result, the data DATA<0:271> can be stored in the first to seventeenth cell groups MG0 to MG16, the lower bits ECC<0:15> of the error correction code ECC<0:31> can be stored in the eighteenth cell group MG17, and the two upper bits ECC<16:31> of the error correction code ECC<0:31> can be stored in the nineteenth cell group MG18. Fig. 8 shows a block diagram representing the error correction circuit 154 according to an embodiment of the present disclosure. Fig. 9 shows a diagram describing a first syndrome SDR_1<0:15> and a second syndrome SDR_2<0:15>, which are generated in a syndrome generation circuit 210 of Fig. 8 according to an embodiment of the present disclosure. Fig. 10 shows a detailed block diagram representing a first multiplier 232_0 of Fig. 8 according to an embodiment of the present disclosure. Fig. 11 shows a detailed circuit diagram representing a syndrome comparator 234 of Fig. 8 according to an embodiment of the present disclosure. Referring to Fig. 8, the error correction circuit 154 can comprise a syndrome generation circuit 210, a syndrome comparison circuit 230, a fault location detector 250 and an error correction device 260. The syndrome generation circuit 210 can generate a first syndrome SDR_1<0:15> and a second syndrome SDR_2<0:15> by calculating a check matrix with the main data DATA'<0:271> and the error correction code ECC<0:31>, which are output by the memory core 110. Specifically, the syndrome generation circuit 210 can comprise a parity calculator 212 and a syndrome generator 214. The parity calculator 212 can generate a preliminary 32-bit error correction code PRE_ECC<0:31> by calculating a check matrix using the 272-bit main data DATA'<0:271> output by the first to seventeenth cell groups MG0 to MG16 of memory core 110. The parity calculator 212 can use the data matrices H0 to H16 described in Fig. 7A. That is, the parity calculator 212 can generate the preliminary 32-bit error correction code PRE_ECC<0:31> by performing a matrix multiplication on a matrix of a vector expression of the main data DATA'<0:271> and the data matrix H0 to H16 of 272 * 32. The syndrome generator 214 can generate the first syndrome SDR_1<0:15> and the second syndrome SDR_2<0:15> by comparing the 32-bit error correction code ECC<0:31>, output by the eighteenth and nineteenth cell groups MG17 and MG18, with the preliminary 32-bit error correction code PRE_ECC<0:31>, generated by the parity computer 212. The syndrome generator 214 can generate the first 16-bit syndrome SDR_1<0:15> by performing a logical XOR operation on the lower 16 bits ECC<0:15> of the error correction code ECC<0:31> and the lower 16 bits PRE_ECC<0:15> of the preliminary error correction code PRE_ECC<0:31>, respectively. The syndrome generator 214 can generate the second 16-bit syndrome SDR_2<0:15> by performing a logical XOR operation on the upper 16 bits ECC<16:31> of the error correction code ECC<0:31> or the upper 16 bits PRE_ECC<16:31> of the preliminary error correction code PRE_ECC<0:31>.The first syndrome, SDR_1<0:15>, can be used to specify an error pattern within a symbol, and the second syndrome, SDR_2<0:15>, can be used to specify the position or location of a symbol containing an error. For example, with reference to Fig. 9, the first syndrome, SDR_1<0:15>, of "01010101 11111111" can mean an error pattern with two error bits in a symbol, and the second syndrome, SDR_2<0:15>, of "10101010 11111110" can indicate that a symbol containing an error is output by the first cell group, MG1. The syndrome comparison circuit 230 can calculate the first syndrome SDR_1<0:15> and a test matrix to generate the first to nineteenth subsyndromes SS0<0:15> to SS18<0:15>, corresponding to the respective first to nineteenth cell groups MG0 to MG18. The syndrome comparison circuit 230 can compare the first to nineteenth subsyndromes SS0<0:15> to SS18<0:15> or the second syndrome SDR_2<0:15> to generate the first to thirty-eighth syndrome comparison signals T0_L, T0_H, T1_L, T1_H, ... T18_L and T18_H. Since in this case each H-matrix of the test matrix is ​​divided into two submatrices, the syndrome comparison circuit 230 can be set up to generate the first to thirty-eighth syndrome comparison signals T0_L to 18_H, each corresponding to the first to thirty-eighth cell blocks MB0 to MB37. Specifically, the syndrome comparison circuit 230 can include a syndrome multiplier 232 and a syndrome comparator 234. The syndrome multiplier 232 can generate the first to nineteenth subsyndromes SS0<0:15> to SS18<0:15> by performing a matrix multiplication on the first syndrome SDR_1<0:15> and a lower section of the check matrix. In this case, as described in Fig. 7A, two identical companion matrices Tkin of the diagonal direction XY1 can be arranged on the lower section of the data matrices H0 to H16, and two unit matrices I or two zero matrices 0 in the diagonal direction XY1 can be arranged on the lower section of the parity matrices H17 and H18. The syndrome multiplier 232 can comprise the first to nineteenth multipliers 232_0 to 232_18, corresponding to the first to nineteenth H-matrices H0 to H18, each of which generates a corresponding subsyndrome by performing matrix multiplication on the first syndrome SDR_1<0:15> and a lower section of a corresponding H-matrix. The first to nineteenth subsyndromes SS0<0:15> to SS18<0:15> can be subdivided into a lower subsyndrome SS#<0:7>, where # is an integer from 0 to 18, and an upper subsyndrome SS#<8:15>. The first to seventeenth syndrome multipliers 232_0 to 232_16 can generate first to seventeenth lower subsyndromes SS0<0:7> to SS16<0:7> by performing a matrix multiplication on the lower 8 bits SDR_1<0:7> of the first syndrome SDR_1<0:15> and an accompanying matrix Tk of 8*8, and generate first to seventeenth upper subsyndromes SS0<8:15> to SS16<8:15> by performing a matrix multiplication on the upper 8 bits SDR_1<8:15> of the first syndrome SDR_1<0:15> and an accompanying matrix Tk of 8*8. For example, with reference to Fig. 10, the first multiplier 232_0 can generate the first lower subsyndrome SS0<0:7> by performing a matrix multiplication on the lower 8 bits SDR_1<0:7> and the companion matrix T1 of 8*8, and can generate the first upper subsyndrome SS0<8:15> by performing a matrix multiplication on the upper 8 bits SDR_1<8:15> and the companion matrix T1 of 8*8.The first to seventeenth multipliers 232_0 to 232_16 can be called data multipliers. The eighteenth multiplier 232_17 can generate the eighteenth lower subsyndrome SS17<0:7> by performing a matrix multiplication on the lower 8 bits SDR_1<0:7> of the first syndrome SDR_1<0:15> and a zero matrix 0 of 8*8, and can generate the eighteenth upper subsyndrome SS17<8:15> by performing a matrix multiplication on the upper 8 bits SDR_1<8:15> of the first syndrome SDR_1<0:15> and a zero matrix 0 of 8*8. As a result, the eighteenth subsyndrome SS17<0:15> can consist entirely of zero bits. Furthermore, the nineteenth multiplier 232_18 can generate the nineteenth lower subsyndrome SS18<0:7> by performing a matrix multiplication on the lower 8 bits SDR_1<0:7> of the first syndrome SDR_1<0:15> and an identity matrix I of 8*8, and can generate the nineteenth upper subsyndrome SS18<8:15> by performing a matrix multiplication on the upper 8 bits SDR_1<8:15> of the first syndrome SDR_1<0:15> and an identity matrix I of 8*8.Consequently, the nineteenth subsyndrome SS18<0:15> can consist of the same bits as the first syndrome SDR_1<0:15>. The eighteenth multiplier 232_17 and the nineteenth multiplier 232_18 can be called parity multipliers. The syndrome comparator 234 can generate the first to thirty-eighth syndrome comparison signals T0_L to T18_H by comparing the lower subsyndrome SS#<0:7> and the upper subsyndrome SS#<8:15>, which are included in the first to nineteenth subsyndromes SS0<0:15> to SS18<0:15>, with the lower 8 bits SDR_2<0:7> and the upper 8 bits SDR_2<8:15>, respectively, of the second syndrome SDR_2<8:15>. Referring to Fig. 11, the syndrome comparator 234 can comprise a first to thirty-eighth comparator 234_0A to 234_18B. Each comparator can output a corresponding syndrome comparison signal by bitwise comparing a corresponding lower subsyndrome SS#<0:7> and the lower 8 bits SDR_2<0:7> of the second syndrome SDR_2<0:15>, or by bitwise comparing a corresponding upper subsyndrome SS#<8:15> and the upper 8 bits SDR_2<8:15> of the second syndrome SDR_2<0:15>. For example, the first comparator 234_0A can compare the first lower subsyndrome SS0<0:7> and the lower 8 bits SDR_2<0:7> of the second syndrome SDR_2<0:15> to output the first syndrome comparison signal T0_L. The first comparator 234_0A can output the first syndrome comparison signal T0_L at a logic high level if the first lower subsyndrome SS0<0:7> is identical to the lower 8 bits SDR_2<0:7>.On the other hand, the first comparator 234_0A can output the first syndrome comparison signal T0_L at a logic low level if one bit of the first lower subsyndrome SS0<0:7> differs from the lower 8 bits SDR_2<0:7>. Each of the comparators 234_0A to 234_18B can be implemented using logic XOR and NOR gates. With the above configuration, if a correctable error is included in a symbol where an error has occurred, and the subsyndromes corresponding to the symbol are identical to the second syndrome SDR_2<0:15>, the syndrome comparison circuit 230 can output a corresponding syndrome comparison signal at a logic high level. Conversely, since the subsyndromes corresponding to symbols where no error has occurred are not identical to the second syndrome SDR_2<0:15>, the syndrome comparison circuit 230 can output a corresponding syndrome comparison signal at a logic low level. Furthermore, if an uncorrectable error exceeding the error correction capability of the error correction circuit 154 is included, and the subsyndromes of all symbols are not identical to the second syndrome SDR_2<0:15>, then the syndrome comparison circuit 230 can output all syndrome comparison signals at a logic low level. The fault location detector 250 can generate a fault location signal ERR_L<0:271> based on the first to thirty-eighth syndrome comparison signals T0_L to T18_H. Based on these signals, the fault location detector 250 can determine a fault location in units of symbols and generate the fault location signal ERR_L<0:271> by reflecting or mapping the determined fault location onto the first syndrome SDR_1<0:15>. The fault location signal ERR_L<0:271> comprises bits corresponding to the bits of the main data DATA'<0:271>, and one bit corresponding to a fault bit among the bits of the main data DATA'<0:271> can be set to a high bit. In one embodiment, a symbol unit can comprise data (①) output by a cell group, as shown in Fig.4A described, or data (② or ③) output by cell blocks arranged at both ends of two adjacent cell groups, based on a sub-line driver shared between them, as described in Fig. 4B. The error correction device 260 can generate error-corrected data DATA<0:271> by correcting an error in the main data DATA'<0:271> according to the error location signal ERR_L<0:271>. The error correction device 260 can perform an error correction operation by inverting an error bit of the main data DATA'<0:271> according to a high bit among the bits of the error location signal ERR_L<0:271>. For example, the error correction device 260 can include logic gates to perform a logical XOR operation on each bit of the error location signal ERR_L<0:271> and the main data DATA'<0:271>. Fig. 12 shows a detailed circuit diagram representing the fault location detector 250 of Fig. 8 according to an embodiment of the present disclosure. Fig. 13 shows a detailed circuit diagram representing a fault location detector 340_0 of Fig. 12 according to an embodiment of the present disclosure. Referring to Fig. 12, the fault location detector 250 can comprise a symbol adding device 300 and a plurality of fault detectors 340_0 to 340_16. The symbol adder 300 can generate the first to seventeenth operating signals HS0 to HS16 based on syndrome comparison signals corresponding to cell blocks contained within a cell group, under the syndrome comparison signals T0_L to T18_H, and generate the first to sixteenth adjacent operating signals HS0' to HS15' based on syndrome comparison signals corresponding to cell blocks located at both ends of two adjacent cell groups. The symbol adder 300 can generate the first to thirty-fourth preliminary detection signals H0_L to H16_H by adding the first to seventeenth operating signals HS0 to HS16 and the first to sixteenth adjacent operating signals HS0' to HS15'. Specifically, the symbol adder 300 can comprise a plurality of first logical AND gates 310_0 to 310_16, a plurality of second logical AND gates 320_01 to 320_1516, and a plurality of logical OR gates 330_0A to 330_16B. The plurality of first logical AND gates 310_0 to 310_16 and the plurality of error detectors 340_0 to 340_16 can be provided in as many quantities (i.e., 17) as there are in the plurality of cell groups for storing data, and the plurality of second logical AND gates 320_01 to 320_1516 can be provided in as many quantities (i.e., 16) as there are in the plurality of cell groups for storing data. The array of first AND gates 310_0 to 310_16 can output the first to seventeenth operation signals HS0 to HS16 by performing a logical AND operation on syndrome comparison signals corresponding to two cell blocks included in each cell group. For example, the first logical AND gate 310_0 can output the first operation signal HS0 by performing a logical AND operation on the first and second syndrome comparison signals T0_L and T0_H, corresponding to the first cell group MG0. The first logical AND gate 310_1 can output the second operation signal HS1 by performing a logical AND operation on the third and fourth syndrome comparison signals T1_L and T1_H, corresponding to the second cell group MG1.In this way, the first logical AND gate 310_16 can output the seventeenth operation signal HS16 by performing a logical AND operation on the thirty-third and thirty-fourth syndrome comparison signals T16_L and T16_H, which correspond to the seventeenth cell group MG16. The multitude of second logic AND gates 320_01 to 320_1516 can output the first to sixteenth adjacent operation signals HS0' to HS15' by performing a logical AND operation on syndrome comparison signals corresponding to two cell blocks located at opposite ends of two adjacent cell groups, based on the shared sub-word line driver. For example, the second logic AND gate 320_01 can output the second adjacent operation signal HS0' by performing a logical AND operation on the first and fourth syndrome comparison signals T0_L and T1_H, corresponding to cell blocks MB0 and MB3 located at opposite ends of the first and second cell groups MG0 and MG1, respectively, based on the shared sub-word line driver.The second logic AND gate 320_12 can output the second adjacent operation signal HS1' by performing a logic AND operation on the third and sixth syndrome comparison signals T1_L and T2_H, corresponding to cell blocks MB2 and MB5, located at the ends of the second and third cell groups MG1 and MG2, respectively, based on the shared sub-word line driver. Similarly, the second logic AND gate 320_1516 can output the sixteenth adjacent operation signal HS15' by performing a logic AND operation on the thirty-first and thirty-fourth syndrome comparison signals T15_L and T16_H, corresponding to cell blocks MB30 and MB33, located at the ends of the sixteenth and seventeenth cell groups MG15 and MG16, respectively, based on the shared sub-word line driver. The array of logic OR gates 330_0A to 330_16B can generate the first to thirty-fourth preliminary detection signals H0_L to H16_H by performing a logic OR operation on corresponding signals among the first to seventeenth operational signals HS0 to HS16 or the first to sixteenth adjacent operational signals HS0' to HS15'. For example, logic OR gate 330_0A can generate the first preliminary detection signal H0_L by performing a logic OR operation on the first operational signal HS0 and the first adjacent operational signal HS0'. The first operational signal HS0 can be output as the second preliminary detection signal H0_H.The logical OR gate 330_1A can generate the third preliminary detection signal H1_L by performing a logical OR operation on the second operating signal HS1 and the second adjacent operating signal HS1', and the logical OR gate 330_1B can generate the fourth preliminary detection signal H1_H by performing a logical OR operation on the second operating signal HS1 and the first adjacent operating signal HS0'. Similarly, the logical OR gate 330_16B can generate the thirty-fourth preliminary detection signal H16_H by performing a logical OR operation on the seventeenth operating signal HS16 and the sixteenth adjacent operating signal HS15'. The seventeenth operating signal HS16 can be output as the thirty-third preliminary detection signal H16_L. The plurality of fault detectors 340_0 to 340_16 can generate the fault location signal ERR_L<0:271> by reflecting or mapping the first syndrome SDR_1<0:15> onto the first to thirty-fourth preliminary detection signals H0_L to H16_H. The plurality of fault detectors 340_0 to 340_16 can perform a logical AND operation on the first to thirty-fourth preliminary detection signals H0_L to H16_H and one of the lower bits SDR_1<0:7> and one of the upper bits SDR_1<8:15> of the first syndrome SDR_1<0:15>. For example, with reference to Fig. 13, the fault detector 340_0 can perform a logical AND operation on the first preliminary detection signal H0_L and the lower 8 bits SDR_1<0:7> to output the bits ERR_L<0:7> of the fault location signal ERR_L<0:271>, and can perform a logical AND operation on the second preliminary detection signal H0_H and the upper 8 bits SDR_1<8:15> to output the bits ERR_L<8:15> of the fault location signal ERR_L<0:271>.With the configuration described above, the fault detectors 340_0 to 340_16 can generate the fault location signal ERR_L<0:271> by mapping fault pattern information contained in the first syndrome SDR_1<0:15> to the first to thirty-fourth preliminary detection signals H0_L to H16_H. Figure 12 illustrates a case where the fault location detector 250 generates only the fault location signal ERR_L<0:271> to correct a fault in the main data DATA'<0:271>, but the fault location detector 250 can also generate a fault location signal to correct a fault in the fault correction code ECC<0:31>. For example, the fault location detector 250 can determine a fault location in units of symbols based on the thirty-fifth to thirty-eighth syndrome comparison signals T17_L, T17_H, T18_L, and T18_H among the first to thirty-eighth syndrome comparison signals T0_L to T18_H and generate a fault location signal to correct a fault in the fault correction code ECC<0:31> by mapping the determined fault location to the first syndrome SDR_1<0:15>. Fig. 14 shows a table describing a configuration of a test matrix according to an operation of the fault location detector 250 of Fig. 12 according to an embodiment of the present disclosure. Referring to Fig. 14, a test matrix MAT1 shown in the upper part can comprise the first to nineteenth H-matrices H0 to H18. The first to seventeenth H-matrices H0 to H16 can correspond to the first to seventeenth operational signals HS0 to HS16, which are generated by performing a logical AND operation on syndrome comparison signals corresponding to two cell blocks, each contained within a cell group. A test matrix MAT2, shown in a lower part, can comprise the first to eighteenth H-matrices H0' to H17'. The first to eighteenth H-matrices H0' to H17' can correspond to the first to sixteenth adjacent operation signals HS0' to HS15', which are generated by a logical AND operation on syndrome comparison signals corresponding to two cell blocks located at opposite ends of two adjacent cell groups, based on a shared sub-line driver. The fault location detector 250 can generate the first to thirty-fourth preliminary detection signals H0_L to H16_H by performing a logical OR operation on the first to seventeenth operational signals HS0 to HS16 and the first to sixteenth adjacent operational signals HS0' to HS15'. Consequently, the first to thirty-fourth preliminary detection signals H0_L to H16_H can be output as a result of determining the fault location in units of symbols according to one embodiment of the present disclosure. As described above, in one embodiment of the present disclosure, a storage device that corrects an error in read data in units of symbols can correct not only an error occurring in a single symbol, but also an error occurring at both ends of two adjacent symbols shared by a sub-word line driver. Therefore, it is possible to extend the error correction capability of the storage device. Fig. 15A and Fig. 15B show diagrams illustrating an error correction operation according to an embodiment of the present disclosure. Referring to Fig. 15A, a case is shown in which an error has occurred in two cell blocks MB0 and MB1, which are included in the first cell group MG0. The syndrome generation circuit 210 can generate the first syndrome SDR_1<0:15>, which indicates an error pattern within a symbol, and the second syndrome SDR_2<0:15>, which indicates a location of a symbol containing an error. The syndrome comparison circuit 230 can output the first syndrome comparison signal T0_L and the second syndrome comparison signal T0_H at a logic high level, since the first subsyndrome SS0<0:15>, which corresponds to a symbol output by the first cell group MG0, is the same as the second syndrome SDR_2<0:15>. On the other hand, the syndrome comparison circuit 230 can output the remaining syndrome comparison signals T1_L to T18_H at a logic low level, since the remaining subsyndromes SS1<0:15> to SS18<0:15> differ from the second syndrome SDR_2<0:15>. The symbol adder 300 can generate the first operational signal HS0 based on the first syndrome comparison signal T0_L and the second syndrome comparison signal T0_H at a logic high level, in order to generate the first preliminary detection signal H0_L and the second preliminary detection signal H0_H at a logic high level. The fault detector 340_0 can output the first syndrome SDR_1<0:15> as corresponding bits ERR_L<0:15> of the fault location signal ERR_L<0:271> according to the first preliminary detection signal H0_L and the second preliminary detection signal H0_H at a logic high level. In this case, the remaining bits ERR_L<16:271> are output at a logic low level. The error correction device 260 can generate the error-corrected data DATA<0:271> by performing a logical XOR operation on each bit of the fault location signal ERR_L<0:271> and the main data DATA'<0:271>. That is, the error correction device 260 can perform an error correction operation by inverting corresponding bits of the main data DATA'<0:271> according to the corresponding bits ERR_L<0:15> of the fault location signal ERR_L<0:271>. As described above, the error correction circuit 154 can correct the error of the main data DATA'<0:271> by setting up a data output from a group of cells (see Fig. 4A) in a symbol unit. If an error occurs only in the first cell block MB0, which is contained in the first cell group MG0, the upper 8 bits SDR_1<8:15> of the first syndrome SDR_1<0:15> and the upper 8 bits SDR_2<8:15> of the second syndrome SDR_2<0:15>, corresponding to the second cell block MB1 where no error occurred, can all contain zero values. Therefore, only the error in the data DATA'<0:7> output by the first cell block MB0 can be corrected. Referring to Fig. 15B, a case is described in which an error occurred in the first cell block MB0, which is included in the first cell group MG0, or in the fourth cell block MB3, which is included in the second cell group MG1. The syndrome generation circuit 210 can generate a first syndrome SDR_1<0:15>, which indicates an error pattern within a symbol, and the second syndrome SDR_2<0:15>, which indicates a location of a symbol containing an error. The syndrome comparison circuit 230 can output the first syndrome comparison signal T0_L at a logic high level because the first lower subsyndrome SS0<0:7>, corresponding to a symbol output by the first cell block MB0, is identical to the second syndrome SDR_2<0:15>. The syndrome comparison circuit 230 can output the fourth syndrome comparison signal T1_H at a logic high level because the second upper subsyndrome SS1<8:15>, corresponding to a symbol output by the fourth cell block MB3, is identical to the second syndrome SDR_2<0:15>. Conversely, the syndrome comparison circuit 230 can output the remaining syndrome comparison signals T0_H, T1_L, and T2_L through T18_H at a logic low level because the remaining subsyndromes differ from the second syndrome SDR_2<0:15>. The symbol adder 300 can generate the first adjacent operational signal HS0' based on the first syndrome comparison signal T0_L and the fourth syndrome comparison signal T1_H at a logic high level, in order to generate the first preliminary detection signal H0_L and the fourth preliminary detection signal H1_H at a logic high level. The fault detector 340_0 can output the lower 8 bits SDR_1<0:7> of the first syndrome SDR_1<0:15> as corresponding bits ERR_L<0:7> of the fault location signal ERR_L<0:271> according to the first preliminary detection signal H0_L at a logic high level. The fault detector 340_1 can output the upper 8 bits SDR_1<8:15> of the first syndrome SDR_1<0:15> as the corresponding bits ERR_L<24:31> of the fault location signal ERR_L<0:271> according to the fourth preliminary detection signal H1_H at a logic high level. In this case, the remaining bits ERR_L<8:23, 32:271> are output at a logic low level. The error correction device 260 can generate the error-corrected data DATA<0:271> by performing a logical XOR operation on each bit of the error location signal ERR_L<0:271> and the main data DATA'<0:271>. That is, the error correction device 260 can perform an error correction operation by inverting corresponding bits of the main data DATA'<0:271> according to the corresponding bits ERR_L<0:7, 24:35> of the error location signal ERR_L<0:271>. As described above, the error correction circuit 154 can correct the error of the main data DATA'<0:271> by setting up data cell blocks arranged at both ends of two adjacent cell groups in a symbol unit based on a shared subword line driver (see Fig. 4B). Fig. 16 shows a block diagram representing a storage system 1000 comprising a storage module 1100 according to an embodiment of the present disclosure. Referring to Fig. 16, the storage system 1000 can comprise the storage module 1100 and a storage controller 1200. The memory controller 1200 can control operations of the memory system 1000 and control data transfer between a host 1300 and the memory module 1100. The memory controller 1200 can generate a command / address signal (C / A) according to a request (REQ) from the host 1300 to provide the command / address signal (C / A) to the memory module 1100, and provide data (DIO) corresponding to the request (REQ) from the host 1300 to the memory module 1100, and provide data read from the memory module 1100 (DIO) to the host 1300. The memory controller 1200 can include an error correction code (ECC) engine 1210. The ECC engine 1210 can detect and correct errors in the data DIO read from the storage device 100 and provide error-corrected data to the host 1300. If the number of error bits in the data DIO exceeds the error correction capability of the ECC engine 1210, the memory controller 1200 can notify the host 1300 that an uncorrectable error (UE) has occurred. The memory module 1100 can include a variety of memory devices (MD) 1101 to 1114 and a module controller (RCD) 1120. The module controller 1120 can include a known register clock driver. The module controller 1120 can control the memory devices 1101 to 1114 under the control of the memory controller 1200. For example, the module controller 1120 can receive the command / address signal C / A from the memory controller 1200 and control the data DIO to be written to or read from the memory devices 1101 to 1114. Each of the storage devices 1101 to 1114 can correspond to the storage device 100 described in Fig. 1. That is, each of the storage devices 1101 to 1114 can comprise a storage core and an ECC engine. The ECC engine can correct not only an error occurring in one symbol, but also an error occurring at both ends of two adjacent symbols. Therefore, it is possible to extend the error correction capability of the storage device. Depending on the embodiment, some (e.g., 1101 to 1112) of each of the storage devices 1101 to 1114 can store main data 'DATA', and the remaining devices (e.g., 1113 and 1114) can store an error correction code (ECC). In this case, the ECC engine 1210 of the memory controller 1200 can correspond to the ECC engine 150 of Fig. 1. That is, the ECC engine 1210 can correct not only an error occurring in one symbol, but also an error occurring at both ends of two adjacent symbols. Depending on the embodiment, the module controller 1120 can include an ECC engine corresponding to the ECC engine 150 of Fig. 1. Fig. 17 shows a block diagram representing a storage system 2000 with a stacked storage device 2300 according to an embodiment of the present disclosure. Referring to Fig. 17, the storage system 2000 can comprise a package substrate 2100, an intermediate element 2200, stacked storage devices 2300 and a processor 2400. The Package Substrate 2100 can comprise a printed circuit board (PCB). The Package Substrate 2100 can be electrically connected to an external system board, mainboard, or module board via bumps. The intermediate element 2200 can be formed on the package substrate 2100. The intermediate element 2200 can be a silicon substrate in which only a wiring configuration is formed. The one or more stacked storage devices 2300 and the processor 2400 can be formed on the intermediate element 2200. The stacked storage devices 2300 and the processor 2400 can be spaced apart from each other on the intermediate element 2200. Although four stacked storage devices 2300 are shown in Fig. 17, the embodiments of the present disclosure are not limited thereto, and one or more stacked storage devices can be formed on the intermediate element 2200. The 2400 processor can include a memory controller and a physical interface circuit. The memory controller can be configured to control the 2300 stacked memory devices. The physical interface circuit can provide an interface between the memory controller and the 2300 stacked memory devices. The physical interface circuit can be an interface circuit that converts signals transmitted by the memory controller into signals suitable for use in the 2300 stacked memory devices, and outputs signals transmitted by the 2300 stacked memory devices into signals suitable for use in the memory controller.The 2400 processor can be one of several different processes, such as a micro-processing unit (MPU), a central processing unit (CPU), a general processing unit (GPU), and a host processing unit (HPU). Each of the stacked memory devices 2300 can comprise a lower chip 2310 and one or more upper chips 2320, stacked vertically on the intermediate element 2200. An example of the stacked memory devices 2300 formed by stacking a large number of chips as described above is a high-bandwidth memory (HBM). Through-electrodes (TSVs) are formed between the lower chip 2310 and the upper chips 2320, through which signals (i.e., instructions, addresses, and data) can be transmitted between the chips. The lower chip 2310 can include a physical interface circuit for an interface with the memory controller. Each of the upper chips 2320 can correspond to the memory device 100 described in Fig. 1. That is, each of the upper chips 2320 can include a memory core and an ECC engine. The ECC engine can correct not only an error occurring in one symbol, but also an error occurring at both ends of two adjacent symbols. Therefore, it is possible to extend the error correction capability of the memory device. Depending on the embodiment, the lower chip 2310 can include an ECC engine corresponding to the ECC engine 150 of Fig. 1. Fig. 18 shows a block diagram representing a mobile system 3000 with a storage device 3200 according to an embodiment of the present disclosure. Referring to Fig. 18, the mobile system 3000 can comprise an application processor (AP) 3100, a storage device 3200, a network device 3300, a storage device 3400 and a user interface 3500. The Application Processor 3100 can control components, an operating system (OS), or a user program included in the Mobile System 3000. For example, the Application Processor 3100 can be implemented as a system-on-a-chip (SoC). The memory device 3200 can function as main memory, operating memory, buffer memory, or cache memory of the mobile system 3000. The memory device 3200 can comprise volatile random-access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR3 SDARM, or non-volatile random-access memory such as PRAM, ReRAM, MRAM, FRAM, etc. According to one embodiment, the memory device 3200 can correspond to the memory device 100 described in Fig. 1. That is, the memory device 3200 can comprise a memory core and an ECC engine. The ECC engine can correct not only an error occurring in one symbol but also an error occurring at both ends of two adjacent symbols. Therefore, it is possible to extend the error correction capability of the memory device. Depending on the embodiment, the memory device 3200 can be configured with the memory module 1000 described in Fig. 16. The Network Device 3300 can communicate with external devices. For example, the Network Device 3300 can support wireless communication such as Code Division Multiple Access (CDMA), Global System for Mobile Communication (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, Wi-Fi, etc. For example, the Network Device 3300 can be integrated into the Application Processor 3100. The storage device 3400 can store data. For example, the storage device 3400 can store data received by the application processor 3100. Alternatively, the storage device 3400 can transfer the stored data to the application processor 3100. For example, the storage device 3400 can be implemented as a non-volatile semiconductor storage device such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash, or three-dimensional NAND flash. While the present invention has been described with respect to specific embodiments, it will be obvious to a person skilled in the art that various changes and modifications can be made without deviating from the meaning and scope of the present disclosure as defined in the following claims. Furthermore, the embodiments can be combined to form additional embodiments.

Claims

A storage device comprising: a memory core with a plurality of cell blocks grouped into a plurality of cell groups, each cell group comprising adjacent cell blocks arranged in a row direction and sharing sub-word drivers with adjacent cell groups; and an error correction circuit configured to correct an error of main data in units of symbols during a read operation by calculating the main data and an error correction code read from the memory core with a check matrix, each unit of symbols comprising data output by a cell group or data output by cell blocks arranged at both ends of two adjacent cell groups, based on a sub-word driver shared between them. Storage device according to claim 1, wherein the check matrix comprises: data matrices corresponding to the principal data, each data matrix comprising an upper section in which two unit matrices are arranged in a first diagonal direction and a lower section in which two identical Tk companion matrices are arranged in the first diagonal direction; and parity matrices corresponding to the error correction code, each parity matrix comprising an upper section in which two unit matrices are arranged in the first diagonal direction and a lower section in which two unit matrices or two zero matrices are arranged in the first diagonal direction. Storage device according to claim 2, wherein each of the unit matrices and the Tk companion matrices has a size of j * j, where “j” is a number of bits of data output by a cell block. Storage device according to claim 2, wherein k values ​​of the Tk companion matrices are distinct positive integers that differ from each data matrix. Storage device according to claim 2, wherein each of the Tk companion matrices is formed by a matrix comprising a plurality of column vectors from αk to αk+m-1, where “m” is a number of data bits output by a cell block, and “α” comprises a primitive element. Storage device according to claim 5, wherein the primitive element “α” is set to 2. Storage device according to claim 1, further comprising: an error correction code (ECC) generation circuit which is set up during a write operation to generate the error correction code by calculating the main data to be written to the memory core using the check matrix. Storage device according to claim 1, wherein the error correction circuit comprises: a syndrome generation circuit configured to generate a first syndrome and a second syndrome by comparing the error correction code with a computation result obtained by calculating the main data with the check matrix; a syndrome comparison circuit configured to generate a plurality of subsyndromes by calculating the first syndrome and a lower section of the check matrix, and to generate a plurality of syndrome comparison signals corresponding to each of the plurality of cell blocks by comparing the plurality of subsyndromes and the second syndrome; a fault location detector configured to generate a fault location signal indicating a fault location in units of symbols based on the plurality of syndrome comparison signals;and an error correction device that is set up to correct an error in the main data according to the error location signal. Storage device according to claim 8, wherein the fault location detector comprises: a symbol adding device configured to generate, from among the plurality of syndrome comparison signals, a plurality of operation signals based on syndrome comparison signals corresponding to cell blocks included in a cell group, a plurality of adjacent operation signals based on syndrome comparison signals corresponding to cell blocks located at both ends of two adjacent cell groups, and a plurality of preliminary detection signals by summing the operation signals and the adjacent operation signals; and a plurality of fault detectors configured to generate the fault location signal by processing the first syndrome and the plurality of preliminary detection signals. Storage device according to claim 1, wherein each of the cell groups comprises: odd-numbered word lines that share odd-numbered sub-word line drivers with a cell group that are adjacent to each other in a first direction of the line direction; and even-numbered word lines that share odd-numbered sub-word line drivers with a cell group that are adjacent to each other in a second direction of the line direction, which is opposite to the first direction. A storage device comprising: a lower chip; and one or more upper chips stacked above the lower chip, each of the upper chips comprising: a memory core with a plurality of cell blocks grouped into a plurality of cell groups, each cell group comprising adjacent cell blocks arranged in a row direction; and an error correction circuit configured during a read operation to correct an error of main data in units of symbols by calculating the main data and an error correction code read from the memory core with a check matrix, each unit of symbols comprising data output by a cell group or data output by cell blocks arranged at both ends of two adjacent cell groups. Storage device according to claim 11, wherein each of the plurality of cell groups is configured to share sub-directory drivers with adjacent cell groups, wherein the cell blocks arranged at both ends of two adjacent cell groups are configured, on the basis of the sub-directory driver shared by the two adjacent cell groups, to be arranged at both ends of two adjacent cell groups. Storage device according to claim 11, wherein the check matrix comprises: data matrices corresponding to the main data, each data matrix comprising an upper section in which two unit matrices are arranged in a first diagonal direction and a lower section in which two identical Tk companion matrices are arranged in the first diagonal direction; and parity matrices corresponding to the error correction code, each parity matrix comprising an upper section in which two unit matrices are arranged in the first diagonal direction and a lower section in which two unit matrices or two zero matrices are arranged in the first diagonal direction. Storage device according to claim 13, wherein each of the unit matrices and the Tk companion matrices has a size of j * j, where “j” is a number of data bits output from a cell block. Error correction device comprising: a syndrome comparison circuit configured to generate a plurality of subsyndromes by calculating a first syndrome specifying an error pattern and a check matrix, and to generate a plurality of syndrome comparison signals corresponding to each of a plurality of cell blocks by comparing the plurality of subsyndromes and a second syndrome specifying a location of an error-containing symbol;a fault location detector configured to generate a fault location signal indicating a fault location in units of symbols based on the plurality of syndrome comparison signals, wherein the units of symbols comprise data output by a cell group among a plurality of cell groups in which adjacent cell blocks are grouped, or data output by cell blocks located at both ends of two adjacent cell groups; and a fault correction device configured to correct an error in a codeword output by the plurality of cell groups according to the fault location signal. Error correction device according to claim 15, wherein each of the plurality of cell groups is configured to share sub-direction drivers with adjacent cell groups, wherein the cell blocks arranged at both ends of two adjacent cell groups are configured to be arranged at both ends of two adjacent cell groups on the basis of the sub-direction driver shared between the two adjacent cell groups. Error correction device according to claim 15, wherein the check matrix comprises: data matrices corresponding to the principal data contained in the codeword, each data matrix comprising an upper section in which two unit matrices are arranged in a first diagonal direction and a lower section in which two identical Tk companion matrices are arranged in the first diagonal direction, wherein k values ​​of the Tk companion matrices are distinct positive integers that differ from each data matrix; and parity matrices corresponding to an error correction code contained in the codeword, each parity matrix comprising an upper section in which two unit matrices are arranged in the first diagonal direction and a lower section in which two unit matrices or two zero matrices are arranged in the first diagonal direction. Error correction device according to claim 17, wherein each of the unit matrices and the Tk companion matrices comprises a size of j * j, where “j” is a number of data bits output by a cell block. Error correction device according to claim 15, further comprising: a parity calculator configured to generate a preliminary error correction code by calculating the principal data and check matrix included in the codeword; and a syndrome generator configured to generate the first syndrome and the second syndrome by comparing an error correction code included in the codeword with the preliminary error correction code. Error correction device according to claim 15, wherein the syndrome comparison circuit comprises: a syndrome multiplier configured to generate the plurality of subsyndromes corresponding to the plurality of groups by performing matrix multiplication on the first syndrome and a lower section of the test matrix; and a syndrome comparator configured to generate the plurality of syndrome comparison signals by comparing the plurality of subsyndromes with the second syndrome. Error correction device according to claim 20, wherein the syndrome multiplier comprises: data multipliers configured to generate lower subsyndromes by performing matrix multiplication on lower bits of the first syndrome and the Tk companion matrices, and to generate upper subsyndromes by performing matrix multiplication on upper bits of the first syndrome and the Tk companion matrices, wherein k values ​​of the Tk companion matrices are distinct positive integers that differ from each data matrix; and parity multipliers configured to generate the lower subsyndromes by performing matrix multiplication on the lower bits of the first syndrome and an identity matrix or a zero matrix, and to generate the upper subsyndromes by performing matrix multiplication on the upper bits of the first syndrome and the identity matrix or the zero matrix. Error correction device according to claim 15, wherein the fault location detector comprises: a symbol adding device configured to generate, from among the plurality of syndrome comparison signals, a plurality of operation signals based on syndrome comparison signals corresponding to cell blocks included in a cell group, a plurality of adjacent operation signals based on syndrome comparison signals corresponding to cell blocks located at both ends of two adjacent cell groups, and a plurality of preliminary detection signals by summing the operation signals and the adjacent operation signals; and a plurality of fault location detectors configured to generate the fault location signal by processing the first syndrome and the plurality of preliminary detection signals. Storage device comprising: a memory core; and an error correction circuit configured during a read operation to correct an error in principal data in units of symbols by calculating the principal data and an error correction code read from the memory core using a check matrix, wherein the check matrix comprises: data matrices corresponding to the principal data, each data matrix comprising an upper section in which two unit matrices are arranged in a first diagonal direction, and a lower section in which two identical Tk companion matrices are arranged in the first diagonal direction, the k values ​​of the Tk companion matrices being distinct positive integers different from each data matrix;and parity matrices corresponding to the error correction code, each parity matrix comprising an upper section containing two unit matrices arranged in the first diagonal direction and a lower section containing either two unit matrices or two zero matrices arranged in the first diagonal direction.

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