Semiconductor device and method for manufacturing the same
A delay circuit with selectable paths and a selection signal addresses timing clock defects and electromigration in semiconductor devices, enhancing precision and reducing rework in the manufacturing process.
DE102025150327A1Pending Publication Date: 2026-06-11RENESAS ELECTRONICS CORP
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Patent Information
- Application Number
- DE102025150327
- Authority / Receiving Office
- DE · DE
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-12-11
- Filing Date
- 2025-12-03
- Publication Date
- 2026-06-11
AI Technical Summary
Technical Problem
Existing semiconductor manufacturing processes face challenges in managing timing clock defects due to wiring delays, which are exacerbated by miniaturization and lower operating voltages, leading to increased rework and electromigration errors when manually correcting locally concentrated circuits.
Method used
The implementation of a delay circuit with multiple selectable delay paths and a selection signal allows for precise delay value adjustment, enabling automatic or manual correction of timing violations while reducing electromigration errors and minimizing rework.
Benefits of technology
This approach enables high-precision delay design with reduced labor hours and rework, effectively addressing timing violations and electromigration issues in semiconductor devices.
✦ Generated by Eureka AI based on patent content.
Abstract
A semiconductor device and its manufacturing process are provided that are capable of designing the intended delay with high precision in just a few steps.The semiconductor device fabrication method disclosed herein arranges several circuits on one plane and connects a wiring system to each, comprising: a placement step of arranging a digital circuit operating on the basis of timing signals and a delay circuit configured with several delay paths having different input / output delay amounts, wherein one of the several delay paths can be selected by a selection signal; a wiring step of connecting the output of the delay circuit so that it becomes the timing signal of the digital circuit; and a delay setting step of selecting one of the several delay paths by connecting a predetermined voltage as the selection signal and selecting the delay amount so that the input / output timing of the digital circuit satisfies predetermined conditions.
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