SYSTEM AND METHOD FOR SUPPRESSING INTERFERENCE FREQUENCIES FOR MODEMS

Abstract

A demodulator (114) comprising the following: a recipient; and a DCR circuit (200) wherein the DCR circuit (200) alternates between the following: a detection mode wherein the DCR circuit (200) operates with a circular gain block (204) having a first circular gain and a first accumulation value to identify a plurality of harmonic interference frequencies, including an interference frequency at 2480 MHz that coincides with a center frequency of a Bluetooth Low Energy radio, resulting from a 16 MHz clock frequency oscillator; and a tracking mode, wherein the DCR circuit (200) operates with the circular gain block (204) which has a second circular gain and a second accumulation value, wherein: the second loop gain is smaller than the first loop gain; wherein each of the first and second loop gains is restricted to powers of 2 and is implemented as bit shifts over a system of registers, where the second accumulation value is defined by multiplying the first accumulation value by the first loop gain and dividing by the second loop gain; a time control for switching between the acquisition mode and tracking mode is programmable; and The DCR circuit (200) re-identifies the interference frequencies each time the receiver is switched from an off state to an on state.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is an international application of U.S. application No. 15 / 631,922, filed June 23, 2017, which claims priority to U.S. provisional application Serial No. 62 / 446,102, filed January 13, 2017. TECHNICAL FIELD

[0002] The present disclosure relates generally to the field of communications devices, and more particularly to techniques and methods for suppressing interference frequencies used in communications devices. BACKGROUND

[0003] A modem (modulator-demodulator) is a network device that modulates and demodulates signals to enable the transmission of information. A modem may employ some type of frequency modulation scheme to implement modulation and demodulation. For example, modems such as Bluetooth modems, ZigBee modems, Bluetooth Low Energy (BLE) modems, and the like may employ some type of frequency modulation scheme called frequency shift keying (FSK). FSK modulation may be configured to enable the transmission of digital information through discrete frequency changes.

[0004] The frequencies used by FSK modems can be controlled using oscillators, which can cause interference signals (also known as spurious frequencies) to appear. Interference frequencies can degrade performance and cause communication outages.

[0005] Furthermore, the disclosures of US 2006 / 0 203 950 A1, US 2003 / 0 235 262 A1, US 2002 / 0 186 799 A1, US 2006 / 0 093 079 A1 and US 2005 / 0 152 463 A1 may be helpful for understanding the present invention.

[0006] US 2006 / 0 203 950 A1 describes frequency control techniques using dual-loop automatic frequency control (AFC). Dual-loop AFC comprises an inner loop that corrects short-term frequency fluctuations (e.g., due to the Doppler effect) and an outer loop that corrects long-term frequency fluctuations (e.g., due to component tolerances and temperature fluctuations). In one embodiment, a first inner loop is implemented for frequency control of a first system (e.g., a broadcast system), a second inner loop is implemented for frequency control of a second system (e.g., a cellular system), and at least one outer loop is implemented for adjusting a reference frequency used for receiving signals from the first and second systems.Each inner loop estimates and corrects the frequency error in an input signal for the associated system and can be activated when the input signal is received by the system. The reference frequency can be used for frequency downconversion, sampling, and / or other purposes.

[0007] US 2003 / 0 235 262 A1 discloses a system and method for improving the performance of a digital PLL through fine-grained adjustments of the loop gain. A preferred embodiment comprises a plurality of loop gain adjusters capable of adjusting the loop gain in steps. The stepwise adjusted loop gains are operated sequentially, so that the loop gain of the digital PLL is slowly reduced. By slowly reducing the loop gain, the digital PLL is less disturbed by smaller noise transients that would require time to settle. Therefore, the digital PLL can quickly acquire a signal and then reduce its loop gain and thus its bandwidth when it only needs to track one signal. The reduced bandwidth also reduces the overall noise in the digital PLL due to the contribution of the reference noise. OVERVIEW

[0008] The present invention relates to demodulators according to claim 1 and claim 9 and to a method for demodulating a signal according to claim 15. Advantageous embodiments may comprise features of dependent claims.

[0009] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily limiting of the present disclosure. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate the subject matter of the disclosure. The descriptions and drawings together serve to explain the basic principles of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The numerous advantages of the disclosure may be better understood by those skilled in the art by reference to the accompanying figures, in which: Fig. 1 is a block diagram of a radio equipped with a demodulator configured in accordance with an embodiment of the present disclosure; Fig. Figure 2 is a simplified block diagram illustrating a direct current removal (DCR) circuit used as part of a digital front end of a demodulator; Fig. 3 is a diagram of a finite state machine for switching a DCR circuit between an acquisition mode and a tracking mode according to an embodiment of the present disclosure; Fig. 4 is a diagram illustrating experimental data illustrating the effectiveness of a DCR circuit configured in accordance with an embodiment of the present disclosure; Fig. 5 is an illustration of a circuit for controlling mode switching according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings.

[0012] Generally referring to Fig. 1, a simplified block diagram illustrating a radio 100 is shown. Since radio devices are well understood by those skilled in the art, it is noted that detailed descriptions of each component of the radio 100 illustrated in Fig. 1, will not be repeated in the present disclosure. In general, the radio 100 may include a radio frequency (RF) transceiver 102, a modem 104, and an oscillator 106. The RF transceiver 102 may include a transmitter 108 and a receiver 110. The transmitter 108 may be configured to transmit signals provided by a modulator 112. The receiver 110, on the other hand, may be configured to receive signals and provide the received signals to a demodulator 114 for processing. It should be understood that although the modulator 112 and the demodulator 114 are shown implementing FSK modulation, the implementation of FSK modulation is shown merely as an illustration and is not meant to be limiting.It is contemplated that the modulator 112 and demodulator 114 may implement various other types of time-based modulations without departing from the spirit and scope of the present disclosure.

[0013] Oscillator 106 may be configured to use a digital clock to generate oscillating signals. Oscillator 106 may generate spurious signals (interference frequencies). For example, a 16 MHz analog-to-digital converter (ADC) clock may generate harmonic interference frequencies of N x 16 MHz, including 2480 MHz, which may coincide with the center frequency of one of the channels used by radio 100 if radio 100 is a BLE radio. As such, spurious frequencies have a significant impact on the performance of radio 100 and should therefore be suppressed or reduced.

[0014] Fig. Figure 2 is a simplified block diagram illustrating a direct current removal (DCR) circuit 200 that may be used as part of the digital front-end of demodulator 114 to help reduce spurious frequency. DCR circuit 200 may include an accumulator 202 and a loop gain block 204. In some embodiments, loop gain values ​​may be limited to powers of 2 and implemented as bit shifts via a system of registers that transfer bits to obtain a higher order value. Since accumulator 202 and loop gain block 204 are configured to perform linear operations, it is contemplated that the order of blocks 202 and 204 may be interchangeable without departing from the spirit and scope of the present disclosure.

[0015] Although the DCR circuit 200 can track and reduce interference frequencies, it is contemplated that its effectiveness may be limited if the radio 100 employs power management solutions. For example, to help reduce power consumption, the receive path (e.g., the receiver 110 and the modulator 112) of the radio 100 can be turned off after receiving a data packet. The receive path can be turned back on to warm up before the arrival of the next data packet. The DCR circuit 200 can continuously track the interference frequency, and the loop gain block 204 can select a gain value to minimize the interference frequency estimate variation to optimize the access code and data demodulation performance. However, the loop gain block 204 may require a relatively long settling time for the DCR circuit 200 to converge.A longer settling / warm-up time implies that the radio 100 must wake up much earlier than the arrival of data packets, effectively increasing its power consumption.

[0016] DCR circuits configured in accordance with some embodiments of the present disclosure may be configured to support multiple modes of interference frequency suppression to improve their effectiveness. For example, in some embodiments, a multi-mode DCR circuit 200 may be configured in the same manner as the one described in Fig. 2. However, instead of using a fixed loop gain block 204, the loop gain block 204 may be dynamically changed and controlled in a multi-mode DCR circuit 200. Because timing is critical, it is contemplated that a hardware finite state machine (FSM) may be implemented to control the dynamic loop gain switching. In some embodiments, the FSM may be configured to cycle among an acquisition mode, a tracking mode, and a hold mode.

[0017] Acquisition mode can be initiated when the receive path of radio 100 is turned on (or woken up). Acquisition mode can be configured with a large loop gain to converge quickly, thereby reducing the settling / warm-up time. Tracking mode can be initiated after a programmable time (e.g., 4 µs) or at the end of acquisition mode. Tracking mode can be configured with a smaller loop gain compared to acquisition mode.

[0018] In some embodiments, the interference frequency estimate acquired in the acquisition mode can be used as the initial value for the tracking mode. To enable this process, the accumulation value maintained by the loop gain block 204 must be correctly escalated when the loop gain block 204 switches from the acquisition mode to the tracking mode. Mathematically, the relationship between the accumulation value and the new accumulation value can be expressed as follows: Accumulation value × loop gain = new accumulation value × new loop gain, which means that the new accumulation value can be determined as: new accumulation value = accumulation value × loop gain new loop gain

[0019] It should be noted that this scaling operation only needs to be performed once during mode switching. Alternatively, if the order of the accumulator 202 and the loop gain block 204 is reversed (with reference to the Fig. 2), the accumulation value does not need to be escalated when the loop gain mode switches because the final loop gain value before the mode switch includes the latest accumulation value.

[0020] In some embodiments, the FSM may be configured to support a third mode, referred to as hold mode. If hold mode is enabled, upon entering hold mode (e.g., after synchronization is complete), the feedback loop of the DCR circuit for data demodulation may freeze. Freezing the feedback loop saves power by maintaining a current loop gain. A timing regulator may cause the circuit to periodically exit hold mode to adjust the current loop gain or restart track mode. Alternatively, a threshold packet error ratio may be used to indicate that the loop gain needs to be adjusted, and the circuit may exit hold mode. If hold mode is disabled, the FSM may simply switch between acquisition mode and track mode as described above.

[0021] It is contemplated that the DCR circuits configured according to embodiments of the present disclosure may be implemented as part of the front end of the demodulators. It is contemplated that a digital front end of a demodulator may be implemented as an application-specific integrated circuit (ASIC), a portion of which may implement the various Fig. 2 that form the demodulator. It is contemplated that demodulators configured in this way may be used in various types of time-based modems, including low-frequency clock and low-power modems.

[0022] Fig. Figure 3 is a representation of a finite state machine for switching a DCR circuit between an acquisition mode and a tracking mode. An acquisition mode is initiated, and a first loop gain is set 300 to converge quickly, thereby reducing the settling / warm-up time. An acquisition mode is set 302 to establish a boundary for the acquisition mode. When the acquisition mode timer expires 304 (e.g., 4 µs), a tracking mode with a second loop gain is initiated 306. The acquisition mode timer may be programmable. Alternatively or additionally, the circuit may identify when the acquisition mode has acquired a signal. The tracking mode may be configured with a smaller loop gain compared to the acquisition mode.In some embodiments, when synchronization 308 is complete, the circuit may be placed in a hold state in which the feedback loop is frozen 310 to continuously update the loop gain value. The receiver is then powered down 314. In some embodiments, a wake-up timer is set 314. When the wake-up timer expires 316, the receiver is re-enabled to warm up in order to receive the next packet.

[0023] The on or off state of the receiver while a wake-up timer is executing may be considered receiver state 320. Similarly, in an acquisition mode with an acquisition timer or when updating a loop gain value during reception, the machine may be considered to be in a DCR state. A finite state machine according to embodiments of the present disclosure may be software-based or hardware-based.

[0024] Fig. Figure 4 is a diagram illustrating experimental data illustrating the effectiveness of multimode DCR circuits when the payload length is set to 37 bytes and the receiver warm-up time is set to 9 µs. Compared to the baseline 400 established using a conventional DCR circuit, a multimode DCR circuit 402 according to the present disclosure significantly reduced the convergence time and met the requirement for a packet error ratio (PER) of 30.8% with a sensitivity level of -95 dBm for interference frequency channels with sufficient margins.

[0025] Fig.5 is an illustration of a circuit for controlling mode switching according to an embodiment of the present disclosure. A radio 500 operating in an analog domain receives a signal that is converted to a digital signal via an analog-to-digital converter 502. A digital mixer 504 includes a mixer 506 that receives the digitally sampled signal from the analog-to-digital converter 502 and a signal from a numerically controlled oscillator (NCO) 508. The mixed output is transferred to a digital front-end demodulator 510 configured to convert the sampling rate, filter the noise, and mitigate DC interference. The digital front-end demodulator 510 includes a decimation filter 512.In some embodiments, decimation filter 512 may bit-shift the incoming signal to convert the signal from a higher-speed clock domain 532 to a lower-speed clock domain 534 and transfer it to a low-pass filter 514. DC noise is removed from the low-pass filtered signal via a noise suppressor / DC remover 516. An interpolation filter 518 then adjusts the signal, for example, via bit shifting, to convert the signal from a lower-speed clock domain 534 to a higher-speed clock domain 536.

[0026] The signal is then fed to an FSK demodulator 520, for example, a Gaussian Frequency Shift Keying (GFSK) demodulator. The FSK demodulator 520 includes a frequency detector 522 to convert the in-phase and quadrature components of the signal to frequency and remove frequency offsets. The frequency signal is sent to a correlator 524 to identify and correlate symbols based on frequency peaks. The identified symbols and the original frequency are sent to a bit sampler 526, which converts the signal to a lower frequency domain 538 suitable for processing by a bit equalizer 528 and slicer 530, which outputs a demodulated bit stream.

[0027] It is believed that the systems and devices disclosed herein, and many of their attendant advantages, are understood from the foregoing description, and it will be appreciated that various changes in the form, construction, and arrangement of components thereof may be made without departing from the broad scope of the present disclosure or without losing all of its material advantages. The form described hereinabove represents merely an illustrative embodiment thereof; it is the intent of the following claims to encompass and embrace such changes.

[0028] The above description is illustrative and not limiting. The embodiments described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments will be apparent to those skilled in the art after reviewing the above description. Throughout this document, the terms "a," "an," or "another" are used, as is common in patent documents, to include one or more than one. Throughout this document, the term "or" is used to mean non-exclusive, or such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise noted.In the event of inconsistent uses of this document and those documents incorporated by reference, the use in the incorporated references shall be considered supplementary to this document; in the event of irreconcilable inconsistencies, the use of this document shall supersede the use in the incorporated references.

[0029] Although the claimed subject matter has been described with reference to specific embodiments, it will be evident that various modifications and changes may be made to those embodiments without departing from the broad spirit and scope of what is claimed. Accordingly, the specification and drawings are to be regarded as illustrative and not restrictive. The scope of the claims should, therefore, be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms "comprising" and "in which" are used as simple equivalents of the respective terms "including" and "wherein."Furthermore, in the following claims, the terms "comprising" and "including" are open-ended; a system, device, article, or process that includes elements in addition to those listed after such a term in a claim is still intended to be within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used only as labels and are not intended to impose numerical requirements on their objects.

Claims

[1] A demodulator (114) comprising: a recipient; and a direct current removal (DCR) circuit (200), the DCR circuit (200) alternating between: a detection mode, wherein the DCR circuit (200) operates with a loop gain block (204) having a first loop gain and a first accumulation value to identify a plurality of harmonic interference frequencies, including an interference frequency at 2480 MHz that coincides with a center frequency of a Bluetooth Low Energy radio, resulting from a 16 MHz clock frequency oscillator; and a tracking mode, wherein the DCR circuit (200) operates with the loop gain block (204) having a second loop gain and a second accumulation value, wherein: the second loop gain is smaller than the first loop gain; wherein each of the first and second loop gains is limited to powers of 2 and is implemented as bit shifts via a system of registers, wherein the second accumulation value is defined by multiplying the first accumulation value by the first loop gain and dividing it by the second loop gain, a timing control of the change between the acquisition mode and tracking mode is programmable; and the DCR circuit (200) re-identifies the interference frequencies each time the receiver is controlled from an off state to an on state. [2] The demodulator (114) of claim 1, wherein the DCR circuit (200) switches to a hold mode to freeze a loop gain of the DCR circuit (200) for data demodulation. [3] Demodulator (114) according to claim 2, wherein the change to the hold mode takes place after completion of a synchronization. [4] Demodulator (114) according to any one of claims 1-3, wherein the change between the acquisition mode and the tracking mode is controlled by a finite hardware state machine. [5] Demodulator (114) according to claim 4, wherein an interference frequency estimate acquired in the acquisition mode is used as an initial value for the tracking mode. [6] The demodulator (114) of claim 5, wherein an accumulation value maintained by the DCR circuit (200) operating in the acquisition mode is scaled when the DCR circuit (200) changes from the acquisition mode to the tracking mode. [7] Demodulator (114) according to one of claims 1-6, wherein the demodulator (114) is a frequency shift keying (FSK) demodulator. [8] Demodulator (114) according to one of claims 1-7, wherein the DCR circuit (200) forms at least part of a digital front end of the demodulator (114). [9] A demodulator (114) comprising: a recipient; and a direct current removal (DCR) circuit (200) having a system of registers configured to transfer the bits of a signal according to one of a plurality of loop gain values, the DCR circuit (200) switching between: a detection mode, wherein the DCR circuit (200) operates with a loop gain block (204) having a first loop gain and a first accumulation value to identify a plurality of harmonic interference frequencies, including an interference frequency at 2480 MHz that coincides with a center frequency of a Bluetooth Low Energy radio, resulting from a 16 MHz clock frequency oscillator (106); a tracking mode, wherein the DCR circuit (200) operates with the loop gain block (204) having a second loop gain and a second accumulation value; and a hold mode, wherein the DCR circuit (200) freezes a loop gain of the DCR circuit (200) for data demodulation, wherein: the second loop gain is smaller than the first loop gain; the second accumulation value is defined by multiplying the first accumulation value by the first loop gain and dividing by the second loop gain, each of the first and second loop gains being limited to powers of 2, a time control for switching between the acquisition mode and tracking mode is programmable; the switch to hold mode occurs after completion of a synchronization; and the DCR circuit (200) re-identifies the interference frequency each time, starting with the frozen loop gain, the receiver is controlled from an off state to an on state. [10] Demodulator (114) according to claim 9, wherein the switching among the acquisition mode, the tracking mode and the hold mode is controlled by a finite hardware state machine. [11] Demodulator (114) according to claim 9 or 10, wherein an interference frequency estimate acquired in the acquisition mode is used as an initial value for the tracking mode. [12] The demodulator (114) of claim 11, wherein an accumulation value maintained by the DCR circuit (200) operating in the acquisition mode is scaled when the DCR circuit (200) changes from the acquisition mode to the tracking mode. [13] Demodulator (114) according to one of claims 9-12, wherein the demodulator (114) is a frequency shift keying (FSK) demodulator. [14] Demodulator (114) according to one of claims 9-13, wherein the DCR circuit (200) forms at least part of a digital front end of the demodulator (114). [15] A method of demodulating a signal, comprising: Placing a DCR circuit (200) in an acquisition mode having a first loop gain, wherein a loop gain block (204) maintains a first accumulation value; setting an acquisition mode timer of a maximum of 4 µs; Identifying an interference frequency in a plurality of harmonic interference frequencies resulting from a 16 MHz clock frequency oscillator (106), wherein the interference frequency at 2480 MHz coincides with a center frequency of a Bluetooth Low Energy radio; Converting a signal by bit shifting using a decimation filter (512) from a first domain with a higher speed clock (532) to a second clock domain with a lower speed clock (534); Placing the DCR circuit (200) in a tracking mode having a second loop gain, wherein the loop gain block (204) maintains a second accumulation value based on at least one of expiring the acquisition mode timer and identifying the interference frequency; and Re-identifying the interference frequency each time the receiver is controlled from an off state to an on state, wherein the second loop gain is less than the first loop gain and the second accumulation value is defined by multiplying the first accumulation value by the first loop gain and dividing by the second loop gain;. [16] The method of claim 15, further including placing the DCR circuit (200) in a hold mode to freeze a loop gain of the DCR circuit (200) for data demodulation. [17] The method of claim 16, further comprising switching from the hold mode to one of the track mode and the capture mode when a packet error ratio exceeds a threshold. [18] The method of any of claims 15-17, wherein identifying when to place the DCR circuit (200) into tracking mode is controlled by a hardware finite state machine. [19] A method according to any one of claims 15-18, further comprising detecting an interference frequency estimate in the detection mode as an initial value for the tracking mode. [20] The method of claim 19, further comprising scaling an accumulation value identified in the acquisition mode before placing the DCR circuit (200) in the tracking mode.

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