GRAPHICS PROCESSOR CACHE FOR DATA FROM MULTIPLE STORAGE SPACES

Abstract

In the disclosed embodiment, a graphics processing unit (GPU) is configured to operate data in multiple memory spaces. Data cache switching logic can cache data for the GPU switching logic, including data from multiple memory spaces. The data cache switching logic can include tag switching logic configured to compare the following information from access requests to the data cache switching logic with tags of entries in the data cache switching logic: memory space information and a tag portion of a requested address. The tag portion of a requested address can be different for at least two of the multiple memory spaces (e.g., a different set of bit indices within the address). The disclosed techniques can advantageously enable caching for different clients with different cache line sizes, address spaces, etc., e.g., in uniform memory architectures.