Display panel and display device

Abstract

A pixel circuit, a display panel, and a display device, relating to the technical field of display. The pixel circuit comprises a driving transistor (T3), an energy storage circuit (RU), a write circuit (DU), and a first light emission control circuit (EU1). A gate of the driving transistor (T3) is connected to a first electrode of the driving transistor (T3) by means of the energy storage circuit (RU); the first electrode of the driving transistor (T3) is adapted to be connected to a light-emitting device (LD); a second electrode of the driving transistor (T3) is connected to the first light emission control circuit (EU1); the first light emission control circuit (EU1) is used for receiving a first power supply signal (VDD); the write circuit is connected to the gate of the driving transistor (T3); the write circuit (DU) is connected to the first electrode of the driving transistor (T3) by means of the energy storage circuit (RU); the write circuit (DU) is used for writing a data signal (Data) to the energy storage circuit (RU); the energy storage circuit (RU) is used for storing the data signal (Data) and a voltage of the first electrode of the driving transistor (T3).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.BACKGROUND

[0002] Organic Light Emitting Diode (OLED) display panels have the advantages of self-luminescence, wide color gamut, high contrast, flexibility, high response and flexibility, etc., and have broad application prospects. However, the uniformity of the luminous brightness of the existing display panels still needs to be improved, and display screen abnormalities are prone to occur.

[0003] It should be noted that the information disclosed in the Background section above is only for enhancing the understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.SUMMARY

[0004] An objective of the present disclosure is to overcome the above-mentioned deficiencies in the prior art and provide a display panel and a display device.

[0005] According to an aspect of the present disclosure, there is provided a pixel circuit, including a driving transistor, an energy storage circuit, a writing circuit and a first light emitting control circuit; a gate of the driving transistor is connected to a first electrode of the driving transistor through the energy storage circuit, the first electrode of the driving transistor is configured to be connected to a light emitting device, and a second electrode of the driving transistor is connected to the first light emitting control circuit, and the first light emitting control circuit is configured to receive a first power signal; and the writing circuit is connected to the gate of the driving transistor; the writing circuit is connected to the first electrode of the driving transistor through the energy storage circuit; the writing circuit is configured to write a data signal to the energy storage circuit; the energy storage circuit is configured to store the data signal and a voltage of the first electrode of the driving transistor.

[0006] In an embodiment of the present disclosure, the energy storage circuit includes a first capacitor and a second capacitor; the writing circuit includes a writing transistor; the first light emitting control circuit includes a first light emitting control transistor; a first electrode of the writing transistor is configured to input the data signal, and a second electrode of the writing transistor is connected to the gate of the driving transistor and a first plate of the first capacitor; a second plate of the first capacitor is connected to the first plate of the second capacitor, and a second plate of the second capacitor is connected to the first electrode of the driving transistor; a first electrode of the first light emitting control transistor is configured to input the first power signal, and a second electrode of the first light emitting control transistor is connected to the second electrode of the driving transistor.

[0007] In an embodiment of the present disclosure, the pixel circuit further includes: a first reset transistor, wherein a first electrode of the first reset transistor is configured to receive a reference signal, and a second electrode of the first reset transistor is connected to the gate of the driving transistor; and a second reset transistor, wherein a first electrode of the second reset transistor is configured to receive the reference signal, and a second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor.

[0008] In an embodiment of the present disclosure, the pixel circuit further includes: a third reset transistor, wherein a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the second plate of the second capacitor.

[0009] In an embodiment of the present disclosure, the pixel circuit further includes a second light emitting control circuit, and the first electrode of the driving transistor is connected to the light emitting device through the second light emitting control circuit.

[0010] In an embodiment of the present disclosure, the second light emitting control circuit includes a second light emitting control transistor; a first electrode of the second light emitting control transistor is connected to the first electrode of the driving transistor, and a second electrode of the second light emitting control transistor is connected to the light emitting device; the pixel circuit further inlcudes: a third reset transistor, wherein a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the second electrode of the second light emitting control transistor.

[0011] In an embodiment of the present disclosure, at least one of the driving transistor, the writing transistor, the first reset transistor, the second reset transistor, the third reset transistor, the first light emitting control transistor, and the second light emitting control transistor is a metal oxide transistor.

[0012] According to an aspect of the present disclosure, there is provided a display panel, including a plurality of pixel circuits arranged in an array along a row direction and a column direction, wherein the pixel circuit includes a plurality of transistors, a first capacitor and a second capacitor, and the transistors includes a driving transistor, a writing transistor, a first light emitting control transistor, a second light emitting control transistor, a first reset transistor, a second reset transistor and a third reset transistor; a first electrode of the first light emitting control transistor is configured to receive a first power signal, and a second electrode of the first light emitting control transistor is connected to a second electrode of the driving transistor; a first electrode of the writing transistor is configured to receive a data signal, a second electrode of the writing transistor is connected to a first plate of the first capacitor and a gate of the driving transistor, a second plate of the first capacitor is connected to a first plate of the second capacitor, and a second plate of the second capacitor is connected to a first electrode of the driving transistor; a first electrode of the second light emitting control transistor is connected to the first electrode of the driving transistor; a first electrode of the first reset transistor and a first electrode of the second reset transistor are configured to receive a reference signal, a second electrode of the first reset transistor is connected to the gate of the driving transistor, and a second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor; a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the first electrode of the driving transistor or the second electrode of the second light emitting control transistor; the display panel includes: a substrate; a semiconductor layer, disposed on a side of the substrate and including an active portion of each of the transistors; a plurality of light emitting devices, disposed on a side of the semiconductor layer away from the substrate, wherein a light emitting device is connected to a second electrode of a second light emitting control transistor of a pixel circuit; one of the first plate and the second plate of the first capacitor is disposed in the same layer as one of the first plate and the second plate of the second capacitor; and one of the first capacitor and the second capacitor is overlapped with an active portion of the driving transistor.

[0013] In an embodiment of the present disclosure, the semiconductor layer includes a first semiconductor portion and a second semiconductor portion distributed at an interval along the row direction; active portions of the writing transistor, the first reset transistor and the second reset transistor are located in the first semiconductor portion and are connected in sequence; active portions of the first light emitting control transistor, the driving transistor, the second light emitting control transistor and the third reset transistor are located in the second semiconductor portion and are connected in sequence.

[0014] In an embodiment of the present disclosure, the first plate of the first capacitor and the first plate of the second capacitor are disposed in the same layer and are distributed at an interval along the column direction; the second plate of the first capacitor and the second plate of the second capacitor are disposed in the same layer and are distributed at an interval along the column direction; the first plate and the second plate of the second capacitor are overlapped with the active portion of the driving transistor.

[0015] In an embodiment of the present disclosure, the first plate of the first capacitor and the second plate of the second capacitor are disposed in the same layer and are distributed at an interval along the column direction; the second plate of the first capacitor and the first plate of the second capacitor are disposed in the same layer and are connected into an integrated structure; the first plate and the second plate of the second capacitor are overlapped with the active portion of the driving transistor.

[0016] In an embodiment of the present disclosure, an active portion of the first light emitting control transistor is overlapped with the first plate and the second plate of the first capacitor.

[0017] In an embodiment of the present disclosure, the first semiconductor portion includes a first semiconductor segment, a second semiconductor segment and a third semiconductor segment; the first semiconductor segment and the third semiconductor segment are extended along the column direction and are distributed at an interval along the row direction; the second semiconductor segment is connected to the first semiconductor segment and the third semiconductor segment; active portions of the writing transistor and the first reset transistor are located in the first semiconductor segment, and an active portion of the second reset transistor is located in the second semiconductor segment; the third semiconductor segment is connected to the first plate of the second capacitor.

[0018] In an embodiment of the present disclosure, a second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the first electrode of the second light emitting control transistor; the second semiconductor portion includes a fourth semiconductor segment and a fifth semiconductor segment, the fourth semiconductor segment is extended along the column direction and is located on a side of the third semiconductor segment away from the first semiconductor segment; active portions of the first light emitting control transistor, the driving transistor and the second light emitting control transistor are sequentially distributed in the fourth semiconductor segment along the column direction; the fifth semiconductor segment is connected to an area of the fourth semiconductor segment located between the active portion of the driving transistor and the active portion of the second light emitting control transistor; an active portion of the third reset transistor is located in the fifth semiconductor segment.

[0019] In an embodiment of the present disclosure, a second electrode of the third reset transistor is connected to the second electrode of the second light emitting control transistor and the light emitting device; the second semiconductor portion includes a fourth semiconductor segment and a fifth semiconductor segment, the fourth semiconductor segment is extended along the column direction and is located on a side of the third semiconductor segment away from the first semiconductor segment; active portions of the first light emitting control transistor, the driving transistor and the second light emitting control transistor are sequentially distributed in the fourth semiconductor segment along the column direction; the fifth semiconductor segment is connected to an area of the fourth semiconductor segment that is located on a side of the active portion of the second light emitting control transistor away from the active portion of the driving transistor; the active portion of the third reset transistor is located in the fifth semiconductor segment.

[0020] In an embodiment of the present disclosure, the display panel further includes a first light emitting control line, a scan line, a first reset control line, a first reset line, a second reset control line, a second light emitting control line, a third reset control line and a second reset line, which are sequentially distributed at intervals along the column direction; the first light emitting control line is extended along the row direction, is connected to a gate of the first light emitting control transistor, and is configured to transmit a first light emitting control signal; the first light emitting control line is overlapped with the first capacitor; the scan line is extended along the row direction, is connected to a gate of the writing transistor, and is configured to transmit a scan signal; the scan line is overlapped with the first capacitor; the first reset control line is extended along the row direction, is connected to the gate of the first reset transistor, and is configured to transmit a first reference control signal; the first reset control line is overlapped with the second capacitor; the first reset line is extended along the row direction, is connected to first electrodes of the first reset transistor and the second reset transistor, and is configured to transmit the reference signal; the first reset line is overlapped with the second capacitor; the second reset control line is extended along the row direction, is connected to a gate of the second reset transistor, and is configured to transmit a second reference control signal; the second light emitting control line is extended along the row direction, is connected to a gate of the second light emitting control transistor, and is configured to transmit a second light emitting control signal; the third reset control line is extended along the row direction, is connected to a gate of the third reset transistor, and is configured to transmit a reset control signal; the second reset line is extended along the row direction, is connected to a first electrode of the third reset transistor, and is configured to transmit the reset signal; an orthographic projection of the active portion of the driving transistor on the substrate is located between orthographic projections of the scan line and the first reset control line on the substrate; an orthographic projection of the active portion of the first reset transistor on the substrate is located between orthographic projections of the scan line and the first reset line on the substrate; an orthographic projection of the active portion of the second reset transistor on the substrate is located between orthographic projections of the first reset line and the second light emitting control line on the substrate; an orthographic projection of the active portion of the third reset transistor on the substrate is located between orthographic projections of the second light emitting control line and the second reset line on the substrate.

[0021] In an embodiment of the present disclosure, the display panel further includes: a plurality of first auxiliary power lines, extended along the row direction and distributed along the column direction; a first auxiliary power line is disposed between two adjacent rows of pixel circuits; the first auxiliary power line is connected to a first electrode of a first light emitting control transistor of a pixel circuit on a side of the first auxiliary power line; a plurality of first power lines, disposed on a side of the first auxiliary power lines away from the substrate, individual first power lines are extended along the column direction and are distributed at intervals along the row direction; a first power line is connected to individual first auxiliary power lines and is overlapped with a column of pixel circuits; the first power lines and the first auxiliary power lines are configured to transmit the first power signal; and a plurality of data lines, disposed on a side of the first auxiliary power lines away from the substrate, individual data lines are extended along the column direction and are distributed at intervals along the row direction; a data line is connected to first electrodes of writing transistors of a column of pixel circuits, and is configured to transmit the data signal.

[0022] In an embodiment of the present disclosure, the display panel further includes: second auxiliary power lines, extended along the row direction, distributed along the column direction, and configured to transmit a second power signal; orthographic projections of the second auxiliary power lines on the substrate are located between orthographic projections of the second light emitting control line and the third reset control line on the substrate.

[0023] In an embodiment of the present disclosure, the display panel further includes: a plurality of second power lines, a plurality of first auxiliary reset lines, and a plurality of second auxiliary reset lines, extended along the column direction and distributed along the row direction, and disposed on the side of the first auxiliary power lines away from the substrate; the second power lines are connected to the second auxiliary power line, the first auxiliary reset line is connected to the first reset line, and the second auxiliary reset line is connected to the second reset line; a first power line and a data line connected to pixel circuits in the same column are defined as a column line group, and the first power line and the data line of the column line group are provided with one of the second power line, the first auxiliary reset line and the second auxiliary reset line; and the light emitting device has a first electrode and a second electrode distributed in a direction away from the substrate, the first electrode is connected to a second electrode of the second light emitting control transistor, and the second electrode is connected to the second power line and the second auxiliary power line.

[0024] In an embodiment of the present disclosure, the semiconductor layer further includes a first auxiliary transfer portion and a second auxiliary transfer portion; the first auxiliary transfer portion is connected to an area of a first semiconductor portion of a pixel circuit that is located between the active portion of the first reset transistor and the active portion of the second reset transistor; the first auxiliary reset line is connected to the first auxiliary transfer portion; and the second auxiliary transfer portion is connected to an area of a second semiconductor portion of a pixel circuit that is located in an area of the active portion of the third reset transistor the is away from the active portion of the second light emitting control transistor; and the second auxiliary reset line is connected to the second auxiliary transfer portion.

[0025] In an embodiment of the present disclosure, the display panel further includes: a light shielding layer, disposed on a side of the substrate, and including the first plate of the first capacitor and the first plate of the second capacitor; a first gate layer, disposed on a side of the light shielding layer away from the substrate, and including the second plate of the first capacitor, the second plate of the second capacitor and the second auxiliary power line; the semiconductor layer is disposed on a side of the first gate layer away from the substrate; a second gate layer, disposed on a side of the semiconductor layer away from the substrate and overlapped with an active portion of each of the transistors; a first source-drain layer, disposed on a side of the second gate layer away from the substrate, and including the first auxiliary power line, the first light emitting control line, the scan line, the first reset control line, the first reset line, the second reset control line, the second light emitting control line, the third reset control line and the second reset line; and a second source-drain layer, disposed on a side of the first source-drain layer away from the substrate, and including the data line, the first power line, the second power line, the first auxiliary reset line and the second auxiliary reset line.

[0026] In an embodiment of the present disclosure, the second gate layer further includes: a first gate portion, overlapped with an active portion of the first light emitting control transistor to form a gate of the first light emitting control transistor, wherein the first gate portion is connected to the first light emitting control line; a second gate portion, overlapped with an active portion of the writing transistor to form a gate of the writing transistor, wherein the second gate portion is connected to the scan line; a third gate portion, overlapped with the active portion of the driving transistor and connected to the third gate portion to form the gate of the driving transistor; a fourth gate portion, overlapped with the active portion of the first reset transistor to form the gate of the first reset transistor, wherein the fourth gate portion is connected to the first reset control line; a fifth gate portion, overlapped with the active portion of the second reset transistor to form the gate of the second reset transistor, wherein the fifth gate portion is connected to the second reset control line; a sixth gate portion, overlapped with the active portion of the second light emitting control transistor to form the gate of the second light emitting control transistor, wherein the sixth gate portion is connected to the second light emitting control line; and a seventh gate portion, overlapped with the active portion of the third reset transistor to form the gate of the third reset transistor, wherein the seventh gate portion is connected to the third reset control line.

[0027] In an embodiment of the present disclosure, the first source-drain layer further includes: a first connection portion, located between the first light emitting control line and the scan line, and connected to the data line and an area of the first semiconductor portion located on a side of the active portion of the writing transistor away from the active portion of the first reset transistor; a second connection portion, located between the scan line and the first reset control line, and connected to the first plate of the first capacitor, the third gate portion, and an area of the first semiconductor portion located between the active portion of the writing transistor and the active portion of the first reset transistor; a third connection portion, located between the scan line and the first reset control line, and connected to the second plate of the first capacitor, the first plate of the second capacitor, and the second electrode of the second reset transistor; a fourth connection portion, located between the second connection portion and the first reset control line, and connected to the second plate of the second capacitor and an area of the second semiconductor portion located between the active portion of the driving transistor and the active portion of the second light emitting control transistor; and a fifth connection portion, located between the second light emitting control line and the third reset control line and connected to an area of the second semiconductor portion on a side of the active portion of the second light emitting control transistor away from the active portion of the driving transistor.

[0028] In an embodiment of the present disclosure, the first source-drain layer further includes: a sixth connection portion, overlapped with the third gate portion and the active portion of the driving transistor and connected to the first power line.

[0029] In an embodiment of the present disclosure, the first source-drain layer further includes: a seventh connection portion, located between the second light emitting control line and the third reset control line, and connected to the second auxiliary power line and the second power line; an eighth connection portion, located between the second light emitting control line and the third reset control line, and connected to the first auxiliary transfer portion and the first auxiliary reset line; and a ninth connection portion, located between the second light emitting control line and the third reset control line, and connected to the second auxiliary transfer portion and the second auxiliary reset line.

[0030] In an embodiment of the present disclosure, the first power line is overlapped with a second connection portion.

[0031] In an embodiment of the present disclosure, one of the second power line, the first auxiliary reset line and the second auxiliary reset line is overlapped with at least a partial area of the active portion of the writing transistor, the active portion of the first reset transistor, and the third connection portion.

[0032] In an embodiment of the present disclosure, a material of the semiconductor layer includes a metal oxide.

[0033] According to an aspect of the present disclosure, there is provided a display device, including any one of the display panels described above.

[0034] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and should not be construed as limiting of the disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description serve to explain principles of the present disclosure. Apparently, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings may be obtained based on these drawings without paying any creative effort. FIG. 1 is a top view of an embodiment of a display panel of the present disclosure. FIG. 2 is a partial cross-sectional schematic diagram of an embodiment of a display panel of the present disclosure. FIG. 3 is a circuit diagram of an embodiment of a first type of pixel circuit of the present disclosure. FIG. 4 is a timing diagram of a driving method for the pixel circuit in FIG. 3. FIG. 5 is a circuit diagram of a first embodiment of a second type of pixel circuit of the present disclosure. FIG. 6 is a timing diagram of a driving method for the pixel circuit in FIG. 5. FIG. 7 is a circuit diagram of a second embodiment of a second type of pixel circuit of the present disclosure. FIG. 8 is a timing diagram of a driving method for the pixel circuit in FIG. 7. FIG. 9 is a circuit diagram of an embodiment of a third type of pixel circuit of the present disclosure. FIG. 10 is a partial top view of a light shielding layer to a second source-drain layer of a single pixel circuit in an embodiment of a first display panel of the present disclosure. FIG. 11 is a partial top view of a light shielding layer to a first source-drain layer of a single pixel circuit in an embodiment of a first display panel of the present disclosure. FIG. 12 is a partial top view of a light shielding layer to a second gate layer of a single pixel circuit in an embodiment of a first display panel of the present disclosure. FIG. 13 is a partial top view of a light shielding layer to a semiconductor layer of a single pixel circuit in an embodiment of a first display panel of the present disclosure. FIG. 14 is a partial top view of a light shielding layer to a first gate layer of a single pixel circuit in an embodiment of a first display panel of the present disclosure. FIGS. 15 to 20 are each a partial top view of each layer from a light shielding layer to a second source-drain layer of a single pixel circuit in an embodiment of a first display panel of the present disclosure. FIG. 21 is a partial top view of a light shielding layer to a second source-drain layer of a single pixel circuit in another embodiment of a first display panel of the present disclosure. FIG. 22 is a partial top view of a light shielding layer to a first source-drain layer of a single pixel circuit in another embodiment of a first display panel of the present disclosure. FIG. 23 is a partial top view of a light shielding layer to a second gate layer of a single pixel circuit in another embodiment of a first display panel of the present disclosure. FIG. 24 is a partial top view of a light shielding layer to a semiconductor layer of a single pixel circuit in another embodiment of a first display panel of the present disclosure. FIG. 25 is a partial top view of a semiconductor layer of a single pixel circuit in another embodiment of a first display panel of the present disclosure. FIG. 26 is a partial top view of a light shielding layer to a first electrode of a plurality of pixel circuits in an embodiment of a first display panel of the present disclosure. FIG. 27 is a partial top view of a light shielding layer to a second source-drain layer of a plurality of pixel circuits in an embodiment of a first display panel of the present disclosure.. FIG. 28 is a partial top view of a light shielding layer to a first source-drain layer of a plurality of pixel circuits in an embodiment of a first display panel of the present disclosure. FIG. 29 is a partial top view of a light shielding layer to a second gate layer of a plurality of pixel circuits in an embodiment of a first display panel of the present disclosure. FIG. 30 is a partial top view of a light shielding layer to a semiconductor layer of a plurality of pixel circuits in an embodiment of a first display panel of the present disclosure. FIG. 31 is a partial top view of a light shielding layer to a first gate layer of a plurality of pixel circuits in an embodiment of a first display panel of the present disclosure. FIGS. 32-35 are each a partial top view of some film layers from a light shielding layer to a second source-drain layer of a plurality of pixel circuits in an embodiment of a first display panel of the present disclosure. FIG. 36 is a partial top view of a light shielding layer to a second source-drain layer of a single pixel circuit in an embodiment of a second display panel of the present disclosure. FIG. 37 is a partial top view of a light shielding layer to a first source-drain layer of a single pixel circuit in an embodiment of a second display panel of the present disclosure. FIG. 38 is a partial top view of a light shielding layer to a second gate layer of a single pixel circuit in an embodiment of a second display panel of the present disclosure. FIG. 39 is a partial top view of a light shielding layer to a semiconductor layer of a single pixel circuit in an embodiment of a second display panel of the present disclosure. FIG. 40 is a partial top view of a light shielding layer to a first gate layer of a single pixel circuit in an embodiment of a second display panel of the present disclosure. FIG. 41 is a partial top view of a first gate layer of a single pixel circuit in an embodiment of a second display panel of the present disclosure. FIG. 42 is a partial top view of a semiconductor layer of a single pixel circuit in an embodiment of a second display panel of the present disclosure. DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more complete and comprehensive so as to convey the idea of the example embodiments to those skilled in this art. The same reference numerals in the drawings denote the same or similar structures, and the repeated description thereof will be omitted. In addition, the drawings are merely schematic representations of the present disclosure and are not necessarily drawn to scale.

[0037] The terms "one", "a", "the", "said", and "at least one" are used to indicate that there are one or more elements / components or the like; the terms "include" and "have" are used to indicate an open meaning of including and means that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as markers, and do not limit the number of objects.

[0038] A row column X and a column direction Y herein are two intersecting directions. In the drawings of the present disclosure, the row direction X may be horizontal and the column direction Y may be vertical, which are perpendicular to each other, but it is not limited thereto. The row direction X and the column direction Y may also be non-perpendicular directions. In addition, those skilled in the art will appreciate that, as a display panel rotates, actual orientations of the row direction X and the column direction Y may change, but relative positions of the row direction X and the column direction Y remain unchanged.

[0039] Feature A and feature B "overlapping" herein means that an orthographic projection of feature A on a plane is at least partially overlapped with an orthographic projection of feature B on the same plane, and the plane may be a surface of a substrate, or another plane parallel to the substrate.

[0040] A and B "being disposed in the same layer" herein means that A and B belong to different continuous or disconnected areas in the same film layer, and the film layer may be a single-layer structure; or, the film layer may be a multi-layer structure including multiple sub-layers. In this case, A and B may be located in the same sub-layer or different sub-layers of the multi-layer structure.

[0041] As shown in FIG. 1, the present disclosure provides a display panel, which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA. Alternatively, the peripheral area WA may also be a discontinuous area surrounding the display area AA.

[0042] As shown in FIG. 2, the display panel may include a driving backplane BP and a plurality of light emitting devices LD disposed a side of the driving backplane BP. The light emitting devices LD may be distributed in an array along the row direction X and the column direction Y, and through a driving circuit in the driving backplane BP, the light emitting devices LD may be driven to emit light so as to display images.

[0043] As shown in FIG. 2, the light emitting devices LD may be located in the display area AA and each may be an OLED (organic light emitting diode) of an organic light emitting material, or may be a LED (light emitting diode) of an inorganic light emitting material, such as Micro LED and Mini LED, or may be a device such as QLED (quantum dot diode). The specific structure of the light emitting device LD is not specifically limited here, as long as it may display images.

[0044] As shown in FIG. 2, the light emitting device LD being OLED is taken as an example, and may include a first electrode ANO, a light emitting layer EL, and a second electrode CAT stacked sequentially along a direction away from the driving backplane BP. By applying electrical signals to the first electrode ANO and the second electrode CAT, the light emitting layer EL may be excited to emit light. The specific principle of light emission will not be described in detail here.

[0045] The driving circuit may include a pixel circuit located in the display area AA and a peripheral circuit located in the peripheral area WA. The pixel circuits may be distributed in an array along the row direction X and the column direction Y. A pixel circuit may be connected to the first electrode ANO of a light emitting device LD. A row of pixel circuits may be connected to the first electrode ANO of each light emitting device LD in a row. Alternatively, the same pixel circuit may also be connected to first electrodes ANO of a plurality of light emitting devices LD. In addition, there may also be some pixel circuits located in the peripheral area WA.

[0046] The peripheral circuit may be connected to the light emitting device LD through the pixel circuit, and applies a first power signal VDD to the first electrode ANO of the light emitting device LD through the pixel circuit. On the other hand, the peripheral circuit may also be connected to the second electrode CAT of the light emitting device LD, and a second power signal VSS may be applied to the second electrode CAT. Current passing through the light emitting device LD may be controlled by the pixel circuit, and hence brightness of the light emitting device LD may be controlled. The peripheral circuit can include at least one gate driving circuit and a light emitting control circuit, the gate driving circuit and the light emitting control circuit each include a plurality of cascaded shift register units, and a signal output by one shift register unit may control at least one row of pixel circuits.

[0047] The pixel circuit is exemplarily described below.Firs type of pixel circuit

[0048] As shown in FIG. 3, the pixel circuit may include a driving transistor T3, a data control circuit CU, an energy storage circuit RU, a writing circuit DU and a first light emitting control circuit EU1.

[0049] A gate of the driving transistor T3 is connected to a first electrode of the driving transistor T3 through the data control circuit CU and the energy storage circuit RU in sequence, the first electrode of the driving transistor T3 is configured to be connected to a light emitting device LD, and a second electrode of the driving transistor T3 is connected to the first light emitting control circuit EU1. The first light emitting control circuit EU1 is configured to receive the first power signal VDD.

[0050] The writing circuit DU is connected to the gate of the driving transistor T3 through the data control circuit CU, and the writing circuit DU is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU.

[0051] The writing circuit DU is configured to write a data signal Data to the energy storage circuit RU, and the energy storage circuit RU is configured to store the data signal Data and a voltage of the first electrode of the driving transistor T3.

[0052] The data signal Data and the voltage of the first electrode of the driving transistor T3 can be stored respectively by the energy storage circuit RU, so as to stabilize a voltage difference between the first electrode and the gate of the driving transistor T3. The on and off between the gate and the first electrode of the driving transistor T3 can be controlled by the data control circuit CU, so as to avoid the data signal Data being directly written to the gate of the driving transistor T3 and interfering with the voltage of the first electrode of the driving transistor T3, and to prevent the actual brightness of the light emitting device LD from being greatly different from the designed brightness of the light emitting device LD due to different interference degrees of different data signals Data, thereby improving the picture quality.

[0053] The energy storage circuit RU is configured to store the data signal Data and a threshold voltage of the driving transistor T3, respectively, and can avoid mutual interference between the data signal Data and the threshold voltage. The writing circuit DU can control the writing and turning off of the data signal Data. The data control circuit CU can turn on and off the gate of the driving transistor T3 and the writing circuit DU, and can also turn on and off the gate of the driving transistor T3 and the energy storage circuit RU. The energy storage circuit RU can be implemented by multiple capacitors, and the writing circuit DU and the data control circuit CU can be implemented by transistors.

[0054] For example, as shown in FIG. 3, in some embodiments of the present disclosure, the energy storage circuit RU may include a first capacitor C1 and a second capacitor C2 connected in series, the data control circuit CU includes a data control transistor T6, and the writing circuit DU may include a writing transistor T4.

[0055] A first electrode of the writing transistor T4 is configured to input the data signal Data, a second electrode of the writing transistor T4 is connected to a first electrode of the data control transistor T6 and a first plate C11 of the first capacitor C1, which can be connected at a node N5. A second electrode of the data control transistor T6 is connected to the gate of the driving transistor T3, which can be connected at a node N1. A second plate C12 of the first capacitor C1 is connected to a first plate C21 of the second capacitor C2, which can be connected at a node N4. A second plate C22 of the second capacitor C2 is connected to the first electrode of the driving transistor T3, which can be connected at a node N3.

[0056] A gate of the writing transistor T4 can receive a scan signal Gate, and the writing transistor T4 can be turned on or off under the control of the scan signal Gate. A gate of the data control transistor T6 can receive a data control signal DC, and the data control transistor T6 can be turned on or off under the control of the data control signal DC.

[0057] In addition, the first light emitting control circuit EU1 can control the connection and disconnection of the first power signal VDD, which can also be achieved by a transistor.

[0058] For example, as shown in FIG. 3, in some embodiments of the present disclosure, the first light emitting control circuit EU1 may include a first light emitting control transistor T5, a first electrode of which is configured to receive the first power signal VDD, and a second electrode of which may be connected to the second electrode of the driving transistor T3. The second electrode of the first light emitting control transistor T5 may be connected to the second electrode of the driving transistor T3 at a node N2.

[0059] A gate of the first light emitting control transistor T5 may receive a light emitting control signal EM, and the first light emitting control transistor T5 may be turned on or off under the control of the light emitting control signal EM.

[0060] In order to eliminate the influence of a signal of the previous frame image, before a signal input of the current frame is displayed, the gate and the first electrode of the driving transistor T3 may be reset, and the energy storage circuit RU may also be reset. As shown in FIG. 3, in some embodiments of the present disclosure, the pixel circuit may further include a first reset transistor T1 and a second reset transistor T2.

[0061] A first electrode of the first reset transistor T1 is configured to receive a reference signal Vref, and a second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3 and the second electrode of the data control transistor T6. As shown in FIG. 3, the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3 and the second electrode of the data control transistor T6 at a node N1.

[0062] A first electrode of the second reset transistor T2 is configured to receive the reference signal Vref, and a second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2. As shown in FIG. 2, the second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 at a node N4.

[0063] Gates of the first reset transistor T1 and the second reset transistor T2 can receive a reference control signal RE1, and the first reset transistor T1 and the second reset transistor T2 can be turned on or off under the control of the reference control signal RE1. That is, the first reset transistor T1 and the second reset transistor T2 can be turned on or off synchronously, both of which can be controlled by the same signal. Alternatively, the gates of the first reset transistor T1 and the second reset transistor T2 can receive the reference control signal RE1 through the same or different signal lines.

[0064] The reference signal Vref can be input to nodes N1 and N4 through the first reset transistor T1 and the second reset transistor T2 to eliminate the influence of the signal when the previous frame image is displayed.

[0065] The reference control signal RE1 received by the gates of the first reset transistor T1 and the second reset transistor T2 may be provided by a shift register of a gate driving circuit. In some embodiments, the gate of the first reset transistor T1 may receive a first reference control signal, and the gate of the second reset transistor T2 may receive a second reference control signal. The first reference control signal of the gate of the first reset transistor T1 of the n+1th row of pixel circuits and the second reference control signal of the gate of the second reset transistor T2 of the nth row of pixel circuits may be the same signal, where n is a positive integer. Thus, the first reset transistor T1 of the n+1th row of pixel circuits and the second reset transistor T2 of the nth row of pixel circuits are simultaneously controlled by the same shift register, that is, one shift register is implemented to simultaneously control multiple rows of pixel circuits, which is conducive to reducing the number of shift registers and simplifying the structure.

[0066] Further, as shown in FIG. 3, the pixel circuit further includes a third reset transistor T7, a first electrode of which is configured to receive a reset signal Vinit, and a second electrode of which is connected to the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2. As shown in FIG. 3, the second electrode of the third reset transistor T7 is connected to the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2 at a node N3. A gate of the third reset transistor T7 can receive a reset control signal RE2, and the third reset transistor T7 can be turned on or off under the control of the reset control signal RE2. The reset signal Vinit can be input to the node N3 through the third reset transistor T7, and the first electrode of the driving transistor T3, the second plate C22 of the second capacitor C2, and a first electrode ANO of the light emitting device LD are reset to eliminate the influence of the signal of the previous frame image.

[0067] At least one of the transistors in the pixel circuit may be a metal oxide transistor, that is, a material of an active portion of the transistor may be a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the material of the active portion of the transistor may be an oxide of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti); or a mixture of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and an oxide thereof. The oxide semiconductor may include a metal oxide such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc gallium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), and zinc tin oxide (ZTO) within the spirit and scope of the disclosure. Accordingly, the transistor may be an N-type transistor. As shown in FIG. 3, if each transistor may be the N-type transistor, the first electrode of each transistor is a source, the second electrode is a drain, and the transistor is turned on when a gate of the transistor receives a high level and is turned off when the gate receives a low level. For example, as shown in FIG. 3, the driving transistor T3, the data control transistor T6, the writing transistor T4, the first reset transistor T1, the second reset transistor T2, the third reset transistor T7 and the first light emitting control transistor T5 are all metal oxide transistors, that is, the transistors of the pixel circuit are all metal oxide transistors, so as to reduce the leakage current. Alternatively, only some of the transistors may be metal oxide transistors.

[0068] As shown in FIG. 4, a driving method for the pixel circuit is exemplarily described below by taking the first type of pixel circuit in FIG. 3 (each transistor is the N-type metal oxide transistor) as an example.

[0069] In a reset stage t1, the reference control signal RE1 received by the gates of the first reset transistor T1 and the second reset transistor T2 is at the high level, and the first reset transistor T1 and the second reset transistor T2 are turned on. The reference signal Vref resets the node N1 and the node N4, and a voltage of the reference signal Vref can be 2.5V. The reset control signal RE2 received by the gate of the third reset transistor T7 is at the high level, the third reset transistor T7 is turned on, the reset signal Vinit resets the node N3, and a voltage of the reset signal Vinit can be 1.5V. In this case, the gate and the first electrode of the driving transistor T3 have a voltage difference and the driving transistor T3 is turned on.

[0070] In addition, the light control signal EM received by the gate of the first light emitting control transistor T5 is at the low level, so that the light emitting control transistor T5 is turned off. The scan signal Gate received by the gate of the writing transistor T4 is at the low level, so that the writing transistor T4 is turned off. The data control signal DC received by the gate of the data control transistor T6 is at the low level, so that the data control transistor T6 is turned off.

[0071] The reset of the node N1 and the node N4 and the reset of the node N3 can be performed in stages. For example, the reset control signal RE2 first changes from the low level to the high level, and then the reference control signal RE1 changes from the low level to the high level. Alternatively, the reset of the node N1 and the node N4 and the reset of the node N3 can also be performed simultaneously.

[0072] In a compensation stage t2, the light control signal EM received by the gate of the light emitting control transistor T5 is at the high level, the first light emitting control transistor T5 is turned on, a voltage of the node N2 is a voltage of the first power signal VDD, and a voltage of the node N3 gradually increases due to the turning on of the driving transistor T3. The voltage of the first power signal VDD can be 11.5V.

[0073] In addition, the reference control signal RE1 is at the high level, and the first reset transistor T1 and the second reset transistor T2 are turned on. The reset control signal RE2 is at the low level, and the third reset transistor T7 is turned off. The data control signal DC is at the low level, and the data control transistor T6 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off.

[0074] In a writing stage t3, the scan signal Gate is at the high level, the writing transistor T4 is turned on, and the data signal Data is written to the node N5 through the writing transistor T4, that is, the data signal Data is stored in the first capacitor C1. The data control signal DC is at the low level, and the data control transistor T6 is turned off.

[0075] In addition, the light emitting control signal EM can continue to be at the high level, the first light emitting control transistor T5 is turned on, and the voltage of the node N3 gradually increases until it increases to Vref-Vth, so that the voltage difference between the gate and the first electrode of the driving transistor T3 is equal to the threshold voltage, that is, the gate-source voltage difference Vgs is equal to Vth. In this case, the driving transistor T3 is turned off, and Vth is the threshold voltage of the driving transistor T3. Thus, the threshold voltage Vth is written to the node N3, that is, stored in the second capacitor C2. That is, the writing of the threshold voltage starts in the compensation stage t2, and the writing of the threshold voltage is completed in the writing stage t3. The writing of the threshold voltage continues from the compensation stage t2 to the writing stage t3, that is, the writing of the threshold voltage and the writing of the data signal Data are independent of each other. The light emitting control signal EM can continue until the driving transistor T3 is turned off, that is, until the writing of the threshold voltage is completed. For example, the light emitting control signal EM can continue until the writing transistor T4 is turned off, that is, until the writing of the data signal Data is completed.

[0076] In addition, the reference control signal RE1 is at the low level, the first reset transistor T1 and the second reset transistor T2 are turned off. The reset control signal RE2 is at the low level, and the third reset transistor T7 is turned off. The data control signal DC is at the low level, and the data control transistor T6 is turned off.

[0077] In a light emitting stage t4, the light emitting control signal EM is at the high level, and the first light emitting control transistor T5 is turned on. The data control signal DC is at the high level, and the data control transistor T6 is turned on. The reference control signal RE1 is at the low level, and the first reset transistor T1 and the second reset transistor T2 are turned off. The reset control signal RE2 is at the low level, and the third reset transistor T7 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off. Under the action of the first capacitor C1, the data signal Data starts to be written to the node N1, and at this time, the voltage of the node N1 is the voltage of the gate of the driving transistor T3, that is, Vg=Vdata+Vld+VSS-(Vref-Vth), the voltage of the node N3 is the voltage of the first electrode of the driving transistor T3, that is, Vs =Vld+VSS, and then the gate-source voltage difference Vgs of the driving transistor T3 is Vdata-Vref+Vth. Vld is a voltage of the light emitting device LD, that is, a voltage of a capacitor Co of the light emitting device LD itself, VSS is a voltage of a second power signal VSS input to a second electrode CAT of the light emitting device LD, and Vdata is a voltage of the data signal Data.

[0078] A current output by the driving transistor T3 satisfies the following formula: I = μWCox / 2 L Vgs − Vth 2

[0079] I is an output current of the driving transistor T3; µ is the carrier mobility; Cox is the gate capacitance per unit area, W is a channel width of the driving transistor T3, and L is a channel length of the driving transistor T3.

[0080] According to the above formula for the output current of the driving transistor T3, the gate-source voltage difference Vgs of the driving transistor T3 in the above pixel circuit is substituted into the above formula to obtain: the output current I of the driving transistor T3 is (µWCox / 2L) (Vdata-Vref) 2< . It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on the output current of the driving transistor T3, and the output current can be controlled by controlling the voltage Vdata of the data signal Data, so as to control the brightness of the light emitting device LD.

[0081] According to the driving method for the pixel circuit, the data control circuit CU is disposed between the gate and the first electrode of the driving transistor T3, and the writing of the data signal Data can be divided into two stages. The first stage is the writing stage t3, during which the data signal Data is stored respectively by the energy storage circuit RU, and the data control circuit CU is turned off, so that the data signal Data is not directly written to the gate of the driving transistor T3. The second stage is the light emitting stage t4, during which the data control circuit CU is turned on, and the data signal Data is applied to the gate of the driving transistor T3 by the energy storage circuit RU. In the compensation stage t2, the threshold voltage of the driving transistor T3 can also be written to the energy storage circuit RU (independent of the storage of the data signal Data).

[0082] The energy storage circuit RU will not interfere with the storage of the threshold voltage when storing the data signal Data. In the light emitting stage t4, the energy storage circuit RU can ensure the stability of the voltage difference between the data signal Data and the first electrode of the driving transistor T3, and can prevent the actual brightness of the light emitting device LD from being greatly different from the designed brightness due to different interference levels of different data signals Data, thereby improving the picture quality.Second type of pixel circuit

[0083] As shown in FIG. 5 and FIG. 7, the pixel circuit may include a driving transistor T3, an energy storage circuit RU, a writing circuit DU, a first light emitting control circuit EU1 and a second light emitting control circuit EU2.

[0084] A gate of the driving transistor T3 is connected to a first electrode of the driving transistor T3 through the energy storage circuit RU, the first electrode of the driving transistor T3 is connected to a light emitting device LD, and a second electrode of the driving transistor T3 is connected to the first light emitting control circuit EU1. The first light emitting control circuit EU1 is configured to receive the first power signal VDD.

[0085] The writing circuit DU is connected to the gate of the driving transistor T3, and the writing circuit DU is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU. The first electrode of the driving transistor is connected to the light emitting device LD through the second light emitting control circuit EU2.

[0086] The writing circuit DU is configured to write a data signal Data to the energy storage circuit RU, and the energy storage circuit RU is configured to store the data signal Data and a voltage of the first electrode of the driving transistor T3.

[0087] The energy storage circuit RU can store the data signal Data and the voltage of the first electrode of the driving transistor T3, respectively, so as to stabilize the voltage difference between the first electrode and the gate of the driving transistor T3, which is beneficial to ensure that the light emitting device LD emits light stably, thereby improving the picture quality.

[0088] As shown in FIG. 5 and FIG. 7, in some embodiments of the present disclosure, the energy storage circuit RU may include a first capacitor C1 and a second capacitor C2 connected in series, the writing circuit DU may include a writing transistor T4, the first light emitting control circuit EU1 includes a first light emitting control transistor T5, and the second light emitting control circuit EU2 includes a second light emitting control transistor T6.

[0089] A first electrode of the writing transistor T4 is configured to input a data signal Data, and a second electrode of the writing transistor T4 is connected to the gate of the driving transistor T3 and the first plate C11 of the first capacitor C1, which can be connected at the node N5. A second plate C12 of the first capacitor C1 is connected to a first plate C21 of the second capacitor C2, which can be connected at the node N4. A second plate C22 of the second capacitor C2 is connected to the first electrode of the driving transistor T3, which can be connected to the node N3. A first electrode of the first light emitting control transistor T5 is configured to receive the first power signal VDD, and a second electrode of the first light emitting control transistor T5 can be connected to the second electrode of the driving transistor T3, and can be connected to the second electrode of the driving transistor T3 at the node N2. A first electrode of the second light emitting control transistor T6 is connected to the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2, which can be connected to the node N3, and a second electrode of the second light emitting control transistor T6 can be connected to a first electrode ANO of the light emitting device LD.

[0090] A gate of the writing transistor T4 can receive a scan signal Gate, and the writing transistor T4 can be turned on or off under the control of the scan signal Gate. A gate of the first light emitting control transistor T5 can receive a first light emitting control signal EM1, and the first light emitting control transistor T5 can be turned on or off under the control of the first light emitting control signal EM1. A gate of the second light emitting control transistor T6 can receive the second light emitting control signal EM2, and the second light emitting control transistor T6 can be turned on or off under the control of the second light emitting control signal EM2.

[0091] In order to eliminate the influence of the signal of the previous frame image, before the signal input of the current frame is displayed, the gate and the first electrode of the driving transistor T3 may be reset, and the energy storage circuit RU may also be reset. As shown in FIG. 5 and FIG. 7, in some embodiments of the present disclosure, the pixel circuit may further include a first reset transistor T1 and a second reset transistor T2.

[0092] A first electrode of the first reset transistor T1 is configured to receive a reference signal Vref, and a second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3. As shown in FIG. 5 and FIG. 7, the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3 at the node N1.

[0093] A first electrode of the second reset transistor T2 is configured to receive the reference signal Vref, and a second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2. As shown in FIGS. 5 and 7, the second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 at the node N4.

[0094] A gate of the first reset transistor T1 can receive a first reference control signal RE1, and the first reset transistor T1 can be turned on or off under the control of the first reference control signal RE1. A gate of the second reset transistor T2 can receive a second reference control signal RE2, and the second reset transistor T2 can be turned on or off under the control of the second reference control signal RE2. The first reference control signal RE1 and the second reference control signal RE2 can be synchronous signals, so that the first reset transistor T1 and the second reset transistor T2 can be turned on or off synchronously. Alternatively, the first reference control signal RE1 and the second reference control signal RE2 can also be asynchronous.

[0095] The reference signal Vref can be input to nodes N1 and N4 through the first reset transistor T1 and the second reset transistor T2 to eliminate the influence of the signal when the previous frame image is displayed.

[0096] In addition, in some embodiments, the first reference control signal RE1 of the gate of the first reset transistor T1 of the n+1th row of pixel circuits and the second reference control signal RE2 of the gate of the second reset transistor T2 of the nth row of pixel circuits may be the same signal, where n is a positive integer. Thus, the first reset transistor T1 of the n+1th row of pixel circuits and the second reset transistor T2 of the nth row of pixel circuits may be controlled simultaneously by the same shift register, that is, it can be realized that one shift register controls multiple rows of pixel circuits simultaneously, which is beneficial to reducing the number of shift registers and simplifying the structure.

[0097] As shown in FIG. 5 and FIG. 7, the pixel circuit further includes a third reset transistor T7, a first electrode of which is configured to receive a reset signal Vinit, and a second electrode of which is configured to reset the node N3.

[0098] For example, in a first embodiment of the second type of pixel circuit, as shown in FIG. 5, a second electrode of the third reset transistor T7 can be connected to the first electrode of the driving transistor T3, the second plate C22 of the second capacitor C2, and the first electrode of the second light emitting control transistor T6, which can be connected at the node N3. A gate of the third reset transistor T7 can receive a reset control signal RE3, and the third reset transistor T7 can be turned on or off under the control of the reset control signal RE3. The reset signal Vinit can be input to the node N3 through the third reset transistor T7 to reset the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2, thereby eliminating the influence of the signal of the previous frame image.

[0099] In a second embodiment of the second type of pixel circuit, as shown in FIG. 7, a second electrode of the third reset transistor T7 can be connected to the second electrode of the second light emitting control transistor T6 and the first electrode ANO of the light emitting device LD, which can be connected at the node N6. The gate of the third reset transistor T7 can receive the reset control signal RE3 and the third reset transistor T7 can be turned on or off under the control of the reset control signal RE3. The reset signal Vinit can be input to the node N6 through the third reset transistor T7 to reset the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2, thereby eliminating the influence of the signal of the previous frame image.

[0100] At least one of the transistors in the pixel circuit may be a metal oxide transistor, that is, a material of an active portion of the transistor may be a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the material of the active portion of the transistor may be an oxide of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti); or a mixture of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and an oxide thereof. The oxide semiconductor may include a metal oxide such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc gallium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), and zinc tin oxide (ZTO) within the spirit and scope of the disclosure. Accordingly, the transistor may be an N-type transistor. As shown in FIG. 5 and FIG. 7, if each transistor may be the N-type transistor, the first electrode of each transistor is a source, the second electrode is a drain, and the transistor is turned on when a gate of the transistor receives a high level and is turned off when the gate receives a low level. For example, as shown in FIG. 5 and FIG. 7, the driving transistor T3, the writing transistor T4, the first reset transistor T1, the second reset transistor T2, the third reset transistor T7, the first light emitting control transistor T5 and the second light emitting control transistor T6 are all metal oxide transistors, that is, the transistors of the pixel circuit are all metal oxide transistors, so as to reduce the leakage current. Alternatively, only some of the transistors can also be metal oxide transistors.

[0101] The driving method for the pixel circuit is described below based on the structure of the pixel circuit in the first embodiment of the second type of pixel circuit.

[0102] As shown in FIGS. 5 and 6, the driving method may include the following contents.

[0103] In a compensation stage t2, the first light emitting control circuit EU1 is turned on and the second light emitting control circuit EU2 is turned off to write the threshold voltage of the driving transistor T3 to the energy storage circuit RU.

[0104] Different voltages can be input to the gate and the first electrode of the driving transistor T3 to turn on the driving transistor T3, and the second light emitting control circuit EU2 is turned off. When the first light emitting control circuit EU1 is turned on, the voltage of the first electrode of the driving transistor T3 gradually increases, and the threshold voltage of the driving transistor T3 starts to be written to the energy storage circuit RU. The compensation stage is to start writing the threshold voltage to the energy storage circuit RU, but it is not limited to complete the writing of the threshold voltage.

[0105] In a writing stage t3, the writing circuit DU and the first light emitting control circuit EU1 are turned on, the second light emitting control circuit EU2 is turned off, the data signal Data is written to the energy storage circuit RU through the writing circuit DU, and the threshold voltage of the driving transistor T3 is written to the energy storage circuit RU.

[0106] The data signal Data is written to the energy storage circuit RU and the gate of the driving transistor T3 through the writing circuit DU. In addition, when the voltage of the first electrode of the driving transistor T3 reaches a difference between the gate voltage and the threshold voltage of the driving transistor T3, the driving transistor T3 is turned off, so that the threshold voltage of the driving transistor T3 can be written to the energy storage circuit RU. In other words, the writing of the threshold voltage and the writing of the data signal Data are independent of each other.

[0107] In a light emitting stage t4, the first light emitting control circuit EU1 and the second light emitting control circuit EU2 are turned on, the writing circuit DU is turned off, and the voltage difference between the gate and the first electrode of the driving transistor T3 is controlled by the energy storage circuit RU to make the light emitting device LD emit light.

[0108] Further, as shown in FIG. 5 and FIG. 6, in some embodiments of the present disclosure, the driving method may further include the following contents.

[0109] In a reset stage t1, the first reset transistor T1, the second reset transistor T2 and the third reset transistor T7 are turned on, and the writing circuit DU, the first light emitting control circuit EU1 and the second light emitting control circuit EU2 are turned off. The gate of the driving transistor T3 is reset and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are reset by the reference signal Vref, and the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2 are reset by the reset signal Vinit. In addition, the driving transistor T3 can be turned on by the voltage difference between the reset signal Vinit and the reference signal Vref.

[0110] According to the driving method for the pixel circuit, the data signal Data and the threshold voltage of the driving transistor T3 can be stored respectively by the energy storage circuit RU, and the energy storage circuit RU will not interfere with the storage of the threshold voltage when storing the data signal Data, so as to ensure that the voltage difference between the data signal Data and the first electrode of the driving transistor T3 remains stable during the light emitting stage, and prevent the actual brightness of the light emitting device LD from being greatly different from the designed brightness due to the different interference levels of different data signals Data, thereby improving the picture quality. In addition, the gate of the driving transistor T3 and the writing circuit DU can be directly connected without being connected through the data control circuit CU, so as to prevent the coupling effect of the data control circuit CU when it is turned on / off from affecting the gate voltage of the driving transistor T3.

[0111] As shown in FIG. 6, the driving method for the pixel circuit is exemplarily described below by taking the first embodiment of the second type of pixel circuit as an example.

[0112] Each transistor in the pixel circuit is an N-type metal oxide transistor.

[0113] In the reset stage t1, the first reference control signal RE1 and the second reference control signal RE2 are at the high level, the first reset transistor T1 and the second reset transistor T2 are turned on. The reference signal Vref resets the node N1 and the node N4, and the voltage of the reference signal Vref can be 2.5V. The reset control signal RE3 is at the high level, the third reset transistor T7 is turned on, the reset signal Vinit resets the node N3, and the voltage of the reset signal Vinit can be 1.5V. In this case, the gate and the first electrode of the driving transistor T3 have a voltage difference and the driving transistor T3 is turned on.

[0114] In addition, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at the low level, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off.

[0115] The reset of the node N1, the node N3 and the node N4 can be performed sequentially. For example, the first reference control signal RE1 and the second reference control signal RE2 first change from the low level to the high level, and the reset control signal RE3 then changes from the low level to the high level, so that the first reset transistor T1 and the second reset transistor T2 are turned on first, and the third reset transistor T7 is turned on later.

[0116] In the compensation stage t2, the first light emitting control signal EM1 is at the high level, the first light emitting control transistor T5 is turned on, and the voltage of the node N2 is the voltage of the first power signal VDD. Since the driving transistor T3 is turned on, the voltage of the node N3 gradually increases until it increases to Vref-Vth, so that the voltage difference between the gate and the first electrode of the driving transistor T3 is equal to the threshold voltage, that is, the gate-source voltage difference Vgs is equal to Vth, in this case, the driving transistor T3 is turned off; Vth is the threshold voltage of the driving transistor T3. Thus, the threshold voltage Vth is written to the node N3, that is, stored in the second capacitor C2, and the first light emitting control signal EM1 can continue until the driving transistor T3 is turned off, that is, until the writing of the threshold voltage is completed. The voltage of the first power signal VDD can be 11.5V.

[0117] In addition, the second light emitting control signal EM2 is at the low level to make the second light emitting control transistor T6 turn off. The first reference control signal RE1 and the second reference control signal RE2 are at the high level, and the first reset transistor T1 and the second reset transistor T2 are turned on. The reset control signal RE3 is at the low level, and the third reset transistor T7 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off.

[0118] In the writing stage t3, the scan signal Gate is at the high level, the writing transistor T4 is turned on. The first reference control signal RE1 is at the low level, and the first reset transistor T1 is turned off. The data signal Data is written to the node N5 through the writing transistor T4, that is, stored in the first capacitor C1. The second reference control signal RE2 continues to maintain the high level, so that the second reset transistor T2 continues to be turned on, which can be maintained until the writing transistor T4 is turned off. The voltage of the node N4 is stabilized to avoid the data signal Data stored in the first capacitor C1 and the threshold voltage stored in the second capacitor C2 from interfering with each other. In addition, the reset control signal RE3 is at the low level, and the third reset transistor T7 is turned off. The low level of the second light emitting control signal EM2 can continue until the writing transistor T4 is turned off, that is, until the writing of the data signal Data is completed.

[0119] In the light emitting stage t4, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at the high level, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on. The first reference control signal RE1 and the second reference control signal RE2 are at the low level, and the first reset transistor T1 and the second reset transistor T2 are turned off. The reset control signal RE3 is at the low level, and the third reset transistor T7 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off. Under the action of the first capacitor C1, the data signal Data starts to be written to the node N1, and at this time, the voltage of the node N1 is the voltage of the gate of the driving transistor T3, that is, Vg=Vdata+Vld+VSS-(Vref-Vth), the voltage of the node N3 is the voltage of the first electrode of the driving transistor T3, that is, Vs =Vld+VSS, and then the gate-source voltage difference Vgs of the driving transistor T3 is Vdata-Vref+Vth. Vld is the voltage of the light emitting device LD, VSS is the voltage of the second power signal VSS input to the second electrode CAT of the light emitting device LD, and Vdata is the voltage of the data signal Data.

[0120] The output current I of the pixel circuit is (µWCox / 2L)(Vgs-Vth) 2< ; I is also the output current of the driving transistor T3; µ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor T3, and L is the channel length of the driving transistor T3.

[0121] According to the above formula for the output current of the driving transistor T3, the gate-source voltage difference Vgs of the driving transistor T3 in the above pixel circuit is substituted into the above formula to obtain: the output current I of the driving transistor T3 is (µWCox / 2L) (Vdata-Vref) 2< . It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on the output current of the driving transistor T3, and the output current can be controlled by controlling the voltage Vdata of the data signal Data, so as to control the brightness of the light emitting device LD. For the specific principle, reference may be made to the description of the current formula in the embodiment of the first type of pixel circuit above, which will not be repeated here.

[0122] The driving method for the pixel circuit is described below based on the structure of the pixel circuit in the second embodiment of the second type of pixel circuit.

[0123] As shown in FIGS. 7 and 8, the driving method may include the following contents.

[0124] In the compensation stage t2, the first light emitting control circuit EU1 is turned on and the second light emitting control circuit EU2 is turned off to write the threshold voltage of the driving transistor T3 to the energy storage circuit RU.

[0125] When the first light emitting control circuit EU1 is turned on, the voltage of the first electrode of the driving transistor T3 gradually increases, and the threshold voltage of the driving transistor T3 is written to the energy storage circuit RU.

[0126] In the writing stage t3, the writing circuit DU and the first light emitting control circuit EU1 are turned on, the second light emitting control circuit EU2 is turned off, and the data signal Data is written to the energy storage circuit RU through the writing circuit DU.

[0127] When the voltage of the first electrode of the driving transistor T3 reaches the difference between the gate voltage and the threshold voltage of the driving transistor T3, the driving transistor T3 is turned off, so that the threshold voltage of the driving transistor T3 can be written to the energy storage circuit RU. In other words, the writing of the threshold voltage and the writing of the data signal Data can be performed independently.

[0128] In the light emitting stage t4, the first light emitting control circuit EU1 and the second light emitting control circuit EU2 are turned on, the writing circuit DU is turned off, and the voltage difference between the gate and the first electrode of the driving transistor T3 is controlled by the energy storage circuit RU to make the light emitting device LD emit light.

[0129] Further, as shown in FIG. 7 and FIG. 8, in some embodiments of the present disclosure, the driving method may further include the following contents.

[0130] In the reset stage t1, the first reset transistor T1, the second reset transistor T2, the third reset transistor T7 and the second light emitting control circuit EU2 are turned on, and the writing circuit DU and the first light emitting control circuit EU1 are turned off. The gate of the driving transistor T3 is reset and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are reset by the reference signal Vref, and the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2 are reset by the reset signal Vinit. In addition, the driving transistor T3 can be turned on by the voltage difference between the reset signal Vinit and the reference signal Vref.

[0131] According to the driving method for the pixel circuit, the data signal Data and the threshold voltage of the driving transistor T3 can be stored respectively by the energy storage circuit RU, and the energy storage circuit RU will not interfere with the storage of the threshold voltage when storing the data signal Data, so as to ensure that the voltage difference between the data signal Data and the first electrode of the driving transistor T3 remains stable during the light emitting stage, and prevent the actual brightness of the light emitting device LD from being greatly different from the designed brightness due to the different interference levels of different data signals Data, thereby improving the picture quality. In addition, the gate of the driving transistor T3 and the writing circuit DU can be directly connected without being connected through the data control circuit CU, so as to prevent the coupling effect of the data control circuit CU when it is turned on / off from affecting the gate voltage of the driving transistor T3.

[0132] As shown in FIG. 7 and FIG. 8, the driving method for the pixel circuit is exemplarily illustrated below by taking the second embodiment of the second type of pixel circuit as an example.

[0133] Each transistor in the pixel circuit is an N-type metal oxide transistor.

[0134] In the reset stage t1, the first reference control signal RE1 and the second reference control signal RE2 are at the high level, and the first reset transistor T1 and the second reset transistor T2 are turned on. The reference signal Vref resets the node N1 and the node N4, and the voltage of the reference signal Vref can be 2.5V. The second light emitting control signal EM2 is at the high level, and the second light emitting control transistor T6 is turned on. The reset control signal RE3 is at the high level, the third reset transistor T7 is turned on, the reset signal Vinit resets the node N3, and the voltage of the reset signal Vinit can be 1.5V. In this case, the gate and the first electrode of the driving transistor T3 have a voltage difference and the driving transistor T3 is turned on.

[0135] In addition, the first light emitting control signal EM1 is at the low level, and the first light emitting control transistor T5 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off.

[0136] The reset of the node N1, the node N3 and the node N4 can be performed sequentially. For example, the first reference control signal RE1 and the second reference control signal RE2 first change from the low level to the high level, and the reset control signal RE3 then changes from the low level to the high level, so that the first reset transistor T1 and the second reset transistor T2 are turned on first, and the third reset transistor T7 is turned on later.

[0137] In the compensation stage t2, the first light emitting control signal EM1 is at the high level, the first light emitting control transistor T5 is turned on, and the voltage of the node N2 is the voltage of the first power signal VDD. Since the driving transistor T3 is turned on, the voltage of the node N3 gradually increases until it increases to Vref-Vth, so that the voltage difference between the gate and the first electrode of the driving transistor T3 is equal to the threshold voltage, that is, the gate-source voltage difference Vgs is equal to Vth, in this case, the driving transistor T3 is turned off; Vth is the threshold voltage of the driving transistor T3. Thus, the threshold voltage Vth is written to the node N3, that is, stored in the second capacitor C2, and the first light emitting control signal EM1 can continue until the driving transistor T3 is turned off, that is, until the writing of the threshold voltage is completed. The voltage of the first power signal VDD can be 11.5V.

[0138] In addition, the second light emitting control signal EM2 is at the low level to make the second light emitting control transistor T6 turn off. The first reference control signal RE1 and the second reference control signal RE2 are at the high level, and the first reset transistor T1 and the second reset transistor T2 are turned on. The reset control signal RE3 is at the low level, and the third reset transistor T7 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off.

[0139] In the writing stage t3, the scan signal Gate is at the high level, and the writing transistor T4 is turned on. The first reference control signal RE1 is at the low level, and the first reset transistor T1 is turned off. The data signal Data is written to the node N5 through the writing transistor T4, that is, stored in the first capacitor C1. The low level of the second light emitting control signal EM2 can continue until the writing transistor T4 is turned off, that is, until the writing of the data signal Data is completed.

[0140] The second reference control signal RE2 continues to maintain the high level, so that the second reset transistor T2 continues to be turned on, which can be maintained until the writing transistor T4 is turned off. The voltage of the node N4 is stabilized to avoid the data signal Data stored in the first capacitor C1 and the threshold voltage stored in the second capacitor C2 from interfering with each other. In addition, the reset control signal RE3 is at the low level, and the third reset transistor T7 is turned off.

[0141] In the light emitting stage t4, the first light emitting control signal EM1 and the second light emitting control signal EM2 are at the high level, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on. The first reference control signal RE1 and the second reference control signal RE2 are at the low level, and the first reset transistor T1 and the second reset transistor T2 are turned off. The reset control signal RE3 is at the low level, and the third reset transistor T7 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off. Under the action of the first capacitor C1, the data signal Data starts to be written to the node N1, and at this time, the voltage of the node N1 is the voltage of the gate of the driving transistor T3, that is, Vg=Vdata+Vld+VSS-(Vref-Vth), the voltage of the node N3 is the voltage of the first electrode of the driving transistor T3, that is, Vs =Vld+VSS, and then the gate-source voltage difference Vgs of the driving transistor T3 is Vdata-Vref+Vth. Vld is the voltage of the light emitting device LD, VSS is the voltage of the second power signal VSS input to the second electrode CAT of the light emitting device LD, and Vdata is the voltage of the data signal Data.

[0142] The output current I of the pixel circuit is (µWCox / 2L)(Vgs-Vth) 2< ; I is also the output current of the driving transistor T3; µ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor T3, and L is the channel length of the driving transistor T3.

[0143] According to the above formula for the output current of the driving transistor T3, the gate-source voltage difference Vgs of the driving transistor T3 in the above pixel circuit is substituted into the above formula to obtain: the output current I of the driving transistor T3 is (µWCox / 2L) (Vdata-Vref) 2< . It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on the output current of the driving transistor T3, and the output current can be controlled by controlling the voltage Vdata of the data signal Data, so as to control the brightness of the light emitting device LD. For the specific principle, reference may be made to the description of the current formula in the first type of embodiment above, which will not be repeated here.Third type of pixel circuit

[0144] As shown in FIG. 9, the pixel circuit may include a driving transistor T3, an energy storage circuit RU, a writing circuit DU and a first light emitting control circuit EU1, but does not include the second light emitting control circuit EU2 mentioned above.

[0145] A gate of the driving transistor T3 is connected to a first electrode of the driving transistor T3 through the energy storage circuit RU, the first electrode of the driving transistor T3 is configured to be connected to a light emitting device LD, and a second electrode of the driving transistor T3 is connected to the first light emitting control circuit EU1. The first light emitting control circuit EU1 is configured to receive the first power signal VDD.

[0146] The writing circuit DU is connected to the gate of the driving transistor T3, and the writing circuit DU is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU. The first electrode of the driving transistor T3 can be directly connected to the light emitting device LD without being indirectly connected to the light emitting device LD through the second light emitting control circuit EU2.

[0147] The writing circuit DU is configured to write a data signal Data to the energy storage circuit RU, and the energy storage circuit RU is configured to store the data signal Data and a voltage of the first electrode of the driving transistor T3.

[0148] The energy storage circuit RU can store the data signal Data and the voltage of the first electrode of the driving transistor T3, respectively, so as to stabilize the voltage difference between the first electrode and the gate of the driving transistor T3, which is beneficial to ensure that the light emitting device LD emits light stably, thereby improving the picture quality.

[0149] As shown in FIG. 9, in some embodiments of the present disclosure, in some embodiments of the present disclosure, the energy storage circuit RU may include a first capacitor C1 and a second capacitor C2 connected in series, the writing circuit DU may include a writing transistor T4, the first light emitting control circuit EU1 includes a first light emitting control transistor T5.

[0150] A first electrode of the writing transistor T4 is configured to input a data signal Data, and a second electrode of the writing transistor T4 is connected to the gate of the driving transistor T3 and the first plate C11 of the first capacitor C1, which can be connected at the node N5. A second plate C12 of the first capacitor C1 is connected to a first plate C21 of the second capacitor C2, which can be connected at the node N4. A second plate C22 of the second capacitor C2 is connected to the first electrode of the driving transistor T3, which can be connected to the node N3. A first electrode of the first light emitting control transistor T5 is configured to receive the first power signal VDD, and a second electrode of the first light emitting control transistor T5 can be connected to the second electrode of the driving transistor T3, and can be connected to the second electrode of the driving transistor T3 at the node N2. The first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2 can be connected to the node N3, and the first electrode ANO of the light emitting device LD is also connected to the node N3.

[0151] A gate of the writing transistor T4 can receive a scan signal Gate, and the writing transistor T4 can be turned on or off under the control of the scan signal Gate. A gate of the first light emitting control transistor T5 can receive a first light emitting control signal EM1, and the first light emitting control transistor T5 can be turned on or off under the control of the first light emitting control signal EM1.

[0152] In order to eliminate the influence of the signal of the previous frame image, before the signal input of the current frame is displayed, the gate and the first electrode of the driving transistor T3 may be reset, and the energy storage circuit RU may also be reset. As shown in FIG.2, in some embodiments of the present disclosure, the pixel circuit may further include a first reset transistor T1 and a second reset transistor T2.

[0153] A first electrode of the first reset transistor T1 is configured to receive a reference signal Vref, and a second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3. As shown in FIG. 2, the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3 at the node N1.

[0154] A first electrode of the second reset transistor T2 is configured to receive the reference signal Vref, and a second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2. As shown in FIG. 2, the second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 at a node N4.

[0155] A gate of the first reset transistor T1 can receive a first reference control signal RE1, and the first reset transistor T1 can be turned on or off under the control of the first reference control signal RE1. A gate of the second reset transistor T2 can receive a second reference control signal RE2, and the second reset transistor T2 can be turned on or off under the control of the second reference control signal RE2. The first reference control signal RE1 and the second reference control signal RE2 can be synchronous signals, so that the first reset transistor T1 and the second reset transistor T2 can be turned on or off synchronously. Alternatively, the first reference control signal RE1 and the second reference control signal RE2 can also be asynchronous.

[0156] The reference signal Vref can be input to nodes N1 and N4 through the first reset transistor T1 and the second reset transistor T2 to eliminate the influence of the signal when the previous frame image is displayed.

[0157] In addition, in some embodiments, the first reference control signal RE1 of the gate of the first reset transistor T1 of the n+1th row of pixel circuits and the second reference control signal RE2 of the gate of the second reset transistor T2 of the nth row of pixel circuits may be the same signal, where n is a positive integer. Thus, the first reset transistor T1 of the n+1th row of pixel circuits and the second reset transistor T2 of the nth row of pixel circuits may be controlled simultaneously by the same shift register, that is, it can be realized that one shift register controls multiple rows of pixel circuits simultaneously, which is beneficial to reducing the number of shift registers and simplifying the structure.

[0158] The pixel circuit further includes a third reset transistor T7, a second electrode of which can be connected to the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2, which can be connected at the node N3. A gate of the third reset transistor T7 can receive the reset control signal RE3, and the third reset transistor T7 can be turned on or off under the control of the reset control signal RE3. The reset signal Vinit can be input to the node N3 through the third reset transistor T7 to reset the first electrode of the driving transistor T3, the second plate C22 of the second capacitor C2, and the first electrode ANO of the light emitting device LD, thereby eliminating the influence of the signal of the previous frame image.

[0159] At least one of the transistors in the above pixel circuit may be a metal oxide transistor, that is, the material of the active portion of the transistor includes a metal oxide such as IGZO ( indium gallium zinc oxide), and accordingly, the transistor may be an N-type transistor. As shown in FIG. 9, if each transistor may be the N-type transistor, the first electrode of each transistor is the source, the second electrode is the drain, and the transistor is turned on when the gate of the transistor receives the high level and turned off when the gate receives the low level. For example, as shown in FIG. 9, the driving transistor T3, the writing transistor T4, the first reset transistor T1, the second reset transistor T2, the third reset transistor T7 and the first light emitting control transistor T5 are all metal oxide transistors, that is, the transistors of the pixel circuit are all metal oxide transistors, so as to reduce the leakage current. Alternatively, only some of the transistors may be metal oxide transistors.

[0160] The driving method for the pixel circuit is exemplarily illustrated below by taking the third type of pixel circuit as an example.

[0161] Each transistor in the pixel circuit is an N-type metal oxide transistor.

[0162] In the reset stage, the first reference control signal RE1 and the second reference control signal RE2 are at the high level, the first reset transistor T1 and the second reset transistor T2 are turned on. The reference signal Vref resets the node N1 and the node N4, and the voltage of the reference signal Vref can be 2.5V. The reset control signal RE3 is at the high level, the third reset transistor T7 is turned on, the reset signal Vinit resets the node N3, and the voltage of the reset signal Vinit can be 1.5V. In this case, the gate and the first electrode of the driving transistor T3 have a voltage difference and the driving transistor T3 is turned on.

[0163] In addition, the first light emitting control signal EM1 is at the low level, and the first light emitting control transistor T5 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off.

[0164] The reset of the node N1, the node N3 and the node N4 can be performed sequentially. For example, the first reference control signal RE1 and the second reference control signal RE2 first change from the low level to the high level, and the reset control signal RE3 then changes from the low level to the high level, so that the first reset transistor T1 and the second reset transistor T2 are turned on first, and the third reset transistor T7 is turned on later.

[0165] In the compensation stage, the first light emitting control signal EM1 is at the high level, the first light emitting control transistor T5 is turned on, and the voltage of the node N2 is the voltage of the first power signal VDD. Since the driving transistor T3 is turned on, the voltage of the node N3 gradually increases until it increases to Vref-Vth, so that the voltage difference between the gate and the first electrode of the driving transistor T3 is equal to the threshold voltage, that is, the gate-source voltage difference Vgs is equal to Vth, in this case, the driving transistor T3 is turned off; Vth is the threshold voltage of the driving transistor T3. Thus, the threshold voltage Vth is written to the node N3, that is, stored in the second capacitor C2, and the first light emitting control signal EM1 can continue until the driving transistor T3 is turned off, that is, until the writing of the threshold voltage is completed. The voltage of the first power signal VDD can be 11.5V.

[0166] In addition, the first reference control signal RE1 and the second reference control signal RE2 are at the high level, and the first reset transistor T1 and the second reset transistor T2 are turned on. The reset control signal RE3 is at the low level, and the third reset transistor T7 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off.

[0167] In the writing stage t3, the scan signal Gate is at the high level, and the writing transistor T4 is turned on. The first reference control signal RE1 is at the low level, and the first reset transistor T1 is turned off. The data signal Data is written to the node N5 through the writing transistor T4, that is, stored in the first capacitor C1.

[0168] The second reference control signal RE2 continues to maintain the high level, so that the second reset transistor T2 continues to be turned on, which can be maintained until the writing transistor T4 is turned off. The voltage of the node N4 is stabilized to avoid the data signal Data stored in the first capacitor C1 and the threshold voltage stored in the second capacitor C2 from interfering with each other. In addition, the reset control signal RE3 is at the low level, and the third reset transistor T7 is turned off. The low level of the second light emitting control signal EM2 can continue until the writing transistor T4 is turned off, that is, until the writing of the data signal Data is completed.

[0169] In the light emitting stage t4, the first light emitting control signal EM1 is at the high level, and the first light emitting control transistor T5 is turned on. The first reference control signal RE1 and the second reference control signal RE2 are at the low level, and the first reset transistor T1 and the second reset transistor T2 are turned off. The reset control signal RE3 is at the low level, and the third reset transistor T7 is turned off. The scan signal Gate is at the low level, and the writing transistor T4 is turned off. Under the action of the first capacitor C1, the data signal Data starts to be written to the node N1. The voltage of the node N1 is the voltage of the gate of the driving transistor T3, that is, Vg=Vdata+Vld+VSS-(Vref-Vth), the voltage of the node N3 is the voltage of the first electrode of the driving transistor T3, that is, Vs=Vld+VSS, and then the gate-source voltage difference Vgs of the driving transistor T3 is Vdata-Vref+Vth. Vld is the voltage of the light emitting device LD, VSS is the voltage of the second power signal VSS input to the second electrode CAT of the light emitting device LD, and Vdata is the voltage of the data signal Data.

[0170] The output current I of the pixel circuit is (µWCox / 2L)(Vgs-Vth) 2< ; I is also the output current of the driving transistor T3; µ is the carrier mobility; Cox is the gate capacitance per unit area, W is the channel width of the driving transistor T3, and L is the channel length of the driving transistor T3.

[0171] According to the above formula for the output current of the driving transistor T3, the gate-source voltage difference Vgs of the driving transistor T3 in the above pixel circuit is substituted into the above formula to obtain: the output current I of the driving transistor T3 is (µWCox / 2L) (Vdata-Vref) 2< . It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on the output current of the driving transistor T3, and the output current can be controlled by controlling the voltage Vdata of the data signal Data, so as to control the brightness of the light emitting device LD. For the specific principle, reference may be made to the description of the current formula in the first type of embodiment above, which will not be repeated here.

[0172] The driving method for the third type of pixel circuit mentioned above is mainly different from the driving method for the second type of pixel circuit mentioned above in that the third type of pixel circuit is not provided with the second light emitting control circuit EU2 and the second light emitting control transistor T6, and does not have the second light emitting control signal EM2, which will not be described in detail here.

[0173] It should be noted that although the various steps of the driving method in the present disclosure are described in a particular order in the drawings, this is not required or implied that the steps must be performed in the specific order, or all the steps shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps and so on.

[0174] A structure of a display panel is described below based on the second type of pixel circuit described above.

[0175] As shown in FIG. 2, the driving backplane BP may include a substrate SU and a driving circuit disposed on a side of the substrate SU. The driving circuit includes a pixel circuit and a peripheral circuit, and the pixel circuit may be a structure of any of the above embodiments.

[0176] As shown in FIG. 2, the driving backplane BP may further include a semiconductor layer SE disposed on a side of the substrate SU, and the active portion of each transistor in the pixel circuit is located on the semiconductor layer SE, that is, active portions of individual transistors are disposed in the same layer. The light emitting device LD is disposed on a side of the semiconductor layer SE away from the substrate SU, and a first electrode ANO of a light emitting device LD may be connected to a first electrode of a driving transistor T3 of a pixel circuit.

[0177] As shown in FIGS. 10-12, 19, 21 and 22, in order to facilitate signal transmission, in some embodiments of the present disclosure, the display panel may further include a first light emitting control line EML1, a second light emitting control line EML2, a first reset control line REL1, a second reset control line REL2, a third reset control line REL3, a scan line GL, a first reset line VRL and a second reset line VIL.

[0178] The first light emitting control line EML1 can extend along the row direction X, overlap and connect with the gate of the first light emitting control transistor T5, and is configured to transmit the first light emitting control signal EM1. There are a plurality of first light emitting control lines EML1, which are distributed at intervals along the column direction Y, and pixel circuits in the same row are connected to a first light emitting control line EML1.

[0179] The scan line GL may extend along the row direction X, overlap and connect with the gate of the writing transistor T4, and is configured to transmit the scan signal Gate. There are multiple scan lines GL, which are distributed at intervals along the column direction Y, and pixel circuits in the same row are connected to a scan line GL.

[0180] The first reset control line REL1 can extend along the row direction X, overlap and connect with the gate of the first reset transistor T1, and is configured to transmit the first reference control signal RE1. There are multiple first reset control lines REL1, which are distributed at intervals along the column direction Y, and pixel circuits in the same row are connected to a first reset control line REL1.

[0181] The first reset line VRL can extend along the row direction X and be connected to the first electrode of the first reset transistor T1 and the first electrode of the second reset transistor T2, and is configured to transmit the reference signal Vref. There are multiple first reset lines VRL, which are distributed at intervals along the column direction Y, and pixel circuits in the same row are connected to a first reset line VRL.

[0182] The second reset control line REL2 can extend along the row direction X, overlap and connect with the gate of the second reset transistor T2, and is configured to transmit the second reference control signal RE2. There are multiple second reset control lines REL2, which are distributed at intervals along the column direction Y, and pixel circuits in the same two rows are connected to a second reset control lines REL2.

[0183] The second light emitting control line EML2 extends along the row direction X, overlaps and connects with the gate of the second light emitting control transistor T6, and is configured to transmit the second light emitting control signal EM2. There are multiple second light emitting control lines EML2, which are distributed at intervals along the column direction Y, and pixel circuits in the same row are connected to a second light emitting control line EML2.

[0184] The third reset control line REL3 extends along the row direction X, overlaps and connects with the gate of the third reset transistor T7, and is configured to transmit the reset control signal RE3. There are multiple third reset control lines REL3, which are distributed at intervals along the column direction Y, and pixel circuits in the same row are connected to a third reset control line REL3.

[0185] The second reset line VIL can extend along the row direction X and is connected to the first electrode of the third reset transistor T7, and is configured to transmit the reset signal Vinit. There are multiple second reset lines VIL, which are distributed at intervals along the column direction Y, and pixel circuits in the same row are connected to a second reset line VIL.

[0186] Further, as shown in FIGS. 10-12, 19, 21 and 22, in some embodiments of the present disclosure, for traces connected to a pixel circuit, the first light emitting control line EML1, the scan line GL, the first reset control line REL1, the first reset line VRL, the second reset control line REL2, the second light emitting control line EML2, the third reset control line REL3 and the second reset line VIL can be distributed at intervals in sequence along the column direction Y, that is, orthographic projections of the aforementioned individual traces on the substrate SU can be distributed at intervals in sequence along the column direction Y.

[0187] As shown in FIGS. 10 to 13, 19 and 21 to 24, an orthographic projection of the active portion ACT3 of the driving transistor T3 on the substrate SU is located between orthographic projections of the scan line GL and the first reset control line REL1 on the substrate SU. An orthographic projection of the active portion ACT1 of the first reset transistor T1 on the substrate SU is located between orthographic projections of the scan line GL and the first reset line VRL on the substrate SU. An orthographic projection of the active portion ACT2 of the second reset transistor T2 on the substrate SU is located between orthographic projections of the first reset line VRL and the second light emitting control line EML2 on the substrate SU. An orthographic projection of the active portion ACT7 of the third reset transistor T7 on the substrate SU is located between orthographic projections of the second light emitting control EML2 and the second reset line VIL on the substrate SU.

[0188] As shown in FIG. 10, FIG. 20 and FIG. 21, in order to provide the first power signal VDD to the pixel circuit, in some embodiments of the present disclosure, the display panel further includes a plurality of first power lines VDL, which may be disposed on a side of the pixel circuit away from the substrate SU. The first power lines VDL may extend along the column direction Y, and individual first power lines VDL may be distributed at intervals along the row direction X. A first power line VDL overlaps with a column of pixel circuits and is connected to the first electrode of the first light emitting control transistor T5 of this column of pixel circuits, thereby providing the first power signal VDD to the pixel circuits.

[0189] As shown in FIG. 10, FIG. 11, FIG. 19, FIG. 21 and FIG. 22, in order to reduce resistance, a plurality of first auxiliary power lines VDLs may be disposed on a side of the pixel circuit away from the substrate SU, and the first power line VDL is located on a side of the first auxiliary power line VDLs away from the substrate SU. Individual first auxiliary power lines VDLs may extend along the row direction X and may be distributed along the column direction Y. A first auxiliary power line VDLs may be disposed between two adjacent rows of pixel circuits, and the first auxiliary power line VDLs is connected to the first electrode of the first light emitting control transistor T5 of a row of pixel circuits on a side of the first auxiliary power line VDLs. A first power line VDL and individual first auxiliary power lines VDLs are located in different layers, connected through contact holes, and overlap with a column of pixel circuits. The first power line VDL may be connected to the pixel circuit through the first auxiliary power line VDLs, and the first power line VDL and the first auxiliary power lines VDLs may form a network for transmitting the first power signal VDD in space, which is conducive to reducing the resistance. Alternatively, in some embodiments of the present disclosure, the first power line VDL or the first auxiliary power line VDLs may not be provided, as long as the first power signal VDD can be transmitted to the first electrode of the first light emitting control transistor T5.

[0190] As shown in FIG. 10, FIG. 11, FIG. 19, FIG. 21 and FIG. 22, in order to provide the data signal Data to the pixel circuit, the display panel may further include a plurality of data lines DAL, which may be disposed on a side of the first auxiliary power line VDLs away from the substrate SU, and may be disposed in the same layer as the first power line VDL. Individual data lines DAL may extend along the column direction Y, and may be distributed at intervals along the row direction X. A data line DAL overlaps with a column of pixel circuits, and is connected to the first electrode of the writing transistor T4 of a column of pixel circuits, and is configured to transmit the data signal Data. However, the pixel circuit overlapped with the data line DAL and the pixel circuit connected to the data signal Data may be adjacent pixel circuits. Alternatively, if space permits, the data line DAL may also be provided to overlap with the pixel circuit connected thereto, for example, an embodiment of a second display panel (see FIG. 36), which is described in details below.

[0191] As shown in FIG. 10, FIG. 11, FIG. 19, FIG. 21 and FIG. 22, in some embodiments of the present disclosure, the display panel further includes a plurality of second power lines VSL, which may be disposed on a side of the first auxiliary power line VDLs away from the substrate SU, and individual second power lines VSL extend along the column direction Y and are distributed at intervals along the row direction X. A second power line VSL may overlap with a column of pixel circuits, but the number of second power lines VSL may be less than the number of columns of pixel circuits, that is, only a portion of the columns of pixel circuits may overlap with the second power lines VSL. The second power line VSL is configured to transmit the second power signal VSS.

[0192] As shown in FIGS. 10 to 14, 16, 21 and 24, in some embodiments of the present disclosure, the display panel further includes a second auxiliary power line VSLs, which may be disposed on a side of the substrate SU close to the semiconductor layer SE. The second auxiliary power lines VSLs extend along the row direction X and are distributed along the column direction Y, and the second auxiliary power line VSLs may transmit the second power signal VSS. An orthographic projection of the second auxiliary power line VSLs on the substrate SU is located between orthographic projections of the second light emitting control line EML2 and the third reset control line REL3 on the substrate SU. In addition, a second power line VSL and individual second auxiliary power lines VSLs are located in different layers, and are connected through contact holes, and overlap with a column of pixel circuits. The second power line VSL may be connected to the pixel circuit through the second auxiliary power line VSLs, and the second power line VSL and the second auxiliary power line VSLs may form a network for transmitting the second power signal VSS in space, which is conducive to reducing resistance. Alternatively, in some embodiments of the present disclosure, the second power line VSL or the second auxiliary power line VSLs may not be provided, as long as the second power signal VSS can be transmitted.

[0193] In addition, the peripheral area WA of the display panel may also be provided with a first power bus and a second power bus, and part or all of the first power lines VDL and the first auxiliary power lines VDLs may extend to the peripheral area WA and may be connected to the first power bus, and the first power signal VDD may be input to the first power line VDL through the first power bus. Part or all of the second power lines VSL and the second auxiliary power lines VSLs may extend to the peripheral area WA and may be connected to the second power bus, and the second power signal VSS may be input to the second power line VSL through the second power bus. Individual light emitting devices LD may share the same second electrode CAT, that is, the second electrode CAT may be a continuous whole-layer structure, and may be connected to the second power bus in the peripheral area WA to receive the second power signal VSS. The resistance may be reduced through the second power line VSL, and a voltage drop of the second power signal VSS may be reduced.

[0194] As shown in FIG. 10, FIG. 11, FIG. 19, and FIG. 20 to FIG. 22, in some embodiments of the present disclosure, the display panel further includes a plurality of first auxiliary reset lines VRLs and a plurality of second auxiliary reset lines VILs.

[0195] The first auxiliary reset line VRLs and the second auxiliary reset line VILs may be disposed on a side of the first auxiliary power line VDLs away from the substrate SU, and the first auxiliary reset line VRLs and the second auxiliary reset line VILs may be disposed in the same layer. Alternatively, the first auxiliary reset line VRLs and the second auxiliary reset line VILs can also be disposed in different layers. Individual first auxiliary reset lines VRLs and individual second auxiliary reset lines VILs each extend along the column direction Y and are each distributed at intervals along the row direction X.

[0196] The first auxiliary reset line VRLs and the first reset line VRL may be located in different layers and may be connected through a contact hole. The first auxiliary reset line VRLs and the first reset line VRL may form a network for transmitting the reference signal Vref in space, which is beneficial to reducing resistance. The second auxiliary reset line VILs and the second reset line VIL may be located in different layers and may be connected through a contact hole. The second auxiliary reset line VILs and the second reset line VIL may form a network for transmitting a reset signal Vinit in space, which is beneficial to reducing resistance.

[0197] A first auxiliary reset line VRLs may overlap with a column of pixel circuits, and a second auxiliary reset line VILs may overlap with a column of pixel circuits. However, the number of first auxiliary reset lines VRLs and the number of second auxiliary reset lines VILs are both less than the number of columns of pixel circuits, that is, only some columns of pixel circuits may overlap with the first auxiliary reset lines VRLs and the second auxiliary reset lines VILs.

[0198] In some embodiments of the present disclosure, as shown in FIG. 10, FIG. 21, FIG. 26, FIG. 27 and FIG. 35, the data line DAL and the first power line VDL connected to the same column of pixel circuits PC may be defined as a column line group YG, that is, each column of pixel circuits PC may be connected to one column line group YG. In addition, one of the second power line VSL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs may be provided between the data line DAL and the first power line VDL of the same column line group YG, that is, the second power line VSL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs are distributed in the space between the data line DAL and the first power line VDL of the column line group YG. Thus, the space can be fully utilized.

[0199] As shown in FIG. 10, FIG. 11, FIG. 19, FIG. 21, FIG. 22, FIG. 26-28, and FIG. 34, in some embodiments of the present disclosure, the first light emitting control line EML1, the scan line GL, the first reset control line REL1, the first reset line VRL, the second reset control line REL2, the second light emitting control line EML2, the second auxiliary power line VSLs and the third reset control line REL3 connected to the same row of pixel circuits can be defined as a row line group, that is, each row of pixel circuits is connected to one row line group. In addition, one first auxiliary power line VDLs and one second reset line VIL can be provided between two adjacent row line groups. One row line group is located between one first auxiliary power line VDLs and one second reset line VIL.

[0200] In some embodiments of the present disclosure, the first light emitting control line EML1, the second light emitting control line EML2, the first reset control line REL1, etc. can adopt a single-layer or multi-layer structure. If the multi-layer structure is adopted, it may include two or more sub-layers, and adjacent sub-layers can be connected through contact holes, so that the resistance can be reduced through multiple sub-layers.

[0201] In order to simplify the structure and process, one of the first plate C11 and the second plate C12 of the first capacitor C1 can be disposed in the same layer as one of the first plate C21 and the second plate C22 of the second capacitor C2, and the film layers disposed in the same layer can be formed simultaneously through the same patterning process, which is conducive to simplifying the structure and process. In addition, one of the first capacitor C1 and the second capacitor C2 can be overlapped with the active portion ACT3 of the driving transistor T3, and the plate of the capacitor can be used as the gate of the driving transistor T3, which is conducive to saving space.

[0202] As shown in FIGS. 10-14 and FIGS. 21-25, in a first display panel, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are disposed in the same layer and are distributed at an interval along the column direction Y. The second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are disposed in the same layer and are distributed an at interval along the column direction Y.

[0203] As shown in FIGS. 36 to 41, in a second display panel, the first plate C11 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are disposed in the same layer and are distributed at an interval along the column direction Y. The second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are disposed in the same layer and are an integrated structure.

[0204] In some embodiments of the present disclosure, orthographic projections of the first capacitor C1 and the second capacitor C2 on the substrate SU are located on a side of the second reset control line REL2 close to the first auxiliary power line VDLs, and the first capacitor C1 at most partially overlaps with the first auxiliary power line VDLs. The first light emitting control line EML1 overlaps with the first capacitor C1, the scan line GL overlaps with the first capacitor C1, the first reset control line REL1 overlaps with the second capacitor C2, and the first reset line VRL overlaps with the second capacitor C2.

[0205] In some embodiments of the present disclosure, for a pixel circuit, the active portion ACT5 of the first light emitting control transistor T5 overlaps with the first plate C11 and the second plate C12 of the first capacitor C1. The first plate C21 and the second plate C22 of the second capacitor C2 overlap with the active portion ACT3 of the driving transistor T3. The active portions of other transistors may not overlap with the first capacitor C1 and the second capacitor C2.

[0206] A pattern of a semiconductor layer corresponding to a pixel circuit is taken as an example for illustration.

[0207] As shown in FIGS. 12, 13, 17, 23 to 25, and 40 to 42, in some embodiments of the present disclosure, the semiconductor layer SE may include a first semiconductor portion SE1 and a second semiconductor portion SE2 distributed at an interval along the row direction X.

[0208] The active portion ACT4 of the writing transistor T4, the active portion ACT1 of the first reset transistor T1, and the active portion ACT2 of the second reset transistor T2 are all located in the first semiconductor portion SE1 and are connected in sequence. The active portion ACT5 of the first light emitting control transistor T5, the active portion ACT3 of the driving transistor T3, the active portion ACT6 of the second light emitting control transistor T6, and the active portion ACT7 of the third reset transistor T7 are located in the second semiconductor portion SE2 and are connected in sequence.

[0209] In some embodiments of the present disclosure, the first semiconductor portion SE1 includes a first semiconductor segment SE11, a second semiconductor segment SE12, and a third semiconductor segment SE13.

[0210] The first semiconductor segment SE11 and the third semiconductor segment SE13 may extend along the column direction Y and may be distributed at an interval along the row direction X, and the third semiconductor segment SE13 is located between the first semiconductor segment SE11 and the second semiconductor portion SE2. The second semiconductor segment SE12 may extend along the row direction X, and one end of the second semiconductor segment SE12 is connected to the first semiconductor segment SE11 and the other end of the second semiconductor segment SE12 is connected to the third semiconductor segment SE13.

[0211] The active portion ACT4 of the writing transistor T4 and the active portion ACT1 of the first reset transistor T1 are located in the first semiconductor segment SE11, and the active portion ACT2 of the second reset transistor T2 is located in the second semiconductor segment SE12. The third semiconductor segment SE13 is connected to the first plate C21 of the second capacitor C2.

[0212] Further, as shown in FIG. 12, FIG. 13, and FIG. 17, for the first embodiment of the second type of pixel circuit described above, the second electrode of the third reset transistor T7 is connected to the first electrode of the driving transistor T3 and the first electrode of the second light emitting control transistor T6. The second semiconductor portion SE2 may include a fourth semiconductor segment SE21 and a fifth semiconductor segment SE22.

[0213] The fourth semiconductor segment SE21 extends along the column direction Y and is located on a side of the third semiconductor segment SE13 away from the first semiconductor segment SE11. The active portion ACT5 of the first light emitting control transistor T5, the active portion ACT3 of the driving transistor T3, and the active portion ACT6 of the second light emitting control transistor T6 are sequentially distributed in the fourth semiconductor segment SE21 along the column direction Y. The active portion ACT3 of the driving transistor T3 may be formed by the fourth semiconductor segment SE21 protruding along the row direction X, so that a width of the active portion ACT3 of the driving transistor T3 is greater than that of other transistors, which is beneficial to increase a width-to-length ratio of the driving transistor T3 and to increase the current.

[0214] The fifth semiconductor segment SE22 is connected to an area of the fourth semiconductor segment SE21 between the active portion ACT3 of the driving transistor T3 and the active portion ACT6 of the second light emitting control transistor T6, and the active portion ACT7 of the third reset transistor T7 is located in the fifth semiconductor segment SE22.

[0215] For example, as shown in FIGS. 13 and 17, the fifth semiconductor segment SE22 may include a first sub-segment SE221, a second sub-segment SE222, a third sub-segment SE223 and a fourth sub-segment SE224 that are sequentially connected. The first sub-segment SE221 and the third sub-segment SE223 are located on a side of the fourth semiconductor segment SE21 away from the first semiconductor portion SE1 and may extend along the row direction X, and the second sub-segment SE222 and the fourth sub-segment SE224 may extend along the column direction Y. The first sub-segment SE221 is connected to an area between the active portion ACT3 of the driving transistor T3 and the active portion ACT6 of the second light emitting control transistor T6, the second sub-segment SE222 connects the first sub-segment SE221 and the third sub-segment SE223, and the third sub-segment SE223 connects the fourth sub-segment SE224 and the second sub-segment SE222. The first sub-segment SE221 overlaps with the second reset control line REL2, and the fourth sub-segment SE224 overlaps with the third reset control line REL3.

[0216] As shown in FIG. 23 to FIG. 25, for the second embodiment of the second type of pixel circuit described above, the second electrode of the third reset transistor T7 is connected to the second electrode of the second light emitting control transistor T6 and the light emitting device LD. The second semiconductor portion SE2 may include a fourth semiconductor segment SE21 and a fifth semiconductor segment SE22.

[0217] The fourth semiconductor segment SE21 extends along the column direction Y and is located on a side of the third semiconductor segment SE13 away from the first semiconductor segment SE11. The active portion ACT5 of the first light emitting control transistor T5, the active portion ACT3 of the driving transistor T3, and the active portion ACT6 of the second light emitting control transistor T6 are sequentially distributed in the fourth semiconductor segment SE21 along the column direction Y. A pattern of the fourth semiconductor segment SE21 may be the same as the pattern of the fourth semiconductor segment SE21 in the first embodiment described above, which will not be described in detail herein.

[0218] The fifth semiconductor segment SE22 is connected to an area of the fourth semiconductor segment SE21 located on a side of the active portion ACT6 of the second light emitting control transistor T6 away from the active portion ACT3 of the driving transistor T3. In addition, the fifth semiconductor segment SE22 can be bent toward a direction close to the first semiconductor portion SE1, and the active portion ACT7 of the third reset transistor T7 is located in the fifth semiconductor segment SE22.

[0219] As shown in FIG. 28, FIG. 29 and FIG. 33, in some embodiments of the present disclosure, the semiconductor layer SE further includes a first auxiliary transfer portion SE3 and a second auxiliary transfer portion SE4.

[0220] The first auxiliary transfer portion SE3 is connected to an area of a first semiconductor portion SE1 of a pixel circuit between the active portion ACT1 of the first reset transistor T1 and the active portion ACT2 of the second reset transistor T2. For example, the first auxiliary transfer portion SE3 is connected to the connection between the first semiconductor segment SE11 and the second semiconductor segment SE12, and extends to the next row of pixel circuits along the column direction Y. The first auxiliary reset line VRLs can be connected to the first auxiliary transfer portion SE3 through a contact hole, thereby connecting to the first reset line VRL. Therefore, the connection between the first reset line VRL and the first auxiliary reset line VRLs can be achieved through the first auxiliary transfer portion SE3 of the semiconductor layer SE.

[0221] The second auxiliary transfer portion SE4 is connected to an end of a second semiconductor portion SE2 of a pixel circuit located on a side of the active portion ACT3 of the third reset transistor T7 away from the active portion ACT3 of the driving transistor T3. For example, the second auxiliary transfer portion SE4 is connected to an end of the fifth semiconductor segment SE22 away from the fourth semiconductor segment SE21, and extends along the column direction Y. The second auxiliary reset line VILs can be connected to the second reset line VIL through the second auxiliary transfer portion SE4. Thus, the connection between the second reset line VIL and the second auxiliary reset line VILs can be achieved through the second auxiliary transfer portion SE4 of the semiconductor layer SE.

[0222] Alternatively, in other embodiments of the present disclosure, the first auxiliary transfer portion SE3 and the second auxiliary transfer portion SE4 may be replaced by other film layer patterns, as long as the connection between the first reset line VRL and the first auxiliary reset line VRLs and the connection between the second reset line VIL and the second auxiliary reset line VILs can be achieved, which will not be described in detail here.

[0223] The following is an exemplary description of individual film layers and their patterns of the driving backplane BP.

[0224] As shown in FIG. 3, in some embodiments of the present disclosure, the display panel includes a light shielding layer BSM, a first gate layer GA1, a second gate layer GA2, a first source-drain layer SD1, and a second source-drain layer SD2.

[0225] As shown in FIGS. 12-15, 23, 24, 30-31 and 38-40, the light shielding layer BSM is disposed on a side of the substrate SU, and the material of the light shielding layer BSM can be metal or other conductive and light shielding materials. The light shielding layer BSM can include partial plates of the first capacitor C1 and the second capacitor C2.

[0226] As shown in FIGS. 12-18, 23, 30-32, and 38-41, the first gate layer GA1 may be disposed on a side of the light shielding layer BSM away from the substrate SU, and the first gate layer GA1 may include partial plates of the first capacitor C1 and the second capacitor C2.

[0227] As shown in FIGS. 12, 18, 23, 30-32 and 38, the second gate layer GA2 may be disposed on a side of the semiconductor layer SE away from the substrate SU, and include gates of at least part of the transistors.

[0228] As shown in FIGS. 11, 19, 18, 22, 28, 34 and 37, the first source-drain layer SD1 may be disposed on a side of the second gate layer GA2 away from the substrate SU, and include a first auxiliary power line VDLs, a first light emitting control line EML1, a scan line GL, a first reset control line REL1, a first reset line VRL, a second reset control line REL2, a second light emitting control line EML2, a third reset control line REL3 and a second reset line VIL.

[0229] As shown in FIGS. 10, 20, 21, 26, 27, 35 and 36, the second source-drain layer SD2 may be disposed on a side of the first source-drain layer SD1 away from the substrate SU, and include a data line DAL, a first power line VDL, a second power line VSL, a first auxiliary reset line VRLs, and a second auxiliary reset line VILs.

[0230] Further, as shown in FIG. 3, in some embodiments of the present disclosure, the display panel may further include insulation film layers, including a buffer layer BUF, a first gate insulation layer GI1, a second gate insulation layer GI2, an interlayer dielectric layer ILD, a passivation layer, a first planar layer PLN1, and a second planar layer PLN2.

[0231] The buffer layer BUF can cover the light shielding layer BSM. The first gate layer GA1 is disposed on a surface of the buffer layer BUF away from the substrate SU. The first gate insulation layer GI1 covers the first gate layer GA1. The semiconductor layer SE is disposed on a surface of the first gate insulation layer GI1 away from the substrate SU. The second gate insulation layer GI2 covers the semiconductor layer SE. The second gate layer GA2 is disposed on a surface of the second gate insulation layer GI2 away from the substrate SU. The interlayer dielectric layer ILD covers the second gate layer GA2. The first source-drain layer SD1 is disposed on a surface of the interlayer dielectric layer ILD away from the substrate SU. The passivation layer covers the first source-drain layer SD1, and the first planar layer PLN1 covers the passivation layer. Alternatively, the passivation layer may not be provided, and the first planar layer PLN1 directly covers the first source-drain layer SD1. The second source-drain layer SD2 is disposed on a surface of the first planar layer PLN1 away from the substrate SU. The second planar layer PLN2 covers the second source-drain layer SD2.

[0232] The first electrode ANO of the light emitting device LD is disposed on a surface of the second planar layer PLN2 away from the substrate SU, and can be defined by a pixel definition layer PDL. Specifically, the pixel definition layer PDL and the first electrode ANO are disposed on a surface of the second planar layer PLN2 away from the substrate SU, the pixel definition layer PDL is provided with a pixel opening exposing the first electrode ANO, and the light emitting layer EL is at least partially disposed in the pixel opening, and a range of a pixel opening is a range of a light emitting device LD.

[0233] The light emitting devices LD can be divided into multiple light emitting units. A light emitting unit includes multiple light emitting devices with different light emitting colors. For example, a light emitting unit may include a first light emitting device that emits blue light, a second light emitting device that emits red light, and a third light emitting device that emits green light. The sizes of the first light emitting device, the second light emitting device, and the third light emitting device can be different and can be distributed in a triangle. Alternatively, other distribution modes can also be used.

[0234] In some embodiments of the present disclosure, as shown in FIG. 26, an area of an orthographic projection of the first light emitting device on the substrate SU is larger than an area of an orthographic projection of the second light emitting device on the substrate SU and an area of an orthographic projection of the third light emitting device on the substrate SU. Accordingly, an area of an orthographic projection of the first electrode ANO1 of the first light emitting device on the substrate SU is larger than an area of an orthographic projection of the first electrode ANO2 of the second light emitting device on the substrate SU and an area of an orthographic projection of the first electrode ANO3 of the third light emitting device on the substrate SU. Further, the area of the orthographic projection of the second light emitting device on the substrate SU is larger than the area of the orthographic projection of the third light emitting device on the substrate SU, and accordingly, the area of the orthographic projection of the first electrode ANO2 of the second light emitting device on the substrate SU is larger than the area of the orthographic projection of the first electrode ANO3 of the third light emitting device on the substrate SU.

[0235] The following is a further description of patterns of some film layers by taking the first display panel as an example.Light shielding layer BSM

[0236] As shown in FIGS. 12-15, 23, 24, 30-31 and 38-40, the light shielding layer BSM includes the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2, which can be distributed at an interval along the column direction Y. A shape of an orthographic projection of the first plate C11 of the first capacitor C1 on the substrate SU and an orthographic projection of the first plate C21 of the second capacitor C2 on the substrate SU can be rectangular or other shapes. A width of the first plate C11 of the first capacitor C1 in the row direction X can be the same as a width of the first plate C21 of the second capacitor C2 in the row direction X.First gate layer GA1

[0237] As shown in FIGS. 12 to 18, 23, 30 to 32, and 38 to 41, the first gate layer GA1 includes the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2, which can be distributed at an interval along the column direction Y. A shape of an orthographic projection of the second plate C12 of the first capacitor C1 on the substrate SU and an orthographic projection of second plate C22 of the second capacitor C2 on the substrate SU can be rectangular or other shapes. In addition, a width of the second plate C12 of the first capacitor C1 in the row direction X can be the same as a width of the second plate C22 of the second capacitor C2 in the row direction X, and the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate SU is located within the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate SU. The orthographic projection of the second plate C22 of the second capacitor C2 on the substrate SU is located within the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate SU.

[0238] In addition, the first gate layer GA1 may further include a second auxiliary power line VSLs, and the second auxiliary power line VSLs is located on a side of the second capacitor C2 away from the first capacitor C1 and extends along the row direction X.Semiconductor layer SE

[0239] The semiconductor layer SE may include the first semiconductor portion SE1 and the second semiconductor portion SE2 distributed at an interval along the row direction X, and may also include a first auxiliary transfer portion SE3 and a second auxiliary transfer portion SE4. The specific patterns have been described above and will not be described in detail here.Second gate layer GA2

[0240] As shown in FIGS. 12, 18, 23, 30 to 32, and 38, the second gate layer GA2 further includes a first gate portion GA21, a second gate portion GA22, a third gate portion GA23, a fourth gate portion GA24, a fifth gate portion GA25, a sixth gate portion GA26, and a seventh gate portion GA27.

[0241] The first gate portion GA21 overlaps with the active portion ACT5 of the first light emitting control transistor T5 to form THE gate of the first light emitting control transistor T5. A shape of an orthographic projection of the first gate portion GA21 on the substrate SU may be rectangular, and a width of the first gate portion GA21 in the row direction X is greater than or equal to a width of the active portion ACT5 in the row direction X.

[0242] The second gate portion GA22 overlaps with the active portion ACT4 of the writing transistor T4 to form the gate of the writing transistor T4. A shape of an orthographic projection of the second gate portion GA22 on the substrate SU may be rectangular, and a width of the second gate portion GA22 in the row direction X is greater than or equal to a width of the active portion ACT4 in the row direction X.

[0243] The third gate portion GA23 overlaps with the active portion ACT3 of the driving transistor T3 and is connected to the third gate portion GA23 to form the gate of the driving transistor T3. A shape of an orthographic projection of the third gate portion GA23 on the substrate SU may be rectangular, and a width of the third gate portion GA23 in the row direction X is greater than or equal to a width of the active portion ACT3 in the row direction X. The orthographic projections of the third gate portion GA23 and the active portion ACT3 on the substrate SU are located within the orthographic projection of the second capacitor C2 on the substrate SU, and the third gate portion GA23 and one of the two plates of the second capacitor C2 close to the active portion ACT3 can both be used as the gate of the driving transistor T3, thereby forming a double-gate structure, which is beneficial to improving the stability of the gate signal. Alternatively, the driving transistor T3 may also adopt the single-gate structure, and only the third gate portion GA23 or one of the two plates of the second capacitor C2 close to the active portion ACT3 may be used as the gate, so as to simplify the structure and reduce parasitic capacitance.

[0244] The fourth gate portion GA24 overlaps with the active portion ACT1 of the first reset transistor T1 to form the gate of the first reset transistor T1. A shape of an orthographic projection of the fourth gate portion GA24 on the substrate SU may be rectangular, and a width of the fourth gate portion GA24 in the row direction X is greater than or equal to the width of the active portion ACT1 in the row direction X.

[0245] The fifth gate portion GA25 overlaps with the active portion ACT2 of the second reset transistor T2 to form the gate of the second reset transistor T2. A shape of an orthographic projection of the fifth gate portion GA25 on the substrate SU may be rectangular, and a width of the fifth gate portion GA25 in the column direction Y is greater than or equal to the width of the active portion ACT2 in the column direction Y, and a length of the fifth gate portion GA25 in the row direction X is less than the length of the second semiconductor segment SE12.

[0246] The sixth gate portion GA26 overlaps with the active portion ACT6 of the second light emitting control transistor T6 to form the gate of the second light emitting control transistor T6. A shape of an orthographic projection of the sixth gate portion GA26 on the substrate SU may be rectangular, and a width of the sixth gate portion GA26 in the row direction X is greater than or equal to a width of the active portion ACT6 in the row direction X.

[0247] The seventh gate portion GA27 overlaps with the active portion ACT3 of the third reset transistor T7 to form the gate of the third reset transistor T7. A shape of an orthographic projection of the seventh gate portion GA27 on the substrate SU may be rectangular, and a width of the seventh gate portion GA27 in the column direction Y is greater than or equal to a width of the active portion ACT3 in the column direction Y.

[0248] The first gate portion GA21, the second gate portion GA22, the third gate portion GA23, the fourth gate portion GA24, the fifth gate portion GA25, the sixth gate portion GA26 and the seventh gate portion GA27 may be distributed in sequence in the column direction Y, and the second gate portion GA22 and the fourth gate portion GA4 may be distributed along the first semiconductor segment SE11. The fifth gate portion GA25 and the sixth gate portion GA26 are located between the second capacitor C2 and the second auxiliary power line VSLs. The first gate portion GA21, the third gate portion GA23 and the sixth gate portion GA26 may be distributed along the fourth semiconductor segment SE21. The seventh gate portion GA27 is located on a side of the second auxiliary power line VSLs away from the second capacitor C2.First source-drain layer SD1

[0249] As shown in FIGS. 11, 19, 18, 22, 28, 34 and 37, the first source-drain layer SD1 may include a first auxiliary power line VDLs, a first light emitting control line EML1, a scan line GL, a first reset control line REL1, a first reset line VRL, a second reset control line REL2, a second light emitting control line EML2, a third reset control line REL3 and a second reset line VIL which are sequentially distributed along the column direction Y, and an orthographic projection of the second auxiliary power line VSLs on the substrate SU is located between orthographic projections of the second light emitting control line EML2 and the third reset control line REL3 on the substrate SU.

[0250] The first light emitting control line EML1 and the scan line GL may overlap with the first capacitor C1. The first reset control line REL1 and the first reset line VRL may overlap with the second capacitor C2. The second reset control line REL2, the second light emitting control line EML2 and the third reset control line REL3 are located on a side of the second capacitor C2 away from the first capacitor C1.

[0251] The first source-drain layer SD1 may further include a first connection portion SL1, a second connection portion SL2, a third connection portion SL3, a fourth connection portion SL4 and a fifth connection portion SL5.

[0252] The first connection portion SL1 is located between the first light emitting control line EML1 and the scan line GL, and is connected to the data line DAL and the first electrode of the writing transistor T4 through the contact hole. The data line DAL can transmit the data signal Data to the first electrode of the writing transistor T4 through the first connection portion SL1.

[0253] An orthographic projection of the second connection portion SL2 on the substrate SU is located between orthographic projections of the scan line GL and the first reset control line REL1 on the substrate SU, and is located between orthographic projections of the first semiconductor segment SE11 and the fourth semiconductor segment SE21 on the substrate SU. The second connection portion SL2 is connected to the first plate C11 of the first capacitor C1, the third gate portion GA23, and an area of the first semiconductor portion SE1 between the active portion ACT4 of the writing transistor T4 and the active portion ACT1 of the first reset transistor T1. Thus, the second connection portion SL2 can be used as a part of the node N1 to connect the first plate C11 of the first capacitor C1, the gate (top gate) of the driving transistor T3, the second electrode of the writing transistor T4 and the second electrode of the first reset transistor T1.

[0254] For example, the second connection portion SL2 may include a first connection segment SL21 and a second connection segment SL22. A first end of the first connection segment SL21 overlaps with the second plate C12 of the first capacitor C1, and a second end of the first connection segment SL21 overlaps with the second plate C22 of the second capacitor C2, and is connected to a first end of the second connection segment SL22. The second connection segment SL22 overlaps with the second plate C22 of the second capacitor C2, and a second end of the second connection segment SL22 extends toward the first semiconductor segment SE11. The second end of the first connection segment SL21 extends in a direction in which the first end of the first connection segment SL21 is away from the fourth semiconductor segment SE21, so that the first connection segment SL21 is deflected toward a side away from the active portion ACT3 of the driving transistor T3, so as not to overlap with the active portion ACT3. The second connection segment SL22 may extend along the row direction X.

[0255] The second plate C12 of the first capacitor C1 is provided with a first capacitor hole C121, and the first end of the second connection portion SL2 can be connected to the first plate C11 of the first capacitor C1 through a contact hole passing through the first capacitor hole C121. The second end of the first connection segment SL21 and the first end of the second connection portion SL2 can be connected to the third gate portion GA23 through the contact hole. The first semiconductor segment SE11 has a semiconductor connection portion SEL located between the active portion ACT4 of the writing transistor T4 and the active portion ACT1 of the first reset transistor T1, which can extend along the row direction X to a position where the semiconductor connection portion SEL overlapps with the second plate C12 of the second capacitor C2 and the second end of the second connection portion SL2, and can be connected to the second end of the second connection portion SL2 through the contact hole.

[0256] An orthographic projection of the third connection portion SL3 on the substrate SU is located between orthographic projections of the scan line GL and the first reset control line REL1 on the substrate SU, and is located between orthographic projections of the first semiconductor segment SE11 and the second connection portion SL2 on the substrate SU. The third connection portion SL3 is connected to the second electrode of the second reset transistor T2, the second plate C12 of the first capacitor C1, and the first plate C 21 of the second capacitor C2. Thus, the third connection portion SL3 can be used as a part of the node N4 to connect the second plate C12 of the first capacitor C1 and the first plate C 21 of the second capacitor C2.

[0257] In some embodiments, the third connection portion SL3 overlaps with an area of the first semiconductor portion SE1 between the active portion ACT4 of the writing transistor and the active portion ACT1 of the first reset transistor T1. For example, the third connection portion SL3 may include a third connection segment SL31, a fourth connection segment SL32, and a fifth connection segment SL33 connected in sequence.

[0258] The third connection segment SL31 is connected to the second plate C12 of the first capacitor C1 through a contact hole. The fourth connection segment SL32 can extend along the column direction Y and overlap with an area of the first semiconductor segment SE11 between the active portion ACT4 of the writing transistor and the active portion ACT1 of the first reset transistor T1. The second plate C22 of the second capacitor C2 is provided with a second capacitor hole C221, and the fifth connection segment SL33 can be connected to the first plate C21 of the second capacitor C2 through a contact hole passing through the second capacitor hole C221, thereby connecting the first capacitor C1 and the second capacitor C2 in series. In addition, the fifth connection segment SL33 can also be connected to an end of the third semiconductor segment SE13 away from the active portion ACT2 of the second reset transistor T2 through the contact hole, thereby connecting to the second electrode of the second reset transistor T2, so as to transmit the reference signal Vref.

[0259] The fourth connection portion SL4 is located between the second connection portion SL2 and the first reset control line REL1, and is connected to the second plate C22 of the second capacitor C2 and an area of the second semiconductor portion SE2 located between the active portion ACT3 of the driving transistor T3 and the active portion ACT6 of the second light emitting control transistor T6. Thus, the fourth connection portion SL4 can be used as at least a part of the node N3 to connect the second plate C22 of the second capacitor C2, the first electrode of the driving transistor T3, and the first electrode of the second light emitting control transistor T6.

[0260] The fifth connection portion SL5 is located between the second light emitting control line EML2 and the third reset control line REL3, and is connected to an area of the second semiconductor portion SE2 on a side of the active portion ACT6 of the second light emitting control transistor 6 away from the active portion ACT3 of the driving transistor T3, that is, connected to the second electrode of the second light emitting control transistor 6. In addition, the fifth connection portion SL5 can be connected to the first electrode ANO of the light emitting device LD through a contact hole. The fifth connection portion SL5 can be used as at least a portion of the node N6 to play the role of connection.

[0261] In some embodiments of the present disclosure, the first source-drain layer SD1 may further include a sixth connection portion SL6. The sixth connection portion SL6 overlaps with the third gate portion GA23, and the sixth connection portion SL6 overlaps with the active portion ACT3 of the driving transistor T3. An orthographic projection of the active portion ACT3 of the driving transistor T3 on the substrate SU is located within an orthographic projection of the sixth connection portion SL6 on the substrate SU, so that the gate of the driving transistor T3 can be shielded by the sixth connection portion SL6. However, the sixth connection portion SL6 is spaced apart the second connection portion SL2. In addition, the sixth connection portion SL6 can be connected to the first power line VDL through the contact hole, so that a constant first power signal VDD can be input to the sixth connection portion SL6 to shield the interference of other signals on the signal at the node N1. Alternatively, the sixth connection portion SL6 can also be connected to the second power signal VSS or other constant signals, which is not specifically limited here.

[0262] As shown in FIG. 28 and FIG. 29, in some embodiments of the present disclosure, the first source-drain layer SD1 may further include a seventh connection portion SL7, an eighth connection portion SL8, and a ninth connection portion SL9.

[0263] The seventh connection portion SL7 is located between the second light emitting control line EML2 and the third reset control line REL3, and is connected to the second auxiliary power line VSLs and the second power line VSL through a contact hole.

[0264] The eighth connection portion SL8 is located between the second light emitting control line EML2 and the third reset control line REL3, and is connected to the first auxiliary transfer portion SE 3 and the first auxiliary reset line VRLs through a contact hole.

[0265] The ninth connection portion SL9 is located between the second light emitting control line EML2 and the third reset control line REL3, and is connected to the second auxiliary transfer portion SE 4 and the second auxiliary reset line VILs through the contact hole.

[0266] The first auxiliary power line VDLs can be connected to, through a contact hole, an end of the second semiconductor portion SE2 on a side of the active portion ACT5 of the first light emitting control transistor T5 away from the active portion ACT3 of the driving transistor T3, thereby connecting the first auxiliary power line VDLs to the first electrode of the first light emitting control transistor T5 to transmit the first power signal VDD. In addition, a first auxiliary power line VDLs is also connected to the first electrode of the first light emitting control transistor T5 of the same row of pixel circuits.

[0267] The first light emitting control line EML1 can be connected to the first gate portion GA21 through the contact hole to transmit the first light emitting control signal EM1 to the gate of the first light emitting control transistor T5. A first light emitting control line EML1 is also connected to the first gate portion GA21 of the same row of pixel circuits, that is, connected to the gate of the first light emitting control transistor T5 of the same row of pixel circuits.

[0268] The scan line GL can also be connected to the second gate portion GA22 through the contact hole, and can transmit the scan signal Gate to the gate of the writing transistor T4. A scan line GL is also connected to the second gate portion GA22 of the same row of pixel circuits, that is, connected to the gate of the same row of writing transistors T3.

[0269] The first reset control line REL1 can also be connected to the fourth gate portion GA24 through the contact hole, and can transmit the first reference control signal RE1 to the gate of the first reset transistor T1. A first reset control line REL1 is also connected to the fourth gate portion GA24 of the same row of pixel circuits, that is, connected to the gate of the first reset transistor T1 of the same row of pixel circuits.

[0270] The second reset control line REL2 can also be connected to the fifth gate portion GA25 through the contact hole, and can transmit the second reference control signal RE 2 to the gate of the second reset transistor T2. A second reset control line REL2 is also connected to the fifth gate portion GA25 of the same row of pixel circuits, that is, connected to the gate of the second reset transistor T2 of the same row of pixel circuits.

[0271] The second light emitting control line EML2 can be connected to the sixth gate portion GA26 through the contact hole to transmit the second light emitting control signal EM2 to the gate of the second light emitting control transistor T6. A second light emitting control line EML2 is also connected to the sixth gate portion GA26 of the same row of pixel circuits, that is, connected to the gate of the second light emitting control transistor T6 of the same row of pixel circuits.

[0272] The third reset control line REL3 is connected to the seventh gate portion GA27 through a contact hole to transmit the reset control signal RE3 to the gate of the third reset transistor T7. A third reset control line REL3 is also connected to the seventh gate portion GA27 of the same row of pixel circuits, that is, connected to the gate of the third reset transistor T7 of the same row of pixel circuits.

[0273] As shown in FIGS. 27 and 28, the first reset line VRL can be connected to, through the contact hole, an area of the first semiconductor segment SE11 on a side of the active portion ACT1 of the first reset transistor T1 close to the second semiconductor segment SE12, thereby being connected to the first electrodes of both the first reset transistor T1 and the second reset transistor T2, and the reference signal Vref can be transmitted to both the first reset transistor T1 and the second reset transistor T2 through the first reset line V RL.

[0274] The second reset line VIL may be connected to an end of the fifth semiconductor segment SE22 away from the driving transistor T3 through a contact hole, thereby being connected to a first electrode of the third reset transistor T7 to transmit a reset signal Vinit.Second source-drain layer SD2

[0275] As shown in FIGS. 10, 20, 21, 26, 27, 35, and 36, the second source-drain layer SD2 may include a first power line VDL, a second power line VSL, a first auxiliary reset line VRLs and a second auxiliary reset line VILs. The specific pattern has been described in detail above and will not be described in detail here.

[0276] In addition, the second source-drain layer SD2 may further include an electrode transfer portion S1, which may be located between two column line groups YG and connected to the fifth connection portion SL through a contact hole. The first electrode ANO of the light emitting device LD may be connected to the electrode transfer portion S1 through the contact hole.

[0277] As shown in FIG. 26, the first electrode ANO of the light emitting device LD may block active portions of some transistor.

[0278] For example, among pixel circuits in the i-th column to the i+2-th column and the j-th row to the j+1-th row, for the same light emitting unit, the first electrode ANO1 of the first light emitting device is connected to, through the electrode transfer portion S1, the second electrode of the second light emitting control transistor T6 of the pixel circuit in the i+2-th column and the j-th row, and the first electrode ANO1 overlaps with the active portions ACT3 of the driving transistors T3 of the pixel circuits in the j-th row and the i-th and i+1-th columns, which can play a light-shielding role, but does not overlap with the active portions ACT3 of the driving transistors T3 of the pixel circuits in the i+2 column.

[0279] The first electrode ANO2 of the second light emitting device is connected to, through the electrode transfer portion S1, the second electrode of the second light emitting control transistor T6 of the pixel circuit in the i-th column and the j-th row, and the first electrode ANO2 overlaps with the active portion ACT5 of the first light emitting control transistor T5 of the pixel circuit in the i-th column and the j+1-th row, which can play a light-shielding role. The first electrode ANO3 of the third light emitting device is connected to, through the electrode transfer portion S1, the second electrode of the second light emitting control transistor T6 of the pixel circuit in the i+1-th column and the j-th row, and the first electrode ANO3 overlaps with the active portion ACT5 of the first light emitting control transistor T5 of the pixel circuit in the i+1-th column and the j+1-th row, which can play a light-shielding role.

[0280] An exemplary description of some film layers of the second display panel is given below.

[0281] As shown in FIGS. 36 to 40, the light shielding layer BSM may include the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2, and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 may be connected as an integrated structure, that is, not discontinuous, which can reduce the connection structure and simplify the preparation process. A shape of the integrated structure on the substrate SU can be rectangular. Alternatively, other shapes are also possible.

[0282] As shown in FIGS. 38 to 41, the first gate layer GA1 may include the first plate C11 of the first capacitor C1 and the second plate C22 of the second capacitor C2, which may be distributed at an interval along the column direction Y. A shape of an orthographic projection of the second plate C12 of the first capacitor C1 on the substrate SU and an orthographic projection of the second plate C22 of the second capacitor C2 on the substrate SU may be rectangular, or may be other shapes. In addition, a width of the second plate C12 of the first capacitor C1 in the row direction X may be the same as a width of the second plate C22 of the second capacitor C2 in the row direction X, and the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate SU and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate SU are located within an orthographic projection of the integrated structure of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 on the substrate SU.

[0283] The first gate layer GA1 may further include a second auxiliary power line VSLs, which may be disposed on a side of the second capacitor C2 away from the first capacitor C1.

[0284] As shown in FIGS. 38, 39 and 42, the semiconductor layer SE may include a first semiconductor portion SE1 and a second semiconductor portion SE2 distributed at an interval along the row direction X, and the second semiconductor portion SE2 may include a fourth semiconductor segment SE21 and a fifth semiconductor segment SE22. For the specific patterns of the first semiconductor portion SE1 and the fourth semiconductor segment SE21, reference may be made to the patterns of the first semiconductor portion SE1 and the fourth semiconductor segment SE21 of the first display panel described above, which will not be described in detail herein.

[0285] The fifth semiconductor segment SE22 may extend closer to the first semiconductor portion SE1, and may be connected to an area of the fourth semiconductor segment SE21 located between the active portion ACT3 of the driving transistor T3 and the active portion ACT6 of the second light emitting control transistor T6.

[0286] For example, the fifth semiconductor segment SE22 may include a first sub-segment and a second sub-segment connected in sequence. The first sub-segment is located on a side of the fourth semiconductor segment SE21 close to the first semiconductor portion SE1 and may extend along the row direction X. The first sub-segment is connected to an area of the fourth semiconductor segment SE21 between the active portion ACT3 of the driving transistor T3 and the active portion ACT6 of the second light emitting control transistor T6, and the first sub-segment overlaps with the third reset control line REL3. The second sub-segment may extend along the column direction Y and may be connected to the first sub-segment. The active portion ACT3 of the third reset transistor T7 is located in the second sub-segment.

[0287] As shown in FIGS. 37 and 38, the second gate layer GA2 may include a first gate portion GA21, a second gate portion GA22, a third gate portion GA23, a fourth gate portion GA24, a fifth gate portion GA25, a sixth gate portion GA26 and a seventh gate portion GA27.

[0288] The first gate portion GA21 overlaps with the active portion ACT5 of the first light emitting control transistor T5 to form the gate of the first light emitting control transistor T5. A shape of an orthographic projection of the first gate portion GA21 on the substrate SU may be rectangular, and a width of the first gate portion GA21 in the row direction X is greater than or equal to a width of the active portion ACT5 in the row direction X.

[0289] The second gate portion GA22 overlaps with the active portion ACT4 of the writing transistor T4 to form the gate of the writing transistor T4. A shape of an orthographic projection of the second gate portion GA22 on the substrate SU may be rectangular, and a width of the second gate portion GA22 in the row direction X is greater than or equal to a width of the active portion ACT4 in the row direction X.

[0290] The third gate portion GA23 overlaps with the active portion ACT3 of the driving transistor T3 and is connected to the third gate portion GA23 to form the gate of the driving transistor T3. For example, the third gate portion GA23 may include a gate portion GA231 and a gate extension portion GA232. The gate portion GA231 may extend along the row direction X and overlap with the active portion ACT3, and may serve as the gate of the driving transistor T3. The gate extension portion GA232 may extend along the column direction Y and overlap with the first plate C11 of the first capacitor, and may be connected to the first plate C11 of the first capacitor C1 through the contact hole, which may reduce the connection structure and simplify the manufacturing process. Orthographic projections of the gate portion GA231 and the active portion ACT3 on the substrate SU are located within an orthographic projection of the second capacitor C2 on the substrate SU, and both the third gate portion GA23 and one of the two plates of the second capacitor C2 close to the active portion ACT3 can be used as the gate of the driving transistor T3, thereby forming a double-gate structure, which is beneficial to improving the stability of the gate signal. For example, the third gate portion GA23 is used as the top gate of the driving transistor T3, and the second plate C22 of the second capacitor C2 is used as the bottom gate of the driving transistor T3, thereby forming the double-gate structure, and the second plate C22 can be connected to the source (first electrode) of the driving transistor T3 when used as the bottom gate, to ensure the stability of the saturation region of the driving transistor T3. Alternatively, the driving transistor T3 can also adopt a single-gate structure, and only the third gate portion GA23 or one of the two plates of the second capacitor C2 close to the active portion ACT3 can be used as the gate, so as to simplify the structure and reduce parasitic capacitance.

[0291] The fourth gate portion GA24 overlaps with the active portion ACT1 of the first reset transistor T1 to form the gate of the first reset transistor T1. A shape of an orthographic projection of the fourth gate portion GA24 on the substrate SU may be rectangular, and a width of the fourth gate portion GA24 in the row direction X is greater than or equal to the width of the active portion ACT1 in the row direction X.

[0292] The fifth gate portion GA25 overlaps with the active portion ACT2 of the second reset transistor T2 to form the gate of the second reset transistor T2. A shape of an orthographic projection of the fifth gate portion GA25 on the substrate SU may be rectangular, and a width of the fifth gate portion GA25 in the column direction Y is greater than or equal to the width of the active portion ACT2 in the column direction Y, and a length of the fifth gate portion GA25 in the row direction X is less than the length of the second semiconductor segment SE12.

[0293] The sixth gate portion GA26 overlaps with the active portion ACT6 of the second light emitting control transistor T6 to form the gate of the second light emitting control transistor T6. A shape of an orthographic projection of the sixth gate portion GA26 on the substrate SU may be rectangular, and a width of the sixth gate portion GA26 in the row direction X is greater than or equal to a width of the active portion ACT6 in the row direction X.

[0294] The seventh gate portion GA27 overlaps with the active portion ACT3 of the third reset transistor T7 to form the gate of the third reset transistor T7. A shape of an orthographic projection of the seventh gate portion GA27 on the substrate SU may be rectangular, and a width of the seventh gate portion GA27 in the column direction Y is greater than or equal to a width of the active portion ACT3 in the column direction Y.

[0295] As shown in FIGS. 36 and 37, the first source-drain layer SD1 may include a first auxiliary power line VDLs, a first light emitting control line EML1, a scan line GL, a first reset control line REL1, a first reset line VRL, a second reset control line REL2, a second light emitting control line EML2, a third reset control line REL3 and a second reset line VIL, which extend along the row direction X and are sequentially distributed along the column direction Y. An orthographic projection of the second auxiliary power line VSLs on the substrate SU is located between orthographic projections of the second light emitting control line EML2 and the third reset control line REL3 on the substrate SU.

[0296] The first source-drain layer SD1 may further include a first connection portion SL1, a second connection portion SL2, a third connection portion SL3, a fourth connection portion SL4, a fifth connection portion SL5, a sixth connection portion SL6 and a seventh connection portion SL7.

[0297] The first connection portion SL1 is located between the first light emitting control line EML1 and the scan line GL, and is connected to the data line DAL and the first electrode of the writing transistor T4 through the contact hole. The data line DAL can transmit the data signal Data to the first electrode of the writing transistor T4 through the first connection portion SL1.

[0298] An orthographic projection of the second connection portion SL2 on the substrate SU is located between orthographic projections of the scan line GL and the first reset control line REL1 on the substrate SU, and the second connection portion SL2 overlaps with the first plate C11 of the first capacitor C1. The second connection portion SL2 can be connected to the gate extension portion GA232 of the third gate portion GA23 and the first plate C11 of the first capacitor C1 through the contact hole, thereby connecting the first plate C11 to the gate of the driving transistor T3.

[0299] The third connection portion SL3 can be connected to, through the contact hole, the gate extension portion GA 232 of the third gate portion GA23 and an area of the first semiconductor portion SE1 between the active portion ACT4 of the writing transistor T4 and the active portion ACT1 of the first reset transistor T1. Thus, the third connection portion SL3 and the second connection portion SL2 can be used as at least a part of the node N1 to connect the first electrode C11 of the first capacitor C1, the gate (top gate) of the driving transistor T3, and the second electrode of the writing transistor T4 and the second electrode of the first reset transistor T1.

[0300] An orthographic projection of the fourth connection portion SL4 on the substrate SU is between orthographic projections of the scan line GL and the first reset control line REL1 on the substrate SU. The fourth connection portion SL4 can be connected to the second electrode of the second reset transistor T2 and the first plate C 21 of the second capacitor C2 through the contact hole. In addition, in order to facilitate the connection with the first plate C21, the first plate C21 can be provided with a capacitor hole or a notch, so that the fourth connection portion SL4 can be connected to the first plate C21 of the second capacitor C2 through the contact hole passing through the capacitor hole or the notch. Thus, the fourth connection portion SL4 can be used as at least a part of the node N4 to connect to the first plate C21 of the second capacitor C2. The second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are an integral structure, so there is no need for a special connection.

[0301] The fifth connection portion SL5 is located between the second connection portion SL2 and the first reset control line REL1, and is connected to the second plate C22 of the second capacitor C2 and an area of the second semiconductor portion SE2 between the active portion ACT3 of the driving transistor T3 and the active portion ACT6 of the second light emitting control transistor T6. Thus, the fifth connection portion SL5 can be used as at least a part of the N3 node to connect the second plate C22 of the second capacitor C2, the first electrode of the driving transistor T3, and the first electrode of the second light emitting control transistor T6. In addition, the second plate C22, as a part of the bottom gate of the driving transistor T3, can be connected to the first electrode (source) of the driving transistor T3 to ensure the stability of the saturation region of the driving transistor T3.

[0302] The sixth connection portion SL6 is located between the second light emitting control line EML2 and the second reset line VIL, and is connected to an area of the second semiconductor portion SE2 on a side of the active portion ACT6 of the second light emitting control transistor T6 away from the active portion ACT3 of the driving transistor T3, that is, connected to the second electrode of the second light emitting control transistor T6. In addition, the sixth connection portion SL6 can be connected to the first electrode ANO of the light emitting device LD through the contact hole.

[0303] The seventh connection portion SL7 is located between the second light emitting control line EML2 and the second reset line VIL, and is connected to the second auxiliary power line VSLs through the contact hole. In addition, the seventh connection portion SL7 is connected to the second power line VSL through the contact hole.

[0304] As shown in FIG. 36, the second source-drain layer SD2 may include the data line DAL and the second power line VSL, and may further include:

[0305] The data line DAL overlaps with the first connection portion SL1, and the data line DAL can be connected to the first connection portion SL1 through the contact hole, so as to transmit the data signal Data to the first electrode of the writing transistor T4 through the first connection portion SL1. The data line DAL is located on a side of the first semiconductor portion SE1 away from the second semiconductor portion SE2, and does not overlap with the writing transistor T4 and the first reset transistor T1 of the pixel circuit connected to the data line DAL, but can overlap with the active portion ACT3 of the driving transistor T3 of the pixel circuit adjacent to the data line DAL. The data line DAL can be away from the node N3 (the fifth connection portion SL5), so that the voltage of the node N3 is more stable.

[0306] The second power line VSL may extend along the column direction Y, and overlap with the second connection portion SL2, the third connection portion SL3, and the fourth connection portion SL4, and may play a shielding role through the constant second power signal VSS of the second power line VSL, which is beneficial to ensure that the voltages of the node N1 and the node N4 are not interfered. The second power line VSL is connected to the second auxiliary power line VSLs through a contact hole, and the second power line VSL and the second auxiliary power line VSLs may form a network for transmitting the second power signal VSS in space, which is beneficial to reducing resistance. Alternatively, in some embodiments of the present disclosure, the second power line VSL or the second auxiliary power line VSLs may not be provided, as long as the second power signal VSS can be transmitted.

[0307] In some embodiments of the present disclosure, multiple first auxiliary reset lines VRLs and multiple second auxiliary reset lines VILs may also be included. The first auxiliary reset lines VRLs and the first reset lines VRL are connected through contact holes to form a mesh structure, and the second auxiliary reset lines VILs and the second reset lines VIL are connected through contact holes to form a mesh structure, which are beneficial to reducing resistance.

[0308] Furthermore, the second source-drain layer SD2 may further include an electrode transfer portion S1, which may be connected to the sixth connection portion SL6 through a contact hole, and the first electrode ANO of the light emitting device LD may be connected to the electrode transfer portion S1 through the contact hole, thereby connecting the first electrode ANO to the second electrode of the second light emitting control transistor T6.

[0309] In addition, in some embodiments of the present disclosure, the above embodiments may also be adopted to divide the display panel into multiple column line groups YG and multiple row line groups, and the data line DAL, the second power line VSL, the first auxiliary reset line VRLs and the second auxiliary reset line VILs are arranged in a manner similar to the above embodiments, which will not be repeated here.

[0310] The present disclosure further provides a display device, and the display device may include a display panel, which is the display panel of any of the above embodiments, and its specific structure and beneficial effects can refer to the embodiments of the display panel above, which will not be described in detail here. The display device of the present disclosure can be a mobile phone, a tablet computer, a television, or an electronic device with a display function such as a smart watch, smart glasses, and a car display, which will not be listed one by one here.

[0311] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the present disclosure disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present disclosure, which are in accordance with the general principles of the present disclosure and include common general knowledge or conventional technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are illustrative, and the real scope and spirit of the present disclosure is defined by the appended claims.

Claims

1. A pixel circuit, comprising a driving transistor, an energy storage circuit, a writing circuit and a first light emitting control circuit; a gate of the driving transistor is connected to a first electrode of the driving transistor through the energy storage circuit, the first electrode of the driving transistor is configured to be connected to a light emitting device, and a second electrode of the driving transistor is connected to the first light emitting control circuit, and the first light emitting control circuit is configured to receive a first power signal; and the writing circuit is connected to the gate of the driving transistor, the writing circuit is connected to the first electrode of the driving transistor through the energy storage circuit, the writing circuit is configured to write a data signal to the energy storage circuit, and the energy storage circuit is configured to store the data signal and a voltage of the first electrode of the driving transistor.

2. The pixel circuit according to claim 1, wherein the energy storage circuit comprises a first capacitor and a second capacitor, the writing circuit comprises a writing transistor, and the first light emitting control circuit comprises a first light emitting control transistor; a first electrode of the writing transistor is configured to input the data signal, and a second electrode of the writing transistor is connected to the gate of the driving transistor and a first plate of the first capacitor; a second plate of the first capacitor is connected to a first plate of the second capacitor, and a second plate of the second capacitor is connected to the first electrode of the driving transistor; and a first electrode of the first light emitting control transistor is configured to input the first power signal, and a second electrode of the first light emitting control transistor is connected to the second electrode of the driving transistor.

3. The pixel circuit according to claim 2, wherein the pixel circuit further comprises: a first reset transistor, wherein a first electrode of the first reset transistor is configured to receive a reference signal, and a second electrode of the first reset transistor is connected to the gate of the driving transistor; and a second reset transistor, wherein a first electrode of the second reset transistor is configured to receive the reference signal, and a second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor.

4. The pixel circuit according to claim 3, wherein the pixel circuit further comprises: a third reset transistor, wherein a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the second plate of the second capacitor.

5. The pixel circuit according to claim 3, wherein the pixel circuit further comprises a second light emitting control circuit, and the first electrode of the driving transistor is connected to the light emitting device through the second light emitting control circuit.

6. The pixel circuit according to claim 5, wherein the second light emitting control circuit comprises a second light emitting control transistor, a first electrode of the second light emitting control transistor is connected to the first electrode of the driving transistor, and a second electrode of the second light emitting control transistor is connected to the light emitting device; and the pixel circuit further comprises: a third reset transistor, wherein a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the second electrode of the second light emitting control transistor.

7. The pixel circuit according to claim 6, wherein at least one of the driving transistor, the writing transistor, the first reset transistor, the second reset transistor, the third reset transistor, the first light emitting control transistor, and the second light emitting control transistor is a metal oxide transistor.

8. A display panel, comprising a plurality of pixel circuits arranged in an array along a row direction and a column direction, wherein the pixel circuit comprises a plurality of transistors, a first capacitor and a second capacitor, and individual transistors comprises a driving transistor, a writing transistor, a first light emitting control transistor, a second light emitting control transistor, a first reset transistor, a second reset transistor and a third reset transistor; a first electrode of the first light emitting control transistor is configured to receive a first power signal, and a second electrode of the first light emitting control transistor is connected to a second electrode of the driving transistor; a first electrode of the writing transistor is configured to receive a data signal, a second electrode of the writing transistor is connected to a first plate of the first capacitor and a gate of the driving transistor, a second plate of the first capacitor is connected to a first plate of the second capacitor, and a second plate of the second capacitor is connected to a first electrode of the driving transistor; a first electrode of the second light emitting control transistor is connected to the first electrode of the driving transistor; a first electrode of the first reset transistor and a first electrode of the second reset transistor are configured to receive a reference signal, a second electrode of the first reset transistor is connected to the gate of the driving transistor, and a second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor; a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the first electrode of the driving transistor or the second electrode of the second light emitting control transistor; the display panel comprises: a substrate; a semiconductor layer, disposed on a side of the substrate and comprising an active portion of each of the transistors; a plurality of light emitting devices, disposed on a side of the semiconductor layer away from the substrate, wherein a light emitting device is connected to a second electrode of a second light emitting control transistor of a pixel circuit; and one of the first plate and the second plate of the first capacitor is disposed in the same layer as one of the first plate and the second plate of the second capacitor, and one of the first capacitor and the second capacitor is overlapped with an active portion of the driving transistor.

9. The display panel according to claim 8, wherein the semiconductor layer comprises a first semiconductor portion and a second semiconductor portion distributed at an interval along the row direction; and active portions of the writing transistor, the first reset transistor and the second reset transistor are located in the first semiconductor portion and are connected in sequence, and active portions of the first light emitting control transistor, the driving transistor, the second light emitting control transistor and the third reset transistor are located in the second semiconductor portion and are connected in sequence.

10. The display panel according to claim 9, wherein the first plate of the first capacitor and the first plate of the second capacitor are disposed in the same layer and are distributed at an interval along the column direction; the second plate of the first capacitor and the second plate of the second capacitor are disposed in the same layer and are distributed at an interval along the column direction; and the first plate and the second plate of the second capacitor are overlapped with the active portion of the driving transistor.

11. The display panel according to claim 9, wherein the first plate of the first capacitor and the second plate of the second capacitor are disposed in the same layer and are distributed at an interval along the column direction; the second plate of the first capacitor and the first plate of the second capacitor are disposed in the same layer and are connected into an integrated structure; and the first plate and the second plate of the second capacitor are overlapped with the active portion of the driving transistor.

12. The display panel according to claim 8, wherein an active portion of the first light emitting control transistor is overlapped with the first plate and the second plate of the first capacitor.

13. The display panel according to claim 10, wherein the first semiconductor portion comprises a first semiconductor segment, a second semiconductor segment and a third semiconductor segment; the first semiconductor segment and the third semiconductor segment are extended along the column direction and are distributed at an interval along the row direction, and the second semiconductor segment is connected to the first semiconductor segment and the third semiconductor segment; the active portions of the writing transistor and the first reset transistor are located in the first semiconductor segment, the active portion of the second reset transistor is located in the second semiconductor segment, and the third semiconductor segment is connected to the first plate of the second capacitor.

14. The display panel according to claim 13, wherein the second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the first electrode of the second light emitting control transistor; the second semiconductor portion comprises a fourth semiconductor segment and a fifth semiconductor segment, the fourth semiconductor segment is extended along the column direction and is located on a side of the third semiconductor segment away from the first semiconductor segment, and the active portions of the first light emitting control transistor, the driving transistor and the second light emitting control transistor are sequentially distributed in the fourth semiconductor segment along the column direction; and the fifth semiconductor segment is connected to an area of the fourth semiconductor segment between the active portion of the driving transistor and the active portion of the second light emitting control transistor, and the active portion of the third reset transistor is located in the fifth semiconductor segment.

15. The display panel according to claim 13, wherein the second electrode of the third reset transistor is connected to the second electrode of the second light emitting control transistor and the light emitting device; the second semiconductor portion comprises a fourth semiconductor segment and a fifth semiconductor segment, the fourth semiconductor segment is extended along the column direction and is located on a side of the third semiconductor segment away from the first semiconductor segment, and the active portions of the first light emitting control transistor, the driving transistor and the second light emitting control transistor are sequentially distributed in the fourth semiconductor segment along the column direction; and the fifth semiconductor segment is connected to an area of the fourth semiconductor segment on a side of the active portion of the second light emitting control transistor away from the active portion of the driving transistor, and the active portion of the third reset transistor is located in the fifth semiconductor segment.

16. The display panel according to claim 10, wherein the display panel further comprises a first light emitting control line, a scan line, a first reset control line, a first reset line, a second reset control line, a second light emitting control line, a third reset control line and a second reset line sequentially distributed at intervals along the column direction; the first light emitting control line is extended along the row direction, is connected to a gate of the first light emitting control transistor, and is configured to transmit a first light emitting control signal, and the first light emitting control line is overlapped with the first capacitor; the scan line is extended along the row direction, is connected to a gate of the writing transistor, and is configured to transmit a scan signal, and the scan line is overlapped with the first capacitor; the first reset control line is extended along the row direction, is connected to a gate of the first reset transistor, and is configured to transmit a first reference control signal, and the first reset control line is overlapped with the second capacitor; the first reset line is extended along the row direction, is connected to first electrodes of the first reset transistor and the second reset transistor, and is configured to transmit the reference signal, and the first reset line is overlapped with the second capacitor; the second reset control line is extended along the row direction, is connected to a gate of the second reset transistor, and is configured to transmit a second reference control signal; the second light emitting control line is extended along the row direction, is connected to a gate of the second light emitting control transistor, and is configured to transmit a second light emitting control signal; the third reset control line is extended along the row direction, is connected to a gate of the third reset transistor, and is configured to transmit a reset control signal; the second reset line is extended along the row direction, is connected to the first electrode of the third reset transistor, and is configured to transmit the reset signal; an orthographic projection of the active portion of the driving transistor on the substrate is located between orthographic projections of the scan line and the first reset control line on the substrate; an orthographic projection of the active portion of the first reset transistor on the substrate is located between orthographic projections of the scan line and the first reset line on the substrate; an orthographic projection of the active portion of the second reset transistor on the substrate is located between orthographic projections of the first reset line and the second light emitting control line on the substrate; and an orthographic projection of the active portion of the third reset transistor on the substrate is located between orthographic projections of the second light emitting control line and the second reset line on the substrate.

17. The display panel according to claim 16, wherein the display panel further comprises: a plurality of first auxiliary power lines, extended along the row direction and distributed along the column direction, wherein a first auxiliary power line is disposed between two adjacent rows of pixel circuits, and the first auxiliary power line is connected to a first electrode of a first light emitting control transistor of a pixel circuit on a side of the first auxiliary power line; a plurality of first power lines, disposed on a side of the first auxiliary power lines away from the substrate, wherein individual first power lines are extended along the column direction and are distributed at intervals along the row direction, a first power line is connected to individual first auxiliary power lines and is overlapped with a column of pixel circuits, and the first power lines and the first auxiliary power lines are configured to transmit the first power signal; and a plurality of data lines, disposed on the side of the first auxiliary power lines away from the substrate, wherein individual data lines are extended along the column direction and are distributed at intervals along the row direction, and a data line is connected to first electrodes of writing transistors of a column of pixel circuits and is configured to transmit the data signal.

18. The display panel according to claim 17, wherein the display panel further comprises: a second auxiliary power line, extended along the row direction, distributed along the column direction, and configured to transmit a second power signal, wherein an orthographic projection of the second auxiliary power line on the substrate is located between orthographic projections of the second light emitting control line and the third reset control line on the substrate.

19. The display panel according to claim 18, wherein the display panel further comprises: a plurality of second power lines, a plurality of first auxiliary reset lines, and a plurality of second auxiliary reset lines, extended along the column direction and distributed along the row direction, and disposed on the side of the first auxiliary power lines away from the substrate, wherein the second power line is connected to the second auxiliary power line, the first auxiliary reset line is connected to the first reset line, and the second auxiliary reset line is connected to the second reset line; a first power line and a data line connected to pixel circuits in the same column are defined as a column line group, and the first power line and the data line of the column line group are provided with one of the second power line, the first auxiliary reset line and the second auxiliary reset line; and the light emitting device has a first electrode and a second electrode distributed in a direction away from the substrate, the first electrode is connected to the second electrode of the second light emitting control transistor, and the second electrode is connected to the second power line and the second auxiliary power line.

20. The display panel according to claim 19, wherein the semiconductor layer further comprises a first auxiliary transfer portion and a second auxiliary transfer portion; the first auxiliary transfer portion is connected to an area of a first semiconductor portion of a pixel circuit between the active portion of the first reset transistor and the active portion of the second reset transistor, and the first auxiliary reset line is connected to the first auxiliary transfer portion; and the second auxiliary transfer portion is connected to an area of a second semiconductor portion of a pixel circuit on a side of the active portion of the third reset transistor away from the active portion of the second light emitting control transistor, and the second auxiliary reset line is connected to the second auxiliary transfer portion.

21. The display panel according to claim 20, wherein the display panel further comprises: a light shielding layer, disposed on the side of the substrate, and comprising the first plate of the first capacitor and the first plate of the second capacitor; a first gate layer, disposed on a side of the light shielding layer away from the substrate, and comprising the second plate of the first capacitor, the second plate of the second capacitor and the second auxiliary power line, wherein the semiconductor layer is disposed on a side of the first gate layer away from the substrate; a second gate layer, disposed on the side of the semiconductor layer away from the substrate and overlapped with the active portion of each of the transistors; a first source-drain layer, disposed on a side of the second gate layer away from the substrate, and comprising the first auxiliary power line, the first light emitting control line, the scan line, the first reset control line, the first reset line, the second reset control line, the second light emitting control line, the third reset control line and the second reset line; and a second source-drain layer, disposed on a side of the first source-drain layer away from the substrate, and comprising the data line, the first power line, the second power line, the first auxiliary reset line and the second auxiliary reset line.

22. The display panel according to claim 21, wherein the second gate layer further comprises: a first gate portion, overlapped with the active portion of the first light emitting control transistor to form the gate of the first light emitting control transistor, wherein the first gate portion is connected to the first light emitting control line; a second gate portion, overlapped with the active portion of the writing transistor to form the gate of the writing transistor, wherein the second gate portion is connected to the scan line; a third gate portion, overlapped with the active portion of the driving transistor and connected to the third gate portion to form the gate of the driving transistor; a fourth gate portion, overlapped with the active portion of the first reset transistor to form the gate of the first reset transistor, wherein the fourth gate portion is connected to the first reset control line; a fifth gate portion, overlapped with the active portion of the second reset transistor to form the gate of the second reset transistor, wherein the fifth gate portion is connected to the second reset control line; a sixth gate portion, overlapped with the active portion of the second light emitting control transistor to form the gate of the second light emitting control transistor, wherein the sixth gate portion is connected to the second light emitting control line; and a seventh gate portion, overlapped with the active portion of the third reset transistor to form the gate of the third reset transistor, wherein the seventh gate portion is connected to the third reset control line.

23. The display panel according to claim 22, wherein the first source-drain layer further comprises: a first connection portion, located between the first light emitting control line and the scan line, and connected to the data line and an area of the first semiconductor portion on a side of the active portion of the writing transistor away from the active portion of the first reset transistor; a second connection portion, located between the scan line and the first reset control line, and connected to the first plate of the first capacitor, the third gate portion, and an area of the first semiconductor portion between the active portion of the writing transistor and the active portion of the first reset transistor; a third connection portion, located between the scan line and the first reset control line, and connected to the second plate of the first capacitor, the first plate of the second capacitor, and the second electrode of the second reset transistor; a fourth connection portion, located between the second connection portion and the first reset control line, and connected to the second plate of the second capacitor and an area of the second semiconductor portion between the active portion of the driving transistor and the active portion of the second light emitting control transistor; and a fifth connection portion, located between the second light emitting control line and the third reset control line and connected to an area of the second semiconductor portion on a side of the active portion of the second light emitting control transistor away from the active portion of the driving transistor.

24. The display panel according to claim 23, wherein the first source-drain layer further comprises: a sixth connection portion, overlapped with the third gate portion and the active portion of the driving transistor and connected to the first power line.

25. The display panel according to claim 23, wherein the first source-drain layer further comprises: a seventh connection portion, located between the second light emitting control line and the third reset control line, and connected to the second auxiliary power line and the second power line; an eighth connection portion, located between the second light emitting control line and the third reset control line, and connected to the first auxiliary transfer portion and the first auxiliary reset line; and a ninth connection portion, located between the second light emitting control line and the third reset control line, and connected to the second auxiliary transfer portion and the second auxiliary reset line.

26. The display panel according to claim 23, wherein the first power line is overlapped with a second connection portion.

27. The display panel of claim 23, wherein one of the second power line, the first auxiliary reset line and the second auxiliary reset line is overlapped with at least a partial area of the active portion of the writing transistor, the active portion of the first reset transistor, and the third connection portion.

28. The display panel according to any one of claims 8 to 27, wherein a material of the semiconductor layer comprises a metal oxide.

29. A display device, comprising the display panel according to any one of claims 8 to 28.

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