Motherboard and array substrate

Abstract

The application provides a mother board, and relates to the technical field of display. The mother board comprises a substrate and a plurality of structure layers which are arranged in a stack on the substrate, at least one of the plurality of structure layers is provided with an alignment mark, the alignment mark is configured to provide a position reference when a next structure layer is processed, and a normal projection of the alignment mark on the substrate is an alignment pattern, the alignment pattern comprises a plurality of alignment lines, and an included angle between two alignment lines connected to each other is greater than 90 degrees. The identification accuracy of the alignment mark is high during processing.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a motherboard and an array substrate. Background Technology

[0002] A display panel consists of multiple stacked structural layers, and each layer needs to be processed layer by layer during the manufacturing process. To ensure the positional accuracy of adjacent structural layers, cross-shaped alignment marks are usually set during processing. In practical applications, situations frequently arise where the alignment marks cannot be identified. Summary of the Invention

[0003] An embodiment of this application provides a motherboard with alignment marks, which have a high success rate in recognizing the alignment marks during processing.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a motherboard is provided, including a substrate and a multilayer structure layer stacked on the substrate, wherein at least one of the multilayer structure layers is provided with an alignment mark, the alignment mark being configured to provide a position reference when processing the next structure layer;

[0006] The orthographic projection of the alignment mark on the substrate is an alignment pattern, which includes multiple alignment lines, and the included angle between two interconnected alignment lines is greater than 90°.

[0007] In some embodiments, the alignment pattern includes at least five sub-alignment patterns, which are symmetrically distributed around the geometric center of the alignment pattern.

[0008] In some implementations, two adjacent sub-aligned images are different along the circumferential direction of the alignment pattern; the circumferential direction of the alignment pattern refers to the circumferential direction of the geometric center of the alignment pattern.

[0009] In some embodiments, a marker pattern is provided between the two ends of the sub-alignment pattern along the radial direction of the alignment pattern, and the marker pattern is different from the two ends of the sub-alignment pattern; the radial direction of the alignment pattern refers to the direction outward from the geometric center of the alignment pattern.

[0010] In some embodiments, along the radial direction of the alignment pattern, the sub-alignment pattern sequentially includes a first pattern and a second pattern, the first pattern having an opening, the second pattern being at least partially inserted into the opening, and the overlapping portions of the first and second patterns forming a marker pattern.

[0011] In some embodiments, the first pattern is formed by connecting multiple first alignment lines of equal length, with an included angle of 120° between two interconnected first alignment lines, and the second pattern is a straight line.

[0012] In some embodiments, the size of the first and / or second graphic is smaller than the field of view of the detection device along the radial direction of the alignment graphic, and the detection device is configured to be able to identify the alignment mark.

[0013] In some embodiments, the multilayer structure layer is formed with at least one array substrate, and the alignment mark is located within the array substrate or between two adjacent array substrates.

[0014] In some embodiments, the alignment mark is located in the non-display area of ​​the array substrate.

[0015] In some embodiments, the multilayer structure includes a patterned conductive layer, and the alignment mark is part of the patterned conductive layer.

[0016] In some embodiments, the multilayer structure is formed with at least one array substrate, the array substrate including fan-out traces, and the alignment mark being a part of the fan-out traces.

[0017] In some embodiments, the included angle between two interconnected alignment lines is greater than or equal to 120°.

[0018] In some embodiments, the multilayer structure layer further includes an annular positioning mark surrounding the array substrate.

[0019] In some embodiments, the multilayer structure includes multiple patterned metal layers, with the circular positioning mark located on the patterned metal layer closest to the substrate.

[0020] In some embodiments, there are multiple alignment markers, which are arranged on the same layer and spaced apart.

[0021] Secondly, an array substrate is provided, which is cut from the aforementioned mother plate.

[0022] This application provides a motherboard and an array substrate. At least one of the multilayer structures of the motherboard has alignment marks. The orthographic projection of the alignment marks onto the substrate is an alignment pattern, and the included angle between two interconnected alignment lines is greater than 90°. Because the included angle between two interconnected alignment lines is greater than 90°, the alignment lines are sparsely arranged at the connection points, thus not affecting the exposure, etching, and other processes of the structural layers. This results in a high consistency between the alignment pattern of the etched alignment marks and the theoretical pattern, thereby improving the success rate of alignment mark recognition. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1a and Figure 1b A schematic diagram of a motherboard provided in an embodiment of this application;

[0025] Figures 2a to 2j A process flow diagram of a motherboard provided in an embodiment of this application;

[0026] Figures 3a to 3q This is a top view of the wiring of the motherboard in Figure 2;

[0027] Figure 4a This is a theoretical diagram of a cross-shaped alignment mark;

[0028] Figure 4b This is an actual graphic representation of a cross-shaped alignment mark;

[0029] Figure 5 This is a schematic diagram showing the position of the field of view of a visual recognition device and the crosshair alignment mark in a related technology.

[0030] Figure 6 A schematic diagram of an alignment mark provided in an embodiment of this application;

[0031] Figure 7 A schematic diagram of another alignment mark provided in an embodiment of this application;

[0032] Figure 8a The graphic within the field of view of the visual recognition device;

[0033] Figure 8b Another graphic within the field of view of a visual recognition device;

[0034] Figure 9 This is another type of graphic within the field of view of a visual recognition device;

[0035] Figure 10 This is another type of graphic within the field of view of a visual recognition device;

[0036] Figure 11 A schematic diagram of yet another alignment mark provided in an embodiment of this application;

[0037] Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0038] Figure label:

[0039] 1-First figure; 2-Second figure;

[0040] 100a-Sub-area;

[0041] 110-Substrate;

[0042] 120-Polycrystalline silicon layer;

[0043] 130 - First gate electrode layer;

[0044] 140 - Second gate electrode layer;

[0045] 150 - First data cable layer; 151 - Circular positioning mark;

[0046] 160 - Second data line layer;

[0047] 170 - Third gate electrode layer;

[0048] 180 - Fourth gate electrode layer;

[0049] 190-SD1 layer;

[0050] 200-SD2 layers;

[0051] 210 - Buffer layer;

[0052] 220 - Anode layer;

[0053] 230-pixel definition layer;

[0054] 240 - Emissive layer;

[0055] 250-Encapsulation layer. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0057] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0058] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0059] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0060] This application provides a motherboard, which refers to the board used in the production of display panels before the display panel is cut and shaped. Figure 1a and Figure 1b This is a schematic diagram of a motherboard provided in an embodiment of this application. Exemplarily, as shown... Figure 1a and Figure 1b As shown, the motherboard includes multiple sub-regions arranged in an array, and each sub-region can be cut to form a display panel.

[0061] The display panel can be an LCD panel or an OLED panel, etc. For ease of description, the following explanation will only use an OLED panel as an example.

[0062] OLEDs are widely used in near-eye display fields such as AR and VR due to their advantages of being thin, light, self-emissive, and having fast response times. OLED display panels used for near-eye displays typically have high pixel densities, and higher pixel densities require higher processing precision. To ensure high pixel density while reducing processing costs, high-pixel-density OLEDs are usually manufactured using a combination of glass-based and silicon-based device processes. That is, some structural layers of the display panel are made using glass-based device processes, while others are made using silicon-based device processes.

[0063] Figures 2a to 2j A process flow diagram of a motherboard provided in an embodiment of this application is shown. For example... Figures 2a to 2j As shown, the motherboard includes a substrate 110 and a multilayer structure layer stacked on the substrate 110.

[0064] The substrate 110 is used to support the multilayer structure layers disposed on the substrate 110. Exemplarily, the substrate 110 is a glass substrate 110, which has high hardness and low cost. The substrate 110 can also be other boards that meet the process requirements, such as silicon wafers.

[0065] A multilayer structure layer refers to some or all of the structural layers used to form a display panel. That is, a multilayer structure layer may include some structural layers of the display panel (e.g., only the structural layers in the array substrate 110) or all structural layers of the display panel (e.g., including both the array substrate 110 and the light-emitting layer, filter layer, etc.).

[0066] In practical applications, high relative positional accuracy is sometimes required between adjacent structural layers. For example, one structural layer may be a patterned metal layer, and the adjacent structural layer may also be a patterned metal layer, with the two patterned metal layers electrically connected in certain areas. When the relative positional accuracy between the two patterned metal layers is low, it can easily lead to the two patterned metal layers not being electrically connected, or the area of ​​electrical connection being reduced, resulting in increased resistance.

[0067] Therefore, at least one of the multi-layered structural layers is provided with alignment marks, which are configured to provide a positional reference when processing the next structural layer. For example, during processing, the alignment marks are identified by a vision recognition device to determine the position of the motherboard, thereby calibrating the position of the motherboard, thus achieving high processing accuracy between adjacent structural layers.

[0068] Alignment marks can be formed by etching structural layers. For example, patterns of a certain shape can be etched onto the structural layer as alignment marks. To make it easier for visual recognition devices to identify alignment marks, alignment marks can be etched onto structural layers with high reflectivity, such as metal layers or polysilicon layers 120.

[0069] In related technologies, cross alignment marks are usually etched on the structural layer. During the alignment process, an image of the cross alignment mark is acquired through a visual recognition device. Then, the acquired image is matched with the theoretical image built into the visual recognition device. If the similarity reaches a certain level, the match is successful, and the cross alignment mark is identified.

[0070] However, in practical applications, the shape of the cross alignment mark formed by etching often differs significantly from the shape in the theoretical image, leading to unsuccessful recognition or slow recognition speed. Figure 4a This is a theoretical diagram of a cross-shaped alignment mark. Figure 4b This is an actual graphic representation of a cross-shaped alignment mark. For example... Figure 4b As shown, the actual etched cross alignment mark has a wider line at its geometric center than in the theoretical image, while the line width near the geometric center is thinner compared to other locations. This results in a significant difference between the actual and theoretical images of the cross alignment mark, making it difficult to identify or slowing down the identification process.

[0071] The inventors discovered that the reason why the cross alignment mark is thinner near the geometric center than at other positions is that the angle between the four lines is 90°, which causes the lines to be arranged more densely at the geometric center, affecting the exposure and etching processes of the structural layer, and thus causing the etched shape to be inconsistent with the theoretical shape.

[0072] Therefore, in this embodiment, a novel alignment mark is provided on the motherboard. The orthographic projection of the alignment mark on the substrate 110 is an alignment pattern, and the included angle between two interconnected alignment lines is greater than 90°. Since the included angle between two interconnected alignment lines is greater than 90°, the alignment lines are sparsely arranged at the connection point, thus not affecting the exposure, etching, and other processes of the structural layer. This results in a high degree of consistency between the alignment pattern of the etched alignment mark and the theoretical pattern, thereby improving the success rate of alignment mark recognition.

[0073] In practical applications, the angle between alignment lines can be flexibly selected according to the actual situation, such as 100°, 110°, 120°, 130°, etc., as long as it is greater than 90°. The larger the angle between alignment lines, the sparser the alignment lines are, and the smaller the difference between the etched alignment mark pattern and the theoretical pattern. To improve the consistency between the alignment pattern and the theoretical pattern, the angle between two interconnected alignment lines can be greater than or equal to 120°.

[0074] The use of cross-shaped alignment marks in related technologies also has the problem of a small detectable range. Specifically, since the field of view of visual recognition devices is usually small, when the positional deviation of the motherboard is large, the cross-shaped alignment marks may not be within the field of view of the visual recognition device, thus making it impossible to recognize the cross-shaped alignment marks. Figure 5 This diagram illustrates the position of the field of view of a visual recognition device relative to the alignment mark in related technologies. The circular area in the diagram represents the field of view of the visual recognition device. Figure 5 As shown, the cross-shaped alignment mark divides the plane into four blank areas. When the field of view of the visual recognition device is completely located in one of the four blank areas (lower left quadrant in the figure), the visual recognition device cannot recognize the cross-shaped alignment mark, resulting in alignment failure.

[0075] To address the issue of the limited detectable range of the cross-shaped alignment mark, the alignment pattern can include at least five sub-aligned patterns, symmetrically distributed around the geometric center of the alignment pattern. This symmetrical distribution divides the plane into five regions. Compared to the cross-shaped alignment mark dividing the plane into four regions, dividing it into five regions results in smaller angles between adjacent regions and a smaller area for each region, reducing the probability that the visual recognition device's field of view is entirely within one of these regions. In other words, the sub-aligned patterns are more likely to appear within the visual recognition device's field of view.

[0076] Figure 6 This is a schematic diagram of an alignment mark provided in an embodiment of this application. For example... Figure 6 As shown, the alignment pattern includes a central circle and six straight lines connecting the circle. Each straight line is a sub-alignment pattern, and the angle between any two adjacent lines is 60°. The six straight lines divide the plane into six blank areas. When the field of view of the visual recognition device remains constant, and the position of the alignment mark off the center of the visual recognition device's field of view remains constant, the alignment lines of the alignment mark are easily visible in the visual recognition device's field of view, thus enabling the identification of the alignment mark.

[0077] In practical applications, the sub-alignment pattern can also be a tree-like pattern or other shapes, and this application does not limit this. When the sub-alignment pattern is set as a non-linear pattern, the blank area between two adjacent sub-alignment patterns is further reduced, thereby increasing the likelihood that the alignment line will appear in the field of view of the visual recognition device, which increases the detectable range of the alignment mark.

[0078] The circumferential direction of the alignment pattern refers to the circumferential direction of the geometric center of the alignment pattern. If two adjacent sub-aligned patterns are identical along the circumferential direction of the alignment pattern, when two adjacent sub-aligned patterns appear in the field of view of the visual inspection device, it is impossible to determine whether the alignment pattern has rotated based on the two adjacent sub-aligned patterns.

[0079] For example, when a portion of two straight lines appears in the field of view of the visual inspection device, it is impossible to determine whether this portion of the straight line is located on the left side of the alignment pattern or on the lower left side of the alignment pattern.

[0080] In order to determine whether the master plate or the alignment pattern has been rotated, adjacent sub-alignment patterns can be different along the circumference of the alignment pattern.

[0081] Figure 7 This is a schematic diagram of an alignment pattern provided in an embodiment of this application. Figure 8a The image is the shape within the field of view of the visual recognition device. Figure 8b This is another graphic within the field of view of a visual recognition device. When the graphic in the field of view is like... Figure 8a As shown, it can be determined that the graphic has not undergone a slight rotation. When the graphic in the field of view is as shown... Figure 8b As shown, it can be determined that the master plate or the alignment pattern has undergone a slight rotation.

[0082] The radial direction of a aligning figure refers to the direction outward from its geometric center. If the sub-aligning figures are identical along the radial direction, it is often impossible to determine the position of the sub-aligning figures within the aligning figure, and consequently, to determine the geometric center of the aligning figure.

[0083] For example, when only a portion of a straight line appears in the field of view of the visual inspection device, it is impossible to determine whether this portion of the straight line is located at the top of the alignment pattern or at the bottom of the alignment pattern.

[0084] In order to determine the position of the identified graphic within the corresponding graphic, and thus the geometric center of the corresponding graphic, a marker graphic is placed between the two ends of the sub-corresponding graphic along the radial direction of the corresponding graphic. The marker graphic is different from the two ends of the sub-corresponding graphic.

[0085] Continue with Figure 6 Let's take the alignment graphic in the image as an example for illustration. When the graphic in the field of view of the visual recognition device is like... Figure 9 As shown, it can be determined that the geometric center of the aligned graphic is located below the field of view. When the graphic in the field of view of the visual recognition device is as shown... Figure 10 As shown, it can be determined that the geometric center of the alignment figure is located above the field of view.

[0086] Continue to refer to Figure 7 Along the radial direction of the alignment pattern, the sub-alignment pattern sequentially includes a first pattern 1 and a second pattern 2. The first pattern 1 has an opening, and the second pattern 2 is at least partially inserted into the opening. The overlapping portion of the first pattern 1 and the second pattern 2 forms a marker pattern. Here, "overlapping" does not mean that the first pattern 1 and the second pattern 2 are connected, but rather that a certain region along the radial direction of the sub-alignment pattern contains both the first pattern 1 and the second pattern 2, and the first pattern 1 and the second pattern 2 are not connected.

[0087] The first graphic 1 and the second graphic 2 form a marker graphic in a non-connected manner, which can reduce the connection points in the alignment graphic, thereby preventing insufficient exposure and etching caused by dense alignment lines at the connection points.

[0088] The first figure 1 is formed by connecting multiple first alignment lines of equal length, with an included angle of 120° between any two connected first alignment lines. The second figure 2 is a straight line. Both the first figure 1 and the second figure 2 are composed of straight lines, which simplifies the alignment pattern structure and thus simplifies the manufacturing process of the alignment mark. The multiple first alignment lines constituting the first figure 1 are of equal length and have an included angle of 120°, making it easy to calculate the position of the geometric center of the alignment pattern based on the first alignment lines.

[0089] Along the radial direction of the alignment pattern, the size of the first pattern 1 and / or the second pattern 2 is smaller than the field of view of the detection device, which is configured to recognize the alignment mark. The detection device refers to a visual recognition device. The smaller size of the first pattern 1 and / or the second pattern 2 allows more patterns to appear in the field of view of the detection device, making it easier to determine the geometric center of the alignment pattern.

[0090] At least one array substrate 110 is formed in a multilayer structure, and alignment marks are located within the array substrate 110 or between two adjacent array substrates 110. (Continue to refer to...) Figure 1a and Figure 1b , Figure 1a and Figure 1b In the example, each motherboard has 25 array substrates 110, and each array substrate 110 has an alignment mark.

[0091] The alignment mark can be located between two adjacent array substrates 110, meaning that the alignment mark is not on the array substrate 110 after the motherboard is cut. In this way, there is no need to reserve an additional area on the array substrate 110 for setting the alignment mark, making the array substrate 110 more spacious for arranging other structures.

[0092] Alignment marks can also be located on the array substrate 110, meaning the alignment marks remain on the array substrate 110 after the motherboard is cut. Setting the alignment marks on the array substrate 110 makes the distance between the alignment marks and the structures on the array substrate 110 closer, resulting in better position calibration.

[0093] When the alignment mark is located between two adjacent array substrates 110, the alignment mark can be set in various positions. For example, the alignment mark can be set on the upper side, lower side, left side or right side of the array substrate 110, or the alignment mark can be set on the outer side of the four corners of the array substrate 110.

[0094] The area on the array substrate 110 opposite to the display area of ​​the display panel can also be called the display area, and correspondingly, the area on the array substrate 110 opposite to the non-display area of ​​the display panel can also be called the non-display area. Alignment marks are located in the non-display area of ​​the array substrate 110. When alignment marks are placed in the display area of ​​the array substrate 110, the alignment marks may encroach on the space of structures (e.g., transistors) arranged in the display area, affecting the performance of the display panel. However, placing the alignment marks in the non-display area does not encroach on the space of the display area.

[0095] The multilayer structure includes patterned conductive layers, and may also include organic or inorganic insulating layers between the patterned conductive layers. Alignment marks may be part of the patterned conductive layers.

[0096] For example, the patterned conductive layer is a patterned metal layer. On the one hand, metal has a high reflectivity, making it easy to be detected by a visual inspection device and improving the recognition rate of alignment marks. On the other hand, since the patterned metal layer itself is patterned, the multiple patterns it includes can serve as alignment marks, thus eliminating the need to set additional patterns as alignment marks, reducing the space occupied by alignment marks, and reducing the number of structures on the array substrate 110, thereby reducing the difficulty of the manufacturing process.

[0097] For example, an area where multiple conductive lines intersect in a patterned conductive layer can be selected as an alignment marker. This area is clearly distinguishable from other areas, preventing identification errors.

[0098] like Figure 11 As shown, the array substrate 110 includes fan-out traces, and the alignment mark is a part of the fan-out traces. The fan-out traces can be fan-out traces electrically connected to data lines. The fan-out traces are not straight and have multiple turning points, clearly distinguishing them from other traces on the array substrate 110, which can reduce the probability of identification errors. Furthermore, multiple fan-out traces are typically arranged side-by-side, and each fan-out trace is different (e.g., the bending angle α of each fan-out trace is different). This allows it to determine which fan-out trace the identified position belongs to, and to determine the current position of the motherboard based on the position of this fan-out trace, thereby performing position calibration. In addition, the fan-out traces occupy a large area; when the position of the motherboard is significantly offset, the field of view of the visual inspection device is less likely to leave the area occupied by the fan-out traces, thus reducing the probability of alignment mark recognition failure.

[0099] It should be noted that in practical applications, in order to save space, the bending angle α of some fan-out routing lines is relatively small. Therefore, when the alignment mark is part of the fan-out routing line, the included angle between the two alignment lines connected in the alignment mark is greater than 90°.

[0100] Figures 2a to 2j The process shown employs a glass-based device fabrication process, which is then transferred to a silicon-based device fabrication process. For example, the motherboard fabricated using the glass-based device process is coated with adhesive for protection. Then, the glass substrate 110 is cut and ground according to the equipment requirements of the silicon-based device process to the size of a silicon wafer. Subsequent film layers (e.g., anode, pixel definition layer, filter layer, light-emitting layer, etc.) are then fabricated using equipment in the silicon-based device process.

[0101] A cross-sectional view of the fabricated display panel is shown below. Figure 12 As shown, the display panel sequentially includes a substrate 110, a buffer layer 210, a polysilicon layer 120, a first gate electrode layer 130, a second gate electrode layer 140, a first data line layer 150, a second data line layer 160, a third gate electrode layer 170, a fourth gate electrode layer 180, an SD1 layer 190, an SD2 layer 200, an anode layer 220, a pixel definition layer 230, a light-emitting layer 240, and an encapsulation layer 250.

[0102] In glass-based device manufacturing processes, glass is typically used as the substrate 110 to support other structural layers, while in silicon-based device manufacturing processes, silicon wafers are typically used as the substrate 110. Correspondingly, the visual recognition device in glass-based device manufacturing processes is adapted to identify alignment marks when glass is used as the substrate 110, while the visual recognition device in silicon-based device manufacturing processes is adapted to identify alignment marks when silicon wafers are used as the substrate 110. However, glass has a higher coefficient of thermal expansion than silicon wafers. This results in a significant misalignment of the alignment marks when transferring the motherboard (glass substrate 110) to the equipment in silicon-based device manufacturing processes, making it impossible for the visual recognition device to identify the alignment marks.

[0103] The alignment marks in the motherboard provided in this application embodiment can improve the detection range of the alignment marks, thereby solving the problem of being unable to identify the alignment marks due to the transfer from glass-based device technology to silicon-based device technology.

[0104] In practical applications, robotic arms are typically used to transfer motherboards from glass-based device processing equipment to silicon-based device processing equipment. To enable the robotic arm to accurately grasp the motherboard, a circular positioning mark 151 can be set on the motherboard to determine the robotic arm's grasping position. The circular positioning mark 151 refers to a positioning mark that is entirely circular; it can be a precise circle or a shape with local modifications to a circle. For example, a notch can be set in a portion of the circle to facilitate determining the rotation angle of the circular positioning mark 151.

[0105] In addition, the circular positioning mark 151 on the motherboard can make the motherboard more accurately placed in the silicon-based device process equipment, and prevent the alignment mark from being out of the field of view of the visual recognition device.

[0106] For example, the robotic arm includes a camera. Before grasping, the camera acquires an image of the motherboard, and the position and orientation of the motherboard are obtained through image analysis. The grasping position of the robotic arm is then determined based on the position and orientation of the motherboard.

[0107] The multilayer structure includes multiple patterned metal layers, with the circular positioning mark 151 located on the patterned metal layer closest to the substrate 110. Exemplarily, the circular positioning mark 151 is located on the first gate electrode layer.

[0108] There are multiple alignment marks, arranged on the same layer and spaced apart. One alignment mark determines the position of one point, two alignment marks determine the positions of two points, and the position and orientation of the motherboard are determined based on the positions of these two points. Here, "alignment marks on the same layer and spaced apart" means that multiple alignment marks used in conjunction are arranged on the same layer and spaced apart.

[0109] For example, in order to determine the position and orientation of the motherboard, it is necessary to identify three alignment marks, which are located at the three corners of the array substrate 110, and these three alignment marks are set on the same layer.

[0110] It should be noted that the number of comparison marks used in this application embodiment is not limited, and can be two, three, four, etc.

[0111] In addition, among the structural layers set on the motherboard, there may be multiple structural layers that need to be set with alignment marks for position calibration. In order to calibrate the position of different structural layers, the alignment marks are set for different layers.

[0112] For example, the motherboard includes a first metal layer and a second metal layer, and a first alignment mark for calibrating the position of the first metal layer and a second alignment mark for calibrating the position of the second metal layer are not set on the same layer.

[0113] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A motherboard, characterized in that, The invention includes a substrate and a multilayer structure layer stacked on the substrate, wherein at least one of the multilayer structure layers is provided with an alignment mark, the alignment mark being configured to provide a position reference when processing the next structure layer; The orthographic projection of the alignment mark on the substrate is an alignment pattern, which includes multiple alignment lines, and the included angle between two interconnected alignment lines is greater than 90°. The alignment pattern includes at least five sub-alignment patterns, and the at least five sub-alignment patterns are symmetrically distributed along the geometric center of the alignment pattern. Wherein, along the radial direction of the alignment pattern, a marking pattern is provided between the two ends of the sub-alignment pattern, and the marking pattern is different from the two ends of the sub-alignment pattern; the radial direction of the alignment pattern refers to the direction outward from the geometric center of the alignment pattern; Along the radial direction of the alignment pattern, the sub-alignment pattern sequentially includes a first pattern and a second pattern, the first pattern having an opening, the second pattern being at least partially inserted into the opening, the overlapping portion of the first pattern and the second pattern forming a marker pattern, and the first pattern and the second pattern not being connected.

2. The mother plate according to claim 1, characterized in that, Along the circumference of the alignment pattern, two adjacent sub-alignment patterns are different; the circumference of the alignment pattern refers to the circumference of the geometric center of the alignment pattern.

3. The mother plate according to claim 1, characterized in that, The first graphic is formed by connecting multiple first alignment lines of equal length, with the included angle between two connected first alignment lines being 120°, and the second graphic is a straight line.

4. The mother plate according to claim 1, characterized in that, Along the radial direction of the alignment pattern, the size of the first pattern and / or the second pattern is smaller than the field of view of the detection device, which is configured to be able to identify the alignment mark.

5. The mother plate according to claim 1, characterized in that, The multilayer structure layer is formed with at least one array substrate, and the alignment mark is located within the array substrate or between two adjacent array substrates.

6. The mother plate according to claim 5, characterized in that, The alignment mark is located in the non-display area of ​​the array substrate.

7. The mother plate according to claim 1, characterized in that, The multilayer structure includes a patterned conductive layer, and the alignment mark is a part of the patterned conductive layer.

8. The mother plate according to claim 7, characterized in that, The multilayer structure layer is formed with at least one array substrate, the array substrate includes fan-out traces, and the alignment mark is a part of the fan-out traces.

9. The mother plate according to claim 1, characterized in that, The angle between two interconnected alignment lines is greater than or equal to 120°.

10. The mother plate according to claim 5, 6, or 8, characterized in that, The multilayer structure also includes a circular positioning mark surrounding the array substrate.

11. The mother plate according to claim 10, characterized in that, The multilayer structure includes multiple patterned metal layers, and the circular positioning mark is located in the patterned metal layer closest to the substrate.

12. The mother plate according to any one of claims 1-9, characterized in that, There are multiple alignment markers, and these multiple alignment markers are arranged on the same layer and spaced apart.

13. An array substrate, characterized in that, It is cut from the mother plate as described in any one of claims 1-12.

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