Array substrate and display device

Abstract

Provided are an array substrate and a display device. The array substrate comprises a base, a driving module, and a plurality of clock signal lines; the base comprises a display area and a peripheral area; the driving module and the plurality of clock signal lines are provided on the base; the driving module and the clock signal lines are provided in the peripheral area; the clock signal lines are provided on the side of the driving module distant from the display area; and the clock signal lines are formed on a first metal layer. The array substrate further comprises a first via hole electrically connected to signal lines; at least one clock signal line adjacent to the first via hole comprises a first clock signal line portion and a second clock signal line portion; the line width of the first clock signal line portion is greater than that of the second clock signal line portion; and the signal lines are the clock signal lines, and / or signal lines arranged in the same layer as the clock signal lines. The present disclosure can reduce fine streaks.

Description

Array substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] When the relevant display devices are working, at room temperature, the grayscale pattern (image) exhibits periodic fine horizontal lines, affecting the image quality. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide an array substrate, including a substrate, a driving module, and multiple clock signal lines;

[0004] The substrate includes a display area and a peripheral area. The driving module and the multiple clock signal lines are disposed on the substrate. The driving module and the clock signal lines are disposed in the peripheral area. The clock signal lines are disposed on the side of the driving module away from the display area. The clock signal lines are formed on a first metal layer.

[0005] The array substrate also includes a first via electrically connected to the signal line;

[0006] At least one clock signal line adjacent to the first via includes a first clock signal line portion and a second clock signal line portion, wherein the line width of the first clock signal line portion is greater than the line width of the second clock signal line portion;

[0007] The signal line is the clock signal line, and / or the signal line is a signal line disposed on the same layer as the clock signal line.

[0008] Optionally, the first clock signal line is disposed on the first side and / or the second side of the first via;

[0009] The first side and the second side are opposite sides.

[0010] Optionally, the extension direction of the first clock signal line is either a first direction or a second direction. The first direction intersects with a third direction but is not perpendicular to the third direction. The second direction intersects with the third direction but is not perpendicular to the third direction.

[0011] The array substrate includes data lines disposed in the display area, and the data lines extend along the third direction.

[0012] Optionally, the signal line is the clock signal line; the first via is electrically connected to the first connection portion formed in the first metal layer and the second connection portion formed in the second metal layer, respectively;

[0013] The area of ​​the first connecting part is larger than the area of ​​the second connecting part.

[0014] Optionally, the signal line is the clock signal line; the first via is electrically connected to a first connection portion formed on the first metal layer and a second connection portion formed on the second metal layer; the second connection portion includes a first edge and a second edge, the first edge and the second edge intersect, and the first connection portion includes a portion away from the second connection portion along the extension line of the first edge.

[0015] Optionally, the first connecting portion includes a first connecting part and at least one second connecting part; the second connecting part is disposed on a third side and / or a fourth side of the first connecting part;

[0016] The third side and the fourth side are opposite sides.

[0017] Optionally, the second connecting portion is a triangular connecting portion.

[0018] Optionally, the surrounding area includes a regular area and an irregularly shaped area; the driving module includes a first driving circuit disposed in the regular area and a second driving circuit disposed in the irregularly shaped area; the first driving circuit includes a first driving transistor and a first storage capacitor; the second driving circuit includes a second driving transistor and a second storage capacitor;

[0019] The shape of the first storage capacitor is different from the shape of the second storage capacitor;

[0020] The shape of the first driving transistor is different from the shape of the second driving transistor.

[0021] Optionally, the gate of the second driving transistor includes a plurality of second gate portions;

[0022] The first plate and the gate of the second storage capacitor are formed on the first metal layer;

[0023] The first electrode plate has a first clearance space to allow at least one of the second gate portions to pass.

[0024] Optionally, the array substrate includes data lines disposed in the display area, the data lines extending along a third direction; a fourth direction is perpendicular to the third direction; the gate of the first driving transistor includes a plurality of first gate portions, and the gate of the second driving transistor includes a plurality of second gate portions;

[0025] The sum of the widths of the plurality of first gate portions along the fourth direction is greater than the widths of the plurality of second gate portions along the fourth direction.

[0026] Optionally, the first driving circuit includes a first reset circuit, and the second driving circuit includes a second reset circuit; the first reset circuit is used to control the potential of the first first node under the control of the first reset terminal; the second reset circuit is used to control the potential of the second first node under the control of the second reset terminal.

[0027] The first reset circuit includes a first transistor, and the second reset circuit includes a second first transistor;

[0028] The shape of the first transistor is different from the shape of the second transistor.

[0029] Optionally, the first driving circuit includes a first first node reset circuit, a first output reset circuit, and a first first frame reset circuit; the second driving circuit includes a second first node reset circuit, a second output reset circuit, and a second first frame reset circuit.

[0030] The first first node reset circuit is used to reset the potential of the first first node under the control of the potential of the first second node; the first output reset circuit is used to reset the first driving signal provided by the first driving signal output terminal under the control of the potential of the first second node; the first first frame reset circuit is used to reset the first driving signal under the control of the frame reset line; the second first node reset circuit is used to reset the potential of the second first node under the control of the potential of the second second node; the second output reset circuit is used to reset the second driving signal provided by the second driving signal output terminal under the control of the potential of the second second node; the second first frame reset circuit is used to reset the second driving signal under the control of the frame reset line; the first first node reset circuit includes a first second transistor, the first output reset circuit includes a first third transistor, and the first first frame reset circuit includes a first fourth transistor; the second first node reset circuit includes a second second transistor, the second output reset circuit includes a second third transistor, and the second first frame reset circuit includes a second fourth transistor; the array substrate includes data lines disposed in the display area, the data lines extending along a third direction; the fourth direction is perpendicular to the third direction;

[0031] The first second transistor, the first fourth transistor, and the first third transistor are arranged along the fourth direction;

[0032] The second transistor and the second fourth transistor are arranged along the third direction, and the second transistor and the second third transistor are arranged along the fourth direction.

[0033] Optionally, the channel of the first fourth transistor extends along a third direction, and the channel of the second fourth transistor extends along a fourth direction.

[0034] Optionally, the first driving circuit includes a first second frame reset circuit, a first pull-down control node control circuit, and a first second node reset circuit, and the second driving circuit includes a second second frame reset circuit, a second pull-down control node control circuit, and a second second node reset circuit.

[0035] The first second frame reset circuit is used to reset the potential of the first first node under the control of the frame reset line; the first pull-down control node control circuit is used to control the potential of the first pull-down control node; the first second node reset circuit is used to reset the potential of the first second node under the control of the potential of the first first node; the second second frame reset circuit is used to reset the potential of the second first node under the control of the frame reset line; the second pull-down control node control circuit is used to control the potential of the second pull-down control node; the second second node reset circuit is used to reset the potential of the second second node under the control of the potential of the second first node.

[0036] The first second frame reset circuit includes a first fifth transistor, the first pull-down control node control circuit includes a first sixth transistor and a first seventh transistor, and the first second node reset circuit includes a first eighth transistor; the second second frame reset circuit includes a second fifth transistor, the second pull-down control node control circuit includes a second sixth transistor and a second seventh transistor, and the second second node reset circuit includes a second eighth transistor; the array substrate includes data lines disposed in the display area, and the data lines extend along a third direction;

[0037] The first seventh transistor and the first sixth transistor are arranged along the third direction, and the first eighth transistor and the first fifth transistor are arranged along the third direction;

[0038] The second seventh transistor, the second sixth transistor, and the second fifth transistor are arranged along a third direction, and the second eighth transistor and the second fifth transistor are arranged along a third direction.

[0039] Optionally, the channel of the first seventh transistor extends along a third direction; the channel of the second seventh transistor extends along a fourth direction.

[0040] The third direction is perpendicular to the fourth direction.

[0041] Optionally, the first driving circuit includes a first second node control circuit, and the second driving circuit includes a second second node control circuit; the first second node control circuit is used to control the potential of the first second node under the control of the potential of the first pull-down control node; the second second node control circuit is used to control the potential of the second second node under the control of the potential of the second pull-down control node.

[0042] The first second node control circuit includes a first ninth transistor, and the second second node control circuit includes a second ninth transistor;

[0043] The channel of the first ninth transistor extends along the fourth direction; the channel of the second ninth transistor extends along the third direction.

[0044] The third direction is perpendicular to the fourth direction.

[0045] Optionally, the surrounding area includes irregularly shaped areas;

[0046] Within the irregularly shaped area, the line width of the clock signal line furthest from the display area is greater than the line width of the clock signal line closest to the display area within the irregularly shaped area.

[0047] The array substrate described in at least one embodiment of this disclosure further includes a start voltage line;

[0048] The starting voltage line is located on the side of the clock signal line away from the display area.

[0049] Optionally, the peripheral area includes a first peripheral area and a second peripheral area, the first peripheral area being disposed on the fifth side of the display area and the second peripheral area being disposed on the sixth side of the display area; the fifth side and the sixth side are opposite sides; the array substrate includes a first driving module and a second driving module, the first driving module being disposed in the first peripheral area and the second driving module including the second peripheral area; n is a positive integer;

[0050] The drive signal output terminal of the (4n-3)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+4)th stage drive circuit included in the first drive module; the drive signal output terminal of the (4n-2)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+3)th stage drive circuit included in the first drive module; the drive signal output terminal of the (4n-1)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+2)th stage drive circuit included in the first drive module; the drive signal output terminal of the (4n)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+1)th stage drive circuit included in the first drive module; and / or Alternatively, the drive signal output terminal of the 4n+4th stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4n-3th stage drive circuit included in the first drive module; the drive signal output terminal of the 4n+3rd stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4n-2th stage drive circuit included in the first drive module; the drive signal output terminal of the 4n+2nd stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4n-1th stage drive circuit included in the first drive module; and the drive signal output terminal of the 4n+1st stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4nth stage drive circuit included in the first drive module.

[0051] The drive signal output terminal of the (4n-3)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+4)th stage drive circuit included in the second drive module; the drive signal output terminal of the (4n-2)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+3)th stage drive circuit included in the second drive module; the drive signal output terminal of the (4n-1)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+2)th stage drive circuit included in the second drive module; the drive signal output terminal of the (4n)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+1)th stage drive circuit included in the second drive module; and / or Alternatively, the drive signal output terminal of the 4n+4th stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4n-3th stage drive circuit included in the second drive module; the drive signal output terminal of the 4n+3rd stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4n-2th stage drive circuit included in the second drive module; the drive signal output terminal of the 4n+2nd stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4n-1th stage drive circuit included in the second drive module; and the drive signal output terminal of the 4n+1st stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4nth stage drive circuit included in the second drive module.

[0052] Optionally, the array substrate includes sixteen clock signal lines; the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth clock signal lines are all disposed in the second peripheral area; the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth clock signal lines are all disposed in the first peripheral area.

[0053] The first driving module includes an 8m-7th stage driving circuit electrically connected to the first clock signal line, an 8m-6th stage driving circuit electrically connected to the third clock signal line, an 8m-5th stage driving circuit electrically connected to the fifth clock signal line, an 8m-4th stage driving circuit electrically connected to the seventh clock signal line, an 8m-3th stage driving circuit electrically connected to the ninth clock signal line, an 8m-2th stage driving circuit electrically connected to the eleventh clock signal line, an 8m-1st stage driving circuit electrically connected to the thirteenth clock signal line, and an 8mth stage driving circuit electrically connected to the fifteenth clock signal line, where m is a positive integer.

[0054] The second driving module includes an 8m-7th stage driving circuit electrically connected to the second clock signal line, an 8m-6th stage driving circuit electrically connected to the fourth clock signal line, an 8m-5th stage driving circuit electrically connected to the sixth clock signal line, an 8m-4th stage driving circuit electrically connected to the eighth clock signal line, an 8m-3th stage driving circuit electrically connected to the tenth clock signal line, an 8m-2th stage driving circuit electrically connected to the twelfth clock signal line, an 8m-1st stage driving circuit electrically connected to the fourteenth clock signal line, and an 8m-1st stage driving circuit electrically connected to the sixteenth clock signal line.

[0055] The array substrate described in at least one embodiment of this disclosure further includes a first start voltage line, a second start voltage line, a third start voltage line, and a fourth start voltage line;

[0056] The input terminals of the first-stage driving circuit and the second-stage driving circuit of the first driving module are electrically connected to the first starting voltage line.

[0057] The input terminals of the third-stage driving circuit and the fourth-stage driving circuit included in the first driving module are electrically connected to the third starting voltage line.

[0058] The input terminal of the first-stage driving circuit included in the second driving module and the input terminal of the second-stage driving circuit included in the second driving module are electrically connected to the second starting voltage line;

[0059] The input terminals of the third-stage drive circuit and the fourth-stage drive circuit included in the second drive module are electrically connected to the fourth starting voltage line.

[0060] In a second aspect, embodiments of this disclosure provide a display device including the array substrate described above. Attached Figure Description

[0061] Figure 1A is a layout diagram of an array substrate according to at least one embodiment of the present disclosure;

[0062] Figure 1B is a layout diagram of the array substrate according to at least one embodiment of the present disclosure;

[0063] Figure 1C is a layout diagram of the gate metal layer in Figure 1B;

[0064] Figure 1D is a layout diagram of the source and drain metal layers in Figure 1B;

[0065] Figure 1E is a layout diagram of the ITO layer in Figure 1B;

[0066] Figure 2 is a layout diagram of the array substrate according to at least one embodiment of the present disclosure;

[0067] Figure 3 is a layout diagram of the gate metal layer in Figure 2;

[0068] Figure 4 is a layout diagram of the source and drain metal layers in Figure 2;

[0069] Figure 5 is a layout diagram of the ITO (indium tin oxide) layer in Figure 2;

[0070] Figure 6A is the layout diagram of Figure 2 with the ITO layer removed;

[0071] Figure 6B is a layout diagram of the gate metal layer in at least one embodiment of this disclosure;

[0072] Figures 7A and 7F are layout diagrams of the array substrate according to at least one embodiment of the present disclosure;

[0073] Figure 7B is a layout diagram of the gate metal layer in Figure 7A;

[0074] Figure 7C is a layout diagram of the semiconductor layer in Figure 7A;

[0075] Figure 7D is a layout diagram of the source and drain metal layers in Figure 7A;

[0076] Figure 7E is a layout diagram of the ITO (indium tin oxide) layer in Figure 7A;

[0077] Figures 8A and 8F are layout diagrams of the array substrate according to at least one embodiment of the present disclosure;

[0078] Figure 8B is a layout diagram of the gate metal layer in Figure 8A;

[0079] Figure 8C is a layout diagram of the semiconductor layer in Figure 8A;

[0080] Figure 8D is a layout diagram of the source and drain metal layers in Figure 8A;

[0081] Figure 8E is a layout diagram of the ITO (indium tin oxide) layer in Figure 8A;

[0082] Figure 9 is a structural diagram of at least one embodiment of the first driving circuit;

[0083] Figure 10 is a circuit diagram of at least one embodiment of the first driving circuit;

[0084] Figure 11 is a structural diagram of at least one embodiment of the second driving circuit;

[0085] Figure 12 is a circuit diagram of at least one embodiment of the second driving circuit;

[0086] Figure 13 is a layout diagram of the array substrate according to at least one embodiment of the present disclosure;

[0087] Figure 14 is a layout diagram of the array substrate according to at least one embodiment of the present disclosure;

[0088] Figure 15A is a structural diagram of the second storage capacitor C21;

[0089] Figure 15B is a layout diagram of the gate metal layer in Figure 15A;

[0090] Figure 15C is a layout diagram of the source and drain metal layers in Figure 15A;

[0091] Figure 15D is a layout diagram of the ITO layer in Figure 15A;

[0092] Figure 16 is a structural diagram of an array substrate according to at least one embodiment of the present disclosure;

[0093] Figure 17 is a timing diagram of at least one embodiment shown in Figure 16. Detailed Implementation

[0094] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0095] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0096] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0097] The array substrate described in this embodiment includes a substrate, a driving module, and multiple clock signal lines;

[0098] The substrate includes a display area and a peripheral area. The driving module and the multiple clock signal lines are disposed on the substrate. The driving module and the clock signal lines are disposed in the peripheral area. The clock signal lines are disposed on the side of the driving module away from the display area. The clock signal lines are formed on a first metal layer.

[0099] The array substrate also includes a first via electrically connected to the signal line;

[0100] At least one clock signal line adjacent to the first via includes a first clock signal line portion and a second clock signal line portion, wherein the line width of the first clock signal line portion is greater than the line width of the second clock signal line portion;

[0101] The signal line is the clock signal line, and / or the signal line is a signal line disposed on the same layer as the clock signal line.

[0102] In a specific implementation, the array substrate includes a first via electrically connected to a clock signal line. Since the first via is required, at least one clock signal line adjacent to the first via needs to be bent so that the length of the at least one clock signal line adjacent to the first via is greater than the length of the other clock signal lines. In at least one embodiment of this disclosure, the at least one clock signal line adjacent to the first via includes a first clock signal line portion and a second clock signal line portion. The line width of the first clock signal line portion is set to be greater than the line width of the second clock signal line portion to compensate for the resistance value of the at least one clock signal line adjacent to the first via, so that the resistance values ​​of the multiple clock signal lines are not significantly different, or the resistance of the clock signal lines is reduced, thereby improving display uniformity and enhancing the effect of fine horizontal lines.

[0103] Optionally, the line width of the second clock signal line may be the same as or substantially the same as the line width of the other clock signal lines among the plurality of clock signal lines, excluding the at least one clock signal line.

[0104] In at least one embodiment of this disclosure, a connection pattern formed on an ITO (indium tin oxide) layer may be provided at the via location. The connection pattern is on the same layer as the pixel electrode or common electrode provided in the display area. Through the connection pattern formed on the ITO layer, an electrical connection between the gate metal layer and the source / drain metal layer can be achieved.

[0105] In at least one embodiment shown in Figure 1A, the line labeled CLK2 is the second clock signal line, the line labeled CLK4 is the fourth clock signal line, the line labeled CLK6 is the sixth clock signal line, the line labeled CLK8 is the eighth clock signal line, the line labeled CLK10 is the tenth clock signal line, the line labeled CLK12 is the twelfth clock signal line, the line labeled CLK14 is the fourteenth clock signal line, and the line labeled CLK16 is the sixteenth clock signal line.

[0106] In Figure 1A, the first via is labeled H11, and the second via is labeled H21. It should be noted that the first via here includes at least one via that overlaps with the gate metal layer on the vertical substrate and at least one via that overlaps with the source / drain metal layer on the vertical substrate. The second via here includes at least one via that overlaps with the gate metal layer on the vertical substrate and at least one via that overlaps with the source / drain metal layer on the vertical substrate.

[0107] The first via H11 is electrically connected to the low voltage line VGL, and the second via H21 is electrically connected to CLK6.

[0108] The signal line electrically connected to the first via H11 is a low voltage line VGL. The low voltage line VGL is set on the same layer as each clock signal line. Both the low voltage line VGL and each clock signal line are formed on the gate metal layer.

[0109] The signal line electrically connected to the second first via H21 is the sixth clock signal line CLK6;

[0110] CLK2 is adjacent to H11, and CLK4 is adjacent to H21;

[0111] The second clock signal line CLK2 includes a first clock signal line section CKB11, a first second clock signal line section CKB12, and a second second clock signal line section CKB22;

[0112] The line width of CKB11 is greater than that of CKB12, and the line width of CKB11 is greater than that of CKB22; optionally, the line width of CKB12 can be equal to that of CKB22.

[0113] The fourth clock signal line CLK4 includes a second first clock signal line section CKB21, a third second clock signal line section CKB32, and a fourth second clock signal line section CKB42;

[0114] The line width of CKB21 is greater than that of CKB32. The line width of CKB21 is equal to that of CKB42. Optionally, the line width of CKB32 can be equal to that of CKB42.

[0115] In Figure 1A, the line labeled STV0 is the frame reset line.

[0116] Optionally, the line width of CKB12 is equal to that of CKB32, meaning that the line width of the non-widened portions of multiple clock signal lines can be set to the same value.

[0117] In at least one embodiment of this disclosure, the first clock signal line is disposed on the first side and / or the second side of the first via;

[0118] The first side and the second side are opposite sides.

[0119] For example, the first side can be the upper side, and the second side can be the lower side.

[0120] As shown in Figure 1A, the first clock signal line CKB11 is disposed on the upper side of the first via H11, and the second clock signal line CKB21 is disposed on the upper side of the second via H21.

[0121] In practice, CKB11 can also be located below H11, and CKB21 can also be located below H21.

[0122] In at least one embodiment of this disclosure, the extension direction of the first clock signal line is a first direction or a second direction, the first direction intersects with a third direction and is not perpendicular to the third direction; the second direction intersects with the third direction and is not perpendicular to the third direction.

[0123] The array substrate includes data lines disposed in the display area, and the data lines extend along the third direction.

[0124] Optionally, the third direction can be the vertical direction.

[0125] As shown in Figure 1A, the first clock signal line CKB11 extends along the first direction, and the second clock signal line CKB21 extends along the second direction. The extension directions of CKB11 and CKB21 are inclined.

[0126] In at least one embodiment shown in Figure 1A, the linewidth of CKB12 can be the same as the linewidth of CKB22, the linewidth of CKB32 can be the same as the linewidth of CKB42, the linewidth of CKB12 can be the same as the linewidths of CLK6, CLK8, CLK10, CLK12, CLK14, and CLK16, and the linewidth of CKB32 can be the same as the linewidths of CLK6, CLK8, CLK10, CLK12, CLK14, and CLK16.

[0127] In Figure 1A, CLK2, CLK4, CLK6, CLK8, CLK10, CLK12, CLK14 and CLK16 are arranged sequentially along the direction away from the display area.

[0128] Figure 7B is a layout diagram of the gate metal layer in Figure 1A, Figure 7C is a layout diagram of the semiconductor layer in Figure 1A, Figure 7D is a layout diagram of the source and drain metal layers in Figure 1A, and Figure 7E is a layout diagram of the ITO (indium tin oxide) layer in Figure 1A.

[0129] As shown in Figure 1B, the second clock signal line CLK2, the fourth clock signal line CLK4, the sixth clock signal line CLK6, the eighth clock signal line CLK8, the tenth clock signal line CLK10, the twelfth clock signal line CLK12, the fourteenth clock signal line CLK14, the sixteenth clock signal line CLK16, the second starting voltage line STV2, and the fourth starting voltage line STV4 are arranged sequentially along the side away from the display area.

[0130] The fifth first via H51 is electrically connected to CLK6, and the sixth first via H61 is electrically connected to CLK8;

[0131] CLK4 is adjacent to H51, and CLK6 is adjacent to H61;

[0132] CLK4 includes a third first clock signal line section CKB31, a fourth first clock signal line section CKB41, a fifth second clock signal line section CKB52, a sixth second clock signal line section CKB62, and a seventh second clock signal line section CKB72;

[0133] The line width of CKB31 is greater than that of CKB52, the line width of CKB31 is greater than that of CKB62, and the line width of CKB31 is greater than that of CKB72.

[0134] The line width of CKB41 is greater than that of CKB52, the line width of CKB41 is greater than that of CKB62, and the line width of CKB41 is greater than that of CKB72.

[0135] CKB31 is located on the upper side of H51, and CKB41 is located on the lower side of H51;

[0136] Optionally, the line width of CKB31 can be equal to that of CKB41; the line widths of the fifth second clock signal line CKB52, the sixth second clock signal line CKB62, and the seventh second clock signal line CKB72 can be the same.

[0137] CKB51 is located on the upper side of H61, and CKB61 is located on the lower side of H61;

[0138] CLK6 includes a fifth first clock signal line section CKB51, a sixth first clock signal line section CKB61, an eighth second clock signal line section CKB82, a ninth second clock signal line section CKB92, and a tenth second clock signal line section CKB102;

[0139] The line width of CKB51 is greater than that of CKB82, the line width of CKB51 is greater than that of CKB92, and the line width of CKB51 is greater than that of CKB102.

[0140] The line width of CKB61 is greater than that of CKB82, the line width of CKB61 is greater than that of CKB92, and the line width of CKB61 is greater than that of CKB102.

[0141] Optionally, the line width of CKB51 is equal to that of CKB61; optionally, the line widths of the eighth second clock signal line CKB82, the ninth second clock signal line CKB92, and the tenth second clock signal line CKB102 are the same.

[0142] Figure 1C is a layout diagram of the gate metal layer in Figure 1B, Figure 1D is a layout diagram of the source and drain metal layers in Figure 1B, and Figure 1E is a layout diagram of the ITO layer in Figure 1B.

[0143] As shown in Figures 1B-1E, the extension direction of CKB31 is inclined, the extension direction of CKB41 is inclined, the extension direction of CKB51 is inclined, and the extension direction of CKB61 is inclined.

[0144] As shown in Figure 1C, the line width of CKB52 can be the same as that of CLK8, the line width of CKB62 can be the same as that of CLK8, the line width of CKB72 can be the same as that of CLK8, the line width of CKB82 can be the same as that of CLK8, the line width of CKB92 can be the same as that of CLK8, and the line width of CKB102 can be the same as that of CLK8.

[0145] In Figure 1D, the part labeled LTB1 is the first connecting graphic part, and the part labeled LTB2 is the second connecting graphic part.

[0146] In Figure 1E, the third connection figure is labeled LX3.

[0147] In at least one embodiment of this disclosure, the signal line is the clock signal line; the first via is electrically connected to a first connection portion formed in the first metal layer and a second connection portion formed in the second metal layer, respectively;

[0148] The area of ​​the first connecting part is larger than the area of ​​the second connecting part.

[0149] Optionally, the first metal layer can be a gate metal layer, and the second metal layer can be a source / drain metal layer.

[0150] In a specific implementation, when the first via is electrically connected to the clock signal line, the first connection portion formed in the gate metal layer that is electrically connected to the first via can be compensated so that the area of ​​the first connection portion is larger than the area of ​​the second connection portion. This can reduce the line resistance at the via of the clock signal line, thereby reducing the difference between the rise times of the clock signals provided by each clock signal line and reducing the charging difference.

[0151] In at least one embodiment shown in Figures 2 and 5, the second clock signal line CLK2, the fourth clock signal line CLK4, the sixth clock signal line CLK6, the eighth clock signal line CLK8, the tenth clock signal line CLK10, the twelfth clock signal line CLK12, the fourteenth clock signal line CLK14, and the sixteenth clock signal line CLK16 are arranged sequentially in a direction away from the display area.

[0152] In Figures 2 and 5, the third first via is labeled H31, and the fourth first via is labeled H41.

[0153] H31 is electrically connected to CLK2, and H41 is electrically connected to CLK4;

[0154] CLK2 and CLK4 are the two clock signal lines closest to the display area;

[0155] Figure 3 is a layout diagram of the gate metal layer in Figure 2, Figure 4 is a layout diagram of the source and drain metal layers in Figure 2, and Figure 5 is a layout diagram of the ITO (indium tin oxide) layer in Figure 2.

[0156] In Figure 5, the fourth connection figure is labeled LX4.

[0157] As shown in Figures 2-4, H31 is electrically connected to the first first connection portion L11 formed in the gate metal layer and the first second connection portion L12 formed in the source and drain metal layers, respectively.

[0158] H41 is electrically connected to the second first connection portion L21 formed on the gate metal layer and the second second connection portion L22 formed on the source and drain metal layers, respectively.

[0159] The area of ​​L11 is greater than the area of ​​L12, and the area of ​​L21 is greater than the area of ​​L22.

[0160] In at least one embodiment of this disclosure, the signal line is the clock signal line; the first via is electrically connected to a first connection portion formed on the first metal layer and a second connection portion formed on the second metal layer; the second connection portion includes a first edge and a second edge, the first edge and the second edge intersect, and the first connection portion includes a portion away from the second connection portion along the extension line of the first edge.

[0161] Figure 6A is the layout diagram of Figure 2 with the ITO layer removed.

[0162] As shown in Figure 6A, the first second connecting part L12 includes a first first edge and a first second edge B12;

[0163] In Figure 6A, the line labeled Y11 is the first extension of the first edge;

[0164] The first first connecting portion L11 includes a portion along the first first edge extension line Y11 away from the first second connecting portion L12;

[0165] The second connecting portion L22 includes a second first edge and a second second edge B22;

[0166] In Figure 6A, the line labeled Y21 is the second extension of the first edge;

[0167] The second first connecting portion L21 includes a portion along the extension line Y21 of the second first edge away from the second second connecting portion L22.

[0168] In at least one embodiment of this disclosure, the first connecting portion includes a first connecting portion and at least one second connecting portion; the second connecting portion is disposed on a third side and / or a fourth side of the first connecting portion;

[0169] The third side and the fourth side are opposite sides.

[0170] Optionally, the third side can be the upper side, and the fourth side can be the lower side.

[0171] Optionally, the second connecting portion is a triangular connecting portion.

[0172] As shown in Figure 3, the first connecting part L11 includes a first connecting portion LB11 and a first connecting portion LB12; LB12 is a triangular connecting portion.

[0173] LB12 is positioned above LB11;

[0174] The second first connecting part L21 includes a second first connecting portion LB21 and a second second connecting portion LB22; LB22 is a triangular connecting portion;

[0175] LB22 is positioned above LB21.

[0176] As shown in Figure 6B, in at least one embodiment of this disclosure, the first first connecting portion L11 may include a first first connecting portion LB11, a first second connecting portion LB12, and a third second connecting portion LB32; optionally, LB12 and LB32 are triangular connecting portions; it should be noted that LB12 and LB32 can be other shapes, such as other polygons, trapezoids, irregular shapes, etc., optionally, at least a portion of the side of the LB12 and / or LB32 shape is in contact with the side of the clock signal;

[0177] LB12 is located above LB11, and LB32 is located below LB11;

[0178] The second first connecting part L21 includes a second first connecting portion LB21, a second second connecting portion LB22, and a fourth second connecting portion LB42; LB22 and LB42 are triangular connecting portions;

[0179] LB22 is positioned above LB21, and LB42 is positioned below LB21.

[0180] In at least one embodiment of this disclosure, the surrounding area includes a regular area and an irregularly shaped area; the driving module includes a first driving circuit disposed in the regular area and a second driving circuit disposed in the irregularly shaped area; the first driving circuit includes a first driving transistor and a first storage capacitor; the second driving circuit includes a second driving transistor and a second storage capacitor;

[0181] The shape of the first storage capacitor is different from the shape of the second storage capacitor;

[0182] The shape of the first driving transistor is different from the shape of the second driving transistor.

[0183] In practice, the surrounding area can include regular areas and irregularly shaped areas;

[0184] As shown in Figure 7F, the drive module may include a first drive circuit GA1 disposed in the regular area AG;

[0185] As shown in Figure 8F, the driving module may include a second driving circuit GA2 disposed in the irregular region AY;

[0186] As shown in Figure 7A, the first driving circuit includes a first driving transistor M01 and a first storage capacitor C11.

[0187] As shown in Figure 8A, the second driving circuit includes a second driving transistor M02 and a second storage capacitor C21.

[0188] As shown in Figures 7A and 8A, the shape of C11 is different from that of C21, and the shape of M01 is different from that of M02.

[0189] As shown in Figure 7A, M14 is positioned between M12 and M13.

[0190] Figure 7B is a layout diagram of the gate metal layer in Figure 7A, Figure 7C is a layout diagram of the semiconductor layer in Figure 7A, Figure 7D is a layout diagram of the source and drain metal layers in Figure 7A, and Figure 7E is a layout diagram of the ITO (indium tin oxide) layer in Figure 7A.

[0191] Figure 8B is a layout diagram of the gate metal layer in Figure 8A, Figure 8C is a layout diagram of the semiconductor layer in Figure 8A, Figure 8D is a layout diagram of the source and drain metal layers in Figure 8A, and Figure 8E is a layout diagram of the ITO (indium tin oxide) layer in Figure 8A.

[0192] In at least one embodiment of this disclosure, the gate of the second driving transistor includes a plurality of second gate portions;

[0193] The first plate and the gate of the second storage capacitor are formed on the first metal layer;

[0194] The first electrode plate has a first clearance space to allow at least one of the second gate portions to pass.

[0195] As shown in Figure 8B, the gate of the second driving transistor M02 includes a first second gate portion GB12, a second second gate portion GB22, and a third second gate portion GB32.

[0196] The first plate C21a of the second storage capacitor C21 is formed on the gate metal layer, and C21a has a first clearance space AB1 to avoid the third second gate portion GB32.

[0197] In at least one embodiment of this disclosure, the array substrate includes data lines disposed in the display area, the data lines extending along a third direction; a fourth direction is perpendicular to the third direction; the gate of the first driving transistor includes a plurality of first gate portions, and the gate of the second driving transistor includes a plurality of second gate portions;

[0198] The sum of the widths of the plurality of first gate portions along the fourth direction is greater than the widths of the plurality of second gate portions along the fourth direction.

[0199] Optionally, the third direction can be a vertical direction, and the fourth direction can be a horizontal direction.

[0200] As shown in Figure 7B, the gate of the first driving transistor M01 includes a first gate portion GB11, a second gate portion GB21 and a third gate portion GB31;

[0201] As shown in Figure 8B, the gate of the second driving transistor M02 includes a first second gate portion GB12, a second second gate portion GB22, and a third second gate portion GB32.

[0202] As shown in Figures 7B and 8B, the sum of the horizontal widths of GB11, GB21, and GB31 is greater than the sum of the horizontal widths of GB12, GB22, and GB32.

[0203] In practical implementation, since the width of the irregular region along the horizontal direction is relatively narrow, the sum of the widths of the plurality of second gate portions along the horizontal direction is set to be less than the widths of the plurality of first gate portions along the horizontal direction, so as to adapt to the transistor layout of the irregular region, making the layout of the driving circuit area more reasonable, thereby achieving the effect of reducing the bezel.

[0204] Optionally, the first driving circuit includes a first reset circuit, and the second driving circuit includes a second reset circuit; the first reset circuit is used to control the potential of the first first node under the control of the first reset terminal; the second reset circuit is used to control the potential of the second first node under the control of the second reset terminal.

[0205] The first reset circuit includes a first transistor, and the second reset circuit includes a second first transistor;

[0206] The shape of the first transistor is different from the shape of the second transistor.

[0207] As shown in Figure 7A, the first driving circuit includes a first reset circuit, and the first reset circuit includes a first transistor M11.

[0208] As shown in Figure 8A, the second driving circuit includes a second reset circuit, and the second reset circuit includes a second first transistor M21;

[0209] The shape of M11 is different from that of M21.

[0210] As shown in Figure 7C, the first transistor M11 includes the first active pattern A11;

[0211] As shown in Figure 8C, the second first transistor M21 includes a second first active pattern A21;

[0212] As shown in Figures 7C and 8C, the length of A11 in the vertical direction is greater than the length of A21 in the vertical direction, and the width of A11 in the horizontal direction is less than the width of A21 in the horizontal direction.

[0213] In Figure 7C, the active pattern labeled A01 is M01, the active pattern labeled A11 is M11, the active pattern labeled A12 is M12, the active pattern labeled A13 is M13, the active pattern labeled A14 is M14, the active pattern labeled A15 is M15, the active pattern labeled A16 is M16, the active pattern labeled A17 is M17, the active pattern labeled A18 is M18, the active pattern labeled A19 is M19, and the active pattern labeled A110 is M110.

[0214] In Figure 7D, the electrode labeled S11 is the source of M11, and the electrode labeled D11 is the drain of M11.

[0215] In Figure 7E, the first connection diagram is labeled LX1, and the second connection diagram is labeled LX2.

[0216] In Figure 8C, the active graphic labeled A02 is M02, the active graphic labeled A21 is M21, the active graphic labeled A22 is M22, the active graphic labeled A23 is M23, the active graphic labeled A24 is M24, the active graphic labeled A25 is M25, the active graphic labeled A26 is M26, the active graphic labeled A27 is M27, the active graphic labeled A28 is M28, the active graphic labeled A29 is M29, and the active graphic labeled A210 is M210.

[0217] In Figure 8D, the electrode labeled S21 is the source of M21, and the electrode labeled D21 is the drain of M21.

[0218] In Figure 8E, the figure labeled LX3 is the third connection figure.

[0219] In at least one embodiment of this disclosure, the first driving circuit includes a first first node reset circuit, a first output reset circuit, and a first first frame reset circuit; the second driving circuit includes a second first node reset circuit, a second output reset circuit, and a second first frame reset circuit.

[0220] The first first node reset circuit is used to reset the potential of the first first node under the control of the potential of the first second node; the first output reset circuit is used to reset the first driving signal provided by the first driving signal output terminal under the control of the potential of the first second node; the first first frame reset circuit is used to reset the first driving signal under the control of the frame reset line; the second first node reset circuit is used to reset the potential of the second first node under the control of the potential of the second second node; the second output reset circuit is used to reset the second driving signal provided by the second driving signal output terminal under the control of the potential of the second second node; the second first frame reset circuit is used to reset the second driving signal under the control of the frame reset line; the first first node reset circuit includes a first second transistor, the first output reset circuit includes a first third transistor, and the first first frame reset circuit includes a first fourth transistor; the second first node reset circuit includes a second second transistor, the second output reset circuit includes a second third transistor, and the second first frame reset circuit includes a second fourth transistor; the array substrate includes data lines disposed in the display area, the data lines extending along a third direction; the fourth direction is perpendicular to the third direction;

[0221] The first second transistor, the first fourth transistor, and the first third transistor are arranged along the fourth direction;

[0222] The second transistor and the second fourth transistor are arranged along the third direction, and the second transistor and the second third transistor are arranged along the fourth direction.

[0223] As shown in Figure 7A, the first first node reset circuit includes a first second transistor M12, the first output reset circuit includes a first third transistor M13, and the first first frame reset circuit includes a first fourth transistor M14.

[0224] As shown in Figure 8A, the second first node reset circuit includes a second second transistor M22, the second output reset circuit includes a second third transistor M23, and the second first frame reset circuit includes a second fourth transistor M24.

[0225] As shown in Figures 7A and 8A, M12, M14 and M13 are arranged sequentially along the horizontal direction;

[0226] M22 and M24 are arranged vertically, while M22 and M23 are arranged horizontally.

[0227] Optionally, the channel of the first fourth transistor extends along a third direction, and the channel of the second fourth transistor extends along a fourth direction.

[0228] As shown in Figures 7A and 8A, the channel of M14 extends vertically, while the channel of M24 extends horizontally.

[0229] In at least one embodiment of this disclosure, the first driving circuit includes a first second frame reset circuit, a first pull-down control node control circuit, and a first second node reset circuit, and the second driving circuit includes a second second frame reset circuit, a second pull-down control node control circuit, and a second second node reset circuit.

[0230] The first second frame reset circuit is used to reset the potential of the first first node under the control of the frame reset line; the first pull-down control node control circuit is used to control the potential of the first pull-down control node; the first second node reset circuit is used to reset the potential of the first second node under the control of the potential of the first first node; the second second frame reset circuit is used to reset the potential of the second first node under the control of the frame reset line; the second pull-down control node control circuit is used to control the potential of the second pull-down control node; the second second node reset circuit is used to reset the potential of the second second node under the control of the potential of the second first node.

[0231] The first second frame reset circuit includes a first fifth transistor, the first pull-down control node control circuit includes a first sixth transistor and a first seventh transistor, and the first second node reset circuit includes a first eighth transistor; the second second frame reset circuit includes a second fifth transistor, the second pull-down control node control circuit includes a second sixth transistor and a second seventh transistor, and the second second node reset circuit includes a second eighth transistor; the array substrate includes data lines disposed in the display area, and the data lines extend along a third direction;

[0232] The first seventh transistor and the first sixth transistor are arranged along the third direction, and the first eighth transistor and the first fifth transistor are arranged along the third direction;

[0233] The second seventh transistor, the second sixth transistor, and the second fifth transistor are arranged along a third direction, and the second eighth transistor and the second fifth transistor are arranged along a third direction.

[0234] As shown in Figure 7A, the first second frame reset circuit includes a first fifth transistor M15, the first pull-down control node control circuit includes a first sixth transistor M16 and a first seventh transistor M17, and the first second node reset circuit includes a first eighth transistor M18.

[0235] As shown in Figure 8A, the second second frame reset circuit includes a second fifth transistor M25, the second pull-down control node control circuit includes a second sixth transistor M26 and a second seventh transistor M27, and the second second node reset circuit includes a second eighth transistor M28.

[0236] As shown in Figures 7A and 8A, M17 and M16 are arranged vertically, and M18 and M15 are arranged vertically.

[0237] M27, M26, and M25 are arranged vertically, while M28 and M25 are arranged vertically.

[0238] Optionally, the channel of the first seventh transistor extends along a third direction; the channel of the second seventh transistor extends along a fourth direction.

[0239] The third direction is perpendicular to the fourth direction.

[0240] As shown in Figures 7A and 7B, the channel of M17 extends vertically, while the channel of M27 extends horizontally.

[0241] In at least one embodiment of this disclosure, the first driving circuit includes a first second node control circuit, and the second driving circuit includes a second second node control circuit; the first second node control circuit is used to control the potential of the first second node under the control of the potential of the first pull-down control node; the second second node control circuit is used to control the potential of the second second node under the control of the potential of the second pull-down control node.

[0242] The first second node control circuit includes a first ninth transistor, and the second second node control circuit includes a second ninth transistor;

[0243] The channel of the first ninth transistor extends along the fourth direction; the channel of the second ninth transistor extends along the third direction.

[0244] The third direction is perpendicular to the fourth direction.

[0245] As shown in Figure 7A, the first second node control circuit includes a first ninth transistor M19; as shown in Figure 7B, the second second node control circuit includes a second ninth transistor M29.

[0246] The channel of M19 extends horizontally, while the channel of M29 extends vertically.

[0247] As shown in Figure 9, the first driving circuit includes a first reset circuit 91, a first output circuit 90, and a first energy storage circuit 900.

[0248] The first output circuit 90 is electrically connected to the first first node PU1, the first output clock signal terminal CK1 and the first drive signal output terminal OT1 respectively, and is used to control the connection or disconnection between the first drive signal output terminal OT1 and the first output clock signal terminal CK1 under the control of the potential of the first first node PU1.

[0249] The first energy storage circuit 900 is electrically connected to the first first node PU1 and the first drive signal output terminal OT1 respectively, and is used to control the potential of the first first node PU1 according to the first drive signal provided by the first drive signal output terminal OT1.

[0250] The first reset circuit 91 is electrically connected to the first reset terminal RST1, the first first node PU1, and the second control voltage line VSD, respectively, and is used to control the connection or disconnection between the first first node PU1 and the second control voltage line VSD under the control of the first reset terminal RST1.

[0251] The first driving circuit includes a first first node reset circuit 92, a first output reset circuit 93, and a first first frame reset circuit 94;

[0252] The first first node reset circuit 92 is electrically connected to the first first node PU1, the first second node PD1 and the low voltage line VGL respectively, and is used to control the connection or disconnection between the first first node PU1 and the low voltage line VGL under the control of the potential of the first second node PD1.

[0253] The first output reset circuit 93 is electrically connected to the first second node PD1, the first drive signal output terminal OT1 and the low voltage line VGL, respectively, and is used to control the connection or disconnection between the first drive signal output terminal OT1 and the low voltage line VGL under the control of the potential of the first second node PD1.

[0254] The first frame reset circuit 94 is electrically connected to the frame reset line STV0, the first drive signal output terminal OT1 and the low voltage line VGL, respectively, and is used to control the connection or disconnection between the first drive signal output terminal OT1 and the low voltage line VGL under the control of the frame reset line STV0.

[0255] The first driving circuit includes a first second frame reset circuit 95, a first pull-down control node control circuit 96, and a first second node reset circuit 97;

[0256] The first second frame reset circuit 95 is electrically connected to the frame reset line STV0, the first first node PU1 and the low voltage line VGL respectively, and is used to control the connection or disconnection between the first first node PU1 and the low voltage line VGL under the control of the frame reset line STV0.

[0257] The first pull-down control node control circuit 96 is electrically connected to the high voltage line GCH, the first pull-down control node PDCN1, the first first node PU1 and the low voltage line VGL respectively, and is used to control the potential of the first pull-down control node PDCN1 under the control of the potential of the first first node PU1.

[0258] The first second node reset circuit 97 is electrically connected to the first first node PU1, the first second node PD1 and the low voltage line VGL respectively, and is used to control the connection or disconnection between the first second node PD1 and the low voltage line VGL under the control of the potential of the first first node PU1.

[0259] The first driving circuit includes a first second node control circuit 98;

[0260] The first second node control circuit 98 is electrically connected to the first pull-down control node PDCN1, the first second node PD1 and the high voltage line GCH respectively, and is used to control the connection or disconnection between the first second node PD1 and the high voltage line GCH under the control of the potential of the first pull-down control node PDCN1.

[0261] The first driving circuit includes a first input circuit 99;

[0262] The first input circuit 99 is electrically connected to the first input terminal I1, the first control voltage line VDS and the first first node PU1 respectively, and is used to control the connection or disconnection between the first first node PU1 and the first control voltage line VDS under the control of the first input terminal I1.

[0263] As shown in Figure 10, based on at least one embodiment of the first driving circuit shown in Figure 9, the first reset circuit includes a first first transistor M11; the first output circuit includes a first driving transistor M01; and the first energy storage circuit includes a first storage capacitor C11.

[0264] The first first node reset circuit includes a first second transistor M12; the first output reset circuit includes a first third transistor M13; the first first frame reset circuit includes a first fourth transistor M14; the first second frame reset circuit includes a first fifth transistor M15; the first pull-down control node control circuit includes a first sixth transistor M16 and a first seventh transistor M17; the first second node reset circuit includes a first eighth transistor M18; the first second node control circuit includes a first ninth transistor M19; and the first input circuit includes a first tenth transistor M110.

[0265] The gate of M01 is electrically connected to the first node PU1, the source of M01 is electrically connected to the first output clock signal terminal CK1, and the drain of M01 is electrically connected to the first drive signal output terminal OT1.

[0266] The first end of C11 is electrically connected to the first node PU1, and the second end of C11 is electrically connected to the first drive signal output terminal OT1.

[0267] The gate of M11 is electrically connected to the first reset terminal RST1, the source of M11 is electrically connected to the first node PU1, and the drain of M11 is electrically connected to the second control voltage line VSD.

[0268] The gate of M12 is electrically connected to the first second node PD1, the source of M12 is electrically connected to the first first node PU1, and the drain of M12 is electrically connected to the low voltage line VGL.

[0269] The gate of M13 is electrically connected to the first second node PD1, the source of M13 is electrically connected to the first drive signal output terminal OT1, and the drain of M13 is electrically connected to the low voltage line VGL.

[0270] The gate of M14 is electrically connected to the frame reset line STV0, the source of M14 is electrically connected to the first drive signal output terminal OT1, and the drain of M14 is electrically connected to the low voltage line VGL.

[0271] The gate of M15 is electrically connected to the frame reset line STV0, the source of M15 is electrically connected to the first node PU1, and the drain of M15 is electrically connected to the low voltage line VGL.

[0272] The gate of M16 is electrically connected to the first node PU1, the source of M16 is electrically connected to the first pull-down control node PDCN1, and the drain of M16 is electrically connected to the low voltage line VGL.

[0273] The gate and source of M17 are electrically connected to the high voltage line GCH, and the drain of M17 is electrically connected to the first pull-down control node PDCN1.

[0274] The gate of M18 is electrically connected to the first node PU1, the source of M18 is electrically connected to the first node PD1, and the drain of M18 is electrically connected to the low voltage line VGL.

[0275] The gate of M19 is electrically connected to the first pull-down control node PDCN1, the source of M19 is electrically connected to the high voltage line GCH, and the drain of M19 is electrically connected to the first second node PD1.

[0276] The gate of M110 is electrically connected to the first input terminal I1, the source of M110 is electrically connected to the first control voltage line VDS, and the drain of M110 is electrically connected to the first node PU1.

[0277] Optionally, the first input terminal I1 of M110 and the source of M110 can be electrically connected.

[0278] In at least one embodiment shown in Figure 10, all transistors are n-type transistors.

[0279] As shown in Figure 11, the second driving circuit includes a second reset circuit 111, a second output circuit 110, and a second energy storage circuit 1100.

[0280] The second output circuit 110 is electrically connected to the second first node PU2, the second output clock signal terminal CK2 and the first drive signal output terminal OT1 respectively, and is used to control the connection or disconnection between the first drive signal output terminal OT1 and the second output clock signal terminal CK2 under the control of the potential of the second first node PU2.

[0281] The second energy storage circuit 1100 is electrically connected to the second first node PU2 and the second drive signal output terminal OT1, respectively, and is used to control the potential of the second first node PU2 according to the second drive signal provided by the second drive signal output terminal OT2;

[0282] The second reset circuit 111 is electrically connected to the second reset terminal RST2, the second first node PU2, and the second control voltage line VSD, respectively, and is used to control the connection or disconnection between the second first node PU2 and the second control voltage line VSD under the control of the second reset terminal RST2.

[0283] The second driving circuit includes a second first node reset circuit 112, a second output reset circuit 113, and a second first frame reset circuit 114;

[0284] The second first node reset circuit 112 is electrically connected to the second first node PU2, the second second node PD2 and the low voltage line VGL respectively, and is used to control the connection or disconnection between the second first node PU2 and the low voltage line VGL under the control of the potential of the second second node PD2.

[0285] The second output reset circuit 113 is electrically connected to the second second node PD2, the second drive signal output terminal OT2 and the low voltage line VGL, respectively, and is used to control the connection or disconnection between the second drive signal output terminal OT2 and the low voltage line VGL under the control of the potential of the second second node PD2.

[0286] The second first frame reset circuit 114 is electrically connected to the frame reset line STV0, the second drive signal output terminal OT2 and the low voltage line VGL, respectively, and is used to control the connection or disconnection between the second drive signal output terminal OT2 and the low voltage line VGL under the control of the frame reset line STV0.

[0287] The second driving circuit includes a second second frame reset circuit 115, a second pull-down control node control circuit 116, and a second second node reset circuit 117;

[0288] The second frame reset circuit 115 is electrically connected to the frame reset line STV0, the second first node PU2 and the low voltage line VGL, respectively, and is used to control the connection or disconnection between the second first node PU2 and the low voltage line VGL under the control of the frame reset line STV0.

[0289] The second pull-down control node control circuit 116 is electrically connected to the high voltage line GCH, the second pull-down control node PDCN2, the second first node PU2 and the low voltage line VGL, respectively, and is used to control the potential of the second pull-down control node PDCN2 under the control of the potential of the second first node PU2.

[0290] The second second node reset circuit 117 is electrically connected to the second first node PU1, the second second node PD2 and the low voltage line VGL respectively, and is used to control the connection or disconnection between the second second node PD2 and the low voltage line VGL under the control of the potential of the second first node PU2.

[0291] The second driving circuit includes a second second node control circuit 118;

[0292] The second second node control circuit 118 is electrically connected to the second pull-down control node PDCN2, the second second node PD2 and the high voltage line GCH respectively, and is used to control the connection or disconnection between the second second node PD1 and the high voltage line GCH under the control of the potential of the second pull-down control node PDCN2.

[0293] The second driving circuit includes a second input circuit 119;

[0294] The second input circuit 119 is electrically connected to the second input terminal I2, the first control voltage line VDS and the second first node PU2 respectively, and is used to control the connection or disconnection between the second first node PU2 and the first control voltage line VDS under the control of the second input terminal I2.

[0295] As shown in Figure 12, based on at least one embodiment of the first driving circuit shown in Figure 11, the second reset circuit includes a second first transistor M21; the second output circuit includes a second driving transistor M02; and the second energy storage circuit includes a second storage capacitor C21.

[0296] The second first node reset circuit includes a second second transistor M22; the second output reset circuit includes a second third transistor M23; the second first frame reset circuit includes a second fourth transistor M24; the second second frame reset circuit includes a second fifth transistor M25; the second pull-down control node control circuit includes a second sixth transistor M26 and a second seventh transistor M27; the second second node reset circuit includes a second eighth transistor M28; the second second node control circuit includes a second ninth transistor M29; and the second input circuit includes a second tenth transistor M210.

[0297] The gate of M02 is electrically connected to the second first node PU2, the source of M02 is electrically connected to the second output clock signal terminal CK2, and the drain of M02 is electrically connected to the second drive signal output terminal OT2.

[0298] The first end of C21 is electrically connected to the second first node PU2, and the second end of C21 is electrically connected to the second drive signal output terminal OT2.

[0299] The gate of M21 is electrically connected to the second reset terminal RST2, the source of M21 is electrically connected to the second first node PU2, and the drain of M21 is electrically connected to the second control voltage line VSD.

[0300] The gate of M22 is electrically connected to the second second node PD2, the source of M22 is electrically connected to the second first node PU2, and the drain of M22 is electrically connected to the low voltage line VGL.

[0301] The gate of M23 is electrically connected to the second node PD2, the source of M23 is electrically connected to the second drive signal output terminal OT2, and the drain of M23 is electrically connected to the low voltage line VGL.

[0302] The gate of M24 is electrically connected to the frame reset line STV0, the source of M24 is electrically connected to the second drive signal output terminal OT2, and the drain of M24 is electrically connected to the low voltage line VGL.

[0303] The gate of M25 is electrically connected to the frame reset line STV0, the source of M25 is electrically connected to the second first node PU2, and the drain of M25 is electrically connected to the low voltage line VGL.

[0304] The gate of M26 is electrically connected to the second first node PU2, the source of M26 is electrically connected to the second pull-down control node PDCN2, and the drain of M26 is electrically connected to the low voltage line VGL.

[0305] The gate and source of M27 are electrically connected to the high voltage line GCH, and the drain of M27 is electrically connected to the second pull-down control node PDCN2.

[0306] The gate of M28 is electrically connected to the second first node PU2, the source of M28 is electrically connected to the second second node PD2, and the drain of M28 is electrically connected to the low voltage line VGL.

[0307] The gate of M29 is electrically connected to the second pull-down control node PDCN2, the source of M29 is electrically connected to the high voltage line GCH, and the drain of M29 is electrically connected to the second node PD2.

[0308] The gate of M210 is electrically connected to the second input terminal I2, the source of M210 is electrically connected to the first control voltage line VDS, and the drain of M210 is electrically connected to the second first node PU2.

[0309] Optionally, the second input terminal I2 of M210 and the source of M210 can be electrically connected.

[0310] In at least one embodiment shown in Figure 12, all transistors are n-type transistors.

[0311] In at least one embodiment of this disclosure, the surrounding area includes an irregularly shaped area;

[0312] Within the irregularly shaped area, the line width of the clock signal line furthest from the display area is greater than the line width of the clock signal line closest to the display area within the irregularly shaped area.

[0313] As shown in Figure 13, in the irregular area AY, the clock signal line farthest from the display area is the sixteenth clock signal line CLK16.

[0314] The sixteenth clock signal line CLK16, the fourteenth clock signal line CLK14, the twelfth clock signal line CLK12, the tenth clock signal line CLK10, the eighth clock signal line CLK8, the sixth clock signal line CLK6, the fourth clock signal line CLK4, and the second clock signal line CLK2 are arranged sequentially along the direction closest to the display area;

[0315] The line width of CLK16 is greater than that of CLK2.

[0316] In irregularly shaped areas, the further away from the display area, the longer the distance of the clock signal lines. In at least one embodiment of this disclosure, in irregularly shaped areas, the extra space can be used to widen the line width of the clock signal lines furthest from the display area, thereby reducing the line resistance of the outermost clock signal lines in irregularly shaped areas. This reduces the difference in the rise time of the clock signals provided by each clock signal line, thereby reducing the charging difference and reducing the brightness difference between each row of pixels. This optimizes the fine horizontal stripe phenomenon caused by brightness differences in grayscale.

[0317] The array substrate described in at least one embodiment of this disclosure further includes a start voltage line;

[0318] The starting voltage line is located on the side of the clock signal line away from the display area to shorten the length of each clock signal line and reduce the line resistance of the clock signal line.

[0319] As shown in Figure 14, the second starting voltage line SV2 and the fourth starting voltage line STV4 are located on the side of each clock signal line away from the display area.

[0320] Figure 15A is a structural diagram of the second storage capacitor C21;

[0321] Figure 15B is a layout diagram of the gate metal layer in Figure 15A, Figure 15C is a layout diagram of the source and drain metal layers in Figure 15A, and Figure 15D is a layout diagram of the ITO layer in Figure 15A.

[0322] In Figure 15B, the first plate of C21 is labeled C21a;

[0323] In Figure 15C, the plate labeled C21b is the second plate of C21;

[0324] In Figure 15D, the plate labeled C21c is the third plate of C21;

[0325] C21a can be electrically connected to C21b, and C21c is located between C21a and C21b.

[0326] As shown in Figures 15A-15D, in the irregular region, the electrode plate of C21 is provided with a groove, and the size of the groove can be different in different irregular regions.

[0327] In at least one embodiment of this disclosure, the peripheral region includes a first peripheral region and a second peripheral region, the first peripheral region being disposed on the fifth side of the display region, and the second peripheral region being disposed on the sixth side of the display region; the fifth side and the sixth side are opposite sides; the array substrate includes a first driving module and a second driving module, the first driving module being disposed in the first peripheral region, and the second driving module including the second peripheral region; n is a positive integer;

[0328] The drive signal output terminal of the (4n-3)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+4)th stage drive circuit included in the first drive module; the drive signal output terminal of the (4n-2)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+3)th stage drive circuit included in the first drive module; the drive signal output terminal of the (4n-1)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+2)th stage drive circuit included in the first drive module; the drive signal output terminal of the (4n)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+1)th stage drive circuit included in the first drive module; and / or Alternatively, the drive signal output terminal of the 4n+4th stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4n-3th stage drive circuit included in the first drive module; the drive signal output terminal of the 4n+3rd stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4n-2th stage drive circuit included in the first drive module; the drive signal output terminal of the 4n+2nd stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4n-1th stage drive circuit included in the first drive module; and the drive signal output terminal of the 4n+1st stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4nth stage drive circuit included in the first drive module.

[0329] The drive signal output terminal of the (4n-3)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+4)th stage drive circuit included in the second drive module; the drive signal output terminal of the (4n-2)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+3)th stage drive circuit included in the second drive module; the drive signal output terminal of the (4n-1)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+2)th stage drive circuit included in the second drive module; the drive signal output terminal of the (4n)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+1)th stage drive circuit included in the second drive module; and / or Alternatively, the drive signal output terminal of the 4n+4th stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4n-3th stage drive circuit included in the second drive module; the drive signal output terminal of the 4n+3rd stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4n-2th stage drive circuit included in the second drive module; the drive signal output terminal of the 4n+2nd stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4n-1th stage drive circuit included in the second drive module; and the drive signal output terminal of the 4n+1st stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4nth stage drive circuit included in the second drive module.

[0330] Optionally, the fifth side can be the right side, and the sixth side can be the left side.

[0331] In at least one embodiment of this disclosure, the array substrate includes sixteen clock signal lines; the first clock signal line, the third clock signal line, the fifth clock signal line, the seventh clock signal line, the ninth clock signal line, the eleventh clock signal line, the thirteenth clock signal line, and the fifteenth clock signal line are all disposed in the second peripheral region; the second clock signal line, the fourth clock signal line, the sixth clock signal line, the eighth clock signal line, the tenth clock signal line, the twelfth clock signal line, the fourteenth clock signal line, and the sixteenth clock signal line are all disposed in the first peripheral region;

[0332] The first driving module includes an 8m-7th stage driving circuit electrically connected to the first clock signal line, an 8m-6th stage driving circuit electrically connected to the third clock signal line, an 8m-5th stage driving circuit electrically connected to the fifth clock signal line, an 8m-4th stage driving circuit electrically connected to the seventh clock signal line, an 8m-3th stage driving circuit electrically connected to the ninth clock signal line, an 8m-2th stage driving circuit electrically connected to the eleventh clock signal line, an 8m-1st stage driving circuit electrically connected to the thirteenth clock signal line, and an 8mth stage driving circuit electrically connected to the fifteenth clock signal line, where m is a positive integer.

[0333] The second driving module includes an 8m-7th stage driving circuit electrically connected to the second clock signal line, an 8m-6th stage driving circuit electrically connected to the fourth clock signal line, an 8m-5th stage driving circuit electrically connected to the sixth clock signal line, an 8m-4th stage driving circuit electrically connected to the eighth clock signal line, an 8m-3th stage driving circuit electrically connected to the tenth clock signal line, an 8m-2th stage driving circuit electrically connected to the twelfth clock signal line, an 8m-1st stage driving circuit electrically connected to the fourteenth clock signal line, and an 8m-1st stage driving circuit electrically connected to the sixteenth clock signal line.

[0334] The array substrate described in at least one embodiment of this disclosure further includes a first start voltage line, a second start voltage line, a third start voltage line, and a fourth start voltage line;

[0335] The input terminals of the first-stage driving circuit and the second-stage driving circuit of the first driving module are electrically connected to the first starting voltage line.

[0336] The input terminals of the third-stage driving circuit and the fourth-stage driving circuit included in the first driving module are electrically connected to the third starting voltage line.

[0337] The input terminal of the first-stage driving circuit included in the second driving module and the input terminal of the second-stage driving circuit included in the second driving module are electrically connected to the second starting voltage line;

[0338] The input terminals of the third-stage drive circuit and the fourth-stage drive circuit included in the second drive module are electrically connected to the fourth starting voltage line.

[0339] As shown in Figure 16, the peripheral area includes a first peripheral area Z1 and a second peripheral area Z2. The first peripheral area Z1 is located on the right side of the display area A0, and the second peripheral area Z2 is located on the left side of the display area A0. The fifth side and the sixth side are opposite sides. The array substrate includes a first driving module and a second driving module. The first driving module is located in the first peripheral area Z1, and the second driving module includes the second peripheral area Z2.

[0340] The drive signal output terminal of the first-stage drive circuit GA11 included in the first drive module is electrically connected to the input terminal of the eighth-stage drive circuit GA18 included in the first drive module; the drive signal output terminal of the second-stage drive circuit GA12 included in the first drive module is electrically connected to the input terminal of the seventh-stage drive circuit GA17 included in the first drive module; the drive signal output terminal of the third-stage drive circuit GA13 included in the first drive module is electrically connected to the input terminal of the fifth-stage drive circuit GA15 included in the first drive module; and the drive signal output terminal of the fourth-stage drive circuit GA14 included in the first drive module is electrically connected to the input terminal of the fifth-stage drive circuit GA15 included in the first drive module.

[0341] The drive signal output terminal of the eighth-stage drive circuit GA18 included in the first drive module is electrically connected to the reset terminal of the first-stage drive circuit GA11 included in the first drive module; the drive signal output terminal of the seventh-stage drive circuit GA17 included in the first drive module is electrically connected to the reset terminal of the second-stage drive circuit GA12 included in the first drive module; the drive signal output terminal of the sixth-stage drive circuit GA16 included in the first drive module is electrically connected to the reset terminal of the third-stage drive circuit GA13 included in the first drive module; and the drive signal output terminal of the fifth-stage drive circuit GA15 included in the first drive module is electrically connected to the reset terminal of the fourth-stage drive circuit GA14 included in the first drive module.

[0342] The drive signal output terminal of the first-stage drive circuit GA21 included in the second drive module is electrically connected to the input terminal of the eighth-stage drive circuit GA28 included in the second drive module; the drive signal output terminal of the second-stage drive circuit GA22 included in the second drive module is electrically connected to the input terminal of the seventh-stage drive circuit GA27 included in the second drive module; the drive signal output terminal of the third-stage drive circuit GA23 included in the second drive module is electrically connected to the input terminal of the sixth-stage drive circuit GA26 included in the second drive module; and the drive signal output terminal of the fourth-stage drive circuit GA24 included in the second drive module is electrically connected to the input terminal of the fifth-stage drive circuit GA25 included in the second drive module.

[0343] The drive signal output terminal of the eighth-stage drive circuit GA28 included in the second drive module is electrically connected to the reset terminal of the first-stage drive circuit GA21 included in the second drive module; the drive signal output terminal of the seventh-stage drive circuit GA27 included in the second drive module is electrically connected to the reset terminal of the second-stage drive circuit GA22 included in the second drive module; the drive signal output terminal of the sixth-stage drive circuit GA26 included in the second drive module is electrically connected to the reset terminal of the third-stage drive circuit GA23 included in the second drive module; and the drive signal output terminal of the fifth-stage drive circuit GA25 included in the second drive module is electrically connected to the reset terminal of the fourth-stage drive circuit GA24 included in the second drive module.

[0344] GA11 is electrically connected to the first clock signal line CLK1, GA12 is electrically connected to the third clock signal line CLK3, GA13 is electrically connected to the fifth clock signal line CLK5, GA14 is electrically connected to the seventh clock signal line CLK7, GA15 is electrically connected to the ninth clock signal line CLK9, GA16 is electrically connected to the eleventh clock signal line CLK11, GA17 is electrically connected to the thirteenth clock signal line CLK13, and GA18 is electrically connected to the fifteenth clock signal line CLK15.

[0345] GA21 is electrically connected to the second clock signal line CLK2, GA22 is electrically connected to the fourth clock signal line CLK4, GA23 is electrically connected to the sixth clock signal line CLK6, GA24 is electrically connected to the eighth clock signal line CLK8, GA25 is electrically connected to the tenth clock signal line CLK10, GA26 is electrically connected to the twelfth clock signal line CLK12, GA27 is electrically connected to the fourteenth clock signal line CLK14, and GA28 is electrically connected to the sixteenth clock signal line CLK16.

[0346] The array substrate described in at least one embodiment of this disclosure further includes a first start voltage line STV1, a second start voltage line STV2, a third start voltage line STV3, and a fourth start voltage line STV4.

[0347] The input terminals of the first-stage driving circuit GA11 and the second-stage driving circuit GA12 of the first driving module are electrically connected to the first starting voltage line STV1.

[0348] The input terminals of the third-stage drive circuit GA13 and the fourth-stage drive circuit GA14 included in the first drive module are electrically connected to the third starting voltage line STV3.

[0349] The input terminals of the first-stage drive circuit GA21 and the second-stage drive circuit GA22 of the second drive module are electrically connected to the second starting voltage line STV2.

[0350] The input terminals of the third-stage drive circuit GA23 and the fourth-stage drive circuit GA24 of the second drive module are electrically connected to the fourth starting voltage line STV4.

[0351] In at least one embodiment shown in Figure 16, the drive signal output terminal of GA11 can be electrically connected to the first row of gate lines, the drive signal output terminal of GA21 can be electrically connected to the second row of gate lines, the drive signal output terminal of GA12 can be electrically connected to the third row of gate lines, the drive signal output terminal of GA22 can be electrically connected to the fourth row of gate lines, the drive signal output terminal of GA13 can be electrically connected to the fifth row of gate lines, the drive signal output terminal of GA23 can be electrically connected to the sixth row of gate lines, the drive signal output terminal of GA14 can be electrically connected to the seventh row of gate lines, and the drive signal output terminal of GA24 can be electrically connected to the eighth row of gate lines. The drive signal output of GA15 can be electrically connected to the ninth row of gate lines, the drive signal output of GA25 can be electrically connected to the tenth row of gate lines, the drive signal output of GA16 can be electrically connected to the eleventh row of gate lines, the drive signal output of GA26 can be electrically connected to the twelfth row of gate lines, the drive signal output of GA17 can be electrically connected to the thirteenth row of gate lines, the drive signal output of GA27 can be electrically connected to the fourteenth row of gate lines, the drive signal output of GA18 can be electrically connected to the fifteenth row of gate lines, and the drive signal output of GA22 can be electrically connected to the sixteenth row of gate lines.

[0352] In at least one embodiment of this disclosure, the driving circuits are symmetrically cascaded in the first driving module and the second driving module, so that the RC loading of the first driving module and the second driving module are uniformly processed, thereby reducing the loading difference between different rows of pixels.

[0353] Furthermore, at least one embodiment of this disclosure can improve the charging capabilities of CLK15 and CLK16 on the basis of uniform loading after changing the cascading method;

[0354] By setting the above parameters, the brightness difference between pixels in each row can be reduced, thus optimizing the fine horizontal stripe phenomenon caused by brightness differences in grayscale.

[0355] Figure 17 is a timing diagram of at least one embodiment shown in Figure 16.

[0356] As shown in Figure 17, the time during which the potential of each clock signal line remains high is 16H, and 1H is the scan time of one line.

[0357] The second clock signal provided by CLK2 is delayed by 1 hour compared to the first clock signal provided by CLK1;

[0358] The third clock signal provided by CLK3 is delayed by 1 hour compared to the second clock signal provided by CLK2;

[0359] The fourth clock signal provided by CLK4 is delayed by 1 hour compared to the third clock signal provided by CLK3;

[0360] The fifth clock signal provided by CLK5 is delayed by 1 hour compared to the fourth clock signal provided by CLK4;

[0361] The sixth clock signal provided by CLK6 is delayed by 1 hour compared to the fifth clock signal provided by CLK5;

[0362] The seventh clock signal provided by CLK7 is delayed by 1 hour compared to the sixth clock signal provided by CLK6;

[0363] The eighth clock signal provided by CLK8 is delayed by 1 hour compared to the seventh clock signal provided by CLK7;

[0364] The fifteenth clock signal provided by CLK15 is delayed by 1 hour compared to the eighth clock signal provided by CLK8;

[0365] The sixteenth clock signal provided by CLK16 is delayed by 1 hour compared to the fifteenth clock signal provided by CLK15;

[0366] The thirteenth clock signal provided by CLK13 is delayed by 1 hour compared to the sixteenth clock signal provided by CLK16;

[0367] The fourteenth clock signal provided by CLK14 is delayed by 1 hour compared to the thirteenth clock signal provided by CLK13;

[0368] The eleventh clock signal provided by CLK11 is delayed by 1 hour compared to the fourteenth clock signal provided by CLK14;

[0369] The twelfth clock signal provided by CLK12 is delayed by 1 hour compared to the eleventh clock signal provided by CLK11;

[0370] The ninth clock signal provided by CLK9 is delayed by 1 hour compared to the twelfth clock signal provided by CLK12;

[0371] The tenth clock signal provided by CLK10 is delayed by 1 hour compared to the ninth clock signal provided by CLK9.

[0372] The display device described in this disclosure includes the array substrate described above.

[0373] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. An array substrate, comprising a substrate, a driving module, and multiple clock signal lines; The substrate includes a display area and a peripheral area. The driving module and the multiple clock signal lines are disposed on the substrate. The driving module and the clock signal lines are disposed in the peripheral area. The clock signal lines are disposed on the side of the driving module away from the display area. The clock signal lines are formed on a first metal layer. The array substrate also includes a first via electrically connected to the signal line; At least one clock signal line adjacent to the first via includes a first clock signal line portion and a second clock signal line portion, wherein the line width of the first clock signal line portion is greater than the line width of the second clock signal line portion; The signal line is the clock signal line, and / or the signal line is a signal line disposed on the same layer as the clock signal line.

2. The array substrate as claimed in claim 1, wherein, The first clock signal line is disposed on the first side and / or the second side of the first via; The first side and the second side are opposite sides.

3. The array substrate as claimed in claim 1, wherein, The extension direction of the first clock signal line is either a first direction or a second direction. The first direction intersects with a third direction, but is not perpendicular to the third direction. The second direction intersects with the third direction, but is not perpendicular to the third direction. The array substrate includes data lines disposed in the display area, and the data lines extend along the third direction.

4. The array substrate according to any one of claims 1 to 3, wherein, The signal line is the clock signal line; the first via is electrically connected to the first connection portion formed in the first metal layer and the second connection portion formed in the second metal layer, respectively; The area of ​​the first connecting part is larger than the area of ​​the second connecting part.

5. The array substrate according to any one of claims 1 to 3, wherein, The signal line is the clock signal line; the first via is electrically connected to the first connection portion formed on the first metal layer and the second connection portion formed on the second metal layer respectively; the second connection portion includes a first edge and a second edge, the first edge and the second edge intersect, and the first connection portion includes a portion away from the second connection portion along the extension line of the first edge.

6. The array substrate as claimed in claim 4 or 5, wherein, The first connecting portion includes a first connecting part and at least one second connecting part; the second connecting part is disposed on a third side and / or a fourth side of the first connecting part; The third side and the fourth side are opposite sides.

7. The array substrate as claimed in claim 6, wherein, The second connecting part is a triangular connecting part.

8. The array substrate according to any one of claims 1 to 3, wherein, The surrounding area includes a regular area and an irregularly shaped area; the driving module includes a first driving circuit disposed in the regular area and a second driving circuit disposed in the irregularly shaped area; the first driving circuit includes a first driving transistor and a first storage capacitor; the second driving circuit includes a second driving transistor and a second storage capacitor; The shape of the first storage capacitor is different from the shape of the second storage capacitor; The shape of the first driving transistor is different from the shape of the second driving transistor.

9. The array substrate as claimed in claim 8, wherein, The gate of the second driving transistor includes a plurality of second gate portions; The first plate and the gate of the second storage capacitor are formed on the first metal layer; The first electrode plate has a first clearance space to allow at least one of the second gate portions to pass.

10. The array substrate as claimed in claim 8, wherein, The array substrate includes data lines disposed in the display area, the data lines extending along a third direction; a fourth direction is perpendicular to the third direction; the gate of the first driving transistor includes a plurality of first gate portions, and the gate of the second driving transistor includes a plurality of second gate portions; The sum of the widths of the plurality of first gate portions along the fourth direction is greater than the widths of the plurality of second gate portions along the fourth direction.

11. The array substrate as claimed in claim 8, wherein, The first driving circuit includes a first reset circuit, and the second driving circuit includes a second reset circuit; the first reset circuit is used to control the potential of the first node under the control of the first reset terminal; The second reset circuit is used to control the potential of the second first node under the control of the second reset terminal; The first reset circuit includes a first transistor, and the second reset circuit includes a second first transistor; The shape of the first transistor is different from the shape of the second transistor.

12. The array substrate as claimed in claim 8, wherein, The first driving circuit includes a first first node reset circuit, a first output reset circuit, and a first first frame reset circuit; the second driving circuit includes a second first node reset circuit, a second output reset circuit, and a second first frame reset circuit. The first node reset circuit is used to reset the potential of the first node under the control of the potential of the first second node. The first output reset circuit is used to reset the first driving signal provided by the first driving signal output terminal under the control of the potential of the first second node; the first first frame reset circuit is used to reset the first driving signal under the control of the frame reset line; the second first node reset circuit is used to reset the potential of the second first node under the control of the potential of the second second node; the second output reset circuit is used to reset the second driving signal provided by the second driving signal output terminal under the control of the potential of the second second node; the second first frame reset circuit is used to reset the second driving signal under the control of the frame reset line; the first first node reset circuit includes a first second transistor, the first output reset circuit includes a first third transistor, and the first first frame reset circuit includes a first fourth transistor; the second first node reset circuit includes a second second transistor, the second output reset circuit includes a second third transistor, and the second first frame reset circuit includes a second fourth transistor; the array substrate includes data lines disposed in the display area, the data lines extending along a third direction; the fourth direction is perpendicular to the third direction; The first second transistor, the first fourth transistor, and the first third transistor are arranged along the fourth direction; The second transistor and the second fourth transistor are arranged along the third direction, and the second transistor and the second third transistor are arranged along the fourth direction.

13. The array substrate as claimed in claim 12, wherein, The channel of the first fourth transistor extends along a third direction, and the channel of the second fourth transistor extends along a fourth direction.

14. The array substrate as claimed in claim 8, wherein, The first driving circuit includes a first second frame reset circuit, a first pull-down control node control circuit, and a first second node reset circuit; the second driving circuit includes a second second frame reset circuit, a second pull-down control node control circuit, and a second second node reset circuit. The first second frame reset circuit is used to reset the potential of the first first node under the control of the frame reset line; the first pull-down control node control circuit is used to control the potential of the first pull-down control node. The first second node reset circuit is used to reset the potential of the first second node under the control of the potential of the first first node; the second second frame reset circuit is used to reset the potential of the second first node under the control of the frame reset line; the second pull-down control node control circuit is used to control the potential of the second pull-down control node. The second second node reset circuit is used to reset the potential of the second second node under the control of the potential of the second first node; The first second frame reset circuit includes a first fifth transistor, the first pull-down control node control circuit includes a first sixth transistor and a first seventh transistor, and the first second node reset circuit includes a first eighth transistor; the second second frame reset circuit includes a second fifth transistor, the second pull-down control node control circuit includes a second sixth transistor and a second seventh transistor, and the second second node reset circuit includes a second eighth transistor; the array substrate includes data lines disposed in the display area, and the data lines extend along a third direction; The first seventh transistor and the first sixth transistor are arranged along the third direction, and the first eighth transistor and the first fifth transistor are arranged along the third direction; The second seventh transistor, the second sixth transistor, and the second fifth transistor are arranged along a third direction, and the second eighth transistor and the second fifth transistor are arranged along a third direction.

15. The array substrate as claimed in claim 14, wherein, The channel of the first seventh transistor extends along a third direction; the channel of the second seventh transistor extends along a fourth direction. The third direction is perpendicular to the fourth direction.

16. The array substrate as claimed in claim 8, wherein, The first driving circuit includes a first second node control circuit, and the second driving circuit includes a second second node control circuit; the first second node control circuit is used to control the potential of the first second node under the control of the potential of the first pull-down control node; the second second node control circuit is used to control the potential of the second second node under the control of the potential of the second pull-down control node. The first second node control circuit includes a first ninth transistor, and the second second node control circuit includes a second ninth transistor; The channel of the first ninth transistor extends along the fourth direction; the channel of the second ninth transistor extends along the third direction. The third direction is perpendicular to the fourth direction.

17. The array substrate according to any one of claims 1 to 3, wherein, The surrounding area includes irregularly shaped areas; Within the irregularly shaped area, the line width of the clock signal line furthest from the display area is greater than the line width of the clock signal line closest to the display area within the irregularly shaped area.

18. The array substrate according to any one of claims 1 to 3, wherein, It also includes the starting voltage line; The starting voltage line is located on the side of the clock signal line away from the display area.

19. The array substrate according to any one of claims 1 to 3, wherein, The peripheral area includes a first peripheral area and a second peripheral area, the first peripheral area being disposed on the fifth side of the display area and the second peripheral area being disposed on the sixth side of the display area; the fifth side and the sixth side are opposite sides; the array substrate includes a first driving module and a second driving module, the first driving module being disposed in the first peripheral area and the second driving module including the second peripheral area; n is a positive integer; The drive signal output terminal of the (4n-3)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+4)th stage drive circuit included in the first drive module; the drive signal output terminal of the (4n-2)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+3)th stage drive circuit included in the first drive module; the drive signal output terminal of the (4n-1)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+2)th stage drive circuit included in the first drive module; the drive signal output terminal of the (4n)th stage drive circuit included in the first drive module is electrically connected to the input terminal of the (4n+1)th stage drive circuit included in the first drive module; and / or Alternatively, the drive signal output terminal of the 4n+4th stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4n-3th stage drive circuit included in the first drive module; the drive signal output terminal of the 4n+3rd stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4n-2th stage drive circuit included in the first drive module; the drive signal output terminal of the 4n+2nd stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4n-1th stage drive circuit included in the first drive module; and the drive signal output terminal of the 4n+1st stage drive circuit included in the first drive module is electrically connected to the reset terminal of the 4nth stage drive circuit included in the first drive module. The drive signal output terminal of the (4n-3)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+4)th stage drive circuit included in the second drive module; the drive signal output terminal of the (4n-2)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+3)th stage drive circuit included in the second drive module; the drive signal output terminal of the (4n-1)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+2)th stage drive circuit included in the second drive module; the drive signal output terminal of the (4n)th stage drive circuit included in the second drive module is electrically connected to the input terminal of the (4n+1)th stage drive circuit included in the second drive module; and / or Alternatively, the drive signal output terminal of the 4n+4th stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4n-3th stage drive circuit included in the second drive module; the drive signal output terminal of the 4n+3rd stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4n-2th stage drive circuit included in the second drive module; the drive signal output terminal of the 4n+2nd stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4n-1th stage drive circuit included in the second drive module; and the drive signal output terminal of the 4n+1st stage drive circuit included in the second drive module is electrically connected to the reset terminal of the 4nth stage drive circuit included in the second drive module.

20. The array substrate as claimed in claim 19, wherein, The array substrate includes sixteen clock signal lines; the first clock signal line, the third clock signal line, the fifth clock signal line, the seventh clock signal line, the ninth clock signal line, the eleventh clock signal line, the thirteenth clock signal line, and the fifteenth clock signal line are all disposed in the second peripheral area; The second clock signal line, the fourth clock signal line, the sixth clock signal line, the eighth clock signal line, the tenth clock signal line, the twelfth clock signal line, the fourteenth clock signal line, and the sixteenth clock signal line are all located in the first peripheral area; The first driving module includes an 8m-7th stage driving circuit electrically connected to the first clock signal line, an 8m-6th stage driving circuit electrically connected to the third clock signal line, an 8m-5th stage driving circuit electrically connected to the fifth clock signal line, an 8m-4th stage driving circuit electrically connected to the seventh clock signal line, an 8m-3th stage driving circuit electrically connected to the ninth clock signal line, an 8m-2th stage driving circuit electrically connected to the eleventh clock signal line, an 8m-1st stage driving circuit electrically connected to the thirteenth clock signal line, and an 8mth stage driving circuit electrically connected to the fifteenth clock signal line, where m is a positive integer. The second driving module includes an 8m-7th stage driving circuit electrically connected to the second clock signal line, an 8m-6th stage driving circuit electrically connected to the fourth clock signal line, an 8m-5th stage driving circuit electrically connected to the sixth clock signal line, an 8m-4th stage driving circuit electrically connected to the eighth clock signal line, an 8m-3th stage driving circuit electrically connected to the tenth clock signal line, an 8m-2th stage driving circuit electrically connected to the twelfth clock signal line, an 8m-1st stage driving circuit electrically connected to the fourteenth clock signal line, and an 8m-1st stage driving circuit electrically connected to the sixteenth clock signal line.

21. The array substrate as claimed in claim 19, wherein, It also includes a first starting voltage line, a second starting voltage line, a third starting voltage line, and a fourth starting voltage line; The input terminals of the first-stage driving circuit and the second-stage driving circuit of the first driving module are electrically connected to the first starting voltage line. The input terminals of the third-stage driving circuit and the fourth-stage driving circuit included in the first driving module are electrically connected to the third starting voltage line. The input terminal of the first-stage driving circuit included in the second driving module and the input terminal of the second-stage driving circuit included in the second driving module are electrically connected to the second starting voltage line; The input terminals of the third-stage drive circuit and the fourth-stage drive circuit included in the second drive module are electrically connected to the fourth starting voltage line.

22. A display device comprising an array substrate as claimed in any one of claims 1 to 21.

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