Gate driving circuit, display panel and driving method thereof, and display device

Abstract

The application discloses a gate driving circuit, a display panel and a driving method thereof, and a display device. The gate driving circuit comprises a plurality of shift register units, each of which comprises an input circuit connected with a trigger signal input end and a first node; a stage transmission signal output circuit connected with the first node, a clock signal end and a stage transmission signal output end; a scanning signal output circuit connected with the first node, the clock signal end and a scanning signal output end; a first pull-up circuit connected with the first node and a second node; and a first pull-down circuit electrically connected with a target signal end and the stage transmission signal output end. The target signal end comprises any one of a cross-unit second node, the trigger signal input end and a first cross-unit stage transmission signal output end. The application can solve the problem of abnormal shift register stage transmission in the related art.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a gate driving circuit, a display panel and its driving method, and a display device. Background Technology

[0002] The display panel may include multiple light-emitting pixels arranged in an array, and each light-emitting pixel may include pixel circuitry and light-emitting elements. Pixel circuitry typically includes TFTs (Thin Film Transistors) and capacitors.

[0003] The display panel may also include a gate drive circuit consisting of multiple cascaded shift registers. In a single display frame, the multiple shift registers sequentially provide valid scan signals to the pixels of the corresponding rows to achieve row-by-row refresh of each pixel row in a single display frame.

[0004] However, in related technologies, some shift registers may experience triggering or failure during the cascading process. Summary of the Invention

[0005] This application provides a gate driving circuit, a display panel and its driving method, and a display device, which can solve the problem of abnormal shift register-level transmission process in related technologies.

[0006] In a first aspect, embodiments of this application provide a gate driving circuit, including multiple cascaded shift register units. Each shift register unit includes: an input circuit connected to a trigger signal input terminal and a first node, wherein the input circuit adjusts the signal of the first node based on the trigger signal from the trigger signal input terminal; a cascade signal output circuit connected to the first node, a clock signal terminal, and a cascade signal output terminal, wherein the cascade signal output circuit controls the cascade signal output by the cascade signal output terminal based on the signals from the first node and the clock signal terminal; and a scan signal output circuit connected to the first node, the clock signal terminal, and the scan signal output terminal, wherein the cascade signal output circuit controls the cascade signal output by the cascade signal output terminal based on the signals from the first node and the clock signal terminal; and a scan signal output circuit connected to the first node, the clock signal terminal, and the scan signal output terminal, wherein the scan signal output circuit controls the cascade signal output by the first node based on the signals from the clock signal terminal. The signal at the clock signal terminal controls the scan signal output at the scan signal output terminal; a first pull-up circuit and a first pull-down circuit, the first pull-up circuit being connected to the first node and the second node, and controlling the signal of the second node based on the signal of the first node; the first pull-down circuit being electrically connected to the target signal terminal and the stage transmission signal output terminal, and controlling the stage transmission signal output at the stage transmission signal output terminal based on the signal of the target signal terminal; wherein, the target signal terminal includes any one of the cross-unit second node, the trigger signal input terminal, and the first cross-unit stage transmission signal output terminal, the cross-unit second node being the second node of another shift register unit, and the first cross-unit stage transmission signal output terminal being the stage transmission signal output terminal of another shift register unit.

[0007] Secondly, embodiments of this application provide a display panel, the display panel including the gate driving circuit as described in any embodiment of the first aspect.

[0008] Thirdly, embodiments of this application provide a driving method for a display panel, applied to the display panel of the second aspect embodiment, wherein the gate driving circuit is electrically connected to a clock signal line group, and the display area of ​​the display panel includes a first display sub-region and a second display sub-region arranged along the column direction; the method includes: In the first refresh subframe of the frequency division drive mode, the control clock signal line group provides clock signals normally in the row scanning cycles corresponding to the first and second display sub-regions. In the second refresh subframe of the frequency division drive mode, the control clock signal line group provides a clock signal normally during the row scan cycle corresponding to the first display sub-area, while the clock signal line group does not provide a clock signal during the row scan cycle corresponding to the second display sub-area.

[0009] Fourthly, embodiments of this application provide a display device, including the display panel described in the second aspect embodiment.

[0010] If the first pull-down circuit of the current shift register unit is connected to the second node of the current shift register unit, when the voltage of the first node increases, the second node of the current shift register unit will be pulled low, causing the first pull-down circuit to switch to the off state, thus failing to achieve filtering and noise reduction at the cascade signal output. However, in the embodiment of this application, the first pull-down circuit of the current shift register unit is connected to the second node of the cross-unit, the trigger signal input terminal, or the first cross-unit cascade signal output terminal. When the voltage of the first node increases, and the voltage of the cascade signal output terminal also increases due to the bootstrap capacitor coupling, the conduction period of the first pull-down circuit can be controlled by the second node of the cross-unit, the trigger signal input terminal, or the first cross-unit cascade signal output terminal, thereby achieving noise reduction at the cascade signal output terminal and solving the problem of abnormal shift register cascade process in related technologies. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a shift register structure in related technologies; Figure 2 yes Figure 1 A simulation timing diagram; Figure 3This is a schematic diagram of a shift register unit provided in an embodiment of this application; Figure 4 yes Figure 3 A comparative structural diagram; Figure 5 yes Figure 3 and Figure 4 A simulation timing diagram; Figure 6 This is a schematic diagram of a display panel provided in an embodiment of this application; Figure 7a This is a schematic diagram of the first structure of the shift register unit provided in the embodiments of this application; Figure 7b This is a timing diagram of a shift register unit provided in an embodiment of this application; Figure 8 This is a schematic diagram of a second structure of the shift register unit provided in the embodiments of this application; Figure 9a This is a schematic diagram of the third structure of the shift register unit provided in the embodiments of this application; Figure 9b This is a schematic diagram of the fourth structure of the shift register unit provided in the embodiments of this application; Figure 10a This is a schematic diagram of the fifth structure of the shift register unit provided in the embodiments of this application; Figure 10b This is a schematic diagram of the sixth structure of the shift register unit provided in the embodiments of this application; Figure 11 yes Figure 9a , Figure 10a and Figure 4 A simulation timing diagram; Figure 12 This is a schematic diagram of the seventh structure of the shift register unit provided in the embodiments of this application; Figure 13 This is a schematic diagram of the eighth structure of the shift register unit provided in the embodiments of this application; Figure 14a This is a schematic diagram of the ninth structure of the shift register unit provided in the embodiments of this application; Figure 14b This is a schematic diagram of the tenth structure of the shift register unit provided in the embodiments of this application; Figure 15a This is an eleventh structural schematic diagram of the shift register unit provided in the embodiments of this application; Figure 15b This is a schematic diagram of the twelfth structure of the shift register unit provided in the embodiments of this application; Figure 16 This is a timing diagram of two voltage terminals; Figure 17 This is another structural schematic diagram of the display panel provided in the embodiments of this application; Figure 18 This is a schematic flowchart of a display panel driving method provided in an embodiment of this application; Figure 19 This is a schematic diagram of a partition of a display panel provided in an embodiment of this application; Figure 20 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0015] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The embodiments will now be described in detail with reference to the accompanying drawings.

[0016] For example, in order to implement segmented frequency driving of the display area, such as Figure 1As shown, the shift register architecture can be designed so that the pass signal and scan signal are output independently. For example, the first output circuit 01 is connected to the first output terminal OUT1, which is used to output the scan signal. The second output circuit 02 is connected to the second output terminal OUT2, which is used to output the pass signal. The scan signal is used to drive the light-emitting pixels. The pass signal output by the current-level shift register serves as the trigger signal for other-level shift registers. For example, in a single display frame, the shift register corresponding to the row of light-emitting pixels in the hold frame can still output the pass signal normally, but does not output a valid scan signal. Therefore, by adjusting whether the shift register of the corresponding row outputs a valid scan signal, the refresh rate of any pixel row in the display area can be controlled.

[0017] To ensure that the shift register in the low-frequency region can provide the cascading signal normally, a bootstrap capacitor is usually set at the output of the cascading signal (e.g., the first end of capacitor C' connected to the second output terminal OUT2). This allows the shift register to stably generate and output the cascading signal when it receives it. However, when the potential at the coupling terminal (the second end of capacitor C', which is connected to node PU') fluctuates, it will cause high noise signals at the output of the cascading signal, leading to false triggering or failure of the cascading process. The inventors have simulated the operating timing of the shift register in related technologies, such as... Figure 2 As shown, at time a, node PU' begins pre-charging, and the potential of node PU' rises. Due to the coupling effect of capacitor C', the noise at the second output terminal OUT2 (output stage transmission signal) is relatively large. If the noise cannot be restored to the normal potential in time, the stage transmission process may be falsely triggered or the stage transmission may fail.

[0018] Therefore, the false triggering of cascaded signals caused by coupling effects in shift registers has become a technical problem that urgently needs to be solved.

[0019] To address the aforementioned technical problems, embodiments of this application provide a gate driving circuit, a display panel, a driving method thereof, and a display device. The various embodiments of this application are described below.

[0020] like Figure 3 As shown, the gate drive circuit provided in this application embodiment includes multiple cascaded shift register units (VSRs). Each shift register unit (VSR) includes an input circuit 11, a cascaded signal output circuit 12, a scan signal output circuit 13, a first pull-up circuit 141, and a first pull-down circuit 151.

[0021] The input circuit 11 is connected to the trigger signal input terminal IN and the first node PU. The input circuit 11 controls the signal of the first node PU based on the trigger signal of the trigger signal input terminal IN. For example, when the trigger signal of the trigger signal input terminal IN is at an active level, the input circuit 11 controls the signal of the first node PU to be at an active level.

[0022] The cascading signal output circuit 12 is connected to the first node PU, the clock signal terminal CK, and the cascading signal output terminal Cout. The cascading signal output circuit 12 controls the cascading signal output from the cascading signal output terminal Cout based on the signals from the first node PU and the clock signal terminal CK. The cascading signal output terminal Cout of the current stage shift register unit can be electrically connected to the trigger signal input terminal IN of other stage shift register units. The cascading signal output terminal Cout of the current stage shift register unit can serve as the trigger signal for other stage shift register units, thereby transmitting the cascading signal step by step. For example, the signal from the first node PU can be used to control whether the cascading signal output circuit 12 is turned on; when the signal from the first node PU is at an active level, the cascading signal output circuit 12 is turned on, and the signal from the clock signal terminal CK is transmitted to the cascading signal output terminal Cout through the cascading signal output circuit 12.

[0023] The scan signal output circuit 13 is connected to the first node PU, the clock signal terminal CK, and the scan signal output terminal Gout. The scan signal output circuit 13 controls the scan signal output by the scan signal output terminal Gout based on the signals from the first node PU and the clock signal terminal CK. The scan signal output terminal Gout is connected to the pixel circuit, and the scan signal output by Gout is used to drive the pixel circuit. For example, when the scan signal output terminal Gout normally outputs a scan signal (i.e., the output scan signal includes a valid level), the pixel circuit can be scanned normally; when the scan signal output terminal Gout does not output a scan signal (i.e., the output signal does not include a valid level), the pixel circuit cannot be scanned. For example, the signal from the first node PU can be used to control whether the scan signal output circuit 13 is turned on; when the signal from the first node PU is at a valid level, the scan signal output circuit 13 is turned on, and the signal from the clock signal terminal CK is transmitted to the scan signal output terminal Gout through the scan signal output circuit 13.

[0024] The first pull-up circuit 141 is connected to the first node PU and the second node PD. The first pull-up circuit 141 controls the signal of the second node PD based on the signal of the first node PU. For example, when the first node PU is at an invalid level, the first pull-up circuit 141 pulls up the potential of the second node PD, making the second node PD at an valid level. Alternatively, when the first node PU is at a valid level, the first pull-up circuit 141 controls the second node PD to be at an invalid level.

[0025] The first pull-down circuit 151 is connected to the target signal terminal and the stage transmission signal output terminal Cout. The target signal terminal includes any one of the cross-unit second node PD(m), the trigger signal input terminal IN, and the first cross-unit stage transmission signal output terminal Cout(nx). The first pull-down circuit 151 controls the stage transmission signal output terminal Cout based on the signal from the target signal terminal. The cross-unit second node PD(m) is the second node PD of another shift register unit, and the first cross-unit stage transmission signal output terminal Cout(nx) is the stage transmission signal output terminal of another shift register unit.

[0026] For example, if the current shift register unit is the nth shift register unit, the second node PD(m) across units is the second node PD of the mth shift register unit, where m ≠ n. If the current shift register unit is the nth shift register unit, the first cross-unit cascade signal output Cout(nx) is the cascade signal output of the nxth shift register unit.

[0027] For example, the cross-unit second node PD(m) or trigger signal input terminal IN or the first cross-unit level transmission signal output terminal Cout(nx) can be connected to the control terminal of the first pull-down circuit 151. When the cross-unit second node PD(m) or trigger signal input terminal IN or the first cross-unit level transmission signal output terminal Cout(nx) is at an effective level, the first pull-down circuit 151 is turned on and can pull down the signal of the level transmission signal output terminal Cout.

[0028] In some embodiments, such as Figure 3 As shown, the shift register unit VSR may also include a bootstrap capacitor C, which is connected between the first node PU and the cascade signal output terminal Cout. When the cascade signal output terminal Cout outputs an effective level, the bootstrap effect of the bootstrap capacitor C can enable the signal from the first node PU to more fully conduct the cascade signal output circuit 12 and the scan signal output circuit 13.

[0029] However, the coupling effect of the bootstrap capacitor C can easily cause noise to affect the signal at the stage transmission signal output terminal Cout.

[0030] As a comparison, for reference Figure 4 For example, when the first pull-down circuit 151 of the current shift register unit is connected to the second node PD of the current shift register unit, when the voltage of the first node PU increases, the second node PD of the current shift register unit will be pulled low, causing the first pull-down circuit 151 to switch to the off state, thus failing to achieve filtering and noise reduction of the cascaded signal output terminal Cout. In the embodiments of this application, such as Figure 3As shown, the first pull-down circuit 151 of the current shift register unit is connected to the second node PD(m) of the cross-unit, the trigger signal input terminal IN, or the first cross-unit cascade signal output terminal Cout(nx). When the voltage of the first node PU rises and the voltage of the cascade signal output terminal Cout also rises due to the coupling effect of the bootstrap capacitor C, the conduction period of the first pull-down circuit 151 can be controlled by the second node PD(m) of the cross-unit, the trigger signal input terminal IN, or the first cross-unit cascade signal output terminal Cout(nx), thereby achieving noise reduction of the cascade signal output terminal Cout and solving the problem of abnormal shift register cascade process in related technologies.

[0031] like Figure 5 , Figure 11 As shown, the inventors of this application also... Figure 3 and Figure 4 The working timing was simulated and compared, where V0 represents... Figure 4 The magnitude by which the corresponding stage transmission signal output terminal Cout is pulled high due to noise is represented by V1, which indicates the magnitude by which the stage transmission signal output terminal Cout is pulled high due to noise when the first pull-down circuit 151 of the current shift register unit is connected to the second node PD(m) of the cross-unit; V3 indicates the magnitude by which the stage transmission signal output terminal Cout is pulled high due to noise when the first pull-down circuit 151 of the current shift register unit is connected to the trigger signal input terminal IN; and V4 indicates the magnitude by which the stage transmission signal output terminal Cout is pulled high due to noise when the first pull-down circuit 151 of the current shift register unit is connected to the first cross-unit stage transmission signal output terminal Cout(nx). Since V1, V3, and V4 are all lower than V0, connecting the first pull-down circuit 151 of the current shift register unit to the second node PD(m) of the cross-unit, the trigger signal input terminal IN, or the first cross-unit stage transmission signal output terminal Cout(nx) can achieve noise reduction of the stage transmission signal output terminal Cout.

[0032] It should be noted that the technical concept of this application is applicable regardless of whether the shift register unit VSR includes a bootstrap capacitor C. For example, even if the shift register unit VSR does not include a bootstrap capacitor C, the staged signal output terminal Cout may still have parasitic capacitance with other structures. Due to the coupling of parasitic capacitance, it will also have a noise effect on the staged signal output terminal Cout. The technical concept of this application can also be applied to reduce the noise generated by the parasitic capacitance at the staged signal output terminal Cout.

[0033] In some embodiments, along the transmission direction of the cascading signal of the multiple shift register units, the cross-unit second node PD(m) is the second node PD of another shift register unit following the current shift register unit.

[0034] For example, such as Figure 6 As shown, the gate drive circuit 10 includes multiple shift register units arranged along the second direction D2, namely the first shift register unit VSR1, the second shift register unit VSR2, the third shift register unit VSR3, etc. The transmission direction of the stage transmission signal of the multiple shift register units can be: the previous shift register unit transmits the stage transmission signal to the shift register unit below.

[0035] For example, the stage pass signal output terminal Cout of the first shift register unit VSR1 transmits the stage pass signal to the third shift register unit VSR3, the stage pass signal output terminal Cout of the second shift register unit VSR2 transmits the stage pass signal to the fourth shift register unit VSR4, the third shift register unit VSR3 transmits the stage pass signal to the fifth shift register unit VSR5, the fourth shift register unit VSR4 transmits the stage pass signal to the sixth shift register unit VSR6, and so on.

[0036] For example, such as Figure 6 As shown, the gate drive circuit 10 may also include some dummy shift register units to ensure the normal operation of each shift register unit (VSR).

[0037] It should be noted that, Figure 6 Taking the cascading of shift register units at intervals as an example, this is merely a cascading example and is not intended to limit this application. The technical concept of this application can also be applied to other cascading methods.

[0038] Along the transmission direction of the cascade signal, the start time of the effective level output by the cascade signal output terminal Cout of the current shift register unit is earlier than the start time of the effective level output by the cascade signal output terminal Cout of the next shift register unit after the current shift register unit.

[0039] In this embodiment, the first pull-down circuit 151 in the current shift register unit is connected to the second node PD of another shift register unit after the current shift register unit. Relative to the voltage rise time of the first node PU in the current shift register unit, the turn-on and turn-off times of the first pull-down circuit 151 can be delayed. In this way, after the voltage rise of the first node PU pulls up the voltage of the stage transmission signal output terminal Cout of the current shift register unit, the first pull-down circuit 151 performs noise reduction on the stage transmission signal output terminal Cout of the current shift register unit, so as to reduce the noise impact of the voltage rise of the first node PU on the stage transmission signal output terminal Cout of the current shift register unit.

[0040] In some embodiments, along the transmission direction of the cascading signals of the multiple shift register units, the second node PD(m) across units is the second node PD of the next shift register unit after the current shift register unit. In other words, the first pull-down circuit 151 in the i-th stage shift register unit is electrically connected to the second node in the (i+1)-th stage shift register unit, wherein the signal of the second node in the (i+1)-th stage shift register unit transitions to the cutoff level later than the signal of the second node in the i-th stage shift register unit transitions to the cutoff level.

[0041] Along the transmission direction of the cascading signals of multiple shift register units, the cascading signal output terminal Cout of the current shift register unit is connected to the trigger signal input terminal IN of the next shift register unit after the current shift register unit, and the cascading signal output terminal Cout of the current shift register unit transmits the cascading signal to the next shift register unit after the current shift register unit.

[0042] For example, still using Figure 6 For example, the second node of the cross-unit connected to the first pull-down circuit 151 in the first shift register unit VSR1 is the second node in the second shift register unit VSR2; the second node of the cross-unit connected to the first pull-down circuit 151 in the second shift register unit VSR2 is the second node in the third shift register unit VSR3; the second node of the cross-unit connected to the first pull-down circuit 151 in the third shift register unit VSR3 is the second node in the fourth shift register unit VSR4; the second node of the cross-unit connected to the first pull-down circuit 151 in the fourth shift register unit VSR4 is the second node in the fifth shift register unit VSR5, and so on.

[0043] In terms of timing, the timing of the next shift register unit following the current shift register unit is immediately adjacent to the timing of the current shift register unit. In this embodiment, the first pull-down circuit 151 of the current shift register unit is connected to the second node PD of the next shift register unit. After the voltage rise of the first node PU pulls up the voltage of the cascade signal output terminal Cout of the current shift register unit, the first pull-down circuit 151 can promptly reduce the noise of the cascade signal output terminal Cout of the current shift register unit, thereby reducing the noise impact of the voltage rise of the first node PU on the cascade signal output terminal Cout of the current shift register unit.

[0044] For example, please refer to Figure 7aThe current shift register unit is the nth stage shift register unit VSR(n). The trigger signal input terminal IN of the nth stage shift register unit VSR(n) can be connected to the stage pass signal output terminal Cout(n-2) of the (n-2)th stage shift register unit VSR(n). That is, the stage pass signal output terminal Cout(n-2) of the (n-2)th stage shift register unit VSR(n) transmits the stage pass signal to the nth stage shift register unit VSR(n). The moment when the stage pass signal output terminal Cout(n-2) of the (n-2)th stage shift register unit VSR(n) outputs a conduction level is earlier than the moment when the stage pass signal output terminal Cout(n) of the nth stage shift register unit VSR(n) outputs a conduction level.

[0045] For example, when the number of clock signal lines electrically connected to a gate driver circuit is four, such as when a gate driver circuit connects two stage clock signal lines and two scan clock signal lines, the first pull-down circuit 151 in the i-th stage shift register unit can be electrically connected to the second node in the (i+1)-th or (i+2)-th stage shift register unit. When the number of clock signal lines electrically connected to the gate driver circuit is eight, such as when a gate driver circuit connects four stage clock signal lines and four scan clock signal lines, the first pull-down circuit 151 in the i-th stage shift register unit can be electrically connected to the second node in the (i+1)-th, (i+2)-th, (i+3)-th, or (i+4)-th stage shift register unit.

[0046] For example, the time when the signal of the second node in the (i+1)th stage shift register unit transitions to the cutoff level is 1H different from the time when the signal of the second node in the i-th stage shift register unit transitions to the cutoff level, where H is the row scan duration of the display panel.

[0047] In some embodiments, such as Figure 7a As shown, the first pull-up circuit 141 may include a first transistor M1 and a second transistor M2, and the first pull-down circuit 151 may include a third transistor M3.

[0048] The gate and first terminal of the first transistor M1 are connected to the first voltage terminal VDDE, and the second terminal of the first transistor M1 is connected to the second node PD. The gate of the second transistor M2 is connected to the first node PU, and the second transistor M2 is connected between the second voltage terminal VGL2 and the second node PD. The second voltage terminal VGL2 is a low-level signal terminal, and the first voltage terminal VDDE is a high-level signal terminal.

[0049] The first transistor M1 is connected in a diode configuration. The anode of the diode formed by the first transistor M1 is connected to the first voltage terminal VDDE, and the cathode of the diode formed by the first transistor M1 is connected to the second node PD. When the second transistor M2 is turned on, the signal at the second voltage terminal VGL2 is transmitted to the second node PD; when the second transistor M2 is turned off, the signal at the first voltage terminal VDDE is transmitted to the second node PD. The state of the second transistor M2 is controlled by the first node PU. When the first node PU is at a conducting level, the second transistor M2 is turned on; when the first node PU is at a cutoff level, the second transistor M2 is turned off.

[0050] The gate of the third transistor M3 is connected to the second node PD(m) of the cross-cell, and the third transistor M3 is connected between the second voltage terminal VGL2 and the stage transmission signal output terminal Cout. When the second node PD(m) of the cross-cell is turned on, the signal at the second voltage terminal VGL2 is transmitted to the stage transmission signal output terminal Cout. For example, please refer to the reference. Figure 7a and Figure 7b The shift register unit's operation includes a precharge phase t1 and an output phase t2. During the precharge phase t1, the first node PU is raised to a high level, and the cascade signal output terminal Cout does not need to output a high level (i.e., during precharge phase t1, the cascade signal output terminal Cout outputs a low level). During the output phase t2, the cascade signal output terminal Cout outputs a high level. During the precharge phase t1, the second node PD(m) of the cross-unit can be on, and the second voltage terminal VGL2 can be written to the signal output from the cascade signal output terminal Cout via the third transistor M3. This reduces the risk of the voltage at the cascade signal output terminal Cout being pulled high due to the bootstrap capacitor C or other parasitic capacitances.

[0051] For example, the current shift register unit is the nth-level shift register unit VSR(n). The gate of the third transistor M3 in the nth-level shift register unit VSR(n) can be connected to the second node PD in the (n+1)th-level shift register unit VSR(n). That is, the second node of the (n+1)th-level shift register unit VSR(n+1) serves as the cross-unit second node PD(m) of the nth-level shift register unit VSR(n). The time when the stage transfer signal output terminal Cout(n-2) of the (n-2)th-level shift register unit VSR(n) outputs a conduction level is earlier than the time when the stage transfer signal output terminal Cout(n) of the nth-level shift register unit VSR(n) outputs a conduction level.

[0052] In some embodiments, such as Figure 8As shown, the low-level signal terminal VGL can include a second voltage terminal VGL2 and a third voltage terminal VGL3. The scan signal output terminal Gout is electrically connected to the third voltage terminal VGL3, and the stage transmission signal output terminal Cout and other nodes can be electrically connected to the second voltage terminal VGL2. The scan signal output terminal Gout is used to drive the light-emitting pixels, and the stage transmission signal output terminal Cout is used to transmit stage transmission signals to other stage shift register units. Connecting the two to different low-level signal terminals is equivalent to distributing the load of the two to two low-level signal terminals, which reduces the load on each low-level signal terminal. The voltages of the second voltage terminal VGL2 and the third voltage terminal VGL3 can be the same or different, and the voltage values ​​of the second voltage terminal VGL2 and the third voltage terminal VGL3 can be set according to actual needs.

[0053] In some embodiments, such as Figure 9a or Figure 9b As shown, the first pull-down circuit 151 may include a fourth transistor M4. The gate of the fourth transistor M4 is connected to the trigger signal input terminal IN, and the fourth transistor M4 is connected between the second voltage terminal VGL2 and the stage transmission signal output terminal Cout. When the voltage of the first node PU increases and the voltage of the stage transmission signal output terminal Cout is pulled up through the bootstrap capacitor C or other parasitic capacitances, the fourth transistor M4 can be turned on by making the trigger signal input terminal IN at the on level. The second voltage terminal VGL2 pulls down the voltage of the stage transmission signal output terminal Cout, thereby reducing noise in the signal at the stage transmission signal output terminal Cout.

[0054] For example, the current shift register unit is the nth level shift register unit VSR(n). The trigger signal input terminal IN of the nth level shift register unit VSR(n) can be connected to the stage transmission signal output terminal Cout(n-2) of the (n-2)th level shift register unit VSR(n). That is, the gate of the fourth transistor M4 in the nth level shift register unit VSR(n) can be connected to the stage transmission signal output terminal Cout(n-2) of the (n-2)th level shift register unit VSR(n).

[0055] As an example, such as Figure 9a As shown, when the gate of the fourth transistor M4 is connected to the trigger signal input IN, the gate of the third transistor M3 can be electrically connected to the second node PD of the current shift register unit. As another example, such as... Figure 9b As shown, when the gate of the fourth transistor M4 is connected to the trigger signal input terminal IN, the gate of the third transistor M3 can be electrically connected to the second node PD(m) of the cross-cell.

[0056] Or, such as Figure 10aAs shown, the first pull-down circuit 151 may further include a fifth transistor M5. The gate of the fifth transistor M5 is connected to the first cross-cell stage transmission signal output terminal Cout(nx), and the fifth transistor M5 is connected between the second voltage terminal VGL2 and the stage transmission signal output terminal Cout. When the voltage of the first node PU increases and the voltage of the stage transmission signal output terminal Cout is pulled up through the bootstrap capacitor C or other parasitic capacitance, the fifth transistor M5 can be turned on by making the first cross-cell stage transmission signal output terminal Cout(nx) on level. The second voltage terminal VGL2 pulls down the voltage of the stage transmission signal output terminal Cout, thereby reducing the noise of the signal at the stage transmission signal output terminal Cout.

[0057] As an example, such as Figure 10a As shown, when the gate of the fifth transistor M5 is connected to the first inter-cell stage signal output Cout(nx), the gate of the third transistor M3 can be electrically connected to the second node PD of the current shift register cell. As another example, such as... Figure 10b As shown, when the gate of the fifth transistor M5 is connected to the first cross-cell stage signal output terminal Cout(nx), the gate of the third transistor M3 can be electrically connected to the second node PD(m) of the cross-cell stage.

[0058] In some embodiments, along the transmission direction of the cascading signals of multiple shift register units, the first cross-unit cascading signal output terminal Cout(nx) is the cascading signal output terminal of the Xth shift register unit before the current shift register unit, where X is a positive integer.

[0059] like Figure 10a or Figure 10b As shown, the current shift register unit is the nth stage shift register unit VSR(n). The gate of the fifth transistor M5 of the nth stage shift register unit VSR(n) is connected to the stage pass signal output terminal Cout(nx) of the nXth stage shift register unit. The stage pass signal output terminal Cout(nx) of the nXth stage shift register unit outputs a turn-on level earlier than the stage pass signal output terminal Cout(n) of the nth stage shift register unit VSR(n). (Reference) Figure 5The cascade signal output terminal Cout(n) is easily coupled and raised before its output conduction level (e.g., high level) due to the increase in the voltage of the first node PU. In this embodiment, the cascade signal output terminal of the Xth shift register unit before the current shift register unit is connected to the first cross-unit cascade signal output terminal of the current shift register unit. This can better ensure that the cascade signal output terminal Cout(n) of the nth shift register unit VSR(n) is noise-reduced before the output conduction level of the cascade signal output terminal Cout(n) of the nth shift register unit VSR(n).

[0060] For example, the current shift register unit is the nth level shift register unit VSR(n), and the gate of the fifth transistor M5 of the nth level shift register unit VSR(n) is connected to the stage pass signal output terminal Cout(n-3) of the (n-3)th level shift register unit.

[0061] like Figure 11 As shown, the inventors of this application also... Figure 9a , Figure 10a and Figure 4 The working timing was simulated and compared, and V0 represents... Figure 4 The corresponding output terminal Cout of the transmission signal is pulled high due to noise; V3 indicates... Figure 9a The corresponding output terminal Cout of the transmission signal is pulled high due to noise; V4 represents... Figure 10a The corresponding output signal Cout is pulled up by noise, and both V3 and V4 are lower than V0. Furthermore, V4 is lower than V3. Therefore... Figure 10a and Figure 9a In comparison, the noise reduction effect of the newly added fifth transistor M5 is better than that of the newly added fourth transistor M4.

[0062] In some embodiments, such as Figures 7a to 10a As shown in any of the attached figures, the first pull-down circuit 151 can also be connected to the second node PD of the current shift register unit. The first pull-down circuit 151 can also control the signal of the first node PU and the signal output by the scan signal output terminal Gout based on the second node PD of the current shift register unit.

[0063] The first pull-up circuit 141 can control the signal of the second node PD based on the signal of the first node PU, and the first pull-down circuit 151 can control the signal of the first node PU based on the signal of the second node PD. In this way, the first node PU and the second node PD can restrain each other, increase the working reliability of the shift register unit, and reduce the risk of the signal output by the scan signal output terminal Gout being disordered.

[0064] In some embodiments, such as Figure 7aAs shown, the first pull-down circuit 151 may further include a sixth transistor M6 and a seventh transistor M7. The gate of the sixth transistor M6 is connected to the second node PD, and the sixth transistor M6 is connected between the second voltage terminal VGL2 and the scan signal output terminal Gout. The gate of the seventh transistor M7 is connected to the second node PD, and the seventh transistor M7 is connected between the second voltage terminal VGL2 and the first node PU.

[0065] For example, when the second node PD is on, the low voltage of the second voltage terminal VGL2 is transmitted to the scan signal output terminal Gout through the sixth transistor M6, and the low voltage of the second voltage terminal VGL2 is transmitted to the first node PU through the seventh transistor M7 to pull down the potential of the first node PU, so as to prevent the scan signal output circuit 13 from being turned on, so that the signal of the clock signal terminal CK will not be transmitted to the scan signal output terminal Gout at this time, so as to avoid the signal of the scan signal output terminal Gout from being disordered.

[0066] In other embodiments, such as Figure 8-10a As shown in any of the accompanying figures, the first pull-down circuit 151 may further include a sixth transistor M6 and a seventh transistor M7. The gate of the sixth transistor M6 is connected to the second node PD, and the sixth transistor M6 is connected between the third voltage terminal VGL3 and the scan signal output terminal Gout. The gate of the seventh transistor M7 is connected to the second node PD, and the seventh transistor M7 is connected between the second voltage terminal VGL2 and the first node PU.

[0067] The scan signal output terminal Gout is electrically connected to the third voltage terminal VGL3, while the stage transmission signal output terminal Cout and other nodes can be electrically connected to the second voltage terminal VGL2. The scan signal output terminal Gout is used to drive the luminous pixels, and the stage transmission signal output terminal Cout is used to transmit stage transmission signals to other stage shift register units. Connecting them to different low-level signal terminals effectively distributes the load across two low-level signal terminals, thus reducing the load on each low-level signal terminal. The voltages of the second voltage terminal VGL2 and the third voltage terminal VGL3 can be the same or different, and their values ​​can be set according to actual requirements.

[0068] In some embodiments, such as Figures 7a-10b As shown in any of the figures, the shift register unit VSR may also include a first reset circuit 161. The first reset circuit 161 may include an eighth transistor M8. The gate of the eighth transistor M8 is connected to the trigger signal input terminal IN. The eighth transistor M8 is connected between the second voltage terminal VGL2 and the second node PD.

[0069] When the trigger signal connected to the trigger signal input terminal IN of the shift register unit VSR is at the on level (e.g., high level), the input circuit 11 controls the first node PU to be at the on level. At this time, the eighth transistor M8 is turned on, and the low level of the second voltage terminal VGL2 is written to the second node PD to realize the reset of the second node PD, which can improve the stability and reliability of the shift register unit.

[0070] In some embodiments, such as Figures 7a-10b As shown in any of the attached figures, the shift register unit VSR may further include a second reset circuit 162. The second reset circuit 162 may include a ninth transistor M9. The gate of the ninth transistor M9 is connected to the second cross-cell stage transfer signal output terminal Cout(n+Y). The ninth transistor M9 is connected between the first node PU and the second voltage terminal VGL2. The second cross-cell stage transfer signal output terminal Cout(n+Y) is the stage transfer signal output terminal of another shift register unit.

[0071] When the second cross-unit cascade signal output terminal Cout(n+Y) is on, the second voltage terminal VGL2 is transmitted to the first node PU through the ninth transistor M9, making the first node PU off. In this way, the cascade signal output terminal Cout of the current shift register unit will not output an on level. When the cascade signal output terminal of another shift register unit (i.e., the second cross-unit cascade signal output terminal Cout(n+Y)) outputs an on level, the cascade signal output terminal Cout of the current shift register unit will not output an on level at the same time, so as to improve the reliability of the gate drive circuit.

[0072] In some embodiments, along the transmission direction of the cascading signals of the multiple shift register units, the second cross-unit cascading signal output terminal Cout(n+Y) is the cascading signal output terminal of the Yth shift register unit after the current shift register unit, where Y is a positive integer.

[0073] The current shift register unit is the nth stage shift register unit VSR(n). The gate of the ninth transistor M9 of the nth stage shift register unit VSR(n) is connected to the stage pass signal output terminal Cout(n+Y) of the (n+Y)th stage shift register unit. The stage pass signal output terminal Cout(n) of the nth stage shift register unit outputs a turn-on level earlier than the stage pass signal output terminal Cout(n+Y) of the (n+Y)th stage shift register unit VSR(n+Y).

[0074] For example, the current shift register unit is the nth level shift register unit VSR(n), and the gate of the ninth transistor M9 of the nth level shift register unit VSR(n) is connected to the stage pass signal output terminal Cout(n+3) of the (n+3)th level shift register unit.

[0075] In some embodiments, such as Figures 7a to 10b As shown, the shift register unit VSR may further include a reset circuit 17, which includes a tenth transistor M10, the gate of which is connected to the reset signal terminal RST, and the tenth transistor M10 is connected between the second voltage terminal VGL2 and the first node PU; and / or, the reset circuit 17 includes an eleventh transistor M11, the gate of which is connected to the reset signal terminal RST, and the eleventh transistor M11 is connected between the stage signal output terminal Cout and the second voltage terminal VGL2; and / or, the reset circuit 17 includes a twelfth transistor M12, the gate of which is connected to the reset signal terminal RST, and the twelfth transistor M12 is connected between the scan signal output terminal Gout and the second voltage terminal VGL2, or the twelfth transistor M12 is connected between the scan signal output terminal Gout and the third voltage terminal VGL3.

[0076] For example, before scanning each row of luminous pixels within a frame, or after power-on and before displaying the screen, the signal of the reset signal terminal RST is controlled to be on, so as to reset the potential of at least one of the first node PU, the transmission signal output terminal Cout, and the scan signal output terminal Gout.

[0077] During the scanning of each row of luminous pixels within a frame, the signal of the reset signal terminal RST can be controlled to be at the cutoff level.

[0078] In some embodiments, such as Figures 7a to 10b As shown, the input circuit 11 may include a thirteenth transistor M13. The gate of the thirteenth transistor M13 is connected to the trigger signal input terminal IN, and the thirteenth transistor M13 is connected between the trigger signal input terminal IN and the first node PU. The thirteenth transistor M13 is configured as a diode. The anode of the diode formed by the thirteenth transistor M13 is connected to the trigger signal input terminal IN, and the cathode of the diode formed by the thirteenth transistor M13 is connected to the first node PU. When the trigger signal input terminal IN is at a conducting level (e.g., a high level), the conducting level of the trigger signal input terminal IN is written to the first node PU.

[0079] The stage transmission signal output circuit 12 includes a fourteenth transistor M14, the gate of which is connected to the first node PU, and the fourteenth transistor M14 is connected between the clock signal terminal CK and the stage transmission signal output terminal Cout.

[0080] The scan signal output circuit 13 includes a fifteenth transistor M15, the gate of which is connected to the first node PU, and the fifteenth transistor M15 is connected between the clock signal terminal CK and the scan signal output terminal Gout.

[0081] The gates of the fourteenth transistor M14 and the fifteenth transistor M15 are both connected to the first node PU. The gates of the fourteenth transistor M14 and the fifteenth transistor M15 can be in the same state at the same time.

[0082] When the first node PU is on, transistors 14 and 15 are turned on. The clock signal from the clock signal terminal CK is transmitted to the stage transmission signal output terminal Cout through transistor 14, and to the scan signal output terminal Gout through transistor 15. The signal output from the scan signal output terminal Gout is used to drive the light-emitting pixels, and the signal output from the stage transmission signal output terminal Cout is used to drive other stage shift register units. By designing the scan signal output terminal Gout and the stage transmission signal output terminal Cout separately, the load is distributed to transistors 14 and 15, which reduces the load on transistors 14 and 15 and improves circuit reliability.

[0083] In some embodiments, such as Figures 7a to 10b As shown, the clock signal terminal CK includes the stage clock signal terminal CKA and the scan clock signal terminal CKB. The fourteenth transistor M14 is connected between the stage clock signal terminal CKA and the stage signal output terminal Cout, and the fifteenth transistor M15 is connected between the scan clock signal terminal CKB and the scan signal output terminal Gout.

[0084] By using the cascade clock signal terminal CKA and the scan clock signal terminal CKB, the signals output by the scan signal output terminal Gout and the cascade signal output terminal Cout can be independently controlled, thus adjusting the refresh frequency of the scan signal output terminal Gout of any shift register unit. For example, if the cascade clock signal terminal CKA provides a normal clock signal, but the scan clock signal terminal CKB does not, the cascade signal output terminal Cout can output a normal cascade signal, while the scan signal output terminal Gout cannot output a scan signal (i.e., the output signal does not include the on-state), which can reduce the refresh frequency of the scan signal output terminal Gout. Alternatively, if both the cascade clock signal terminal CKA and the scan clock signal terminal CKB provide a normal clock signal, the cascade signal output terminal Cout can output a normal cascade signal, and the scan signal output terminal Gout can also output a normal scan signal (i.e., the output signal includes the on-state), which can maintain a high refresh frequency for the scan signal output terminal Gout.

[0085] In some embodiments, such as Figures 12 to 15b As shown, the second node PD includes a first child node PD1 and a second child node PD2, as follows: Figure 12 , Figure 13 , Figure 14b and Figure 15b The cross-unit second node includes the cross-unit first child node PD1(m) and the cross-unit second child node PD2(m). The cross-unit second node includes the cross-unit first child node PD1(m), which is the first child node in another shift register unit, and the cross-unit second child node PD2(m), which is the second child node in another shift register unit. The cross-unit first child node PD1(m) and the cross-unit second child node PD2(m) belong to the same shift register unit.

[0086] The first pull-up circuit 141 and the first pull-down circuit 151 are connected to the first sub-node PD1 and the cross-unit first sub-node PD1(m); the shift register unit VSR may also include a second pull-up circuit 142 and a second pull-down circuit 152. The second pull-up circuit 142 is connected to the first node PU and the second sub-node PD2. The second pull-up circuit 142 controls the signal of the second sub-node PD2 based on the signal of the first node PU. The second pull-down circuit 152 is connected to the cross-unit second sub-node PD2(m) and the stage transmission signal output terminal Cout. The second pull-down circuit 152 controls the stage transmission signal of the stage transmission signal output terminal Cout based on the signal of the cross-unit second sub-node PD2(m).

[0087] In addition, the first pull-up circuit 141 is connected to the first voltage terminal VDDE, and the second pull-up circuit 142 is connected to the fourth voltage terminal VDDO.

[0088] like Figure 16 As shown, the signals on the first voltage terminal VDDE and the fourth voltage terminal VDDO can alternately be at the on level (e.g., high level). When the first voltage terminal VDDE provides the on level, the fourth voltage terminal VDDO provides the off level; or, when the first voltage terminal VDDE provides the off level, the fourth voltage terminal VDDO provides the on level. This allows one of the first pull-up circuit 141 and the second pull-up circuit 142 to be in the working state while the other is in the non-working state. Similarly, it allows one of the first pull-down circuit 151 and the second pull-down circuit 152 to be in the working state while the other is in the non-working state. This is equivalent to reducing the working time of any pull-up circuit and pull-down circuit, thereby reducing the risk of device failure caused by the transistors in the pull-up circuit and pull-down circuit being subjected to high voltage for a long time.

[0089] In some embodiments, such as Figures 12 to 15bAs shown, the second pull-up circuit 142 may include a sixteenth transistor M16 and a seventeenth transistor M17. The gate and first terminal of the sixteenth transistor M16 are connected to the fourth voltage terminal VDDO, and the second terminal of the sixteenth transistor M16 is connected to the second sub-node PD2. The gate of the seventeenth transistor M17 is connected to the first node PU, and the seventeenth transistor M17 is connected between the second sub-node PD2 and the second voltage terminal VGL2.

[0090] The sixteenth transistor M16 is configured as a diode. The anode of this diode is connected to the fourth voltage terminal VDDO, and the cathode is connected to the second sub-node PD2. When the seventeenth transistor M17 is turned on, the signal at the second voltage terminal VGL2 is transmitted to the second sub-node PD2; when the seventeenth transistor M17 is turned off, the signal at the fourth voltage terminal VDDO is transmitted to the second sub-node PD2. The state of the seventeenth transistor M17 is controlled by the first node PU. When the first node PU is at a conducting level, the seventeenth transistor M17 is turned on; when the first node PU is at a cutoff level, the seventeenth transistor M17 is turned off.

[0091] The second pull-down circuit 152 may include an eighteenth transistor M18, a nineteenth transistor M19, and a twentieth transistor M20. The gate of the eighteenth transistor M18 is connected to the second sub-node PD2(m) of the cross-cell or the second node PD of the current shift register cell, and the eighteenth transistor M18 is connected between the second voltage terminal VGL2 and the cascade signal output terminal Cout. The gate of the nineteenth transistor M19 is connected to the second sub-node PD2, and the nineteenth transistor M19 is connected between the scan signal output terminal Gout and the second voltage terminal VGL2, or the nineteenth transistor M19 is connected between the scan signal output terminal Gout and the third voltage terminal VGL3. The gate of the twentieth transistor M20 is connected to the second sub-node PD2, and the twentieth transistor M20 is connected between the first node PU and the second voltage terminal VGL2.

[0092] For example, during the period when the first node PU is raised to a high level and the cascade signal output terminal Cout does not need to output a high level, the second sub-node PD2(m) of the cross-cell is at the on level, and the second voltage terminal VGL2 is written to the cascade signal output terminal Cout through the eighteenth transistor M18, so as to reduce the risk of the voltage of the cascade signal output terminal Cout being pulled up due to the bootstrap capacitor C or other parasitic capacitances.

[0093] For example, the current shift register unit is the nth-level shift register unit VSR(n). The gate of the third transistor M3 in the nth-level shift register unit VSR(n) can be connected to the first child node PD1 in the (n+1)th-level shift register unit VSR(n), and the gate of the eighteenth transistor M18 in the nth-level shift register unit VSR(n) can be connected to the second child node PD2 in the (n+1)th-level shift register unit VSR(n+1). In other words, the first child node of the (n+1)th-level shift register unit VSR(n+1) serves as the first child node PD1(m) of the nth-level shift register unit VSR(n), and the second child node of the (n+1)th-level shift register unit VSR(n+1) serves as the second child node PD2(m) of the nth-level shift register unit VSR(n).

[0094] For example, such as Figure 14a or Figure 14b As shown, when the gate of transistor M4b in the second pull-down circuit 152 is connected to the trigger signal input terminal IN, the gate of the eighteenth transistor M18 is connected to the second sub-node PD2(m) of the cross-cell or the second node PD of the current shift register cell. Figure 15a or Figure 15b As shown, when the gate of transistor M4b in the second pull-down circuit 152 is connected to the first cross-cell stage signal output terminal Cout(nX), the gate of the eighteenth transistor M18 is connected to the cross-cell second sub-node PD2(m) or the second node PD of the current shift register unit.

[0095] In some embodiments, such as Figure 6 As shown, each shift register unit (VSR) includes a trigger signal input (IN), a staged signal output (Cout), a scan signal output (Gout), a staged clock signal (CKA), and a scan clock signal (CKB). For the nth shift register unit, its trigger signal input (IN) is connected to the start signal line (not shown in the figure, the start signal line is connected to the driver chip) or the staged signal output (Cout) of the nith shift register unit. Its staged signal output (Cout) is connected to the trigger signal input (IN) of the (n+i)th shift register unit. Its scan signal output (Gout) is connected to the scan signal line (GL), which is connected to the light-emitting pixel 20. Its staged clock signal (CKA) is connected to the corresponding staged clock signal line (clka), and its scan clock signal (CKB) is connected to the corresponding scan clock signal line (clkb). Here, i is a positive integer.

[0096] For example, with i=2, the cascading signal output Cout of the first shift register unit VSR1 is connected to the trigger signal input IN of the third shift register unit VSR3; the cascading signal output Cout of the second shift register unit VSR2 is connected to the trigger signal input IN of the fourth shift register unit VSR4; the third shift register unit VSR3 is connected to the trigger signal input IN of the fifth shift register unit VSR5; the fourth shift register unit VSR4 is connected to the trigger signal input IN of the sixth shift register unit VSR6, and so on. In this cascading method, multiple shift register units are cascaded at intervals.

[0097] For example, the stage clock signal line clka includes a first stage clock signal line 31 and a second stage clock signal line 32. The stage clock signal terminal CKA of the odd-numbered shift register units is connected to the first stage clock signal line 31, and the stage clock signal terminal CKA of the even-numbered shift register units is connected to the second stage clock signal line 32.

[0098] The scan clock signal line clkb includes a first scan clock signal line 41 and a second scan clock signal line 42. The scan clock signal terminal CKB of the odd-numbered shift register units is connected to the first scan clock signal line 41, and the scan clock signal terminal CKB of the even-numbered shift register units is connected to the second scan clock signal line 42.

[0099] It should be noted that, Figure 6 The number and connection method of the clock signal lines are merely an example and are not intended to limit this application. The technical concept of this application can also be applied to the setting and connection method of other clock signal lines.

[0100] The following is combined Figure 7a and Figure 7b Taking the nth-level shift register unit as an example, where n can be any value, the working process of the shift register unit is illustrated as follows: During the precharge phase t1, the cascade clock signal terminal CKA and the scan clock signal terminal CKB provide a low level, while the trigger signal input terminal IN provides a high level. The thirteenth transistor T13 is turned on, precharging the first node PU, causing PU to jump to a high level. The second transistor M2 is turned on, pulling the second node PD potential low. Due to the increased voltage of the first node PU, the voltage of the cascade signal output terminal Cout also increases due to the coupling effect of the bootstrap capacitor C. At least during the initial period of the precharge phase t1, since the second node PD(m) across units is at a high level, the third transistor M3 is turned on, which can pull down the voltage of the cascade signal output terminal Cout, thereby reducing noise at the cascade signal output terminal Cout and solving the problem of abnormal shift register cascade process in related technologies.

[0101] During the output phase t2, the stage clock signal terminal CKA and the scan clock signal terminal CKB provide a high level, while the trigger signal input terminal IN provides a low level. The fourteenth transistor M14 and the fifteenth transistor M15 are turned on, and the stage signal output terminal Cout and the scan signal output terminal Gout output a high level. As the stage signal output terminal Cout changes from a low level to a high level, the potential of the first node PU is higher due to the coupling effect of the bootstrap capacitor C, which makes the fourteenth transistor M14 and the fifteenth transistor M15 conduct more fully.

[0102] During the reset phase t3, the second inter-unit cascade signal output terminal Cout(n+Y) provides a high level, the ninth transistor M9 is turned on, the first node PU is pulled low, the second transistor M2 is turned off, and the second node PD is pulled high. The signal at the second inter-unit cascade signal output terminal Cout(n+Y) transitions to a high level later than the signal at the cascade signal output terminal Cout transitions to a low level, achieving a delayed reset. This ensures that the first node PU potential is pulled low only after the signal at the cascade signal output terminal Cout has been pulled low, thus preventing the output of the cascade signal output terminal Cout from being a non-low level.

[0103] After the reset phase t3, there is a maintenance phase, during which the first node PU remains at a low level and the second node PD remains at a high level.

[0104] At the beginning and / or end of a frame, the reset signal terminal RST is provided with a high level, and the tenth transistor M10, the eleventh transistor M11 and the twelfth transistor M12 are turned on, clearing the residual / accumulated charge on the first node PU, the cascade signal output terminal Cout and the scan signal output terminal Gout.

[0105] Based on the same technical concept, embodiments of this application also provide a display panel. For example... Figure 6 As shown, the display panel 100 includes light-emitting pixels 20 and a gate driving circuit 10 as described in any of the above embodiments.

[0106] The display panel provided in this application embodiment has the beneficial effects of the gate driving circuit provided in this application embodiment. For details, please refer to the specific description of the gate driving circuit in the above embodiments. This embodiment will not repeat the description here.

[0107] Based on the same technical concept, this application embodiment also provides a driving method for a display panel, which can be applied to the display panel 100 as shown in the above embodiment.

[0108] like Figure 6 As shown, the gate drive circuit is electrically connected to the clock signal line group, as follows: Figure 17As shown, the first display area A1 includes a first display sub-area A11 and a second display sub-area A12 arranged along the column direction D2. Please refer to the reference. Figure 17 and Figure 18 The driving method provided in this application embodiment may include: S181, In the first refresh subframe of the frequency division drive mode, the control clock signal line group provides clock signals normally in the row scanning cycle corresponding to the first and second display sub-areas. S182, in the second refresh subframe of the frequency division drive mode, the control clock signal line group normally provides a clock signal during the row scan cycle corresponding to the first display sub-area, and does not provide a clock signal during the row scan cycle corresponding to the second display sub-area.

[0109] The row scan period corresponding to the display sub-region is: the theoretical time period during which the display sub-region is scanned.

[0110] In the first refresh subframe, clock signals are provided normally during the row scan cycles corresponding to the first and second display sub-regions. In this way, the gate driving circuit outputs scan signals normally to the first and second display sub-regions, driving the first display sub-region A11 and the second display sub-region A12 normally. In the second refresh subframe, the clock signal line group provides clock signals normally only during the row scan cycle corresponding to the first display sub-region A11. The gate driving circuit 10 can drive the first display sub-region A11 normally, but the gate driving circuit 10 cannot drive the second display sub-region A12.

[0111] The first display sub-region A11 can be understood as being in a refresh frame in both the first and second refresh sub-frames. The second display sub-region A12 is in a refresh frame in the first refresh sub-frame and in a hold frame in the second refresh sub-frame. Overall, this makes the refresh frequency of the first display sub-region A11 greater than the refresh frequency of the second display sub-region A12, thus achieving vertical and horizontal frequency-divided display in the column direction.

[0112] In some embodiments, such as Figure 6 As shown, the clock signal line group includes the cascading clock signal line clka and the scan clock signal line clkb. S182 may specifically include: In the second refresh subframe of the frequency division drive mode, the control-level clock signal line and the scan clock signal line normally provide clock signals during the row scan cycle corresponding to the first display sub-area, the control-level clock signal line normally provides clock signals during the row scan cycle corresponding to the second display sub-area, and the control scan clock signal line does not provide clock signals during the row scan cycle corresponding to the second display sub-area.

[0113] The transmission clock signal line and the scan clock signal line provide clock signals normally during the row scan cycle corresponding to the first display sub-area, and the gate drive circuit 10 can output scan signals normally to drive the first display area A1 normally; however, the scan clock signal line clkb does not provide clock signals during the row scan cycle corresponding to the second display sub-area, and the gate drive circuit 10 cannot output valid scan signals (i.e., the signal output by the gate drive circuit 10 does not include the on level), and the gate drive circuit 10 cannot drive the second display area A2.

[0114] In other embodiments, such as Figure 19 As shown, the display panel 100 includes a first display area A1 and a second display area A2 arranged along a row direction D1. Both the first display area A1 and the second display area A2 include light-emitting pixels 20. A first gate line GL1 in the first display area A1 and a second gate line GL2 in the second display area A2 are disconnected from each other. The gate driving circuit 10 includes a first gate driving circuit 101 and a second gate driving circuit 102. The first gate driving circuit 101 is connected to the light-emitting pixels 20 in the first display area A1 via the first gate line GL1, and the second gate driving circuit 102 is connected to the light-emitting pixels 20 in the second display area A2 via the second gate line GL2. The first gate driving circuit 101 provides a scanning signal to the light-emitting pixels 20 in the first display area A1, and the second gate driving circuit 102 provides a scanning signal to the light-emitting pixels 20 in the second display area A2.

[0115] The display panel 100 further includes a first clock signal line group 51 and a second clock signal line group 52. The first clock signal line group 51 is connected to each shift register unit in the first gate driving circuit 101, and the second clock signal line group 52 is connected to each shift register unit in the second gate driving circuit 102. Both the first gate driving circuit 101 and the second gate driving circuit 102 may include the gate driving circuit described in any of the above embodiments.

[0116] The first clock signal line group 51 and the second clock signal line group 52 are connected to different clock signal pins of the drive signal, that is, the clock signals on the first clock signal line group 51 and the second clock signal line group 52 can be controlled independently of each other.

[0117] In this embodiment, for the two display areas on the row direction D1, different gate driving circuits are used to drive them respectively. The signals input to the two gate driving circuits can be controlled to be different, resulting in different refresh frequencies for the scan signals output by the two gate driving circuits. This causes the first display area A1 and the second display area A2 to display images at different frequencies, achieving segmented frequency display. Alternatively, the signals input to the two gate driving circuits can be controlled to be the same, making the refresh frequencies of the scan signals output by the two gate driving circuits the same, thus allowing the first display area A1 and the second display area A2 to display images at the same refresh frequency.

[0118] Based on the same technical concept, embodiments of this application also provide a driving method for a display panel, which can be applied to, for example... Figure 19 The display panel 100 shown.

[0119] The driving method may include: In the first display frame of the frequency division drive mode, both the first clock signal line group and the second clock signal line group provide clock signals normally. In the second display frame of the frequency division drive mode, the first clock signal line group is controlled to provide a clock signal normally, while the second clock signal line group does not provide a clock signal.

[0120] In frequency division driving mode, the operation of the display panel includes a first display frame and a second display frame. The first display frame and the second display frame can be two adjacent display frames, or they can be non-adjacent.

[0121] Please refer to Figure 19 In the first display frame, the first clock signal line group 51 and the second clock signal line group 52 normally provide clock signals, so the first gate driving circuit 101 can normally output scanning signals to drive the first display area A1 normally; the second gate driving circuit 102 can also normally output scanning signals to drive the second display area A2 normally.

[0122] In the second display frame, the first clock signal line group 51 provides a clock signal normally, so the first gate driving circuit 101 can output a scan signal normally to drive the first display area A1 normally; however, in the second display frame, the second clock signal line group 52 does not provide a clock signal, and the second gate driving circuit 102 cannot output a valid scan signal (i.e., the signal output by the second gate driving circuit 102 does not include the on level), and the second gate driving circuit 102 cannot drive the second display area A2.

[0123] The first display area A1 can be understood as being in the refresh frame in both the first and second display frames. The second display area A2 is in the refresh frame in the first display frame and in the hold frame in the second display frame. Overall, this makes the refresh frequency of the first display area A1 greater than the refresh frequency of the second display area A2, thus achieving segmented frequency display in the row direction.

[0124] In some embodiments, at least one of the first display frame and the second display frame includes a first refresh subframe and a second refresh subframe, such as... Figure 19 As shown, the first display area A1 includes a first display sub-area A11 and a second display sub-area A12 arranged along the column direction D2. Please refer to the reference. Figure 17 and Figure 19 The driving method provided in this application embodiment may further include: In the first refresh subframe, the first clock signal line group 51 is controlled to provide clock signals normally during the row scanning cycle corresponding to the first display sub-region A11 and the second display sub-region A12; in the second refresh subframe, the first clock signal line group 51 is controlled to provide clock signals normally during the row scanning cycle corresponding to the first display sub-region A11, but does not provide clock signals during the row scanning cycle corresponding to the second display sub-region A12.

[0125] The row scan period corresponding to the display sub-region is: the theoretical time period during which the display sub-region is scanned.

[0126] In the first refresh subframe, the first clock signal line group 51 provides a clock signal normally, so the first gate driving circuit 101 can output a scan signal normally to drive the first display sub-region A11 and the second display sub-region A12 normally. In the second refresh subframe, the first clock signal line group 51 only provides a clock signal normally within the row scan cycle corresponding to the first display sub-region A11. The first gate driving circuit 101 can drive the first display sub-region A11 normally, but the first gate driving circuit 101 cannot drive the second display sub-region A12.

[0127] The first display sub-region A11 can be understood as being in a refresh frame in both the first and second refresh sub-frames. The second display sub-region A12 is in a refresh frame in the first refresh sub-frame and in a hold frame in the second refresh sub-frame. Overall, this makes the refresh frequency of the first display sub-region A11 greater than the refresh frequency of the second display sub-region A12, thus achieving vertical and horizontal frequency-divided display in the column direction.

[0128] Of course, for the second display area A2, the signal input to the second gate driving circuit 102 can also be controlled to realize the upper and lower division frequency display of the second display area A2 in the column direction.

[0129] In some embodiments, such as Figure 17 As shown, both the first clock signal line group 51 and the second clock signal line group 52 include a cascading clock signal line clka and a scanning clock signal line clkb. S182 may specifically include: In the second display frame driven by frequency division, the cascading clock signal line clka controlling the first clock signal line group 51 and the second clock signal line group 52 both provide clock signals normally, the scanning clock signal line clkb controlling the first clock signal line group 51 provides clock signals normally, and the scanning clock signal line clkb controlling the second clock signal line group 52 does not provide clock signals.

[0130] The cascading clock signal lines clka of the first clock signal line group 51 and the second clock signal line group 52 both provide clock signals normally, so the cascading signals of the first gate driving circuit 101 and the second gate driving circuit 102 can be cascaded normally. The scanning clock signal line clkb of the first clock signal line group 51 provides clock signals normally, so the first gate driving circuit 101 can output scanning signals normally and drive the first display area A1 normally. However, the scanning clock signal line clkb of the second clock signal line group 52 does not provide clock signals, so the second gate driving circuit 102 cannot output valid scanning signals (i.e., the signals output by the second gate driving circuit 102 do not include the on level), and the second gate driving circuit 102 cannot drive the second display area A2.

[0131] For example, such as Figure 17 and Figure 19 As shown, in the second refresh subframe, the first clock signal line group 51 provides a clock signal normally during the row scan cycle corresponding to the first display sub-region A11, and does not provide a clock signal during the row scan cycle corresponding to the second display sub-region A12. Specifically, this may include: In the second refresh subframe, the cascading clock signal line clka and the scanning clock signal line clkb of the first clock signal line group 51 provide clock signals normally during the row scanning cycle corresponding to the first display sub-region A11. The cascading clock signal line clka of the first clock signal line group 51 provides clock signals normally during the row scanning cycle corresponding to the second display sub-region A12. The scanning clock signal line clkb of the first clock signal line group 51 does not provide clock signals during the row scanning cycle corresponding to the second display sub-region A12.

[0132] In some embodiments, at least one of the first display area A1 and the second display area A2 includes a first display sub-region A11 and a second display sub-region A12. Taking the first display area A1 including the first display sub-region A11 and the second display sub-region A12 as an example, the two areas have different refresh rates, and the refresh rates of the first display sub-region A11, the second display sub-region A12, and the second display area A2 can be the same or different. The specific driving method can be a combination of the two driving methods described above, which will not be elaborated here.

[0133] In some embodiments, such as Figures 12 to 16 As shown, the shift register unit VSR is connected to a first voltage terminal VDDE and a fourth voltage terminal VDDO. The driving method for the display panel provided in this embodiment may further include: controlling the first voltage terminal VDDE and the fourth voltage terminal VDDO to alternately provide on-level signals. In this way, when one of the first pull-up circuit 141 and the second pull-up circuit 142 is in the working state, the other is in the non-working state. Similarly, when one of the first pull-down circuit 151 and the second pull-down circuit 152 is in the working state, the other is in the non-working state. This is equivalent to reducing the working time of any pull-up circuit and pull-down circuit, thereby reducing the risk of device failure caused by prolonged exposure of transistors in the pull-up and pull-down circuits to high voltage levels.

[0134] Based on the same technical concept, embodiments of this application also provide a display device, including the display panel provided in this application. Please refer to... Figure 20 , Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 20 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 20 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, tablets, and vehicle-mounted display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0135] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A gate driving circuit, characterized in that, This includes multiple cascaded shift register units, each shift register unit comprising: An input circuit is connected to a trigger signal input terminal and a first node, and the input circuit adjusts the signal of the first node based on the trigger signal at the trigger signal input terminal. A cascade signal output circuit is connected to the first node, the clock signal terminal, and the cascade signal output terminal. The cascade signal output circuit controls the cascade signal output by the cascade signal output terminal based on the signals of the first node and the clock signal terminal. A scanning signal output circuit is connected to the first node, the clock signal terminal, and the scanning signal output terminal. The cascade signal output circuit controls the scanning signal output by the scanning signal output terminal based on the signals of the first node and the clock signal terminal. A first pull-up circuit and a first pull-down circuit, wherein the first pull-up circuit is connected to the first node and the second node, and controls the signal of the second node based on the signal of the first node; the first pull-down circuit is electrically connected to the target signal terminal and the cascade signal output terminal, and controls the cascade signal output by the cascade signal output terminal based on the signal of the target signal terminal; wherein the target signal terminal includes any one of the cross-unit second node, the trigger signal input terminal, and the first cross-unit cascade signal output terminal, the cross-unit second node is the second node of another shift register unit, and the first cross-unit cascade signal output terminal is the cascade signal output terminal of another shift register unit.

2. The gate driving circuit according to claim 1, characterized in that, Along the transmission direction of the cascading signals of the plurality of shift register units, the cross-unit second node is the second node of another shift register unit following the current shift register unit.

3. The gate driving circuit according to claim 2, characterized in that, Along the transmission direction of the cascading signals of the plurality of shift register units, the cross-unit second node is the second node of the next shift register unit after the current shift register unit.

4. The gate driving circuit according to claim 1, characterized in that, The first pull-up circuit includes: The first transistor has its gate and a first terminal connected to a first voltage terminal, and its second terminal connected to the second node. The second transistor has its gate connected to the first node and is connected between the second voltage terminal and the second node; The first pull-down circuit includes: The third transistor has its gate connected to the second node of the cross-cell and is connected between the second voltage terminal and the stage signal output terminal.

5. The gate driving circuit according to claim 1, characterized in that, The first pull-down circuit includes: The fourth transistor, the gate of which is connected to the trigger signal input terminal, is connected between the second voltage terminal and the stage signal output terminal; or, The fifth transistor has its gate connected to the first cross-cell stage transmission signal output terminal, and is connected between the second voltage terminal and the stage transmission signal output terminal.

6. The gate driving circuit according to claim 5, characterized in that, Along the transmission direction of the cascading signals of the plurality of shift register units, the first cross-unit cascading signal output terminal is the cascading signal output terminal of the Xth shift register unit preceding the current shift register unit; where X is a positive integer.

7. The gate driving circuit according to claim 1, characterized in that, The first pull-down circuit is also connected to the second node of the current shift register unit, and the first pull-down circuit also controls the signal of the first node and the scan signal output by the scan signal output terminal based on the signal of the second node of the current shift register unit.

8. The gate driving circuit according to claim 7, characterized in that, The first pull-down circuit also includes: A sixth transistor, the gate of which is connected to the second node, and the sixth transistor is connected between the second voltage terminal and the scan signal output terminal; A seventh transistor, the gate of which is connected to the second node, and the seventh transistor is connected between the second voltage terminal and the first node.

9. The gate driving circuit according to claim 7, characterized in that, The first pull-down circuit also includes: The sixth transistor has its gate connected to the second node and is connected between the third voltage terminal and the scan signal output terminal. A seventh transistor, the gate of which is connected to the second node, and the seventh transistor is connected between the second voltage terminal and the first node.

10. The gate driving circuit according to claim 7, characterized in that, The shift register unit further includes a first reset circuit, which includes: The eighth transistor has its gate connected to the trigger signal input terminal and is connected between the second voltage terminal and the second node.

11. The gate driving circuit according to claim 7, characterized in that, The shift register unit further includes a second reset circuit, which includes: The ninth transistor, whose gate is connected to the signal output terminal of the second inter-cell stage, is connected between the second voltage terminal and the first node; wherein, The second cross-unit cascade signal output terminal is the cascade signal output terminal of another shift register unit.

12. The gate driving circuit according to claim 11, characterized in that, Along the transmission direction of the cascading signals of the plurality of shift register units, the second cross-unit cascading signal output terminal is the cascading signal output terminal of the Y-th shift register unit after the current shift register unit; where Y is a positive integer.

13. The gate driving circuit according to claim 9, characterized in that, The shift register unit further includes a reset circuit, which includes: The tenth transistor has its gate connected to the reset signal terminal and is connected between the second voltage terminal and the first node; And / or, the eleventh transistor, the gate of which is connected to the reset signal terminal, and the eleventh transistor is connected between the second voltage terminal and the stage signal output terminal; And / or, a twelfth transistor, the gate of which is connected to the reset signal terminal, the twelfth transistor being connected between the second voltage terminal and the scan signal output terminal, or the twelfth transistor being connected between the third voltage terminal and the scan signal output terminal.

14. The gate driving circuit according to claim 1, characterized in that, The input circuit includes a thirteenth transistor, the cascade signal output circuit includes a fourteenth transistor, and the scan signal output circuit includes a fifteenth transistor. The gate of the thirteenth transistor is connected to the trigger signal input terminal, and the thirteenth transistor is connected between the trigger signal input terminal and the first node; The gate of the fourteenth transistor is connected to the first node, and the fourteenth transistor is connected between the clock signal terminal and the cascade signal output terminal. The gate of the fifteenth transistor is connected to the first node, and the fifteenth transistor is connected between the clock signal terminal and the scan signal output terminal.

15. The gate driving circuit according to claim 14, characterized in that, The clock signal terminal includes a transmission clock signal terminal and a scan clock signal terminal; The fourteenth transistor is connected between the stage transmission clock signal terminal and the stage transmission signal output terminal, and the fifteenth transistor is connected between the scan clock signal terminal and the scan signal output terminal.

16. The gate driving circuit according to claim 1, characterized in that, The second node includes a first child node and a second child node. The cross-cell second node includes a cross-cell first child node and a cross-cell second child node. The first pull-up circuit and the first pull-down circuit are connected to the first child node and the cross-cell first child node. The shift register unit further includes: A second pull-up circuit and a second pull-down circuit are connected. The second pull-up circuit is connected to the first node and the second child node, and controls the signal of the second child node based on the signal of the first node. The second pull-down circuit is connected to the second child node across the unit and the cascade signal output terminal, and controls the cascade signal output by the cascade signal output terminal based on the signal of the second child node across the unit. The first pull-up circuit is connected to the first voltage terminal, and the second pull-up circuit is connected to the fourth voltage terminal.

17. The gate driving circuit according to claim 16, characterized in that, The second pull-up circuit includes: The sixteenth transistor has its gate and first terminal connected to the fourth voltage terminal, and its second terminal connected to the second sub-node. The seventeenth transistor, the gate of which is connected to the first node, and the seventeenth transistor is connected between the second voltage terminal and the second sub-node; The second pull-down circuit includes: The eighteenth transistor, the gate of which is connected to the second sub-node of the cross-cell, is connected between the second voltage terminal and the cascade signal output terminal; The nineteenth transistor, the gate of which is connected to the second sub-node, is connected between the second voltage terminal and the scan signal output terminal; or, the nineteenth transistor is connected between the third voltage terminal and the scan signal output terminal. The twentieth transistor has its gate connected to the second child node and is connected between the second voltage terminal and the first node.

18. The gate driving circuit according to claim 1, characterized in that, The shift register unit further includes: A bootstrap capacitor is connected between the first node and the cascade signal output terminal.

19. The gate driving circuit according to claim 1, characterized in that, Each shift register unit includes a trigger signal input terminal, a cascade signal output terminal, a scan signal output terminal, a cascade clock signal terminal, and a scan clock signal terminal; For the nth shift register unit, the trigger signal input is connected to the start signal line or the cascade signal output of the nith shift register unit, the cascade signal output is connected to the trigger signal input of the (n+i)th shift register unit, the scan signal output is connected to the scan signal line of the corresponding row, the cascade clock signal is connected to the corresponding cascade clock signal line, and the scan clock signal is connected to the corresponding scan clock signal line; where i is a positive integer.

20. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 1-19.

21. A driving method for a display panel, characterized in that, Applied to the display panel of claim 20, wherein the gate driving circuit is electrically connected to the clock signal line group, and the display area of ​​the display panel includes a first display sub-region and a second display sub-region arranged along the column direction, the method includes: In the first refresh subframe of the frequency division drive mode, the clock signal line group is controlled to provide clock signals normally in the row scanning cycle corresponding to the first and second display sub-areas. In the second refresh subframe of the frequency division drive mode, the clock signal line group is controlled to provide a clock signal normally during the row scan cycle corresponding to the first display sub-area, and the clock signal line group does not provide a clock signal during the row scan cycle corresponding to the second display sub-area.

22. The driving method for a display panel according to claim 21, characterized in that, The clock signal line group includes a cascade clock signal line and a scan clock signal line; In the second refresh subframe of the frequency division drive mode, controlling the clock signal line group to normally provide a clock signal during the row scan cycle corresponding to the first display sub-area, and the clock signal line group not providing a clock signal during the row scan cycle corresponding to the second display sub-area, includes: In the second refresh subframe of the frequency division drive mode, the cascading clock signal line and the scanning clock signal line are controlled to provide clock signals normally during the row scanning cycle corresponding to the first display sub-area, the cascading clock signal line is controlled to provide clock signals normally during the row scanning cycle corresponding to the second display sub-area, and the scanning clock signal line is controlled not to provide clock signals during the row scanning cycle corresponding to the second display sub-area.

23. A display device, characterized in that, Includes the display panel as described in claim 20.

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