Cmos-based ising machine with quantized states and current-mode coupling

Abstract

A network of comprises a plurality of coupled computation nodes and active coupling units, each computation node comprising an input configured to receive current from a subset of the coupling units, an output configured to generate at least two discrete output voltages, a capacitor configured to store state, a quantizer connected to the capacitor, configured to quantize the voltage on the capacitor, the quantizer having an output connected to the output of the computation node, and wherein each active coupling unit comprises an input receiving an output voltage from one of the plurality of computation nodes, an output connected to the input of one of the plurality of computation nodes, a programmable current source, a programmable current sink, and a control circuit configured to connect the current source or current sink to the output of the coupling unit as a function of the input of the active coupling unit.

Description

Attorney docket # 204606-0171-00WO 2-24010 CMOS-BASED ISING MACHINE WITH QUANTIZED STATES AND CURRENT-MODE COUPLING CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to US Provisional Patent Application No.63 / 517,750, filed on August 4, 2023, incorporated herein by reference in its entirety. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under FA8650-23-C-7312 awarded by the Air Force Research Laboratory. The government has certain rights in the invention. BACKGROUND OF THE INVENTION

[0003] Physical Ising machines (IM) are promising platforms to provide extreme performance and efficiency to a variety of optimization problems. IMs have been shown to solve combinatoric optimization problems with orders-of-magnitude improvements in speed and energy efficiency over von Neumann systems. However, building such a system is still in its infancy and a scalable, robust implementation remains challenging.

[0004] For a long time, the industry focused on improving general-purpose systems and improving the power of computing by orders of magnitude. But in recent years, special-purpose designs have been increasingly adopted for their efficacy in solving specific types of tasks such as encryption and network operations (see C. Johnson, et al., in 2010 IEEE International Solid- State Circuits Conference-(ISSCC). IEEE, 2010; B. Erbagci, et al., in 2015 IEEE Custom Integrated Circuits Conference (CICC), 2015; S. Song, et al., in 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018; H. Kaul, et al., in 2016 IEEE International Solid-StateAttorney docket # 204606-0171-00WO 2-24010 Circuits Conference (ISSCC). IEEE, 2016). At the same time, computations require better mechanisms to solve a wide array of modern problems.

[0005] To facilitate computation for diverse workloads, researchers are trying to map an entire algorithm to physical processes such that the resulting state represents an answer to the mapped algorithm. An example is Quantum annealer from D-Wave Systems (P. I. Bunyk, et al., IEEE Transactions on Applied Superconductivity, 2014) where a combinatorial optimization problem is mapped to a system of qubits such that the system's Hamiltonian is subjected to minimization. Careful control is required for the system to settle to an equilibrium (i.e. optimal solution), and the qubit states are read out as the solution to the mapped problem.

[0006] The common properties of Ising machines are that: (1) a problem is mapped to its physical setup, (2) the internal state evolves according to machine-dependent physics, (3) the evolution optimizes a particular formula (the “Ising model”), and (4) the machine's physical state is read out to achieve a solution to the mapped problem. Different from the von Neumann machine, these nature-based machines follow no explicit algorithm. Recently, diverse Ising machines have been implemented in a variety of ways (see T. Inagaki, et al., Science, 2016; T. Wang et al., 2019; C. Roques-Carmes, et al., Nature Communications, 2020) which differ in complexity in their underlying physics principles.

[0007] Despite their potential of outperforming conventional computers in terms of power and time to find solutions, building a robust and general IM substrate remains challenging and scalability is one of the key factors that need to be considered. As the complexity of the problem to solve increases, the amount of required hardware components grows exponentially. In order to sustain a small form factor and chip area comparable to (or better than) a conventional computing substrate, simple building blocks are preferred for an Ising machine’s implementation. However, a trade-off between the size, power, and precise functionality of the building blocks must be considered. To address these issues, disclosed herein is a CMOS- compatible Ising machine with Quantized nodal States and Current-mode based nodal interactions (QS-CIM), which significantly improves the predictability and robustness of the nodal coupling with respect to device mismatch as well as process, voltage, and temperature (PVT) variations. The dynamical system naturally seeks local minima in the objective function'sAttorney docket # 204606-0171-00WO 2-24010 energy landscape. By applying spin-fix annealing, the system reaches a global minimum with a high probability. SUMMARY OF THE INVENTION

[0008] In one aspect, a network comprises a plurality of coupled computation nodes and a plurality of active coupling units, each computation node comprising an input configured to receive current from a subset of the plurality of coupling units in the network, an output configured to generate at least two discrete output voltages, a capacitor configured to store internal state as a voltage, a quantizer electrically connected to the capacitor, configured to quantize the voltage on the capacitor to one of at least two discrete values, the quantizer having an output connected to the output of the computation node, and wherein each active coupling unit comprises an input receiving an output voltage from one of the plurality of computation nodes, an output connected to the input of one of the plurality of computation nodes, a programmable current source, a programmable current sink, and a control circuit configured to connect either the current source or the current sink to the output of the active coupling unit as a function of the voltage measured at the input of the active coupling unit.

[0009] In one embodiment, the quantizer in each computation node is a comparator configured to compare the voltage across the capacitor against a threshold and generate two discrete voltages at the output of the computation node depending on the result of the comparison operation. In one embodiment, each of the quantizers are clocked by the same or essentially the same clock, configured to produce outputs at the same or essentially the same clock edge. In one embodiment, the currents from current source or current sink in the active coupling unit are connected to a constant voltage source when not connected to the output of the active coupling unit. In one embodiment, each active coupling unit further comprises a one-bit memory unit having a stored value, the stored value used to modulate the input to the active coupling unit.

[0010] In one embodiment, the stored value is a complement of the input to the active coupling unit. In one embodiment, the programmable current source and the programmable current sink in at least one of the active coupling units are implemented as metal-oxide-semiconductor transistors. In one embodiment, the programmable current source and the programmable current sink in at least one of the active coupling units are implemented as non-volatile memory devicesAttorney docket # 204606-0171-00WO 2-24010 selected from flash memory transistors or charge-trap transistors. In one embodiment, the network further comprises at least one programming unit configured to program the programmable current source and the programmable current sink.

[0011] In one embodiment, the programming unit comprises at least one binary polarity output configured to provide a polarity value to at least one active coupling unit in the network, at least one magnitude output configured to provide a magnitude voltage value to bias either the current source or current sink or both in at least one active coupling unit in the network, a polarity memory element connected to the at least one binary polarity output, configured to store and provide the polarity value to the at least one binary polarity output, an array of memory elements configured to store the magnitude voltage value as a set of binary values, a digital-to-analog converter connected to the array of memory elements and configured to produce the magnitude voltage value from the set of binary values, and a current mirroring element connected to the digital-to-analog converter and the magnitude output, configured to mirror a current emitted by the digital-to-analog converter to the magnitude output.

[0012] In one embodiment, the network further comprises an inverted binary polarity output connected to an inverting output of the polarity memory element, and configured to provide a binary value having the opposite polarity of the at least one binary polarity output. In one embodiment, the network further comprises a current conveyor circuit having an input connected to the input of the computation node and an output connected to the capacitor, the current conveyor configured to hold its input at a constant voltage and mirror a current proportional to the current received at the input into the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The foregoing purposes and features, as well as other purposes and features, will become apparent with reference to the description and accompanying figures below, which are included to provide an understanding of the invention and constitute a part of the specification, in which like numerals represent like elements, and in which: Fig.1 is an exemplary computing device.Attorney docket # 204606-0171-00WO 2-24010 Fig.2 is an example block diagram showing components of a 3-node QS-CIM system. In the diagram, nodes are labelled Node i and coupling units CUij. Fig.3 is an example circuit implementation of a QS-CIM node. Fig.4 is an example of a diagonal coupling unit in a coupling array. Fig.5 is an example circuit schematic of a non-diagonal coupling unit in the coupling array. Fig.6 is an example circuit diagram of a programming unit in the coupling array. Fig.7 is a diagram showing connectivity between a coupling unit and a programming unit in the coupling array. DETAILED DESCRIPTION

[0014] It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for the purpose of clarity, many other elements found in related systems and methods. Those of ordinary skill in the art may recognize that other elements and / or steps are desirable and / or required in implementing the present invention. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and steps is not provided herein. The disclosure herein is directed to all such variations and modifications to such elements and methods known to those skilled in the art.

[0015] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, exemplary methods and materials are described.Attorney docket # 204606-0171-00WO 2-24010

[0016] As used herein, each of the following terms has the meaning associated with it in this section.

[0017] The articles “a” and “an” are used herein to refer to one or to more than one (i.e., to at least one) of the grammatical object of the article. By way of example, “an element” means one element or more than one element.

[0018] “About” as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, is meant to encompass variations of ±20%, ±10%, ±5%, ±1%, and ±0.1% from the specified value, as such variations are appropriate.

[0019] Throughout this disclosure, various aspects of the invention can be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 2.7, 3, 4, 5, 5.3, 6 and any whole and partial increments therebetween. This applies regardless of the breadth of the range.

[0020] In some aspects of the present invention, software executing the instructions provided herein may be stored on a non-transitory computer-readable medium, wherein the software performs some or all of the steps of the present invention when executed on a processor.

[0021] Aspects of the invention relate to algorithms executed in computer software. Though certain embodiments may be described as written in particular programming languages, or executed on particular operating systems or computing platforms, it is understood that the system and method of the present invention is not limited to any particular computing language, platform, or combination thereof. Software executing the algorithms described herein may be written in any programming language known in the art, compiled or interpreted, including but not limited to C, C++, C#, Objective-C, Java, JavaScript, MATLAB, Python, PHP, Perl, Ruby, or Visual Basic. It is further understood that elements of the present invention may be executedAttorney docket # 204606-0171-00WO 2-24010 on any acceptable computing platform, including but not limited to a server, a cloud instance, a workstation, a thin client, a mobile device, an embedded microcontroller, a television, or any other suitable computing device known in the art.

[0022] Parts of this invention are described as software running on a computing device. Though software described herein may be disclosed as operating on one particular computing device (e.g. a dedicated server or a workstation), it is understood in the art that software is intrinsically portable and that most software running on a dedicated server may also be run, for the purposes of the present invention, on any of a wide range of devices including desktop or mobile devices, laptops, tablets, smartphones, watches, wearable electronics or other wireless digital / cellular phones, televisions, cloud instances, embedded microcontrollers, thin client devices, or any other suitable computing device known in the art.

[0023] Similarly, parts of this invention are described as communicating over a variety of wireless or wired computer networks. For the purposes of this invention, the words “network”, “networked”, and “networking” are understood to encompass wired Ethernet, fiber optic connections, wireless connections including any of the various 802.11 standards, cellular WAN infrastructures such as 3G, 4G / LTE, or 5G networks, Bluetooth®, Bluetooth® Low Energy (BLE) or Zigbee® communication links, or any other method by which one electronic device is capable of communicating with another. In some embodiments, elements of the networked portion of the invention may be implemented over a Virtual Private Network (VPN).

[0024] Fig.1 and the following discussion are intended to provide a brief, general description of a suitable computing environment in which the invention may be implemented. While the invention is described above in the general context of program modules that execute in conjunction with an application program that runs on an operating system on a computer, those skilled in the art will recognize that the invention may also be implemented in combination with other program modules.

[0025] Generally, program modules include routines, programs, components, data structures, and other types of structures that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the invention may be practiced with other computer system configurations, including hand-held devices, multiprocessor systems,Attorney docket # 204606-0171-00WO 2-24010 microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0026] Fig.1 depicts an illustrative computer architecture for a computer 100 for practicing the various embodiments of the invention. The computer architecture shown in Fig.1 illustrates a conventional personal computer, including a central processing unit 150 (“CPU”), a system memory105, including a random access memory 110 (“RAM”) and a read-only memory (“ROM”) 115, and a system bus 135 that couples the system memory 105 to the CPU 150. A basic input / output system containing the basic routines that help to transfer information between elements within the computer, such as during startup, is stored in the ROM 115. The computer 100 further includes a storage device 120 for storing an operating system 125, application / program 130, and data.

[0027] The storage device 120 is connected to the CPU 150 through a storage controller (not shown) connected to the bus 135. The storage device 120 and its associated computer-readable media provide non-volatile storage for the computer 100. Although the description of computer- readable media contained herein refers to a storage device, such as a hard disk or CD-ROM drive, it should be appreciated by those skilled in the art that computer-readable media can be any available media that can be accessed by the computer 100.

[0028] By way of example, and not to be limiting, computer-readable media may comprise computer storage media. Computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EPROM, EEPROM, flash memory or other solid state memory technology, CD-ROM, DVD, or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer.Attorney docket # 204606-0171-00WO 2-24010

[0029] According to various embodiments of the invention, the computer 100 may operate in a networked environment using logical connections to remote computers through a network 140, such as TCP / IP network such as the Internet or an intranet. The computer 100 may connect to the network 140 through a network interface unit 145 connected to the bus 135. It should be appreciated that the network interface unit 145 may also be utilized to connect to other types of networks and remote computer systems.

[0030] The computer 100 may also include an input / output controller 155 for receiving and processing input from a number of input / output devices 160, including a keyboard, a mouse, a touchscreen, a camera, a microphone, a controller, a joystick, or other type of input device. Similarly, the input / output controller 155 may provide output to a display screen, a printer, a speaker, or other type of output device. The computer 100 can connect to the input / output device 160 via a wired connection including, but not limited to, fiber optic, Ethernet, or copper wire or wireless means including, but not limited to, Wi-Fi, Bluetooth, Near-Field Communication (NFC), infrared, or other suitable wired or wireless connections.

[0031] As mentioned briefly above, a number of program modules and data files may be stored in the storage device 120 and / or RAM 110 of the computer 100, including an operating system 125 suitable for controlling the operation of a networked computer. The storage device 120 and RAM 110 may also store one or more applications / programs 130. In particular, the storage device 120 and RAM 110 may store an application / program 130 for providing a variety of functionalities to a user. For instance, the application / program 130 may comprise many types of programs such as a word processing application, a spreadsheet application, a desktop publishing application, a database application, a gaming application, internet browsing application, electronic mail application, messaging application, and the like. According to an embodiment of the present invention, the application / program 130 comprises a multiple functionality software application for providing word processing functionality, slide presentation functionality, spreadsheet functionality, database functionality and the like.

[0032] The computer 100 in some embodiments can include a variety of sensors 165 for monitoring the environment surrounding and the environment internal to the computer 100. These sensors 165 can include a Global Positioning System (GPS) sensor, a photosensitiveAttorney docket # 204606-0171-00WO 2-24010 sensor, a gyroscope, a magnetometer, thermometer, a proximity sensor, an accelerometer, a microphone, biometric sensor, barometer, humidity sensor, radiation sensor, or any other suitable sensor.

[0033] The present disclosure relates to a Complementary Metal-oxide-semiconductor (CMOS) compatible Ising machine with quantized nodal states (or nodal variables) and current-based nodal interactions (QS-CIM). The spin of nodal variables (nodal output) in QS-CIM is represented as a polarity of capacitor voltage and the coupling between the nodes is achieved through an array of programmable current sources whose outputs are controlled by the corresponding spin values.

[0034] In one embodiment of the present invention, QS-CIM consists of N nodes (node example shown in Fig.2) and an array of (N-1) x (N-1) coupling units each containing a current source with programmable current magnitude and a polarity that is controlled by the output from the corresponding node as well as N current programming units each containing a Digital-to-Analog converter that converts digital representation of coupling coefficients to analog value supplied to the current sources for programming. Each of the N nodes contains a capacitor whose voltage is quantized to a binary value (e.g., 0V or Vdd) forming the outputs of the nodes. The binary output of node Niis then used to control polarity (i.e. sign or direction) of the output current generated by the current sources in the ithrow. For example, if the output from Ni node is Vdd volts, the current sources in the ^௧^row will generate positive currents at their outputs, while for 0V nodal output, the output currents will be negative. All currents from current-sources of the jthcolumn (where j = 1,..,N, j ≠ i) are summed up and the resulting total current is fed into the capacitor of jthnode charging (or discharging) its voltage. The current magnitude of all current-sources in the array is programmed by the corresponding current programming units. An example operation of the QS-CIM in this embodiment is as follows: (1) Map coupling coefficients Jij onto current- sources by: a) connect the jthcolumn of coupling units to the column of current-programming units, b) convert the digital representation of coupling coefficient magnitude |Jij|, 1 ≤ i ≤ N to an analog value which is stored within coupling units of the jthcolumn to bias current sources. In this step the polarity bit of the coupling coefficients is also stored within the coupling units of the jthcolumn, c) move to the next column and repeat steps a) through c) until the last column in the array is programmed. (2) The capacitor voltages are initialized to some initial vales (e.g.Attorney docket # 204606-0171-00WO 2-24010 initialized at 0V or Vdd at random). (3) The internal state (i.e. capacitor voltages) evolves according to machine-dependent physics, (4) the evolution optimizes a particular formula (e.g. the “Ising model”), (5) the machine's physical state is quantized (i.e. each capacitor voltage is compared against a threshold and quantized to a binary value) and read out to achieve a solution to the mapped problem. The Ising Model

[0035] The Ising model is used to describe the Hamiltonian of a system of spins. The spins can have values either +1 or -1. The energy of the system is a function of pair-wise coupling Jij of the spins and each spin's reaction hito some external magnetic field (μ). The resulting Hamiltonian is as follows: ^= −^^^^^^^^ − ^ ^ℎ^^^^

[0036] If the external field is ignored, the Hamiltonian simplifies to: ^= −^^^^^^^^

[0037] This simplified version is more useful for the purposes of this disclosure. As contemplated herein, “the Ising model” or “the Ising formula” refers to Equation 2.

[0038] A physical system with such a Hamiltonian naturally tends towards low-energy states. It can therefore be used to solve an optimization problem with a formulation equivalent to the Ising formula if parameters (e.g. Jij) can be configured to match that of the problem. Relation between the Ising model and the Max-Cut Problem

[0039] Many optimization problems naturally map to an Ising machine. Perhaps the most straightforward problem to map is the Max-Cut problem. Given a graph, G = (V,E), a “cut” is aAttorney docket # 204606-0171-00WO 2-24010 partition of vertices into two sets of, e.g., V+and V-, where V- = V-V+. The goal is to find a cut such that the combined weight of the edges spanning the two sets of vertices is maximized. In other words, the maximum cut is argmaxۇۊ ^^^^^శ∈^^^^ۈۋ^^,^^∈ாۉ^∈^శ;^∈^ష یEquation 3 where Wij is the weight of edge (i,j).

[0040] It is easy to see thebetween Equation 2 and Equation 3. In fact, if the coupling weight (Jij) is set to be the negative of the edge weight (-Wij) then the Ising formula issimply twice the negative cut value plus a problem-specific constant (∑ ^^^) as follows (fornotational simplicity, for ^ ≥ ^ we set ^^^ to 0):^= −^^^^^^^^ = ^ ^^^^^^^ + ^ ^^^^^^^^^^

[0041] Hence if the machine finds the ground state of the Hamiltonian, it finds the maximum cut. Finding out the maximum cut of an arbitrary graph is an NP-hard problem. Practical algorithms only try to find a good answer. Similarly, existing Ising machines (including the disclosed design) are all Ising “sampling” machines that typically provide a good sample of a low-energy state, with no guarantee of optimality.

[0042] Because of the trivial mapping of the Max-Cut problem to the Ising formula, designers of Ising machines often focus on this optimization problem. However, other optimization problems can also be mapped to an Ising machine.Attorney docket # 204606-0171-00WO 2-24010

[0043] Existing Ising Machines may be divided into three categories based on the technology used for their design: Quantum, Optical, and Electronic annealers.

[0044] The latest Quantum Ising annealer manufactured by D-wave can support up to 2000 qubits (see “The D-Wave 2000Q Quantum Computer.”). The qubits are coupled to form a chimera graph. As a result of local coupling, the D-wave machine can only map up to 64 nodes in an all to all connected graph (see R. Hamerly, et al., Science advances, 2019; and R. Hamerly, et al., arXiv, 2018) These annealers are also susceptible to noise, necessitating a cryogenic operating condition that consumes much power (25KW for D-Wave 2000q) (see “The D-Wave 2000Q Quantum Computer.”).

[0045] The most popular optics-based Ising machine is the Coherent Ising Machine (CIM) (see T. Inagaki, et al., Science, 2016; Y. Yamamoto, et al., npj Quantum Information, 2017; P. L. McMahon, et al, Science, 2016; K. Takata, et al., Scientific Reports, 2016; and F. Bohm, et al., Nature Communications, 2019). It uses an optical parametric oscillator (OPO) to generate and manipulate the signal to represent one spin. Unlike D-Wave, CIM nodes are all-to-all coupled. The machine has two components; an optical cavity built using kilometers of fiber optic cable, and an auxiliary computer to implement coupling between nodes. Every pulse's amplitude and phase in the optical cavity is detected, and its interaction with all other pulses is calculated using an auxiliary computer (FPGA). This computation is then used to modulate new pulses that are injected back into the optical cavity. Strictly speaking, the current implementation is a nature- simulation hybrid Ising machine. Thus, beyond the challenge of constructing the cavity, CIM also requires a significant supporting structure that involves fast conversions between optical and electrical signals.

[0046] The operating principle of CIM can be viewed as a Kuramoto model (see Y. Takeda, et al., Quantum Science and Technology, 2017) so in theory, a similar goal may be achieved using other oscillators. This led to the design of electronic Oscillator-based Ising Machines (OIM). These systems use the phase of oscillations in LC-tank oscillators or in ring-oscillators to represent spins and (programmable) resistors as coupling units. However, inductors in LC-tank based oscillators are often a source of practical challenges for on-chip integration. OIM based machines are area intensive and have undesirable parasitics with reduced quality and increasedAttorney docket # 204606-0171-00WO 2-24010 phase noise, which poses practical challenges in maintaining frequency uniformity and phase synchronicity between thousands of on-chip oscillators.

[0047] Another electronic design with resistive coupling are the Bistable Resistively-coupled Ising Machines (BRIM) (see R. Afoakwa, et al., 2021.) and Quantized BRIM (QuBRIM) (Y. Zhang, et al., in 2022 IEEE / ACM International Conference On Computer Aided Design (ICCAD), 2022) in which the Ising spin is implemented as capacitor voltage or polarity of the capacitor voltage, respectively. Since they use voltage or its polarity (as opposed to phase) to represent spin, they enable a straightforward interface to additional architectural support for computational tasks. In QuBRIM, the polarity of the voltage across the capacitor represents the spin of the node and the coupling strength is inversely proportional to the resistance of thecoupling resistors, i.e., ^^^ = ^ / ห^^^ห, where R is a scaling coefficient and the negative couplingis achieved by cross coupling the coupling resistors. Additional information about BRIM and QuBRIM may be found in U.S. Patent Application No.17 / 996,283, filed on October 14, 2022, and International Application No. PCT / US2023 / 060567, filed on January 12, 2023, incorporated herein by reference in their entireties.

[0048] Researchers have also designed different chips to accelerate simulated annealing (see S. Kirkpatrick, et al., Science, 1983) or a variant of the classic algorithm (see M. Yamaoka, et al., in 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015; and T. Takemoto, et al., in IEEE International Solid- State Circuits Conference, 2019). In these designs, the spins are virtual in that they are bits in memory and manipulated by an algorithm (simulated annealing). These machines are specially built to accelerate that algorithm. Hence such machines are referred to as “Accelerated Simulated Annealers” (ASA). These are fundamentally different from regular Ising machines as they follow a particular algorithm, whereas the physical laws themselves guide the regular Ising machines.

[0049] Coupling between nodes is a key factor to build robust Ising machines because the problem to solve is directly embedded in it. Although the spin only takes two discrete values, the physical quantity that represents the spin can experience a large swing, which may pose many issues. For example, in resistively coupled Ising machines (see R. Afoakwa, et al., 2021; and S. Dutta, et al., Nature Electronics, 2021) this may cause a large variation in the coupling resistance, and very likely the machine is solving different problems at different times. Also, theAttorney docket # 204606-0171-00WO 2-24010 trade-off between the size, power, and precise functionality of the building blocks limits the scalability (see A. Sharma, et al., in Proceedings of the 49th Annual International Symposium on Computer Architecture, ser. ISCA, 2022). To address these issues, disclosed herein is QS-CIM, a CMOS-based Ising machine which utilizes current-mode coupling between the interacting nodes that, along with the 2-value outputs (i.e. binary outputs) from interacting nodes connected to the inputs to the coupling units, allows for better coupling linearity, accuracy and reduced sensitivity to PVT and mismatch.

[0050] Provided herein is a theoretic analysis to support QS-CIM's ability for optimum-seeking, then the high-level design of QS-CIM system is discussed and an example circuit level implementation is disclosed. The dynamic of QS-CIM can be described by the change of each nodal voltage caused by other nodes connected to it. Without loss of generality, the following description follows only the dynamic of one node to make the analysis neat, however, it can be easily extended to the whole system ^^^^ = ^^^^^^, ^ଶ^^^, …   , ^ே^^^^்.

[0051] The dynamic of node i is^^^ 1^^ =^ ^^^^൫^^^൯ ∙ ^^^ ∙ ^൫^^൯where the summation on the right side represents the currents flow to node i from other nodes with ^^^൫^^^൯ indicating the coupling polarity (i.e. ^^^^^^ = +1;  ^ ≥ 0 and -1 otherwise) forunit at location (i,j) in the array. ^^^ = αห^^^ห represents a current magnitude suppliedby the coupling unit at location (i,j) in theithnode, where α is a scaling constant with unit of Amperes. It should be noted that the total current supplied to the ithnode does not depend on yi but only on the quantized voltage of other nodes, i.e., ^൫^^൯, where ^൫^^൯ = ^^^൫^^൯.^^^^ 1^= ∙ = ^^^^ ∙Attorney docket # 204606-0171-00WO 2-24010

[0052] Given the set of differential equations above describing QS-CIM as a dynamic system, it can be shown that a Lyapunov function in the following form exists: ^= −^^^^ ∙ ^^^^^ ∙ ^൫^^൯Because the quantity ^൫^^൯ in Equation 7 only takes the values of {−1, +1} and can be used todirectly represent the spin of the node j, the Lyapunov function in Equation 7 directly relates to the Ising Hamiltonian in Equation 2 (i.e. by minimizing the Lyapunov function in Equation 7, QS-CIM simultaneously seeks a minimum in the Ising Hamiltonian).

[0053] To show the ability for optimum-seeking of QS-CIM, a Lyapunov stability analysis, is presented below, which states that if a function H(v) can be found such that ௗு^௩^ eௗ௧ = 0 at point vand ௗு^௩^< 0 in the region around ve eௗ௧ , then v is the equilibrium point (seeSystem Analysis.1978.) In the disclosed case, the equilibrium point corresponds to the solution to the equation set ௗ௩^ௗ௧ = 0;  ^ = 1..^.

[0054] Taking the timeof Equation 7, the following result is obtained after applying the chain rule: ^^^^^ ^^^^^ ^^^^ ^ ^^^^ ^ ^^ ^^^^ ^^^ ^ ^ ^ ^ ^ ^ ^ ^where the last portion is the direct result of Equation 6. More importantly, one should notice that the product in the brackets is non-negative because vi and ^^^^^always change in the same direction. As a result, the time derivative of H(v) is non-positive (i.e. H(v) is a non-increasing function), so QuBRIM indeed satisfies the Lyapunov stability criterion. In other words, once the system enters a region, it will inevitably evolve towards lowering H(v) until it reaches theAttorney docket # 204606-0171-00WO 2-24010 equilibrium point ve. Consequently, minimizing H(v) is equal to minimizing the Ising formula in Equation 2. System Level Design and Circuit Implementation

[0055] The QS-CIM design at the system level is described below. An example 3-node QS-CIM system is illustrated in Fig.2 and can be viewed as a group of components as follows:

[0056] First, the nodes (201) at the left of the diagram in Fig.2 are referred to herein as Ni. Each of the nodes 201 contains a capacitor that holds the node's state vi. Note that the capacitor's voltage vi is an analog value that spans a certain range (e.g. rail-to-rail such as 0V to Vdd, but in some embodiments the range could be lower to reduce power). The capacitor in each node is charged / discharged by the output current from the current conveyor placed within each of the nodes, where a current conveyor is a circuit that receives an input current Iin and provides an output current Iout that is equal to the input current or its scaled up / down version. Typically, a current conveyor holds the voltage at its input at, or close to, a fixed potential (e.g. a common- mode voltage VCM =Vdd / 2) providing a so-called virtual ground at its input. In some embodiments, a current conveyor is not included in a node, and the capacitor in some or all nodes may be charged / discharged via a direct electrical connection.

[0057] Each node may also include a comparator that compares the capacitor's voltage against a threshold (e.g. VCM) and provides a voltage output that is either high (e.g. Vdd) or low (e.g.0V) depending on the result of the comparison operation. The node's comparator performs the quantization operation ^^^^^ described above. The nodes are connected to each other through an array of coupling units (CUs) and each node Nihas three terminals. One terminal is an input terminal that receives currents from all coupling units in the ithcolumn except from the couplingunit at the location in the array where the row number is equal to the column number (i.e. ^ ^^^).The nodes also contain two output terminals providing both the output from the comparator and its complementary value to the coupling units of the ithrow. An example circuit-level implementation of one node in QS-CIM is shown in Fig.3, where transistors M1-M10 constitute a current conveyor with input at the circuit node Y, output at the circuit node Z, while the circuit node X is held at a fixed potential^^ெ. Transistors M9-M10 constitute a simple inverter-based comparator. The circuit in Fig.3 also shows a nodal capacitor connected between circuit nodes ZAttorney docket # 204606-0171-00WO 2-24010 and X. The nodes can also include additional circuitry such as switches S1 and S2 to configure the initial spins of the system (e.g. set the initial capacitor voltage to 0V or Vdd) before the machine's states are allowed to evolve in seeking an energy minimum. Another function of these switches is to perform spin-fix perturbations, which allow the machine to escape local energy minima in search of the optimal solution. ^^^ାand ^^^ିare two non-overlapping signals controlled by the control logic during the machine's state evolution, which introduces random or pseudo-random spin-fix perturbation as described in Y. Zhang, et al., in 2022 IEEE / ACM International Conference On Computer Aided Design (ICCAD), 2022. Each of the nodes may also include a D Flip-Flop used to sample the output of the comparator (\ie the spin configuration) when necessary.

[0058] Second, the coupling units 203, shown as part of the coupling array 202 in Fig.2 contains two types of coupling units. The diagonal coupling units (i.e. i = j), as shown in Fig.4, are passive units providing connections between the rows and columns of the array as well as to pass output from the nodes, control signals and biasing voltages (e.g.^^^^and^^^^) from theprogramming units ^ ^^ as well as control signals from the column selector 204 to theneighboring coupling units. As shown in Fig.4, the diagonal CUs pass the following signals: (1)Two outputs th^^_^௨௧ and ^^_^௨௧ from node Ni to non-diagonal CUs in the i row, (2) Input ( ^^_^^)to the current conveyor of the Ni node, which is connected to the outputs (Out) of all non- diagonal CUs in the ithcolumn, (3) Biasing voltages^^^^and^^^^generated by the programmingunit at the end of the ith row (see ^ ^^ in Fig. 2), (4) Coupling polarity programming signals ^^and ^^ generated by the programming unit ^ ^^ to store the coupling polarity within each of thenon-diagonal CUs of the ^௧^ row during the CU programming phase, (5) Column selector signal^^ and its complement ^^, which activate access transistors within each of the non-diagonal CUfor programming, (6) Power lines ( ௗ^ௗ and ground) as well as reference voltages such as ^^ெ. Invarious embodiments, some or all coupling units may comprise a memory, for example a volatile or non-volatile memory. In one embodiment, some or all coupling units comprise a one-bit memory unit, which may be volatile or non-volatile, configured to store a value used to modulate the input to the coupling unit, for example configured to store an inverse or complement of an input to the coupling unit.Attorney docket # 204606-0171-00WO 2-24010

[0059] Unlike diagonal CUs, the non-diagonal CUs are active (i.e. include power sources such as current sources) and an example circuit schematic of a non-diagonal CU is shown in Fig.5. The non-diagonal CUs in this embodiment of the current invention contain twenty transistors. Transistors M1 and M2 act as a current source and current sink, respectively. The gate-source biasing for M1 and M2 is provided during the programming phase by asserting access switches M7 and M8 that connect the gates of M1 and M2 to the biasing voltages^^^^and^^^^,respectively, where the biasing voltages are generated by the programming unit at the end of the^௧^ row. Note that during the machine's normal operation (i.e. the machine's internal state isallowed to evolve), the two access switches M7 and M8 are deactivated, while the gate capacitance of M1 and M2 preserves the programmed biasing voltages. Additional capacitors may be added to the gate terminals of M1 and M2 to counteract gate bias loss due to gate leakage currents. Transistors M5 and M6 serve as output switches that connect either current source M1 or current sink M2 to the output of the coupling unit. The choice between current sourcing orcurrent sinking depends on the coupling polarity bit ( ^^^), which is stored within the CU duringthe programming phase, as well as the output of the node ( ^^_^௨௧). For example, if the couplingpolarity of the CU at location ^^, ^^ is positive (e.g. ^^^ = ௗ^ௗ or logic 1) and the output from thenode ^^ is negative (e.g. ^^_^௨௧ = 0^ or logic 0)gate control signal G is positive (or logic 1)which activates output switch M6 connecting the current sink M2 to the output Out resulting in a negative current (i.e. current flowing into the CU). Transistors M9 to M12 serve as a 2-to-1 multiplexer whose control signals are polarity bit^^^and its complement. The multiplexer's inputs are the two outputs from node^^(i.e.and its complement). The multiplexer produces gate control signal Ggates of the output switches M5 and M6. Transistors M13 and M14 form an inverter that generates signal ^ that is complementary to G to drive gates of switches M3 and M4 which in turn connect the drain terminals of the current source M1 and the current sink M2 to a fixed potential (e.g.^^ெ) steering the currents from M1 and M2 away from the output when M5 or M6 are not engaged. It should be noted that the inverter (M13 / M14) and switches M3 and M4 are not essential for the operation of the coupling unit, but their use is advantages to maintain currents in M1 and M2 stable over the machine's operation time. Without the use of switches M3 and M4, the drain terminals of M1 and M2 would be experiencing large and typically abrupt voltage swings that might propagate through drain-Attorney docket # 204606-0171-00WO 2-24010 gate parasitic capacitance affecting the voltage on the gates and their current magnitude. For example, when M5 switch is on, the drain terminal of M1 is at^^ெ, which is typically atௗ^ௗ / 2, while during the M5's off-time the drain terminal of M1 is charged toௗ^ௗresulting in total change ofௗ^ௗ / 2 which could be substantial. One approach to minimize the effect of the charge injection from drain terminals to gates of M1 and M2 is to increase the size of the capacitors connected to the gates. However, this approach may result in a substantial increase of the total CU area and cost. The more efficient approach to minimize charge injection from drain terminals is to maintain the drain voltages at a constant voltage (e.g.^^ெas show in the schematic) , which is achieved by the addition of switches M3 and M4 that are controlled by a signal complementary to the control signal G of the switches M5 and M6.

[0060] In various embodiments, some or all of the current sources or current sinks in coupling units disclosed herein may be programmable. In some embodiments, some or all of the programmable current sources or programmable current sinks are implemented as metal-oxide- semiconductor transistors. In some embodiments, some or all of the programmable current sources or programmable current sinks are implemented as volatile or non-volatile memory devices, for example flash memory transistors or charge-trap transistors.

[0061] The non-diagonal CUs also include a memory element in the form of a latch (transistors M15-M18) and its access switches M19 and M20. The latch of each non-diagonal CU is accessed through the access switches during the CU programming phase by using the column control signal ^^, which connects the latch to the programming bit^^and its complement^^.Programming bits ^^ and ^^ are supplied by the programming unit ^ ^^. The latch holds thepolarity of the CU's coupling in the form of bit^^^and its complement that is used to control the 2-to-1 multiplexer (M9-M12). For example, if the polarity of the coupling coefficient ^^^is positive, the polarity bit^^^is programmed to logic 1 (orௗ^ௗ).

[0062] Finally the programming units 205 (^ ^^) are shown at the right of the diagram in Fig. 2.An example programming unit is shown Fig.6. The programming unit in this embodiment generates biasing voltages^^^^and^^^^by supplying programming current ^^^^^to the reference devices (or so-called diode-connected devices) M1 and M2 which establishes basing voltages at their gate. For example, during the programming of ^௧^column, the control signals ^^Attorney docket # 204606-0171-00WO 2-24010 and ^^are asserted connecting the gates of M1 and M2 in non-diagonal CUs to the reference devices M1 and M2 within the PU forming a current mirror. Assuming that the aspect ratio ofreference devices is k times larger (where ^ ≥ 1) with respect to the current source M1 andcurrent sink M2 within a CU, the established biasing voltages will ensure that the currents produced by the CU are a scaled version of ^^^^^achieving the programming operations. The two transistors M3 and M4 in the PU of Fig.6 are provided to match the switches M5 and M6 in the CU so that overall matching accuracy within the established current mirror is improved. The programming current sources ^^^^^in the PU may be generated by a digital-to-analog converter (DAC) (see Fig.6) such as a current-steering DAC, whose digital input is obtained from memory (e.g. SRAM or DRAM) through a memory interface. In addition to programming current magnitude ^^^of CUs through the reference-devices M1 and M2, ^^^^^, and DAC, each PU contains a register 601 to store the coupling coefficient polarity (e.g. ^^^(^^^) that is then supplied to the CUs through^^and^^and stored in the latches of the CUs (see transistors M15- M20 in Fig.5).

[0063] A diagram showing exemplary interconnections between a coupling unit (as shown in Fig.5) and a programming unit (as shown in Fig. D) is shown in Fig.7.

[0064] The disclosures of each and every patent, patent application, and publication cited herein are hereby incorporated herein by reference in their entirety. While this invention has been disclosed with reference to specific embodiments, it is apparent that other embodiments and variations of this invention may be devised by others skilled in the art without departing from the true spirit and scope of the invention. The appended claims are intended to be construed to include all such embodiments and equivalent variations. References

[0065] The following publications are incorporated herein by reference in their entireties.

[0066] C. Johnson, D. H. Allen, J. Brown, S. Vanderwiel, R. Hoover, H. Achilles, C.-Y. Cher, G. A. May, H. Franke, J. Xenedis et al., “A wire-speed power tm processor: 2.3 ghz 45nm soi with 16 cores and 64 threads,” in 2010 IEEE International Solid-State Circuits Conference- (ISSCC). IEEE, 2010, pp.104–105.Attorney docket # 204606-0171-00WO 2-24010

[0067] B. Erbagci, N. E. C. Akkaya, C. Teegarden, and K. Mai, “A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm,” in 2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, pp.1–4.

[0068] S. Song, W. Tang, T. Chen, and Z. Zhang, “LEIA: A 2.05mm2140mW lattice encryption instruction accelerator in 40nm CMOS,” in 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, pp.1–4.

[0069] H. Kaul, M. A. Anders, S. K. Mathew, G. Chen, S. K. Satpathy, S. K. Hsu, A. Agarwal, and R. K. Krishnamurthy, “14.4 a 21.5 m-query-vectors / s 3.37 nj / vector reconfigurable k- nearest-neighbor accelerator with adaptive precision in 14nm tri-gate cmos,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2016, pp.260–261.

[0070] P. I. Bunyk, E. M. Hoskinson, M. W. Johnson, E. Tolkacheva, F. Altomare, A. J. Berkley, R. Harris, J. P. Hilton, T. Lanting, A. J. Przybysz, and J. Whittaker, “Architectural Considerations in the Design of a Superconducting Quantum Annealing Processor,” IEEE Transactions on Applied Superconductivity, vol.24, no.4, pp.1–10, 2014.

[0071] T. Inagaki, Y. Haribara, K. Igarashi, T. Sonobe, S. Tamate, T. Honjo, A. Marandi, P. L. McMahon, T. Umeki, K. Enbutsu, O. Tadanaga, H. Takenouchi, K. Aihara, K.-i. Kawarabayashi, K. Inoue, S. Utsunomiya, and H. Takesue, “A coherent ising machine for 2000-node optimization problems,” Science, vol.354, no.6312, pp.603–606, 2016.

[0072] T. Wang and J. Roychowdhury, “OIM: Oscillator-Based Ising Machines for Solving Combinatorial Optimisation Problems,” 2019.

[0073] C. Roques-Carmes, Y. Shen, C. Zanoci, M. Prabhu, F. Atieh, L. Jing, T. Dubcˇek, C. Mao, M. R. Johnson, V. Cˇ eperic´, J. D. Joannopoulos, D. Englund, and M. Soljaˇci´c, “Heuristic recurrent algorithms for photonic Ising machines,” Nature Communications, vol.11, no.1, p.249, 2020.

[0074] “The D-Wave 2000Q Quantum Computer.” [Online]. Available: https: / / docs.dwavesys.com / docs / latest / c gs 4.htmlid1Attorney docket # 204606-0171-00WO 2-24010

[0075] R. Hamerly, T. Inagaki, P. L. McMahon, D. Venturelli, A. Marandi, T. Onodera, E. Ng, C. Langrock, K. Inaba, T. Honjo et al., “Experimental investigation of performance differences between coherent ising machines and a quantum annealer,” Science advances, vol.5, no.5, p. eaau0823, 2019.

[0076] R. Hamerly, T. Inagaki, P. L. McMahon, D. Venturelli, A. Marandi, T. Onodera, E. Ng, C. Langrock, K. Inaba et al., “Scaling advantages of all-to-all connectivity in physical annealers: the coherent ising machine vs. d-wave 2000q,” arXiv:arXiv:1807.00089, 2018.

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[0078] Y. Yamamoto, K. Aihara, T. Leleu, K.-i. Kawarabayashi, S. Kako, M. Fejer, K. Inoue, and H. Takesue, “Coherent ising machines—optical neural networks operating at the quantum limit,” npj Quantum Information, vol.3, no.1, p.49, 2017.

[0079] P. L. McMahon, A. Marandi, Y. Haribara, R. Hamerly, C. Langrock, S. Tamate, T. Inagaki, H. Takesue, S. Utsunomiya, K. Aihara, R. L. Byer, M. M. Fejer, H. Mabuchi, and Y. Yamamoto, “A fully programmable 100-spin coherent ising machine with all-to-all connections,” Science, vol.354, no.6312, pp.614–617, 2016.

[0080] K. Takata, A. Marandi, R. Hamerly, Y. Haribara, D. Maruo, S. Tamate, H. Sakaguchi, S. Utsunomiya, and Y. Yamamoto, “A 16-bit coherent ising machine for one-dimensional ring and cubic graph problems,” Scientific Reports, vol.6, no.1, p.34089, 2016.

[0081] F. Bohm, G. Verschaffelt, and G. Van der Sande, “A poor man’s coherent ising machine based on opto-electronic feedback systems for solving optimization problems,” Nature Communications, vol.10, no.1, p.3538, 2019. [Online]. Available: https: / / doi.org / 10.1038 / s41467-019-11484-3

[0082] Y. Takeda, S. Tamate, Y. Yamamoto, H. Takesue, T. Inagaki, and S. Utsunomiya, “Boltzmann sampling for an XY model using a non-degenerate optical parametric oscillator network,” Quantum Science and Technology, vol.3, no.1, p.014004, nov 2017.Attorney docket # 204606-0171-00WO 2-24010

[0083] R. Afoakwa, Y. Zhang, U. K. R. Vengalam, Z. Ignjatovic, and Michael, “Brim: Bistable resistively coupled ising machine,” 2021.

[0084] Y. Zhang, U. K. R. Vengalam, A. Sharma, M. Huang, and Z. Ignjatovic, “Qubrim: A cmos compatible resistively-coupled ising machine with quantized nodal interactions,” in 2022 IEEE / ACM International Conference On Computer Aided Design (ICCAD), 2022, pp.1–8.

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Claims

Attorney docket # 204606-0171-00WO 2-24010 CLAIMS What is claimed is:

1. A network comprising a plurality of coupled computation nodes and a plurality of active coupling units, each computation node comprising: an input configured to receive current from a subset of the plurality of coupling units in the network; an output configured to generate at least two discrete output voltages; a capacitor configured to store internal state as a voltage; a quantizer electrically connected to the capacitor, configured to quantize the voltage on the capacitor to one of at least two discrete values, the quantizer having an output connected to the output of the computation node; and wherein each active coupling unit comprises: an input receiving an output voltage from one of the plurality of computation nodes; an output connected to the input of one of the plurality of computation nodes; a programmable current source; a programmable current sink; and a control circuit configured to connect either the current source or the current sink to the output of the active coupling unit as a function of the voltage measured at the input of the active coupling unit.

2. The network of claim 1, wherein the quantizer in each computation node is a comparator configured to compare the voltage across the capacitor against a threshold and generate two discrete voltages at the output of the computation node depending on the result of the comparison operation.

3. The network of claim 1 or 2, where each of the quantizers are clocked by the same or essentially the same clock, configured to produce outputs at the same or essentially the same clock edge.Attorney docket # 204606-0171-00WO 2-24010 4. The network of any of claims 1-3, wherein the currents from current source or current sink in the active coupling unit are connected to a constant voltage source when not connected to the output of the active coupling unit.

5. The network of any of claims 1-4, wherein each active coupling unit further comprises a one-bit memory unit having a stored value, the stored value used to modulate the input to the active coupling unit.

6. The network of claim 5, wherein the stored value is a complement of the input to the active coupling unit.

7. The network of any of claims 1-6, wherein the programmable current source and the programmable current sink in at least one of the active coupling units are implemented as metal- oxide-semiconductor transistors.

8. The network of any of claims 1-7, wherein the programmable current source and the programmable current sink in at least one of the active coupling units are implemented as non- volatile memory devices selected from flash memory transistors or charge-trap transistors.

9. The network of any of claims 1-8, further comprising at least one programming unit configured to program the programmable current source and the programmable current sink.

10. The network of claim 9, wherein the programming unit comprises: at least one binary polarity output configured to provide a polarity value to at least one active coupling unit in the network; at least one magnitude output configured to provide a magnitude voltage value to bias either the current source or current sink or both in at least one active coupling unit in the network; a polarity memory element connected to the at least one binary polarity output, configured to store and provide the polarity value to the at least one binary polarity output;Attorney docket # 204606-0171-00WO 2-24010 an array of memory elements configured to store the magnitude voltage value as a set of binary values; a digital-to-analog converter connected to the array of memory elements and configured to produce the magnitude voltage value from the set of binary values; and a current mirroring element connected to the digital-to-analog converter and the magnitude output, configured to mirror a current emitted by the digital-to-analog converter to the magnitude output.

11. The network of claim 10, further comprising an inverted binary polarity output connected to an inverting output of the polarity memory element, and configured to provide a binary value having the opposite polarity of the at least one binary polarity output.

12. The network of any of claims 1-11, further comprising a current conveyor circuit having an input connected to the input of the computation node and an output connected to the capacitor, the current conveyor configured to hold its input at a constant voltage and mirror a current proportional to the current received at the input into the capacitor.

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