Electrical signal processing device
The processing device with integrated circuits and monolithic microwave circuits addresses the challenge of minimal phase and gain differences in radio direction finders, achieving low signal variations and a compact design.
Patent Information
- Application Number
- FR2022014534
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-12-27
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2042-12-27
AI Technical Summary
Existing radio direction finders with a large number of receivers face significant challenges in achieving minimal phase and gain differences between processed signals while maintaining a reduced footprint.
A processing device with M stages of integrated circuits connected between a first terminal and second terminals, where each stage includes sets of integrated circuits, minimizing phase and gain differences, and utilizing monolithic microwave integrated circuits with low bulk.
The device achieves low phase and gain differences between numerous second terminals while maintaining a small footprint, suitable for radiofrequency and microwave signals.
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Abstract
Description
Title of the invention: Electrical signal processing device
[0001] The present invention relates to an electrical signal processing device to be processed, the processing comprising a division of an electrical signal to be divided into divided electrical signals or a combination of electrical signals to be combined into a combined electrical signal, comprising:
[0002] - a support;
[0003] - a substrate at least partially covering the support;
[0004] - an electrical signal processing module, arranged on the substrate;
[0005] - a first terminal arranged on the substrate and connected to the processing module, the first terminal being capable of receiving an electrical signal to be processed by the processing module or of distributing an electrical signal processed by the processing module;
[0006] - N second terminals arranged on the substrate, N being an integer greater than or equal to 5, each second terminal being connected to the processing module and being capable of receiving an electrical signal to be processed by the processing module or of distributing an electrical signal processed by the processing module.
[0007] Such processing devices are for example used in a radio direction finder in association with a plurality of transmitters / receivers. In particular, in a radio direction finder, such a device makes it possible to combine the signals received by a plurality of receivers.
[0008] In order for the radiogoniometer to be able to accurately determine the direction of arrival of the received signals, it is necessary to calibrate its receivers. To do this, it is known to send to the receivers a calibration signal divided by the processing device and distributed to each of the receivers. In order for the calibration to be accurate, the phase difference and the gain difference generated by the processing device between each of the calibration signals received by the receivers must be as small as possible.
[0009] However, some radio direction finders have a large number of receivers, in particular greater than or equal to 5. The processing devices of the state of the art, with 5 inputs or outputs offering sufficient phase difference and gain difference performance, have a significant footprint.
[0010] An aim of the invention is to provide a processing device which makes it possible to obtain the smallest possible phase difference and gain difference between processed signals passing through numerous second terminals while having a reduced footprint.
[0011] To this end, the invention relates to a processing device comprising M stages for processing electrical signals successively connected between the first terminal and the second terminals, M being an integer greater than or equal to 2,
[0012] a first processing stage comprising a first integrated circuit for processing electrical signals arranged on the substrate and connected to the first terminal;
[0013] in which for K an integer between 2 and M, the K-th stage comprises at least one set of K-th integrated circuits for processing electrical signals arranged on the substrate, the K-th integrated circuits of each set respectively being connected to a respective Kl-th integrated circuit of the Kl-th stage,
[0014] each second terminal being connected to an M-th integrated circuit for processing electrical signals of the M-th stage.
[0015] The integrated signal processing circuits of each stage generate small phase and gain differences on the signals they process and have minimal bulk.
[0016] Consequently, the networking of these integrated circuits according to the claimed arrangement then makes it possible to obtain low phase and gain differences between the numerous second terminals and makes it possible to obtain a device having a small footprint.
[0017] According to particular embodiments, the processing device also comprises one or more of the following characteristics, taken in isolation or in any technically conceivable combination:
[0018] - the support has a support surface on which the substrate, the module of treatment, the first terminal and the second terminals extend, the support surface having:
[0019] - a central portion opposite which the integrated circuits of the M stages of electrical signal processing are grouped together;
[0020] - an annular portion centered on the central portion, opposite which the first terminal and the second terminals are arranged, the first and second terminals being uniformly angularly distributed around the central portion;
[0021] - the central portion of the surface of the support has:
[0022] - a central position on which the first integrated circuit is arranged;
[0023] - Ml concentric circles centered on the central position;
[0024] in which when M is greater than or equal to 3:
[0025] - for P an integer between 1 and M-2, the radius of the P+l-th circle is greater to the radius of the P-th concentric circle;
[0026] - for L an integer between 1 and Ml, the L+l-th integrated circuits of the The L+l-th processing stage are arranged substantially on the L-th concentric circle;
[0027] - the electrical signals are radiofrequency signals, in particular hy perfrequency, microwave signals preferably having a frequency between 2 MHz and 8 GHz;
[0028] - integrated circuits are monolithic microwave integrated circuits configured to split or combine electrical signals;
[0029] - the device comprises a plurality of electrical signal transmission lines etched on the substrate, each line extending between a first electronic element and a second electronic element,
[0030] the first electronic element being an integrated circuit,
[0031] the second electronic element being another integrated circuit, the first terminal or a second terminal,
[0032] each transmission line having a length measured between the first and second electronic elements of between 0.1 mm and 10 cm;
[0033] - each transmission line has a width between 0.1 mm and 10.0 mm ;
[0034] - each transmission line has a thickness between 1 pm and 1 mm;
[0035] - the substrate has a thickness of between 0.1 mm and 10.0 mm; and
[0036] - the substrate is made of a material having a relative permittivity of between 1.1 and 10.0, preferably substantially equal to 3.7.
[0037] Other aspects and advantages of the invention will appear on reading the following description, given by way of example and with reference to the appended drawings, in which:
[0038] [Fig-1] [Fig.l] is a simplified schematic representation of an example of treatment device according to the invention;
[0039] [Fig.2] [Fig.2] is an example of an embodiment of the device for processing the [Fig.l];
[0040] [Fig.3] [Fig.3] is a simplified schematic representation in side view of a portion of the processing device of [Fig.2];
[0041] [Fig.4] [Fig.4] is a simplified schematic representation in top view of the portion of the processing device of [Fig.3].
[0042] With reference to Figures 1 to 4, a device 10 for processing electrical signals to be processed is described.
[0043] By processing is meant the division of an electrical signal to be divided into divided electrical signals or a combination of electrical signals to be combined into a combined electrical signal.
[0044] By division of an electrical signal is meant the reproduction of an electrical signal to be reproduced into reproduced electrical signals, having characteristics substantially identical to the electrical signal to be reproduced.
[0045] In particular, the reproduced signals are identical in frequency and phase to the signal to be reproduced but have a lower level (in other words a lower power).
[0046] By combination of an electrical signal is meant the combination of electrical signals to be combined into a combined electrical signal, having characteristics substantially identical to the electrical signals to be combined.
[0047] In particular, the combined signal is identical in frequency and phase to the signals to be combined but has a higher level (in other words a higher power).
[0048] The electrical signals are, for example, radiofrequency signals, in particular microwave signals. The microwave signals preferably have a frequency of between 2 MHz and 8 GHz.
[0049] The processing device 10 comprises a support 20, a substrate 40 covering the support 20, a first terminal 50, N second terminals 52 and a module 60 for processing electrical signals.
[0050] Advantageously, the processing device 10 further comprises lines 80 for transmitting electrical signals.
[0051] The support 20 is for example a ROGERS RO4350™ plate extending substantially along a plane P substantially orthogonal to a direction D and having a thickness E1 measured along the direction D, between 25 pm and 1 cm.
[0052] Advantageously, the support 20 is made of a dielectric type material.
[0053] For example, the support 20 has a disc shape.
[0054] The support 20 has a support surface 22 on which the substrate 40, the processing module 60, the first terminal 50, the second terminals 52 and the transmission lines 80 extend.
[0055] The support surface 22 has a surface area of between 2 cm2 and 200 cm2. According to the example illustrated in Figures 1 and 2, the surface area of the support 22 has a surface area of less than 4 cm2.
[0056] With reference to [Fig.2], the support surface 22 has a central portion 24 opposite which integrated circuits 64 of M processing stages 62 of the processing module 60 are grouped.
[0057] The support surface 22 further has an annular portion 26 centered on the central portion 24, opposite which the first terminal 50 and the second terminals 52 are arranged.
[0058] The central portion 24 of the surface of the support 22 has:
[0059] - a central position 28 on which a first integrated circuit 64 is arranged; and
[0060] - Ml concentric circles 30 centered on the central position.
[0061] When M is greater than or equal to 3:
[0062] - for P an integer between 1 and M-2, the radius of the P+1-th concentric circle 30 is greater than the radius of the P-th concentric circle 30;
[0063] - for L an integer between 1 and Ml, L+l-th integrated circuits of a The l+1-th processing stage 62 of the processing module 60 are arranged sen- possibly on the L-th concentric circle 30.
[0064] The substrate 40 at least partially covers the support 20, in particular the support surface 22.
[0065] Advantageously, with reference to [Fig. 3], the substrate 40 has a thickness E2, measured along the direction D, of between 0.1 mm and 10.0 mm.
[0066] Also advantageously, the substrate 40 is made of a material having a relative permittivity of between 1.1 and 10.0. The relative permittivity of the substrate is for example substantially equal to 3.7.
[0067] Still advantageously, the substrate 40 is made of a material comprising epoxy resin and glass fibers.
[0068] The first terminal 50 is arranged on the substrate 40 and is connected to the processing module 60.
[0069] The first terminal 50 is capable of receiving an electrical signal to be processed by the processing module 60 or of distributing an electrical signal processed by the processing module 60.
[0070] As illustrated in the example of [Fig.2], the first terminal 50 is arranged opposite the annular portion 26 of the surface of the support 22.
[0071] The N second terminals 52 are arranged on the substrate 40.
[0072] Each second terminal 52 is connected to the processing module 60 and is capable of receiving an electrical signal to be processed by the processing module 60 or of distributing an electrical signal processed by the processing module 60.
[0073] N is an integer greater than or equal to 5.
[0074] According to the example illustrated in Figures 1 and 2, N is equal to 5.
[0075] Each second terminal 52 is connected to an M-th integrated circuit 64 of processing of electrical signals of an M-th stage of processing 62 of electrical signals belonging to the module 60 of processing of electrical signals.
[0076] As illustrated in the example of [Fig.2], the second terminals 52 are arranged opposite the annular portion 26 of the surface of the support 22.
[0077] Still with reference to the example of [Fig.2], the second terminals 52 as well as the first terminal 50 are distributed uniformly angularly around the central portion 28 of the surface of the support 22.
[0078] The electrical signal processing module 60 is arranged on the substrate 40.
[0079] The processing module 60 comprises M signal processing stages 62 electrical successively connected between the first terminal 50 and the second terminals 52.
[0080] M is an integer greater than or equal to 2.
[0081] According to the example illustrated in Figures 1 and 2, M is equal to 2.
[0082] A first processing stage 62, 62A comprises a first integrated circuit 64A of electrical signal processing arranged on the substrate 40 and connected to the first terminal 50.
[0083] For K an integer between 2 and M, the K-th stage 62 comprises at least one set 66 of K-th integrated circuits 64 for processing electrical signals arranged on the substrate 40.
[0084] The K-th integrated circuits 64 of each set 66 are connected to a respective Kl-th integrated circuit 64 of the Kl-th stage 62.
[0085] According to the example illustrated in Figures 1 and 2, the second stage 62B comprises a single set 66 of second integrated circuits 64B for processing electrical signals.
[0086] The second integrated circuits 64B of the single set 66 of the second stage 62B are connected to the integrated circuit 64A of the first stage 62A.
[0087] Still according to the example illustrated in Figures 1 and 2, at least one second integrated circuit 64B, generally an M-th integrated circuit 64, is connected to ground via a resistor, in particular a 50 ohm resistor.
[0088] Advantageously, the integrated circuits 64 for processing electrical signals are monolithic microwave integrated circuits configured to divide or combine electrical signals, in particular microwave signals.
[0089] In particular, the microwave monolithic integrated circuits have signal processing circuits of the resistive type and / or of the Wilkinson type. In addition, the microwave monolithic integrated circuits used have low phase and gain differences between channels in the targeted frequency band.
[0090] Each integrated circuit 64 for processing electrical signals comprises a first point 70 for connection to an integrated circuit 64 of a lower stage 62 or to the first terminal 50 and a plurality of second points 72 for connection to integrated circuits 64 of a higher stage 62 or to second terminals 52.
[0091] In the example of Figures 1 and 2, the first integrated circuit 64A of the first processing stage 62A comprises four second connection points 72 to the integrated circuits 64B of the second stage 62B and a first connection point 70 to the first terminal 50.
[0092] Still using the example of Figures 1 and 2, the second integrated circuits 64B of the second processing stage 62B each comprise a first connection point 70 to the first integrated circuit 64A of the first stage 62A and two second connection points 72 to a second terminal 52 or to ground via a resistor.
[0093] Each integrated circuit 64 comprises at most four second connection points 72.
[0094] Each integrated circuit 64 is such that the electrical signals passing through its seconds 72 connection points present:
[0095] - a phase difference of less than 5° when the electrical signals present a frequency between 2 MHz and 5 GHz;
[0096] - a phase difference of less than 10° when the electrical signals present a frequency between 5 GHz and 8 GHz; and
[0097] - a gain difference of less than 0.4 dB.
[0098] In particular, each monolithic microwave integrated circuit has a surface area projected onto the plane P less than or equal to 9 mm2.
[0099] With reference to Figures 1 to 4, the electrical signal transmission lines 80 are etched on the substrate 40 and each line 80 extends between a first electronic element 82 and a second electronic element 84.
[0100] With reference to Figures 3 and 4, each transmission line 80 has a length L measured between the first 82 and second 84 electronic elements of between 0.1 mm and 10 cm.
[0101] With reference to [Fig.4], each transmission line 80 has a width W of between 0.1 mm and 10.0 mm.
[0102] With reference to [Fig.3], each transmission line 80 has a thickness H of between 1 pm and 1 mm.
[0103] The first electronic element 82 is an integrated circuit 64 and the second electronic element 84 is another integrated circuit 64, the first terminal 50 or a second terminal 52.
[0104] In the following, a particular example is described in which the processing device 10 is a device for dividing an electrical signal to be divided.
[0105] The processing module 60 is then a division module configured to divide the electrical signal to be divided into divided electrical signals.
[0106] The first terminal 50 is intended to receive the electrical signal to be divided.
[0107] Each second terminal 52 is intended to distribute a divided electrical signal.
[0108] The division module comprises M signal division stages 62.
[0109] The first division stage 62 comprises a first division integrated circuit 64 electrical signal configured to divide the electrical signal to be divided received by the first terminal 50 into divided electrical signals.
[0110] For K an integer between 2 and Ml, each of the K-th division integrated circuits 64 of the K-th stage 62 are configured to divide an electrical signal to be divided received from a Kl-th division integrated circuit 64 of the Kl-th stage 62 into divided electrical signals.
[0111] Each M-th division integrated circuit 64 of the M-th stage 62 being configured to divide an electrical signal to be divided received from an integrated circuit 64 of the M-1-th stage 62 into divided electrical signals and transmit one of said divided electrical signals to at least one second terminal 52.
[0112] In the following, a particular example is described in which the device of processing 10 is a device for combining electrical signals to be combined.
[0113] The processing module 60 is then a combination module configured to combine the electrical signals to be combined into a combined electrical signal.
[0114] The first terminal 50 is intended to distribute the combined electrical signal.
[0115] Each second terminal 52 is intended to receive an electrical signal to be combined.
[0116] The combination module 60 comprises M stages 62 of signal combination.
[0117] Each M-th combining integrated circuit 64 of the M-th stage being configured to combine electrical signals to be combined received from at least a second terminal 52 into a combined electrical signal.
[0118] For K an integer between 2 and Ml, each of the K-th integrated circuits 64 of the K-th stage 62 being configured to combine electrical signals to be combined received from respectively K+l-th combining integrated circuits 64 of the K+l-th stage 62 into a combined electrical signal.
[0119] The first combining integrated circuit 64 of the first combining stage 62 is configured to combine electrical signals to be combined received from at least one second combining integrated circuit 64 of the second stage 62 into a combined electrical signal and transmit said combined electrical signal to the first terminal 50.
[0120] Thanks to the invention, it is possible to obtain an electrical signal processing device such that the electrical signals passing through a large number of second terminals have:
[0121] - a phase difference of less than 5° when the electrical signals present a frequency between 2 MHz and 5 GHz;
[0122] - a phase difference of less than 10° when the electrical signals present a frequency between 5 GHz and 8 GHz; and
[0123] - a gain difference of less than 0.4 dB;
[0124] for electrical signals with power up to 27 dBm.
[0125] The invention also makes it possible to obtain these advantageous characteristics while limiting the size of the device. Indeed, the surface of the support 22 has a surface area of less than 4 cm2, which is much smaller than that of the devices of the state of the art.
Claims
Claims
1. Device (10) for processing electrical signals to be processed, the processing comprising a division of an electrical signal to be divided into divided electrical signals or a combination of electrical signals to be combined into a combined electrical signal, comprising: - a support (20); - a substrate (40) at least partially covering the support (20); - an electrical signal processing module (60), arranged on the substrate (40); - a first terminal (50) arranged on the substrate (40) and connected to the processing module (60), the first terminal (50) being capable of receiving an electrical signal to be processed by the processing module (60) or of distributing an electrical signal processed by the processing module (60); - N second terminals (52) arranged on the substrate (40), N being an integer greater than or equal to 5, each second terminal (52) being connected to the processing module (60) and being capable of receiving an electrical signal to be processed by the processing module (60) or of distributing an electrical signal processed by the processing module (60); characterized in that the processing module (60) comprises M stages (62) for processing electrical signals successively connected between the first terminal (50) and the second terminals (52), M being an integer greater than or equal to 2, a first processing stage (62) comprising a first integrated circuit (64) for processing electrical signals arranged on the substrate (40) and connected to the first terminal (50); in which for K an integer between 2 and M, the K-th stage (62) comprises at least one set (66) of K-th integrated circuits (64) for processing electrical signals arranged on the substrate (40), the K-th integrated circuits (64) of respectively each set (66) being connected to a respective Kl-th integrated circuit (64) of the Kl-th stage (62), each second terminal (52) being connected to an M-th integrated circuit (64) for processing electrical signals of the M-th stage (62), the support (20) having a support surface (22) on which the substrate (40), the processing module (60), the first terminal (50) and the second terminals (52) extend, the support surface (22) having: - a central portion (24) opposite which the integrated circuits (64) M stages (62) for processing electrical signals are grouped; - an annular portion (26) centered on the central portion (24), opposite which the first terminal (50) and the second terminals (52) are arranged, the first (50) and second (52) terminals being uniformly distributed angularly around the central portion (24); the central portion (24) of the surface of the support (22) having: - a central position (28) on which the first integrated circuit (64) is arranged; - Ml concentric circles (30) centered on the central position (28); wherein when M is greater than or equal to 3: - for P an integer between 1 and M-2, the radius of the P+l-th circle (30) is greater than the radius of the P-th concentric circle (30); - for L an integer between 1 and Ml, the L+l-th integrated circuits (64) of the L+l-th processing stage (62) are arranged substantially on the L-th concentric circle (30).
2. Device (10) according to claim 1, in which the electrical signals are radiofrequency signals, in particular microwave signals, the microwave signals preferably having a frequency between 2 MHz and 8 GHz.
3. The device (10) of claim 1 or 2, wherein the integrated circuits (64) are monolithic microwave integrated circuits configured to divide or combine electrical signals.
4. Device (10) according to any one of the preceding claims, further comprising a plurality of electrical signal transmission lines (80) etched on the substrate (40), each line (80) extending between a first electronic element (82) and a second electronic element (84), the first electronic element (82) being an integrated circuit (64), the second electronic element (84) being another integrated circuit (64), the first terminal (50) or a second terminal (52), each transmission line (80) having a length (L) measured between the first (82) and second (84) electronic elements of between 0.1 mm and 10 cm.
5. A device (10) according to claim 4, wherein each transmission line (80) has a width (W) of between 0.1 mm and 10.0 mm.
6. Device (10) according to claim 4 or 5, in which each transmission line (80) has a thickness (H) of between 1 pm and 1mm.
7. Device (10) according to any one of the preceding claims, wherein the substrate (40) has a thickness (E2) of between 0.1 mm and 10.0 mm.
8. Device (10) according to any one of the preceding claims, in which the substrate (40) is made of a material having a relative permittivity of between 1.1 and 10.0, preferably substantially equal to 3.7.