Pixel circuit, display panel, and display device

Abstract

Disclosed are a pixel circuit, a display panel, and a display device. The display device comprises a timing control circuit (110), a gate driving circuit (20), and multiple voltage signal lines (50). The timing control circuit (110) is connected to the multiple voltage signal lines (50), and is configured to: when load information of the gate driving circuit (110) changes, determine an enable signal and a first signal, and on the basis of the enable signal and the first signal, regulate the voltage of at least one voltage signal line among the multiple voltage signal lines (50). The gate driving circuit (110) comprises multiple cascaded shift register units (10) respectively connected to the multiple voltage signal lines (50), and is configured to output a gate scanning signal. The width of voltage regulation is determined on the basis of the pulse width of the first signal, and the starting position of the voltage regulation is determined on the basis of the enable signal. The method can reduce the influence of a sudden load change of the gate driving circuit (110) on an output waveform, thereby improving the uniformity of picture display, eliminating the brightness difference, and optimizing the display effect.

Description

Pixel circuit, display panel, and display device Technical Field

[0001] Embodiments of the present disclosure relate to a pixel circuit, a display panel, and a display device. Background Art

[0002] In the field of display technology, for example, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel generally includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines. The driving of the gate lines can be achieved by a bound integrated drive circuit. In recent years, with the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line drive circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA including multiple cascaded shift register units can be used to provide switching state voltage signals (scanning signals) for multiple rows of gate lines of a pixel array, so as to control multiple rows of gate lines to open in sequence, and at the same time, the data line provides a data signal to the pixel units of the corresponding rows in the pixel array, so as to form the grayscale voltage required for each grayscale of the displayed image in each pixel unit, thereby displaying a frame of image.

[0003] The pixel circuits in OLED display panels generally use a matrix drive method, which is divided into active matrix (AM) and passive matrix (PM) drive, depending on whether switching components are introduced into each pixel unit. Although PMOLED has a simple process and low cost, it cannot meet the needs of high-resolution, large-size displays due to shortcomings such as crosstalk, high power consumption, and short lifespan. In contrast, AMOLED integrates a set of thin-film transistors and storage capacitors in the pixel circuit of each pixel. By controlling the drive of the thin-film transistors and storage capacitors, the current flowing through the OLED is controlled, allowing the OLED to emit light as needed. Compared with PMOLED, AMOLED requires less driving current, consumes less power, and has a longer lifespan, which can meet the needs of high-resolution, multi-grayscale, large-size displays. At the same time, AMOLED has significant advantages in viewing angle, color reproduction, power consumption, and response time, making it suitable for high-information, high-resolution display devices.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a display device, comprising a timing control circuit, a gate drive circuit, and a plurality of voltage signal lines; the timing control circuit is connected to the plurality of voltage signal lines and is configured to determine an enable signal and a first signal when load information of the gate drive circuit changes, and to adjust the voltage of at least one voltage line among the plurality of voltage signal lines based on the enable signal and the first signal; the gate drive circuit comprises a plurality of cascaded shift register units, which are respectively connected to the plurality of voltage signal lines and are configured to output gate scan signals row by row; the width of the voltage adjustment is determined based on the pulse width of the first signal, and the starting position of the voltage adjustment is determined based on the enable signal.

[0006] For example, in the display device provided in at least one embodiment of the present disclosure, the multiple voltage signal lines include a first voltage signal line and a second voltage signal line, which are configured to provide a first voltage VGH and a second voltage VGL to the multiple shift register units; in the display stage, the voltage adjustment includes adjusting the first voltage VGH to VGH+ΔV111 or adjusting the second voltage VGL to VGL-ΔV211 when the enable signal drops, wherein the widths of the ΔV111 and ΔV211 are the same as the pulse width of the first signal.

[0007] For example, in the display device provided by at least one embodiment of the present disclosure, in the blanking stage, the voltage adjustment includes adjusting the first voltage VGH to VGH-ΔV12 or adjusting the second voltage VGL to VGL-ΔV22 in response to the rising edge of the enable signal, wherein the widths of ΔV12 and ΔV22 are the same as the pulse width of the first signal.

[0008] For example, in the display device provided in at least one embodiment of the present disclosure, the multiple voltage signal lines include a first voltage signal line and a second voltage signal line, which are configured to provide a first voltage VGH and a second voltage VGL to the multiple shift register units; the voltage adjustment includes adjusting the first voltage VGH to VGH-ΔV112 and adjusting the second voltage VGL to VGL-ΔV212 when the enable signal drops, wherein the width of the ΔV112 is the same as the pulse width of the first signal, the width of the ΔV212 is smaller than the pulse width of the first signal, and the amplitudes of the ΔV112 and ΔV212 are respectively smaller than the amplitudes of the ΔV111 and ΔV211.

[0009] For example, in the display device provided by at least one embodiment of the present disclosure, the first voltage is greater than the second voltage.

[0010] For example, the display device provided by at least one embodiment of the present disclosure also includes a pixel circuit arranged in an array, wherein the multiple voltage signal lines include a first scan line and a first reset line, the first scan line is connected to the data write circuit of the pixel circuit to send the first scan signal received from the first scan line to the control end of the data write circuit; the first reset line is connected to the control end of the first reset circuit of the pixel circuit to provide a first reset signal, wherein the first reset circuit is turned on in response to the first reset signal; the multiple voltage signal lines also include a first reset voltage line, connected to the first reset circuit to provide a first reset voltage VINIT1; the timing control circuit is further configured to determine a first phase difference based on the first scan signal and the first reset signal; the voltage adjustment also includes adjusting the first reset voltage VINIT1 to VINIT1+ΔV31 at the position of the first phase difference from the falling edge of the enable signal when the enable signal falls, wherein the width of the ΔV31 is the same as the pulse width of the first signal.

[0011] For example, the display device provided by at least one embodiment of the present disclosure also includes a pixel circuit arranged in an array, wherein the multiple voltage signal lines include a first scan line, and the first scan line is connected to the data writing circuit of the pixel circuit to send a first scan signal to the control end of the data writing circuit, and the voltage adjustment includes adjusting the first level VGL_P in the gate driving circuit that outputs the first scan signal to VGL_P+ΔV51 when the enable signal drops to adjust the first scan signal, wherein the width of the ΔV51 is the same as the pulse width of the first signal.

[0012] For example, in the display device provided in at least one embodiment of the present disclosure, the multiple voltage signal lines include multiple clock signal lines, which are configured to provide multiple clock signals to the gate drive circuit that outputs the first scanning signal, and the voltage adjustment includes adjusting the first level V0 of the multiple clock signals to V0-ΔV61 when the enable signal drops to adjust the first scanning signal, wherein the number of voltage-adjusted clock signals is determined according to the pulse width of the first signal.

[0013] For example, in the display device provided by at least one embodiment of the present disclosure, the multiple voltage signal lines also include a second scan line and a second reset line, the second scan line is connected to the threshold compensation circuit of the pixel circuit to send a second scan signal to the control end of the threshold compensation circuit; the second reset line is connected to the second reset circuit of the pixel circuit to provide a second reset signal, wherein the second reset circuit is turned on in response to the second reset signal; the multiple voltage signal lines also include a second reset voltage line, connected to the second reset circuit to provide a second reset voltage VINIT2; the timing control circuit is also configured to determine a second phase difference based on the second scan signal and the second reset signal; the voltage regulation also includes adjusting the second reset voltage VINIT2 to VINIT2+ΔV32 at the position of the second phase difference from the falling edge of the enable signal when the enable signal falls, wherein the width of the ΔV32 is the same as the pulse width of the first signal.

[0014] For example, in the display device provided by at least one embodiment of the present disclosure, the multiple voltage signal lines also include a data line, which is connected to the digital write circuit of the pixel circuit and is configured to provide a data signal Vdt to the digital write circuit; the timing control circuit is also configured to determine a third phase difference based on the first scanning signal and the second scanning signal; the voltage adjustment also includes adjusting the first level of the data signal Vdt to Vdt+ΔV41 at the position of the third phase difference from the falling edge of the enable signal when the enable signal falls, wherein the width of the ΔV41 is the same as the pulse width of the first signal.

[0015] For example, in the display device provided in at least one embodiment of the present disclosure, the plurality of voltage signal lines further include a trigger signal line configured to provide a trigger signal to the gate drive circuit; and the first signal is a trigger signal.

[0016] At least one embodiment of the present disclosure further provides a pixel circuit, comprising: a driving circuit, a data writing circuit, a threshold compensation circuit, a storage circuit, a first light-emitting control circuit, and a first reset circuit; the driving circuit comprises a control terminal, a first terminal, and a second terminal, and is configured to control a driving current flowing through a light-emitting element; the data writing circuit is connected to the first terminal of the driving circuit, and is configured to write a data signal to the first terminal of the driving circuit in response to a first scan signal; the threshold compensation circuit is connected between the control terminal of the driving circuit and the second terminal of the driving circuit, and is configured to write a compensation signal based on the data signal to the control terminal of the driving circuit in response to a second scan signal; the storage circuit is connected to the control terminal of the driving circuit and a first voltage line, and is configured to store the compensation signal and keep the compensation signal at the control terminal of the driving circuit; the first light-emitting control circuit The gate drive circuit includes a first reset circuit and a threshold compensation circuit, and a first reset voltage circuit. The first reset circuit is connected to the threshold compensation circuit and is configured to apply a first reset voltage to the control end of the drive circuit in response to the first reset signal. The control end of the drive circuit is connected to the storage circuit at a first node, and the first light-emitting control circuit is connected to the first end of the drive circuit at a second node. The voltage of the first scan signal, the second scan signal, the data signal or the first reset voltage is configured to be adjusted based on the enable signal and the first signal determined when the load information of the gate drive circuit changes, wherein the width of the voltage adjustment is determined based on the pulse width of the first signal, and the starting position of the voltage adjustment is determined based on the enable signal.

[0017] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the voltage adjustment includes adjusting the first reset voltage VINIT1 to VINIT1+ΔV31 at a position of a first phase difference from the falling edge of the enable signal when the enable signal falls, wherein the width of the ΔV31 is the same as the pulse width of the first signal.

[0018] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the first phase difference is determined based on the first scanning signal and the first reset signal.

[0019] For example, in the pixel circuit provided in at least one embodiment of the present disclosure, the voltage adjustment includes adjusting the first level VGL_P of the first scanning signal to VGL_P-ΔV51 when the enable signal drops, wherein the width of ΔV51 is the same as the pulse width of the first signal.

[0020] For example, in the pixel circuit provided in at least one embodiment of the present disclosure, the pixel circuit also includes a second light-emitting control circuit and a second reset circuit; the second light-emitting control circuit is connected to the second end of the driving circuit and the light-emitting element, and is configured to apply the voltage of the second end of the driving circuit to the light-emitting element in response to a second light-emitting control signal; the second reset circuit is connected to the second light-emitting control circuit and the light-emitting element, and is configured to apply a second reset voltage to the light-emitting element in response to a second reset signal; the second light-emitting control circuit and the second end of the driving circuit are connected to a third node, and the second reset circuit and the second light-emitting control circuit and the light-emitting element are connected to a fourth node; the voltage regulation also includes adjusting the second reset voltage based on the enable signal and the first signal.

[0021] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the voltage adjustment includes adjusting the second reset voltage VINIT2 to VINIT2+ΔV32 at a second phase difference from the falling edge of the enable signal when the enable signal falls, wherein the width of the ΔV32 is the same as the pulse width of the first signal.

[0022] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the second phase difference is determined based on the second scanning signal and the second reset signal.

[0023] For example, in the pixel circuit provided in at least one embodiment of the present disclosure, the voltage regulation also includes adjusting the first level of the data signal Vdt to Vdt+ΔV41 at a position of a third phase difference from the falling edge of the enable signal when the enable signal falls, wherein the width of the ΔV41 is the same as the pulse width of the first signal.

[0024] For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the third phase difference is determined based on the first scanning signal and the second scanning signal.

[0025] At least one embodiment of the present disclosure further provides a display panel comprising a plurality of pixel units; each pixel unit comprises the pixel circuit provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0027] FIG1 is a schematic diagram of a shift register unit provided by at least one embodiment of the present disclosure;

[0028] FIG2 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure;

[0029] FIG3 is a flow chart of a voltage regulation method provided by at least one embodiment of the present disclosure;

[0030] FIG4A is a schematic diagram of regulating a second voltage during a display phase according to at least one embodiment of the present disclosure;

[0031] FIG4B is a schematic diagram of regulating the second voltage during the blanking phase according to at least one embodiment of the present disclosure;

[0032] FIG5 is a schematic diagram of regulating a first voltage according to at least one embodiment of the present disclosure;

[0033] FIG6 is a schematic diagram of voltage regulation of a clock signal provided by some embodiments of the present disclosure;

[0034] FIG7 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

[0035] FIG8 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG7 ;

[0036] FIG9 is a timing diagram for the pixel circuit shown in FIG8 provided in some embodiments of the present disclosure;

[0037] FIG10 is a schematic diagram of regulating the voltage of the first reset voltage VINIT1 according to at least one embodiment of the present disclosure;

[0038] FIG11 is a schematic diagram of regulating the second reset voltage VINIT2 according to at least one embodiment of the present disclosure;

[0039] FIG12 is a schematic diagram of voltage regulation of a data signal according to at least one embodiment of the present disclosure;

[0040] FIG13 is a schematic diagram of voltage regulation of a first scan signal S3 according to at least one embodiment of the present disclosure;

[0041] FIG14 is a schematic diagram of combining and adjusting a first voltage and a second voltage according to some embodiments of the present disclosure;

[0042] FIG15 is a schematic block diagram of a display panel provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0045] As AMOLED applications expand and specifications increase, the display area (e.g., the AA (Active Area)) of AMOLED displays is expanding, while the bezels are shrinking. The gate driver circuit, which controls pixel operation and influences key nodes within the pixel, is experiencing a decreasing layout area (and increasing internal resistance). Simultaneously, the increased width of the AA area and higher pixel density (Pixels Per Inch, PPI) increase the number of gate driver circuit signals and the number of nodes within the pixel, leading to an increase in parasitic capacitance between individual pixels and the gate driver circuit signal.

[0046] For gate driver circuits that output waveforms using a combined power supply voltage (VGH / VGL), such as the gate driver circuit composed of 13T3C shift register units shown in Figure 1, there are significant differences in the actual output current between load-delivered and non-load-delivered operating states (such as when the gate driver circuit output is manually paused or in a blank region). These differences lead to differences in the power supply voltage, such as a shift in the reference voltage or differences in the shape of the periodic waveform. These differences directly affect the pixel node transitions and the switching transconductance of the associated transistors.

[0047] Since the output waveform width of this type of gate drive circuit is relatively wide, when the load of a certain row of gate drive circuits suddenly changes, the voltages of the gate drive circuit waveforms of several rows before and after it are affected, resulting in brightness differences in the AA areas before and after the load change row, forming bright bands or dark bands, affecting the display quality.

[0048] At least one embodiment of the present disclosure provides a display device, including a timing control circuit (IC), a gate drive circuit and multiple voltage signal lines; the timing control circuit is connected to the multiple voltage signal lines and is configured to determine an enable signal and a first signal when load information of the gate drive circuit changes, and adjust the voltages of the multiple voltage signal lines based on the enable signal and the first signal; the gate drive circuit includes multiple cascaded shift register units, which are respectively connected to the multiple voltage signal lines and are configured to output gate scan signals row by row; the width of the voltage adjustment is determined based on the pulse width of the first signal, and the starting position of the voltage adjustment is determined based on the enable signal.

[0049] The display device provided by the above-mentioned embodiments of the present disclosure adjusts the waveform of the voltage signal input to the gate drive circuit before and after the load of the gate drive circuit changes, realizes the voltage change during the load change period, corrects the impact of the sudden load change of the gate drive circuit on the output waveform, makes the output of the gate drive circuit during this period consistent with the output of other gate drive circuits, improves the uniformity of the picture display, eliminates the brightness difference, optimizes the display effect, and improves the display quality.

[0050] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements described above.

[0051] Figure 1 is a schematic diagram of a shift register unit provided in at least one embodiment of the present disclosure; Figure 2 is a schematic diagram of a display device provided in at least one embodiment of the present disclosure; Figure 3 is a flowchart of a voltage regulation provided in at least one embodiment of the present disclosure; Figure 4A is a schematic diagram of a method of regulating the second voltage in the display phase provided in at least one embodiment of the present disclosure; Figure 4B is a schematic diagram of a method of regulating the second voltage in the blanking phase provided in at least one embodiment of the present disclosure; Figure 5 is a schematic diagram of a method of regulating the first voltage provided in at least one embodiment of the present disclosure.

[0052] An embodiment of the present disclosure provides a display device 1. As shown in FIG2 , the display device 1 includes a timing control circuit 110, a gate drive circuit 20, a plurality of voltage signal lines 50, and a plurality of pixel units 410 arranged in an array. For example, the display device 1 also includes a display panel 40, in which a pixel array composed of the plurality of pixel units 410 is disposed.

[0053] The gate drive circuit 20 includes a shift register unit 10 (as shown in FIG. 1 , but not limited to the shift register unit 10 shown in FIG. 1 ) that outputs a gate scan signal, which is provided to the pixel unit 410. For example, the gate drive circuit 20 is electrically connected to the pixel unit 410 via a gate line GL (for example, as shown in FIG. 8 , the gate line GL includes a first scan line S3 and a second scan line S4). The gate drive circuit 20 is configured to provide a drive signal to the pixel array. For example, the drive signal can drive a scan transistor and a reset transistor in the pixel unit 410.

[0054] For example, the display device 1 may further include a data driving circuit 30, which is configured to provide data signals to the pixel array. For example, the data driving circuit 30 is electrically connected to the pixel unit 410 via a data line DL.

[0055] It should be noted that the display device 1 in this embodiment can be any product or component with display function, such as: LCD panel, LCD TV, monitor, OLED panel, OLED TV, electronic paper display device, mobile phone, tablet computer, laptop computer, digital photo frame, navigator, etc.

[0056] For example, the timing control circuit 110 is connected to the plurality of voltage signal lines 50 and is configured to determine the enable signal EN and the first signal when the load information of the gate driving circuit 20 changes, and adjust the voltages of the plurality of voltage signal lines 50 based on the enable signal and the first signal.

[0057] For example, as shown in conjunction with Figures 1 and 2 , the plurality of voltage signal lines 50 further include a trigger signal line STV configured to provide a trigger signal to the shift register unit. The first signal can be a trigger signal or an output signal of the shift register unit. The first signal is used to ensure that the pulse width of the voltage regulation is the same as the pulse width of the output signal. Therefore, as long as the pulse width of the voltage signal and the pulse width of the output signal can be made equal, the embodiments of the present disclosure are not limited thereto. The following description uses the first signal as a trigger signal as an example.

[0058] For example, the gate driving circuit 20 includes a plurality of cascaded shift register units 10 , each of which is connected to a plurality of voltage signal lines 50 , and is configured to output gate scanning signals row by row.

[0059] For example, the shift register unit can be the shift register unit 10 shown in Figure 1, or it can be other shift register units in the art, and the embodiments of the present disclosure are not limited to this. The shift register unit 10 shown in Figure 1 is introduced below as an example. As shown in Figure 1, the shift register unit 10 includes a first transistor T1, a second transistor T2...a thirteenth transistor T13 and a first capacitor C1, a second capacitor C2 and a third capacitor C3. For example, the shift register unit can output the first voltage VGH as a gate scan signal row by row at the output end. For example, the output end of the shift register unit shown in Figure 1 is connected to the second scan signal line S5 shown in Figure 8 to control the conduction of the M2 transistor, that is, the gate scan signal output by Figure 1 can be used as the second scan signal in Figure 8.

[0060] For example, the plurality of voltage signal lines 50 include a first voltage signal line VGH and a second voltage signal line VGL respectively connected to the first voltage terminal VGH and the second voltage terminal VGL of the shift register unit 10 to provide the first voltage VGH and the second voltage VGL.

[0061] For example, the width of the voltage regulation is determined based on the pulse width H of the first signal STV, and the starting position of the voltage regulation is determined based on the enable signal EN. For example, in the embodiment of the present disclosure, the pulse width H of the first signal is the pulse width of the output waveform of the GOA, and the following embodiments are the same.

[0062] For example, as shown in Figure 3, the host side obtains the working state of the gate drive circuit 20, which includes, for example, manually pausing the output of the gate drive circuit 20 or a blank area, such as an area where the gate drive circuit 20 does not output a waveform, which will cause the load to suddenly decrease, thereby obtaining load information, for example, the load information includes a decrease or increase in the load, etc. For example, the load information of the GOA includes an output waveform and an output DC load that differs by an A / A load, and the A / A load is the parasitic capacitance and resistance of the corresponding GOA output in the pixel. Usually, when the load of the gate drive circuit 20 suddenly decreases, it will generally cause the second voltage VGL to decrease (change to a negative direction) and the first voltage VGH to increase (change to a positive direction). In some examples, the output abnormality caused by the load change is adjusted by adjusting the signal voltage input to the shift register unit.

[0063] Taking the timing setting of local refresh as an example, the enable signal EN controls the output waveform of the shift register unit through logical high and low. Taking the shift register unit outputting a logic high level (e.g., the first voltage VGH, or other voltages) as the waveform output (outputting an AC signal to drive the pixel to refresh) as an example, at the falling edge of the EN signal (i.e., when the load information of the gate driver circuit 20 changes (e.g., the gate driver circuit 20 does not output, resulting in a load drop)), the waveform of the second voltage VGL input to the gate driver circuit 20 is adjusted to have a minimum voltage of VGL-ΔV, or the waveform of the first voltage VGH input to the gate driver circuit 20 is adjusted to have a pull-up waveform with a maximum voltage of VGH+ΔV. This ΔV can be adjusted to suit different panels. For example, the waveform can be a square wave, a triangle wave, or other waveform. The waveform width is based on the output waveform width of the gate driver circuit 20. Due to delays in actual transmission, the actual setting width can be fine-tuned. The timing is shown in Figures 4A or 4B.

[0064] As shown in Figure 3, in the actual module driving process, the host end 130 sends out the waveform output on-off row number information, and the enable signal EN and the first signal STV are generated in the timing control circuit 110. At the same time, the waveform of the voltage that needs to be adjusted (for example, the first voltage VGL, the second voltage VGH, the first scan signal S3, the second scan signal S5, the data signal Vdt, the first reset voltage VINIT1 or the second reset voltage VINIT2) is generated according to the preset phase structure. The corresponding waveform is generated to compensate for the GOA power supply voltage caused by the load, and the above-mentioned adjusted voltage after compensation is input into the gate drive circuit or pixel circuit in the display panel, thereby eliminating the brightness difference and improving the uniformity of the picture display.

[0065] For example, as shown in FIG5 , during the display phase, voltage regulation includes adjusting the first voltage VGH to VGH+ΔV111 when the enable signal EN drops; or, as shown in FIG4A , adjusting the second voltage VGL to VGL-ΔV211. For example, the widths of ΔV111 and ΔV211 are the same as the pulse width of the first signal STV. For example, the first signal STV is a trigger signal input to the GOA. For example, ΔV111 can be approximately 50mV-150mV (millivolts), and ΔV211 can be approximately 0.8V-1.5V (volts), depending on the actual situation, for example, based on the actual display effect (e.g., grayscale brightness uniformity). The embodiments of the present disclosure are not limited to this.

[0066] For example, each frame includes a blanking phase and a display phase. During the display phase, the gate drive circuit outputs waveforms line by line. During the blanking phase, the gate drive circuit 20 stops outputting waveforms. When the gate drive circuit 20 does not output waveforms, the power supply load decreases, which will also cause similar problems. The compensation method is shown in Figure 4B.

[0067] For example, as shown in FIG4B , only the first frame Frame1 and the second frame Frame2 are shown. Of course, more frames may be included, and the embodiments of the present disclosure are not limited to this. For example, during the blanking phase of the first frame Frame1 and the second frame Frame2, the voltage regulation includes adjusting the second voltage VGL to VGL-ΔV22 in response to the rising edge of the enable signal EN. For example, the widths of ΔV12 and ΔV22 are the same as the pulse width of the first signal STV. For example, the first signal STV is a trigger signal input to the GOA connected to the first voltage line VGH and the second voltage line VGL. For example, the rising edge of the enable signal EN is located at the beginning of each frame.

[0068] For example, in other examples, the plurality of voltage signal lines include a plurality of clock signal lines, which are configured to provide a plurality of clock signals to a plurality of shift register units (to a plurality of shift register units in a gate drive circuit that outputs the first scan signal S3 shown in FIG8 ). For example, as shown in FIG6 , the plurality of voltage signal lines include a first clock signal line CLK connected to the first clock signal terminal CK shown in FIG1 to provide a first clock signal CLK, and a second clock signal line CLKB connected to the second clock signal terminal CB to provide a second clock signal CLKB. It should be noted that the number of clock signal lines is only an example, and the embodiments of the present disclosure do not limit this, and may be determined according to actual circumstances. The first scan signal S3 will be described in FIG8 below and will not be repeated here.

[0069] For example, in this example, the voltage of the clock signal can be adjusted to adjust the waveform of the GOA clock signal at the falling edge of the EN signal (i.e., during the period when the GOA is not outputting and the power supply load is suddenly reduced), so that the low-level voltage at this time is adjusted by ΔV. This voltage change of ΔV can gradually achieve a stable output of the GOA to adapt to the phenomenon adjustment. For example, the total number of CLK pulses can be changed based on the width of the GOA output waveform for fine-tuning. For example, in the embodiment of the present disclosure, the pulse width H of the GOA output waveform is the same as the width H of the first signal STV.

[0070] Figure 6 is a schematic diagram illustrating voltage regulation of the first scan signal S3 by adjusting a clock signal in a gate driver circuit that outputs the first scan signal S3. For example, as shown in Figure 6, voltage regulation includes adjusting the first level V0 of multiple clock signals to V0-ΔV61 when the enable signal falls to adjust the first scan signal S3. For example, the number of pulses in the voltage-regulated clock signal is determined based on the pulse width of the first signal. For example, the first signal STV is a trigger signal input to the gate driver circuit that outputs the first scan signal S3 shown in Figure 8.

[0071] For example, the first level V0 is a low level, and the voltage regulation pulls down the low level of the clock signal when the enable signal falls, so as to ensure the normal output of the shift register unit.

[0072] The display device provided by the above-mentioned embodiments of the present disclosure adjusts the waveform of the voltage signal input to the gate drive circuit before and after the load of the gate drive circuit changes, realizes the voltage change during the load change period, corrects the impact of the sudden load change of the gate drive circuit on the output waveform, makes the output of the gate drive circuit during this period consistent with the output of other gate drive circuits, improves the uniformity of the picture display, eliminates the brightness difference, optimizes the display effect, and improves the display quality.

[0073] In other embodiments, the voltage of the signal input to the pixel circuit may be adjusted to ensure uniform display.

[0074] FIG7 is a schematic block diagram of a pixel circuit provided by at least one embodiment of the present disclosure.

[0075] As shown in FIG. 7 , the pixel circuit 411 includes a driving circuit 412 , a data writing circuit 120 , a threshold compensation circuit 130 , a storage circuit 140 , a first light emission control circuit 150 , and a first reset circuit 160 .

[0076] For example, the driving circuit 412 includes a first terminal 111, a second terminal 112 and a control terminal 113, and the driving circuit 412 is configured to control the driving current flowing through the light-emitting element 170. For example, in the light-emitting stage, the driving circuit 412 can provide a driving current to the light-emitting element 170 to drive the light-emitting element 170 to emit light, and can emit light according to the required "grayscale". For example, the light-emitting element 170 can adopt any type of applicable device, which can include a variety of structures, which can be selected and set according to actual needs, and the embodiments of the present disclosure are not limited to this. For example, the light-emitting element 170 can be an OLED, a quantum dot light emitting diode (Quantum Dot Light Emitting Diode, QLED) or a micro light-emitting diode (Micro Light Emitting Diode, Micro LED), etc., which can be determined according to actual needs.

[0077] The data write circuit 120 is connected to the first terminal 111 of the driver circuit 412 and is configured to write a data signal to the first terminal 111 of the driver circuit 412 in response to a first scan signal. For example, the data write circuit 120 is connected to the first scan line S3 and the data line DL, where the first scan line S3 is used to provide the first scan signal, and the data line DL is used to provide the data signal. During the data write phase, the data write circuit 120 is turned on in response to the first scan signal provided by the first scan line S3, thereby writing the data signal provided by the data line DL to the first terminal 111 of the driver circuit 412. The data signal is further written to the control terminal 113 of the driver circuit 412 through the driver circuit 412 and the threshold compensation circuit 130, and is stored in the storage circuit 140. During the light-emitting phase, a drive current is generated based on the data signal to drive the light-emitting element 170 to emit light.

[0078] The threshold compensation circuit 130 is connected between the control terminal 113 of the driving circuit 412 and the second terminal 112 of the driving circuit 412, and is configured to write a compensation signal based on the data signal into the control terminal 113 of the driving circuit 412 in response to the second scan signal. For example, the threshold compensation circuit 130 can be directly connected to the control terminal 113 and the second terminal 112 of the driving circuit 412, that is, directly connected between the control terminal 113 and the second terminal 112 of the driving circuit 412. Of course, the threshold compensation circuit 130 can also be indirectly connected between the control terminal 113 and the second terminal 112 of the driving circuit 412, that is, other circuits (such as the leakage protection circuit 230 described below) can also be provided between the threshold compensation circuit 130 and the control terminal 113 of the driving circuit 412, and between the threshold compensation circuit 130 and the second terminal 112 of the driving circuit 412. The embodiments of the present disclosure are not limited in this regard.

[0079] For example, the threshold compensation circuit 130 is connected to the second scan line S5, which is used to provide a second scan signal. When the first scan signal provided by the first scan line S3 and the second scan signal provided by the second scan line S5 are both at an active level, the data write circuit 120 and the threshold compensation circuit 130 are both turned on. At this time, the driver circuit 412 is also turned on. The data signal is transmitted to the threshold compensation circuit 130 via the data write circuit 120 and the driver circuit 412. The threshold compensation circuit 130 generates a compensation signal based on the data signal and writes the compensation signal to the control terminal 113 of the driver circuit 412. For example, during the data write phase, the threshold compensation circuit 130 can electrically connect the control terminal 113 of the driver circuit 412 to the second terminal 112, so that the relevant information of the threshold voltage of the driver circuit 412 is also stored in the storage circuit 140. Therefore, during the light-emitting phase, the stored voltage including the data signal and the threshold voltage can be used to control the driver circuit 412, so that the driver circuit 412 can be compensated.

[0080] The storage circuit 140 is connected to the control terminal 113 of the driving circuit 412 and the first voltage line VDD, and is configured to store the compensation signal and maintain the compensation signal at the control terminal 113 of the driving circuit 412 .

[0081] The first light-emission control circuit 150 is connected to the first voltage line VDD and the first terminal 111 of the driver circuit 412, and is configured to apply a first voltage provided by the first voltage line VDD to the first terminal 111 of the driver circuit 412 in response to a first light-emission control signal. For example, the first light-emission control circuit 150 is connected to the first light-emission control line S1, which is used to provide the first light-emission control signal. The first light-emission control circuit 150 can be turned on in response to the first light-emission control signal, electrically connecting the first terminal 111 of the driver circuit 412 to the first voltage line VDD, thereby applying the first voltage provided by the first voltage line VDD to the first terminal 111 of the driver circuit 412.

[0082] The first reset circuit 160 is connected to the threshold compensation circuit 130 and is configured to apply a first reset voltage to the control terminal 113 of the driver circuit 412 in response to a first reset signal. For example, the first reset circuit 160 is connected to a first reset line S4 and a first reset voltage line INIT1. The first reset line S4 is configured to provide a first reset signal, and the first reset voltage line INIT1 is configured to provide a first reset voltage. The first reset circuit 160 can be turned on in response to the first reset signal, thereby transmitting the first reset voltage to the second terminal 112 of the driver circuit 412. The first reset voltage is further transmitted to the control terminal 113 of the driver circuit 412 via the threshold compensation circuit 130, thereby resetting the control terminal 113 of the driver circuit 412.

[0083] The anode of the light emitting element 170 receives the driving current provided by the driving circuit 412 , and the cathode of the light emitting element 170 is connected to the second voltage line VSS, which is used to provide a second voltage.

[0084] It should be noted that, for descriptive purposes, in each embodiment of the present disclosure, the first voltage signal line VGH and the first voltage line VDD, for example, maintain input of a DC high-level signal, and this DC high-level signal is referred to as the first voltage; and the second voltage signal line VGL and the second voltage line VSS, for example, maintain input of a DC low-level signal, and this DC low-level signal is referred to as the second voltage (which may be a ground voltage), which is lower than the first voltage. The following embodiments are similar to this and will not be described in detail.

[0085] For example, in some examples, the pixel circuit 411 further includes a second light emitting control circuit 180 and a second reset circuit 190 .

[0086] The second light-emission control circuit 180 is connected to the second terminal 112 of the driver circuit 412 and the light-emitting element 170, and is configured to apply the voltage at the second terminal 112 of the driver circuit 412 to the light-emitting element 170 in response to a second light-emission control signal. For example, the second light-emission control circuit 180 is connected to a second light-emission control line S2, which is used to provide the second light-emission control signal. The second light-emission control circuit 180 can be turned on in response to the second light-emission control signal, electrically connecting the second terminal 112 of the driver circuit 412 to the light-emitting element 170 (e.g., the anode of the light-emitting element 170), thereby applying the voltage at the second terminal 112 of the driver circuit 412 to the light-emitting element 170.

[0087] The second reset circuit 190 is connected to the second light-emitting control circuit 180 and the light-emitting element 170 and is configured to apply a second reset voltage to the light-emitting element 170 (e.g., the anode of the light-emitting element 170) in response to a second reset signal. For example, the second reset circuit 190 is connected to a second reset line S6 and a second reset voltage line INIT2. The second reset line S6 is used to provide the second reset signal, and the second reset voltage line INIT2 is used to provide the second reset voltage. The second reset circuit 190 can be turned on in response to the second reset signal to transmit the second reset voltage to the connection between the second light-emitting control circuit 180 and the light-emitting element 170, thereby resetting the light-emitting element 170.

[0088] For example, the control terminal 113 of the driving circuit 412 and the storage circuit 140 are connected to a first node P1, the first light-emitting control circuit 150 and the first terminal 111 of the driving circuit 412 are connected to a second node P2, the second light-emitting control circuit 180 and the second terminal 112 of the driving circuit 412 are connected to a third node P3, and the second reset circuit 190, the second light-emitting control circuit 180, and the light-emitting element 170 are connected to a fourth node P4. For example, the potential of the third node P3 after being reset by the first reset circuit 160 is greater than the potential of the fourth node P4 after being reset by the second reset circuit 190. This can achieve a better reset effect and better reduce or eliminate the influence of residual charge on the potential of the anode of the light-emitting device during the light-emitting phase.

[0089] For example, the pixel circuit shown in FIG7 further includes a third reset circuit 191 connected to the second node P2 and configured to apply a third reset voltage to the second node P2 in response to a third reset signal. For example, the third reset circuit 191 is connected to a third reset line S7 and a third reset voltage line INIT3. The third reset line S7 is configured to provide the third reset signal, and the third reset voltage line INIT3 is configured to provide the third reset voltage. The third reset circuit 191 can be turned on in response to the third reset signal to transmit the third reset voltage to the second node P2, thereby resetting the second node P2.

[0090] FIG8 is a schematic diagram of the circuit structure of the pixel circuit shown in FIG7 . As shown in FIG8 , the pixel circuit 411 includes: transistors M1 to M7 and a storage capacitor Cst. For example, the transistor M3 is used as a driving transistor, and the other transistors are used as switching transistors. The light-emitting element 170 can be implemented as a light-emitting element EL. The light-emitting element EL can be, for example, an OLED. The embodiments of the present disclosure include but are not limited to this. The following embodiments are all described using OLED as an example and will not be repeated here. The OLED can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light or white light, etc., and the embodiments of the present disclosure are not limited to this.

[0091] For example, as shown in FIG8 , in more detail, the driving circuit 412 can be implemented as a driving transistor, that is, a transistor M3. The gate of the driving transistor (transistor M3) serves as the control terminal 113 of the driving circuit 412, the first electrode of the driving transistor (transistor M3) serves as the first terminal 111 of the driving circuit 412, and the second electrode of the driving transistor (transistor M3) serves as the second terminal 112 of the driving circuit 412.

[0092] The data write circuit 120 can be implemented as a data write transistor, namely, a transistor M4. The gate of the data write transistor (transistor M4) is connected to the first scan line (scan line S3) to receive the first scan signal, the first electrode of the data write transistor (transistor M4) is connected to the data line (data line DL) to receive the data signal, and the second electrode of the data write transistor (transistor M4) and the first electrode of the drive transistor (transistor M3) are connected to the second node P2.

[0093] The threshold compensation circuit 130 can be implemented as a threshold compensation transistor, namely, transistor M2. The gate of the threshold compensation transistor (transistor M2) is connected to the second scan line (scan line S5) to receive the second scan signal. The first electrode of the threshold compensation transistor (transistor M2) and the second electrode of the driving transistor (transistor M3) are connected to the third node P3. The second electrode of the threshold compensation transistor (transistor M2) and the gate of the driving transistor (transistor M3) are connected to the first node P1.

[0094] The storage circuit 140 may be implemented as a storage capacitor Cst, a first electrode of the storage capacitor Cst being connected to the first voltage line VDD, and a second electrode of the storage capacitor Cst being connected to the gate of the driving transistor (transistor M3 ) at the first node P1 .

[0095] The first light control circuit 150 can be implemented as a first light control transistor, namely, transistor M5. The gate of the first light control transistor (transistor M5) is connected to the first light control line (scan line S1) to receive the first light control signal. The first electrode of the first light control transistor (transistor M5) is connected to the first voltage line VDD. The second electrode of the first light control transistor (transistor M5) is connected to the first end of the driving circuit, that is, the first electrode of the driving transistor (transistor M3) is connected to the second node P2.

[0096] The first reset circuit 160 can be implemented as a first reset transistor, namely, transistor M1. The gate of the first reset transistor (transistor M1) is connected to the first reset line (scan line S4) to receive the first reset signal, the first electrode of the first reset transistor (transistor M1) is connected to the first reset voltage line (voltage line INIT1) to receive the first reset voltage, and the second electrode of the first reset transistor (transistor M1) and the second electrode of the drive transistor (transistor M3) are connected to the third node P3.

[0097] The second light-emission control circuit 180 can be implemented as a second light-emission control transistor, namely, transistor M6. The gate of the second light-emission control transistor (transistor M6) is connected to the second light-emission control line (scan line S2) to receive the second light-emission control signal. The first electrode of the second light-emission control transistor (transistor M6) is connected to the second end of the driving circuit, namely, the second electrode of the driving transistor (transistor M3) is connected to the third node P3. The second electrode of the second light-emission control transistor (transistor M6) is connected to the anode of the light-emitting element EL at a fourth node P4.

[0098] The second reset circuit 190 can be implemented as a second reset transistor, namely, transistor M7. The gate of the second reset transistor (transistor M7) is connected to the second reset line (scan line S6) to receive the second reset signal, the first electrode of the second reset transistor (transistor M7) is connected to the second reset voltage line (voltage line INIT2) to receive the second reset voltage, and the second electrode of the second reset transistor (transistor M7) is connected to the second electrode of the second emission control transistor (transistor M6) and the light-emitting element EL to the fourth node P4.

[0099] The third reset circuit 191 can be implemented as a third reset transistor, namely, transistor M8. The first electrode of the third reset transistor (transistor M8) is connected to the third reset line INIT3, the second electrode is connected to the second node P2, and the gate is connected to the third reset line (scan line S7). In response to the scan line S7 being turned on, the third reset line INIT3 is connected to the second node P2 to reset the second node P2.

[0100] For example, the driving transistor (transistor M3), the data writing transistor (transistor M4), the first light-emitting control transistor (transistor M5), and the first reset transistor (transistor M1) are transistors of the first type; the threshold compensation transistor (transistor M2) is a transistor of the second type; and the first type is different from the second type. For example, in some examples, the first type of transistor includes a P-type thin film transistor, and the second type of transistor includes an N-type thin film transistor, that is, the driving transistor (transistor M3), the data writing transistor (transistor M4), the first light-emitting control transistor (transistor M5), and the first reset transistor (transistor M1) are P-type thin film transistors, and the threshold compensation transistor (transistor M2) is an N-type transistor. Of course, the embodiments of the present disclosure are not limited to this, and the types of certain transistors used in the pixel circuit 411 can be changed according to actual needs, for example, changing a P-type thin film transistor to an N-type thin film transistor, or changing an N-type thin film transistor to a P-type thin film transistor.

[0101] FIG. 9 is a timing diagram for the pixel circuit shown in FIG. 8 provided in some embodiments of the present disclosure.

[0102] As shown in FIG9 , in some examples, in the first phase T1, the gate of transistor M5 is connected to scan line S1, which is at a low potential, transistor M5 is turned on, and the high potential of the first voltage line VDD is written to the first electrode of transistor M3, that is, to the second node P2. The potential of the second node P2 is V1, which can be VDD or greater than 0 and less than VDD. The gate of transistor M1 is connected to scan line S4, which is at a low potential, transistor M1 is turned on, and the gate of transistor M2 is connected to scan line S5, which is at a high potential, transistor M2 is turned on, and the low potential of voltage line INIT1 is written to the second electrode of transistor M3 (that is, the third node P3) and the gate of transistor M3 (that is, the first node P1). The gate of transistor M7 is connected to scan line S6, which is at a low potential, transistor M7 is turned on, and the low potential of voltage line INIT2 is written to the anode of light-emitting element EL (that is, the fourth node P4). Therefore, in the first stage T1, the anode of the light emitting element EL and the first, second and gate electrodes of the transistor M3 are reset, eliminating the residual charge displayed in the previous frame, which is conducive to accurate data writing in the second stage T2.

[0103] During the second phase T2, S3 and S5 are at a low level and a high level, respectively. Transistors M4 and M2 are turned on, and the data signal is written to the gate of transistor M3 via transistors M4, M3, and M2, respectively. At this point, the potential of first node P1 is Vdt + |Vth|. Vdt represents the data signal, and Vth represents the threshold voltage of transistor M3. To ensure that fourth node P4 maintains a stable low potential before emitting light, transistor M7 remains turned on during the second phase T2, and the low potential of voltage line INIT2 is written to fourth node P4. In other words, fourth node P4 is reset during both the first phase T1 and the second phase T2.

[0104] In the third stage T3, the potentials of S1 and S2 are low, the transistors M5 and M6 are turned on, and the light-emitting element EL emits light. The current flowing through the transistor M3 is: I = 1 / 2μ*W / L*Cox(Vgs-Vth) 2 =1 / 2μ*W / L*Cox(VDD-Vdt) 2 Where W / L is the width-to-length ratio of transistor M3, Cox is the dielectric constant of the channel insulating layer of transistor M3, and μ is the channel carrier mobility of transistor M3. Simulations yielded good results, with the following conditions: VDD = 4.6V, VSS = -3V, Vinit (i.e., INIT1 and INIT2) = -3V, Vdt = 3V, and Vth = -2V. Good simulation results refer to high data accuracy during writing, and the potential of the anode of the light-emitting device during the light-emitting phase is virtually unaffected by residual charge.

[0105] As shown in Figure 9, during the third phase T3, i.e., the light-emitting phase, the potential of the first voltage line VDD is VDD. During the non-light-emitting phase, including the first phase T1 for resetting and the second phase T2 for data writing, the potential of the first voltage line can be reduced to V1 to save power. The potential of the second node P2 can be V1, i.e., greater than 0 and less than or equal to VDD, thereby achieving a reset function.

[0106] In this example, S2 and S5 can be signals output by the same gate drive circuit (e.g., GOA); S3 and S4 can be provided by the same type of GOA. For example, S3 is a signal provided by a shift register unit at a certain level in the GOA, and S4 is a signal provided by a shift register unit at the previous level in the GOA. Therefore, for a row of pixel circuits, at least four GOAs are required, or a shift register unit at a level of the GOA needs to output four shift signals (if the GOA used can output multiple signals, for example, a GOA can output two signals with different pulse widths or two signals with different potentials).

[0107] For example, in some examples, the first voltage VGH and / or the second voltage VGL in the GOA outputting the above-mentioned S2-S6 can be voltage-regulated so that the scanning signals S2-S5 output to the pixel circuit are normal, thereby ensuring display uniformity. The specific method of regulating the first voltage and / or the second voltage can be referred to the description of the above embodiment.

[0108] For example, in other examples, by adjusting the driving voltage in the pixel, taking the LTPO (Low Temperature Polycrystalline Oxide) circuit as an example, its driving involves GOA connected to S3, S4, S5, S6, S1 and S2, as well as reference voltages such as VINIT1, VINIT2, VDD, VSS and the data voltage Vdt.

[0109] For example, in some examples, display uniformity near the GOA load switching position can be improved by adjusting the waveform in the DC reference potential (e.g., increasing the waveform ΔV as shown below). For example, in some examples, the first reset voltage VINIT1 can be adjusted. Taking the bright band caused by the S3 waveform at the switching position as an example, a pull-up waveform is generated at a specific position (e.g., at a first phase difference from the falling edge of the enable signal as described below). The phase relationship between the falling edge of the pull-up waveform and the falling edge of the enable signal EN is based on the phase difference between the waveform of the first scan signal S3 and the waveform of the first reset signal S4. Fine-tuning is performed based on the delay state and display effect.

[0110] FIG10 is a schematic diagram of voltage regulation of a first reset voltage VINIT1 according to at least one embodiment of the present disclosure. For example, in this example, the plurality of voltage signal lines may include a first scan line S3 and a first reset line S4. For example, as shown in FIG7 and FIG8 , the first scan line S3 is connected to the data write circuit 120 of the pixel circuit to send the first scan signal S3 to the control terminal of the data write circuit 120; the first reset line S4 is connected to the control terminal of the first reset circuit 160 of the pixel circuit to provide the first reset signal S4. For example, the first reset circuit 160 is turned on in response to the first reset signal S4; the plurality of voltage signal lines 50 also includes a first reset voltage line INIT1, which is connected to the first reset circuit 160 to provide the first reset voltage VINIT1; and the timing control circuit 110 is further configured to determine a first phase difference based on the first scan signal S3 and the first reset signal S4. For example, as shown in FIG10 , voltage regulation further includes adjusting the first reset voltage VINIT1 to VINIT1 + ΔV31 at a first phase difference from the falling edge of the enable signal EN when the enable signal EN falls. For example, the width of ΔV31 is the same as the pulse width of the first signal STV, for example, the same as the pulse width of S3. For example, the first signal STV is a trigger signal input to the gate drive circuit that outputs the first scan signal S3 shown in FIG8 . For example, ΔV31 can be approximately 1V, depending on the actual situation, for example, based on the actual display effect (for example, grayscale brightness uniformity), and the embodiments of the present disclosure are not limited to this.

[0111] For example, in other examples, taking the bright band caused by the S5 waveform at the switching position as an example, a pull-down or pull-up waveform is created at a specific position. The phase relationship between its falling edge and the falling edge of the enable signal EN is based on the phase difference between the S5 waveform and the S6 waveform. Specific adjustments are made based on the delay state and display effect (such as grayscale brightness). The waveform timing is shown in Figure 11.

[0112] 11 is a schematic diagram of regulating the second reset voltage VINIT2 according to at least one embodiment of the present disclosure. For example, in this example, the plurality of voltage signal lines further include a second scan line S5 and a second reset line S6.

[0113] For example, the second scan line S5 is connected to the threshold compensation circuit 130 of the pixel circuit to send the second scan signal S5 to the control end of the threshold compensation circuit 130; the second reset line S6 is connected to the second reset circuit 190 of the pixel circuit to provide a second reset signal, wherein the second reset circuit 190 is turned on in response to the second reset signal; the multiple voltage signal lines also include a second reset voltage line VINIT2, which is connected to the second reset circuit 190 to provide a second reset voltage VINIT2.

[0114] For example, the timing control circuit is further configured to determine a second phase difference based on the second scan signal S5 and the second reset signal S6; for example, as shown in FIG11 , the voltage regulation further includes adjusting the second reset voltage VINIT2 to VINIT2+ΔV32 at the position of the second phase difference from the falling edge of the enable signal EN when the enable signal EN falls, wherein the width of ΔV32 is the same as the pulse width of the first signal, for example, the same as the pulse width of S5. For example, the first signal STV is a trigger signal input to the gate drive circuit that outputs the second scan signal S5 shown in FIG8 . For example, ΔV32 can be approximately 1V, and can be a positive number or a negative number, depending on the actual situation, for example, based on the actual display effect (for example, grayscale brightness uniformity), and the embodiments of the present disclosure are not limited to this.

[0115] For example, in other examples, the display uniformity near the GOA load switching position can be improved by adding an additional compensation voltage to the data signal Vdt.

[0116] For example, taking the bright band caused by the S5 waveform at the switching position as an example, a pull-up waveform is created at a specific position. The waveform shape can be adjusted to be a square wave or a triangle wave. The phase relationship between its falling edge and the falling edge of EN is based on the phase difference between the S5 waveform and the S3 waveform. The visual delay state and display effect can be fine-tuned, and the embodiments of the present disclosure are not limited to this. The timing is shown in Figure 12.

[0117] For example, in this example, the plurality of voltage signal lines also includes a data line DL, which is connected to the digital write circuit 120 of the pixel circuit and configured to provide a data signal Vdt to the digital write circuit 120. For example, the timing control circuit is further configured to determine a third phase difference S5-S3 based on the first scan signal S3 and the second scan signal S5. As shown in FIG12 , the voltage adjustment further includes adjusting the first level of the data signal Vdt to Vdt+ΔV41 at a position of the third phase difference S5-S3 from the falling edge of the enable signal EN when the enable signal EN falls. For example, the width of ΔV41 is the same as the pulse width of the first signal, for example, the same as the pulse width of S5. For example, the first signal STV is a trigger signal input to the gate drive circuit that outputs the second scan signal S5 shown in FIG8 . For example, ΔV41 can be approximately 30mV-50mV (millivolts), depending on the actual situation, for example, based on the actual display effect (e.g., grayscale brightness uniformity), and the embodiments of the present disclosure are not limited in this regard.

[0118] For example, in other examples, uniform display of the display panel can be achieved by adjusting the output of the first scanning signal S3. For example, when the pixel is affected and becomes brighter (or darker), the charging rate of the pixel can be increased (or decreased), thereby compensating for the band brightness difference caused by the waveform difference of other GOA outputs caused by load changes. For example, adjusting the waveform of the first scanning signal S3 can be achieved by adjusting the first level in the gate drive circuit 20 that outputs the first scanning signal S3 or the voltage setting of the clock signal of the gate drive circuit 20 that outputs the first scanning signal S3.

[0119] For example, the voltage adjustment of the clock signal of the gate driving circuit 20 that outputs the first scanning signal S3 is shown in Figure 6 above and will not be repeated here; the adjustment of the first level VGL_P of the gate driving circuit can be referred to the description in the embodiment described in Figure 13 below.

[0120] For example, the first scan signal S3 is adjusted by adjusting the voltage of the first level VGL_P (eg, low voltage) in the gate driving circuit outputting the first scan signal S3 from VGL_P to VGL_P+ΔV, where ΔV can be positive or negative.

[0121] For example, at the falling edge of the EN signal (e.g., when the GOA does not output, causing a sudden drop in the power supply load), the waveform of the first level of the gate driver circuit 20 outputting the first scan signal S3 is adjusted so that there is a waveform with a minimum voltage of, for example, VGL_P+ΔV. This waveform can be a square wave, a triangular wave, or other waveforms. The waveform width is based on the width of the GOA output waveform (e.g., the first scan signal S3). Due to delays in actual transmission, the actual set width can be fine-tuned, and the embodiments of the present disclosure are not limited to this. The timing is shown in Figure 13.

[0122] FIG13 is a schematic diagram of at least one embodiment of the present disclosure providing a method for voltage-regulating the first scanning signal S3 by adjusting the waveform of the first level of the gate drive circuit 20 that outputs the first scanning signal S3. As shown in FIG13 , the voltage regulation includes adjusting the first level VGL_P (e.g., a low level) of the first scanning signal S3 to VGL_P+ΔV51 when the enable signal EN drops. For example, the width of ΔV51 is the same as the pulse width of the first signal, for example, the same as the pulse width of S3. For example, the first signal STV is a trigger signal input to the gate drive circuit that outputs the first scanning signal S3 shown in FIG8 . For example, the ΔV51 can be around 0.8V-1.5V, and can be a positive number or a negative number, depending on the actual situation, for example, based on the actual display effect (e.g., grayscale brightness) being uniform. The embodiments of the present disclosure are not limited to this.

[0123] For example, the first level may be provided by the first voltage line VGL, or may be provided by other voltage lines, and the embodiments of the present disclosure are not limited thereto.

[0124] The voltage adjustments involved in various embodiments of the present disclosure are different and can correspond to fine adjustment (high precision) and coarse adjustment (power saving). Therefore, the adjustments involved in various embodiments of the present disclosure can be arbitrarily combined to achieve precise control of the compensation amplitude (controllable row by row or region by region) while ensuring that the compensation signals do not undergo fine adjustment (such as voltage gradient, special waveform, etc.), thereby saving power. The following is an example of the combination of the first voltage VGH and the second voltage VGL.

[0125] For example, in other examples, as shown in FIG14 , voltage regulation includes regulating the first voltage VGH to VGH-ΔV112 and the second voltage VGL to VGL-ΔV212 when the enable signal EN falls, wherein the width of ΔV112 is the same as the pulse width H of the first signal, the width of ΔV212 is smaller than the pulse width H of the first signal, and the amplitudes of ΔV112 and ΔV212 are smaller than the amplitudes of ΔV111 and ΔV211, respectively, thereby achieving compensation while reducing power consumption. For example, the first signal STV is a trigger signal input to a gate driver circuit connected to the first voltage line VGH and the second voltage line VGL.

[0126] It should be noted that it can also be combined with other signal voltages, such as a clock signal, a data signal, a scan signal or a reset voltage, etc., and the embodiments of the present disclosure do not limit this.

[0127] It should be noted that the voltage regulation changes ΔV in the figures are shown in the form of square waves, but the embodiments of the present disclosure are not limited to this. It can also be a triangle wave or other waveforms as long as the stable output of the GOA can be achieved.

[0128] At least one embodiment of the present disclosure further provides a pixel circuit. As shown in FIG7 , the pixel circuit 411 includes a driving circuit 412, a data writing circuit 120, a threshold compensation circuit 130, a storage circuit 140, a first light-emitting control circuit 150, and a first reset circuit 160. The specific structure and operation of the pixel circuit can be found in the description of FIG7 to FIG9 , and will not be further described here.

[0129] For example, in some examples, the voltage of the first scan signal S3, the second scan signal S5, the data signal Vdt, or the first reset voltage VINIT1 is configured to be adjusted based on the enable signal EN and the first signal STV determined when the load information of the gate drive circuit 20 changes. For example, the width of the voltage adjustment is determined based on the pulse width of the first signal STV, and the starting position of the voltage adjustment is determined based on the enable signal EN.

[0130] For example, in some examples, as shown in FIG10 , voltage regulation includes adjusting the first reset voltage VINIT1 to VINIT1 + ΔV31 at a first phase difference from the falling edge of the enable signal EN when the enable signal EN falls. For example, the width of ΔV31 is the same as the pulse width of the first signal, for example, the same as the pulse width of the first scan signal S4. For example, ΔV31 can be approximately 1V, depending on actual conditions, such as the actual display effect (e.g., grayscale brightness uniformity), and the embodiments of the present disclosure are not limited thereto.

[0131] For example, in some examples, as shown in FIG10 , the first phase difference is determined based on the first scan signal S3 and the first reset signal S4 , that is, the first phase difference is the phase difference between the first scan signal S3 and the first reset signal S4 .

[0132] For example, in some examples, as shown in FIG13 , the voltage regulation further includes adjusting the first level VGL_P of the first scan signal S3 to VGL_P-ΔV51 when the enable signal EN falls. For example, the width of ΔV51 is the same as the pulse width of the first signal. For example, ΔV51 can be approximately 0.8V-1.5V, depending on the actual situation, such as the actual display effect (e.g., grayscale brightness uniformity), and the embodiments of the present disclosure are not limited thereto.

[0133] For example, as shown in Figure 7, the pixel circuit further includes a second light emitting control circuit 180 and a second reset circuit 190. The specific structure and operation process of the pixel circuit can be referred to the description of Figures 7 to 9, which will not be repeated here.

[0134] For example, in this example, the voltage regulation further includes regulating the second reset voltage VINIT2 based on the enable signal EN and the first signal STV.

[0135] For example, as shown in FIG11 , the voltage adjustment includes adjusting the second reset voltage VINIT2 to VINIT2 + ΔV32 at a second phase difference from the falling edge of the enable signal EN when the enable signal EN falls. For example, the width of ΔV32 is the same as the pulse width of the first signal, for example, the same as the pulse width of the second scan signal S5. For example, ΔV32 can be approximately 1V, depending on the actual situation, such as the actual display effect (e.g., grayscale brightness uniformity), and the embodiments of the present disclosure are not limited thereto.

[0136] For example, the second phase difference is determined based on the second scanning signal S5 and the second reset signal S6 , that is, the second phase difference is the phase difference between the second scanning signal S5 and the second reset signal S6 .

[0137] For example, as shown in FIG12 , in some examples, voltage regulation further includes adjusting the first level of the data signal Vdt to Vdt+ΔV41 at a position of a third phase difference from the falling edge of the enable signal EN when the enable signal EN falls. For example, the width of ΔV41 is the same as the pulse width of the first signal. For example, ΔV41 can be approximately 30mV-50mV (millivolts), depending on actual circumstances, such as the actual display effect (e.g., grayscale brightness uniformity), and the embodiments of the present disclosure are not limited thereto.

[0138] For example, the third phase difference is determined based on the first scanning signal S3 and the second scanning signal S5 , that is, the third phase difference is the phase difference between the first scanning signal S3 and the second scanning signal S5 .

[0139] It should be noted that the embodiments of the present disclosure are not limited to the above-mentioned voltage regulation, but can also perform combined regulation of various signal voltages, for example, adjusting at least two of the first scanning signal S3, the second scanning signal S5, the data signal Vdt, the first reset voltage VINIT1 and the second reset voltage VINIT2, so as to achieve precise control of the compensation amplitude (controllable row by row or region by region) while ensuring that each compensation signal is not finely adjusted (such as voltage gradualness, special waveform, etc.), thereby reducing power consumption.

[0140] The pixel circuit provided in the embodiment of the present disclosure can eliminate brightness differences by adjusting the first scan signal S3, the second scan signal S5, the data signal Vdt, the first reset voltage VINIT1 and the second reset voltage VINIT2 required for pixel driving during the period of GOA load change, thereby improving display quality.

[0141] At least one embodiment of the present disclosure further provides a display panel comprising a plurality of pixel units, each pixel unit comprising a pixel circuit provided by any embodiment of the present disclosure. The display panel can eliminate brightness differences, thereby improving display quality.

[0142] FIG15 is a schematic block diagram of a display panel provided in some embodiments of the present disclosure. As shown in FIG15 , in some embodiments, the display panel 40 includes a plurality of pixel units 410, such as arranged in an array. Each pixel unit 410 includes a pixel unit 411. Pixel unit 411 may be a pixel circuit provided in any embodiment of the present disclosure, such as the pixel circuit 10 described above.

[0143] For example, the display panel 40 may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, or other suitable display panels. Each pixel unit 410 includes not only a pixel unit 411 but also a light-emitting element (e.g., OLED, QLED, etc.).

[0144] For example, the display panel 40 can be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel. Furthermore, the display panel 40 can be not only a flat panel but also a curved panel or even a spherical panel. For example, the display panel 40 can also have a touch function, that is, the display panel 40 can be a touch display panel. For example, the display panel 40 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. For example, the display panel 40 can be a flexible display panel, thereby meeting various practical application requirements. For example, the display panel 40 can be applied to a curved screen.

[0145] For the sake of clarity and brevity, the embodiments of the present disclosure do not illustrate all components of the display panel 40. To achieve the basic functions of the display panel 40, those skilled in the art may provide and configure other structures not shown as needed, and the embodiments of the present disclosure do not limit this.

[0146] Regarding the technical effects of the display panel 40 provided in the above embodiment, reference may be made to the technical effects of the pixel circuit 411 provided in the embodiment of the present disclosure, which will not be repeated here.

[0147] There are a few points to note:

[0148] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0149] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0150] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display device, comprising a timing control circuit, a gate drive circuit and a plurality of voltage signal lines; wherein: The timing control circuit is connected to the plurality of voltage signal lines and is configured to determine an enable signal and a first signal when load information of the gate drive circuit changes, and adjust a voltage of at least one voltage signal line among the plurality of voltage signal lines based on the enable signal and the first signal; The gate driving circuit includes a plurality of cascaded shift register units, respectively connected to the plurality of voltage signal lines, and configured to output a gate scanning signal; The width of the voltage regulation is determined based on the pulse width of the first signal, and the starting position of the voltage regulation is determined based on the enable signal.

2. The display device according to claim 1, wherein: The plurality of voltage signal lines include a first voltage signal line and a second voltage signal line, configured to provide a first voltage VGH and a second voltage VGL to the plurality of shift register units; Among them, the time period of a frame includes a display stage and a blanking stage. In the display stage, the voltage regulation includes adjusting the first voltage VGH to VGH+ΔV111 or adjusting the second voltage VGL to VGL-ΔV211 when the enable signal drops, wherein the widths of ΔV111 and ΔV211 are the same as the pulse width of the first signal.

3. The display device according to claim 2, wherein: In the blanking phase, the voltage adjustment includes adjusting the first voltage VGH to VGH-ΔV12 or adjusting the second voltage VGL to VGL-ΔV22 in response to the rising edge of the enable signal, wherein the widths of ΔV12 and ΔV22 are the same as the pulse width of the first signal.

4. The display device according to claim 2, wherein: The plurality of voltage signal lines include a first voltage signal line and a second voltage signal line, configured to provide a first voltage VGH and a second voltage VGL to the plurality of shift register units; Wherein, the voltage regulation includes adjusting the first voltage VGH to VGH-ΔV112 and adjusting the second voltage VGL to VGL-ΔV212 when the enable signal decreases, wherein the width of the ΔV212 is the same as the pulse width of the first signal, the width of the ΔV112 is smaller than the pulse width of the first signal, and the amplitudes of the ΔV112 and ΔV212 are respectively smaller than the amplitudes of the ΔV111 and ΔV211.

5. The display device according to any one of claims 2 to 4, wherein: The first voltage is greater than the second voltage.

6. The display device according to any one of claims 1 to 5, further comprising pixel circuits arranged in an array, wherein: The plurality of voltage signal lines include a first scan line and a first reset line, Wherein, the first scan line is connected to the data writing circuit of the pixel circuit so as to send the first scan signal received from the first scan line to the control end of the data writing circuit; The first reset line is connected to a control terminal of a first reset circuit of the pixel circuit to provide a first reset signal, wherein the first reset circuit is turned on in response to the first reset signal; The plurality of voltage signal lines further include a first reset voltage line connected to the first reset circuit to provide a first reset voltage; The timing control circuit is further configured to determine a first phase difference based on the first scanning signal and the first reset signal; The voltage regulation further includes regulating the first reset voltage VINIT1 to VINIT1+ΔV31 at the first phase difference from the falling edge of the enable signal when the enable signal falls, wherein the width of ΔV31 is the same as the pulse width of the first signal.

7. The display device according to any one of claims 1 to 6, further comprising pixel circuits arranged in an array, wherein: The plurality of voltage signal lines include a first scanning line, The first scanning line is connected to the data writing circuit of the pixel circuit to send the first scanning signal S3 to the control end of the data writing circuit. The voltage adjustment includes adjusting the first level VGL_P in the gate driving circuit outputting the first scan signal to VGL_P+ΔV51 to adjust the first scan signal when the enable signal drops, wherein the width of ΔV51 is the same as the pulse width of the first signal.

8. The display device according to claim 7, wherein: The plurality of voltage signal lines include a plurality of clock signal lines configured to provide a plurality of clock signals to a gate driving circuit that outputs the first scanning signal. The voltage regulation includes regulating the first level V0 of the plurality of clock signals to V0-ΔV61 to regulate the first scanning signal when the enable signal decreases, wherein the number of the voltage-regulated clock signals is determined according to the pulse width of the first signal.

9. The display device according to claim 6, wherein: The plurality of voltage signal lines further include a second scan line and a second reset line, Wherein, the second scanning line is connected to the threshold compensation circuit of the pixel circuit to send the second scanning signal to the control end of the threshold compensation circuit; The second reset line is connected to a second reset circuit of the pixel circuit to provide a second reset signal, wherein the second reset circuit is turned on in response to the second reset signal; The plurality of voltage signal lines further include a second reset voltage line connected to the second reset circuit to provide a second reset voltage; The timing control circuit is further configured to determine a second phase difference based on the second scanning signal and the second reset signal; The voltage regulation further includes adjusting the second reset voltage VINIT2 to VINIT2+ΔV32 at the second phase difference from the falling edge of the enable signal when the enable signal falls, wherein the width of ΔV32 is the same as the pulse width of the first signal.

10. The display device according to claim 6, wherein: The plurality of voltage signal lines further include a data line connected to a digital writing circuit of the pixel circuit and configured to provide a data signal Vdt to the digital writing circuit; Wherein, the timing control circuit is further configured to determine a first scanning signal based on the first scanning signal and the second scanning signal. Three phase differences; The voltage regulation further includes adjusting the first level of the data signal Vdt to Vdt+ΔV41 at the position of the third phase difference from the falling edge of the enable signal when the enable signal falls, wherein the width of ΔV41 is the same as the pulse width of the first signal.

11. The display device according to any one of claims 1 to 10, wherein: The plurality of voltage signal lines further include a trigger signal line configured to provide a trigger signal to the gate drive circuit; Wherein, the first signal is a trigger signal.

12. A pixel circuit comprising: A driving circuit, a data writing circuit, a threshold compensation circuit, a storage circuit, a first light emitting control circuit and a first reset circuit; The driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the light emitting element; The data writing circuit is connected to the first end of the driving circuit and is configured to write a data signal into the first end of the driving circuit in response to a first scanning signal; The threshold compensation circuit is connected between the control terminal of the driving circuit and the second terminal of the driving circuit, and is configured to write a compensation signal based on the data signal into the control terminal of the driving circuit in response to a second scanning signal; The storage circuit is connected to the control terminal of the driving circuit and the first voltage line, and is configured to store the compensation signal and keep the compensation signal at the control terminal of the driving circuit; The first light emitting control circuit is connected to the first voltage line and the first end of the driving circuit, and is configured to apply a first voltage provided by the first voltage line to the first end of the driving circuit in response to a first light emitting control signal; The first reset circuit is connected to the threshold compensation circuit and is configured to apply a first reset voltage to the control terminal of the drive circuit in response to a first reset signal; The control end of the driving circuit and the storage circuit are connected to a first node, and the first light emitting control circuit and the first end of the driving circuit are connected to a second node; Wherein, the voltage of the first scan signal, the second scan signal, the data signal or the first reset voltage is configured to be adjusted based on the enable signal and the first signal determined when the load information of the gate drive circuit changes, wherein the width of the voltage adjustment is determined based on the pulse width of the first signal, and the starting position of the voltage adjustment is determined based on the enable signal.

13. The pixel circuit according to claim 12, wherein: The voltage regulation includes regulating the first reset voltage VINIT1 to VINIT1+ΔV31 at a first phase difference from a falling edge of the enable signal when the enable signal falls, wherein the width of ΔV31 is the same as the pulse width of the first signal.

14. The pixel circuit according to claim 13, wherein: The first phase difference is determined based on the first scanning signal and the first reset signal.

15. The pixel circuit according to claim 12, wherein: The voltage regulation includes adjusting the first level VGL_P in the gate driving circuit that outputs the first scanning signal to VGL_P+ΔV51 or adjusting the first level V0 of multiple clock signals in the gate driving circuit that outputs the first scanning signal to V0-ΔV61 to adjust the first scanning signal when the enable signal drops, wherein the width of ΔV51 is the same as the pulse width of the first signal.

16. The pixel circuit according to any one of claims 12 to 15, wherein: The pixel circuit also includes a second light emitting control circuit and a second reset circuit; The second light emitting control circuit is connected to the second terminal of the driving circuit and the light emitting element, and is configured to apply the voltage of the second terminal of the driving circuit to the light emitting element in response to a second light emitting control signal; The second reset circuit is connected to the second light emitting control circuit and the light emitting element, and is configured to apply a second reset voltage to the light emitting element in response to a second reset signal; The second light emitting control circuit and the second end of the driving circuit are connected to a third node, and the second reset circuit, the second light emitting control circuit and the light emitting element are connected to a fourth node; The voltage regulation further includes regulating the second reset voltage based on the enable signal and the first signal.

17. The pixel circuit according to claim 16, wherein: The voltage regulation includes regulating the second reset voltage VINIT2 to VINIT2+ΔV32 at a second phase difference from a falling edge of the enable signal when the enable signal falls, wherein the width of ΔV32 is the same as the pulse width of the first signal.

18. The pixel circuit according to claim 17, wherein: The second phase difference is determined based on the second scanning signal and the second reset signal.

19. The pixel circuit according to any one of claims 12 to 18, wherein: The voltage regulation further includes regulating the first level of the data signal Vdt to Vdt+ΔV41 at a position of a third phase difference from a falling edge of the enable signal when the enable signal falls, wherein the width of ΔV41 is the same as the pulse width of the first signal.

20. The pixel circuit according to claim 19, wherein: The third phase difference is determined based on the first scanning signal and the second scanning signal.

21. A display panel comprising a plurality of pixel units, wherein: Each pixel unit comprises the pixel circuit according to any one of claims 12-20.