Data access method of phase change memory, related device and storage medium

Abstract

The embodiment of the invention provides a data access method of a phase change memory, related equipment and a storage medium. In the embodiment of the invention, a small amount of SRAM (Static Random Access Memory) resources are added in a PCM (Pulse Code Modulation) controller, and in a writing stage, whether writing operation occurs in each coarse-grained unit time or not can be recorded by utilizing a bitmap provided by the SRAM; the Bloom filter provided by the SRAM can be used for recording whether write operation occurs in each fine-grained unit time or not. Therefore, in the subsequent reading stage, even under the condition of large bandwidth, the bitmap and the Bloom filter provided by the SRAM resource can be utilized to correctly distinguish the reading voltage of three gears designed for the phase change memory, so that the correct reading voltage responding to a read I / O request can be found at one time with a relatively large probability, the number of Read Retry times is remarkably reduced, and the reading efficiency of the phase change memory is improved. And the QoS of a service system using the phase change memory is greatly optimized under the condition that the time delay and bandwidth of the whole system are hardly influenced.

Description

(19) State Intellectual Property Office (12) Invention Patent Application (10) Application Publication Number (43) Application Publication Date (21) Application Number 202410192161.9 (22) Application Date 2024.02.20 (71) Applicant Hangzhou Aliyun Feitian Information Technology Co., Ltd. Address 311100 Room 553, 5th Floor, Building 3, No. 969, Wenyi West Road, Wuchang Street, Yuhang District, Hangzhou City, Zhejiang Province (72) Inventors Chen Xun, Li Shu, Chen Jian (74) Patent Agency Beijing Taihe Jiusi Intellectual Property Agency Co., Ltd. 11610 Patent Attorney Cai Li (51) Int.Cl. G11C 11 / 419 (2006.01) G11C 7 / 10 (2006.01) (54) Invention Title Data Access Method, Related Device and Storage Medium for Phase Change Memory (57) Abstract This application provides a data access method, related device and storage medium for phase change memory. In this embodiment, a small amount of SRAM resources are added to the PCM controller. During the write phase, the bitmap provided by the SRAM can record whether a write operation occurs at each coarse-grained unit of time; the Bloom filter provided by the SRAM can record whether a write operation occurs at each fine-grained unit of time. Thus, in the subsequent read phase, even under high bandwidth conditions, the bitmap and Bloom filter provided by the SRAM resources can correctly distinguish the three read voltage levels of the phase-change memory design, enabling the correct read voltage to be found in response to the read I / O request with a high probability on the first attempt. This significantly reduces the number of read retries and greatly optimizes the QoS of the service system using the phase-change memory without significantly affecting the overall system latency and bandwidth. Claims 5 pages, Description 31 pages, Drawings 13 pages, CN 120526820 A 2025.08.22 CN 1 20 52 68 20 A 1. A data access method for a phase-change memory, characterized in that the phase-change memory includes at least: a controller and a storage medium, the controller including at least a first static random access memory (SRAM) and a second SRAM, the phase-change memory being configured with a first read voltage, a second read voltage, and a third read voltage in ascending order of minimum post-write read latency; the method is executed by the controller, the method including: In response to a write I / O request including a write address, selecting a target bitmap from a first bitmap and a second bitmap included in the first SRAM according to the parity type of a coarse-grained unit time of the current timing, wherein the duration of the coarse-grained unit time is related to the minimum post-write read latency of the third read voltage, the first bitmap and the second bitmap being used to select the third read voltage during the read phase; storing a first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier represents...The following steps are performed: A write operation is executed on the target memory cell corresponding to the write address in the storage medium; a target Bloom filter is selected from the first and second Bloom filters included in the second SRAM based on the parity of the current fine-grained unit time, wherein the duration of the fine-grained unit time is related to the minimum post-write read latency of the second read voltage, and the first and second Bloom filters are used to select the first or second read voltage during the read phase; a second write operation identifier of the write address is stored in the target Bloom filter, wherein the second write operation identifier indicates that the target memory cell has performed a write operation; the data requested by the write I / O request is written into the target memory cell. 2. The method according to claim 1, characterized in that, selecting a target bitmap from the first bitmap and the second bitmap included in the first SRAM according to the odd / even type of the current coarse-grained unit time includes: if the odd / even type indicates that the current coarse-grained unit time is an odd-numbered coarse-grained unit time, selecting the first bitmap from the first bitmap and the second bitmap included in the first SRAM as the target bitmap, wherein the first bitmap is associated with the odd-numbered coarse-grained unit time; if the odd / even type indicates that the current coarse-grained unit time is an even-numbered coarse-grained unit time, selecting the second bitmap from the first bitmap and the second bitmap included in the first SRAM as the target bitmap, wherein the second bitmap is associated with the even-numbered coarse-grained unit time. 3. The method according to claim 1, characterized in that, storing the first write operation identifier of the write address in the target bitmap includes: shifting the write address to the right by M bits, where M is a positive integer; determining the first mapping position corresponding to the write address in the bit array of the target bitmap based on the right-shifted write address; setting the value of the bit at the first mapping position to the first write operation identifier of the write address, so as to store the first write operation identifier of the write address in the target bitmap. 4. The method according to any one of claims 1 to 3, characterized in that, before storing the first write operation identifier of the write address in the target bitmap, it further includes: if the current time is the start time of the coarse-grained unit time of the current timing, then clearing the target bitmap to zero. 5. The method according to claim 1, characterized in that, selecting a target Bloom filter from the first Bloom filter and the second Bloom filter included in the second SRAM according to the parity type of the fine-grained unit time of the current timing, includes: if the parity type indicates that the fine-grained unit time of the current timing is the odd-numbered fine-grained unit time, selecting the first Bloom filter as the target Bloom filter from the first Bloom filter and the second Bloom filter included in the second SRAM according to claim 1 / 5 page 2 CN 120526820 AThe target Bloom filter, wherein the first Bloom filter is associated with the odd-numbered fine-grained unit time; if the odd / even type indicates that the current fine-grained unit time is the even-numbered fine-grained unit time, the second Bloom filter is selected from the first and second Bloom filters included in the second SRAM as the target Bloom filter, the second Bloom filter being associated with the even-numbered fine-grained unit time. 6. The method according to claim 1, wherein storing the second write operation identifier of the write address in the target Bloom filter comprises: determining a second mapping position of the write address in the bit array of the target Bloom filter; setting the value of the bit at the second mapping position to the second write operation identifier of the write address, so as to store the second write operation identifier of the write address in the target Bloom filter. 7. The method according to any one of claims 1-3, 5 and 6, wherein before storing the second write operation identifier of the write address in the target Bloom filter, the method further comprises: if the current time is the start time of the current fine-grained unit time, then clearing the target Bloom filter. 8. A data access method for a phase-change memory (PCM), characterized in that the PCM includes at least a controller and a storage medium, the controller includes at least a first SRAM and a second SRAM, and the PCM is configured with a first read voltage, a second read voltage, and a third read voltage in ascending order of minimum write-to-read latency; the method is executed by the controller, and the method includes: responding to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bit map and a second bit map included in the first SRAM; if the first write operation identifier of the read address is not found in either the first bit map or the second bit map, selecting the third read voltage as the target read voltage; if the first write operation identifier of the read address is found in the first bit map and / or the second bit map, selecting one of the first read voltage and the second read voltage as the target read voltage based on the existence of a second write operation identifier of the read address in a first Bloom filter and a second Bloom filter included in the second SRAM; and performing a read operation on the storage cell corresponding to the read address in the storage medium according to the target read voltage. 9. The method according to claim 8, characterized in that, based on the existence of a second write operation identifier of the read address in the first Bloom filter and the second Bloom filter included in the second SRAM, selecting one of the first read voltage and the second read voltage as the target read voltage includes: searching for the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter; if the second write operation identifier of the read address is not found, then selecting the second read voltage as the target read voltage from the first read voltage and the second read voltage;If a second write operation identifier for the read address is found, then the first read voltage is selected as the target read voltage from the first read voltage and the second read voltage. 10. The method according to claim 9, characterized in that, after performing a read operation on the storage cell corresponding to the read address in the storage medium according to the target read voltage, it further includes: if the target read voltage is the first read voltage, performing error checking and correction ECC processing on the read data; if the ECC processing result indicates that the read data is incorrect, then sequentially using the second read voltage and the third read voltage as target read voltages, and performing the step of reading data from the storage cell corresponding to the read address in the storage medium according to the target read voltage, until the ECC processing result indicates that the read data is correct. 11. A data access method for a phase-change memory (PCM), characterized in that the PCM comprises at least: a controller and a storage medium, the controller comprising at least a third SRAM, the PCM being configured with a fourth read voltage and a fifth read voltage in ascending order of minimum post-write read latency; the method is executed by the controller, the method comprising: responding to a write I / O request including a write address, selecting a target bitmap from a third bitmap and a fourth bitmap included in the third SRAM according to the parity type of the current time unit, wherein the third bitmap is associated with the odd-numbered time unit, the fourth bitmap is associated with the even-numbered time unit, and the duration of the time unit is associated with the minimum post-write read latency of the fifth read voltage; storing a write operation identifier of the write address in the target bitmap, wherein the write operation identifier indicates that a write operation has been performed on the target storage cell corresponding to the write address in the storage medium; and writing the data requested by the write I / O request into the target storage cell. 12. The method according to claim 11, further comprising: responding to a read I / O request including a read address, searching for a write operation identifier of the read address in the third bitmap and the fourth bitmap; if the write operation identifier of the read address is not found in either the third bitmap or the fourth bitmap, selecting the fifth read voltage as the target read voltage; if the write operation identifier of the read address is found in the third bitmap and / or the fourth bitmap, selecting the fourth read voltage as the target read voltage; performing a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage. 13. A data access method for a phase-change memory, wherein the phase-change memory includes at least: a controller and a storage medium, the controller includes at least a third SRAM, the phase-change memory is configured with a fourth read voltage and a fifth read voltage in ascending order of minimum post-write read latency; the method is executed by the controller, the method comprising:In response to a write I / O request including a write address, a target Bloom filter is selected from the third and fourth Bloom filters included in the third SRAM based on the parity of the current time unit, wherein the third Bloom filter is associated with the odd-numbered time unit and the fourth Bloom filter is associated with the even-numbered time unit, and the duration of the time unit is associated with the minimum post-write read latency of the fifth read voltage; a write operation identifier of the write address is stored in the target Bloom filter, wherein the write operation identifier indicates that a write operation has been performed on the target memory cell corresponding to the write address in the storage medium; the data requested by the write I / O request is written into the target memory cell. 14. The method according to claim 13, further comprising: responding to a read I / O request including a read address, searching for a write operation identifier of the read address in the third Bloom filter and the fourth Bloom filter; if no write operation identifier of the read address is found in either the third Bloom filter or the fourth Bloom filter, selecting the fifth read voltage as the target read voltage; if a write operation identifier of the read address is found in either the third Bloom filter or the fourth Bloom filter, selecting the fourth read voltage as the target read voltage; and performing a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage. 15. The method according to claim 14, characterized in that, after performing a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage, it further includes: If the target read voltage is the fourth read voltage, performing error checking and correction ECC processing on the read data; If the ECC processing result indicates that the read data is incorrect, then using the fifth read voltage as the target read voltage, and re-executing the step of reading data from the memory cell corresponding to the read address in the storage medium according to the target read voltage. 16. A data access method for a phase-change memory, characterized in that the phase-change memory includes at least: a controller and a storage medium, the controller including at least a first SRAM and a second SRAM, the phase-change memory being configured with a first read voltage, a second read voltage, and a third read voltage in ascending order of minimum post-write read latency; the method is executed by the controller, the method comprising: in response to a write I / O request including a write address, selecting a target bitmap from a first bitmap and a second bitmap included in the first SRAM according to the parity type of a coarse-grained unit time of the current timing, wherein the duration of the coarse-grained unit time is related to the minimum post-write read latency of the third read voltage, the first bitmap and the second bitmap being used to select the third read voltage during a read phase; storing a first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier represents...The following steps are performed: First, a write operation is executed on the target memory cell corresponding to the write address in the storage medium. Second, based on the target arrangement position of the sub-unit time within the current fine-grained unit time, a target Bloom filter located at the target arrangement position is selected from the Bloom filter group included in the second SRAM. The fine-grained unit time comprises n sequentially divided sub-unit times, the duration of which is related to the minimum write-to-read latency of the second read voltage. The Bloom filter group is used to select the first read voltage or the second read voltage during the read phase, and comprises n sequentially arranged Bloom filters. Third, a second write operation identifier of the write address is stored in the target Bloom filter, whereby the second write operation identifier indicates that the target memory cell has undergone a write operation. Finally, the data requested by the write I / O request is written into the target memory cell. 17. A data access method for a phase-change memory (PCM), characterized in that the PCM includes at least a controller and a storage medium, the controller including at least a first SRAM and a second SRAM, and the PCM is configured with a first read voltage, a second read voltage, and a third read voltage in ascending order of minimum write-to-read latency; the method is executed by the controller, and the method includes: responding to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bit map and a second bit map included in the first SRAM; if the first write operation identifier of the read address is not found in either the first bit map or the second bit map, selecting the third read voltage as a target read voltage; if the first write operation identifier of the read address is found in the first bit map and / or the second bit map, selecting one of the first read voltage and the second read voltage as the target read voltage based on the existence of a second write operation identifier of the read address in a Bloom filter group included in the second SRAM; and performing a read operation on the storage cell corresponding to the read address in the storage medium according to the target read voltage. 18. A data access method for a phase-change memory, characterized in that the phase-change memory includes at least: a controller and a storage medium, the controller including at least a third SRAM, the phase-change memory being configured with a fourth read voltage and a fifth read voltage in ascending order of minimum write-after-read latency; the method is executed by the controller, the method comprising: in response to a write I / O request including a write address, selecting a target Bloom filter located at the target arrangement position in a Bloom filter group included in the third SRAM according to the target arrangement position of the sub-unit time to which the current time belongs in the current time unit, wherein the unit time includes n sequentially divided sub-unit times, the duration of the unit time is related to the minimum write-after-read latency of the fifth read voltage, and the Bloom filter group includes n sequentially arranged Bloom filters;The write operation identifier of the write address is stored in the target Bloom filter, wherein the write operation identifier indicates that a write operation has been performed on the target memory cell corresponding to the write address in the storage medium; the data requested to be written by the write I / O request is written into the target memory cell. 19. A data access method for a phase-change memory, characterized in that the phase-change memory includes at least: a controller and a storage medium, the controller includes at least a third SRAM, and the phase-change memory is configured with a fourth read voltage and a fifth read voltage in ascending order of minimum post-write read latency; the method is executed by the controller, the method including: in response to a read I / O request including a read address, searching for a write operation identifier of the read address in a Bloom filter group included in the third SRAM; if no write operation identifier of the read address is found in the Bloom filter group, then selecting the fifth read voltage as the target read voltage; if a write operation identifier of the read address is found in the Bloom filter group, then selecting the fourth read voltage as the target read voltage; performing a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage. 20. A phase-change memory, characterized in that it comprises at least: a controller and a storage medium, the controller comprising at least one SRAM; the controller being configured to execute the steps of the method according to any one of claims 1-19. 21. A memory database system, characterized in that it comprises at least: the phase-change memory according to claim 20. 22. A cloud service product, characterized in that it comprises at least: the memory database system according to claim 21. 23. A computer-readable storage medium storing a computer program, characterized in that, when the computer program is executed by a processor, it causes the processor to implement the steps of the method according to any one of claims 1-19. Claims 5 / 5 Page 6 CN 120526820 A Data Access Method, Related Devices, and Storage Medium for Phase-Change Memory Technical Field

[0001] This application relates to the field of computer technology, and more particularly to a data access method, related devices, and storage medium for a phase-change memory. Background Technology

[0002] Phase Change Memory (PCM) is a new type of memory that uses phase change materials as storage media. It stores 0 bits or 1 bits by inducing a reversible transition between a high-resistivity amorphous state and a low-resistivity crystalline state in the phase change material. Due to its advantages such as low latency, byte accessibility, long lifespan, low cost, large capacity, and non-volatility, PCM is increasingly widely used. For example, more and more cloud service products use Main Memory Database (MMDB) systems, which commonly use PCM, thus effectively reducing the overall TCO (Total Cost of Ownership) of cloud service products.Ownership (Total Cost of Ownership).

[0003] Due to its material properties, phase-change memory (PCM) suffers from read voltage drift. Read voltage drift refers to the phenomenon that the read voltage required to read the correct data from the storage cell (cell) that has been written with data in the PCM storage medium drifts over time. In practical applications, multiple read voltage levels are usually designed to solve the read voltage drift problem. When responding to read I / O (Input / Output) requests, PCM uses Read Retry to continuously retry reading operations on the storage cell in the PCM storage medium using different read voltage levels until the correct read voltage is found and the correct data is read using the correct read voltage.

[0004] However, if most read I / O requests require multiple Read Retry attempts to find the correct read voltage, the I / O latency will increase, greatly degrading the QoS (Quality of Service) of the service system using PCM.

[0005] This application provides a data access method, related device, and storage medium for a phase-change memory (PCM), which can find the correct read voltage in response to a read I / O request with a high probability in one go, thereby greatly optimizing the QoS of a service system using the PCM.

[0006] An embodiment of this application provides a data access method for a PCM, wherein the PCM includes at least a controller and a storage medium, the controller includes at least a first SRAM and a second SRAM, and the PCM is configured with a first read voltage, a second read voltage, and a third read voltage with a minimum post-write read latency of small to large; the method is executed by the controller, and the method includes: in response to a write I / O request including a write address, selecting a target bitmap from a first bitmap and a second bitmap included in the first SRAM according to the parity type of the current coarse-grained unit time, wherein the duration of the coarse-grained unit time is related to the minimum post-write read latency of the third read voltage, and the first bitmap and the second bitmap Used to select a third read voltage during the read phase; a first write operation identifier of the write address is stored in the target bitmap, wherein the first write operation identifier indicates that the target memory cell corresponding to the write address in the storage medium has performed a write operation; a target Bloom filter is selected from the first Bloom filter and the second Bloom filter included in the second SRAM according to the parity type of the fine-grained unit time of the current timing, wherein the duration of the fine-grained unit time is related to the minimum post-write read latency of the second read voltage, and the first Bloom filter and the second Bloom filter are used to select the first read voltage or the second read voltage during the read phase; a second write operation identifier of the write address is stored in the target Bloom filter, wherein, Specification 1 / 31 page 7 CN 120526820 AThe second write operation identifier indicates that the target memory cell has performed a write operation; the data requested by the write I / O request is written into the target memory cell.

[0007] This application embodiment also provides a data access method for a phase change memory, wherein the phase change memory includes at least: a controller and a storage medium, the controller includes at least a first SRAM and a second SRAM, and the phase change memory is configured with a first read voltage, a second read voltage and a third read voltage in ascending order of minimum write-to-read latency; the method is executed by the controller, and the method includes: in response to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bit map and a second bit map included in the first SRAM; if the first write operation identifier of the read address is not found in either the first bit map or the second bit map, then selecting the third read voltage as the target read voltage; if the first write operation identifier of the read address is found in the first bit map and / or the second bit map, then selecting one of the first read voltage and the second read voltage as the target read voltage based on the existence of the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter included in the second SRAM; performing a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0008] This application embodiment also provides a data access method for a phase-change memory, wherein the phase-change memory includes at least a controller and a storage medium, the controller includes at least a third SRAM, and the phase-change memory is configured with a fourth read voltage and a fifth read voltage with a minimum write-after-read latency in ascending order; the method is executed by the controller, and the method includes: in response to a write I / O request including a write address, selecting a target bitmap from a third bitmap and a fourth bitmap included in the third SRAM according to the parity type of the current time unit, wherein the third bitmap is associated with the odd-numbered time unit, the fourth bitmap is associated with the even-numbered time unit, and the duration of the time unit is associated with the minimum write-after-read latency of the fifth read voltage; storing a write operation identifier of the write address in the target bitmap, wherein the write operation identifier indicates that a write operation has been performed on the target storage cell corresponding to the write address in the storage medium; and writing the data requested by the write I / O request into the target storage cell.

[0009] This application embodiment also provides a data access method for a phase-change memory (PCM). The PCM includes at least a controller and a storage medium. The controller includes at least a third SRAM. The PCM is configured with a fourth read voltage and a fifth read voltage, with the minimum write-after-read latency increasing from small to large. The method is executed by the controller and includes: in response to a write I / O request including a write address, selecting a target Bloom filter from a third Bloom filter and a fourth Bloom filter included in the third SRAM according to the parity type of the current time unit, wherein the third Bloom filter is associated with the odd-numbered time unit, the fourth Bloom filter is associated with the even-numbered time unit, and the duration of the time unit is related to the minimum write-after-read latency of the fifth read voltage.Close; store the write operation identifier of the write address in the target Bloom filter, where the write operation identifier indicates that the target storage cell corresponding to the write address in the storage medium has performed a write operation; write the data requested by the write I / O request to the target storage cell.

[0010] This application embodiment also provides a data access method for a phase-change memory (PCM). The PCM includes at least a controller and a storage medium. The controller includes at least a first SRAM and a second SRAM. The PCM is configured with a first read voltage, a second read voltage, and a third read voltage, with the minimum write-after-read latency increasing from small to large. The method is executed by the controller and includes: in response to a write I / O request including a write address, selecting a target bitmap from a first bitmap and a second bitmap included in the first SRAM according to the parity type of the current coarse-grained unit time, wherein the duration of the coarse-grained unit time is related to the minimum write-after-read latency of the third read voltage, and the first bitmap and the second bitmap are used to select the third read voltage during the read phase; storing a first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier indicates that the target memory cell corresponding to the write address in the storage medium has performed a write operation; selecting a target Bloom filter located at the target arrangement position in the fine-grained unit time of the current time according to the target arrangement position of the sub-unit time to which the current time belongs in the current timing, wherein... The fine-grained unit time includes n sequentially divided sub-unit times. The duration of the fine-grained unit time is related to the minimum post-write read latency of the second read voltage as stated on page 2 / 31 of the specification (8 CN 120526820 A). The Bloom filter set is used to select the first read voltage or the second read voltage during the read phase. The Bloom filter set includes n sequentially arranged Bloom filters. The second write operation identifier of the write address is stored in the target Bloom filter, wherein the second write operation identifier indicates that the target memory cell has performed a write operation. The data requested by the write I / O request is written into the target memory cell.

[0011] This application embodiment also provides a data access method for a phase-change memory, the phase-change memory including at least a controller and a storage medium, the controller including at least a first SRAM and a second SRAM, the phase-change memory being configured with a first read voltage, a second read voltage, and a third read voltage in ascending order of minimum write-after-read latency; the method is executed by the controller, the method including: in response to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bit map and a second bit map included in the first SRAM; if the first write operation identifier of the read address is not found in either the first bit map or the second bit map, then selecting the third read voltage as the target read voltage ...If a first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, then based on the existence of a second write operation identifier of the read address in the Bloom filter group included in the second SRAM, one of the first read voltage and the second read voltage is selected as the target read voltage; and a read operation is performed on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0012] This application embodiment also provides a data access method for a phase-change memory, the phase-change memory including at least a controller and a storage medium, the controller including at least a third SRAM, the phase-change memory being configured with a fourth read voltage and a fifth read voltage with minimum write-after-read latency from small to large; the method is executed by the controller, the method including: in response to a write I / O request including a write address, selecting a target Bloom filter located at the target arrangement position in the Bloom filter group included in the third SRAM according to the target arrangement position of the sub-unit time to which the current time belongs in the current time unit, wherein the unit time includes n sub-unit times divided in sequence, the duration of the unit time is related to the minimum write-after-read latency of the fifth read voltage, and the Bloom filter group includes n Bloom filters arranged in sequence; storing a write operation identifier of the write address in the target Bloom filter, wherein the write operation identifier indicates that the target memory cell corresponding to the write address in the storage medium has performed a write operation; writing the data requested by the write I / O request into the target memory cell.

[0013] This application embodiment also provides a data access method for a phase-change memory, the phase-change memory including at least a controller and a storage medium, the controller including at least a third SRAM, the phase-change memory being configured with a fourth read voltage and a fifth read voltage in ascending order of minimum write-to-read latency; the method is executed by the controller, the method including: in response to a read I / O request including a read address, searching for a write operation identifier of the read address in a Bloom filter group included in the third SRAM; if no write operation identifier of the read address is found in the Bloom filter group, then selecting the fifth read voltage as the target read voltage; if a write operation identifier of the read address is found in the Bloom filter group, then selecting the fourth read voltage as the target read voltage; performing a read operation on the storage cell corresponding to the read address in the storage medium according to the target read voltage.

[0014] This application embodiment also provides a phase-change memory, including at least a controller and a storage medium, the controller including at least one SRAM; the controller is used to execute the steps in the data access method for the phase-change memory.

[0015] This application embodiment also provides a memory database system, including at least the phase-change memory provided in this application embodiment.

[0016] This application embodiment also provides a cloud service product, including at least: the in-memory database system provided in this application embodiment.

[0017] This application embodiment also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to implement the steps in the phase-change memory data access method.

[0018] In this application embodiment, a small amount of SRAM (Static Random Access Memory) resources are added to the PCM controller. During the write phase, the bitmap provided by the SRAM can be used to record whether a write operation has occurred at each coarse-grained unit of time; the Bloom filter provided by the SRAM can be used to record whether a write operation has occurred at each fine-grained unit of time. In this way, during the subsequent read phase, even under high bandwidth conditions, the bitmap and Bloom filter provided by the SRAM resources can correctly distinguish the three read voltage levels of the phase-change memory design, achieving a high probability of finding the correct read voltage to respond to the read I / O request at once, significantly reducing the number of read retryes, and greatly optimizing the QoS of the service system using the phase-change memory without affecting the overall system latency and bandwidth.

[0019] The accompanying drawings, which are included to provide a further understanding of this application and constitute a part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an improper limitation of this application. In the accompanying drawings:

[0020] Figure 1 is a schematic diagram of the read voltage drift of a phase-change memory;

[0021] Figure 2 is a structural schematic diagram of a phase-change memory provided in an embodiment of this application;

[0022] Figure 3 is a flowchart of a data access method for a phase-change memory provided in an embodiment of this application;

[0023] Figure 4 is a schematic diagram of one process of data access for a phase-change memory provided in an embodiment of this application;

[0024] Figure 5 is a schematic diagram of another process of data access for a phase-change memory provided in an embodiment of this application;

[0025] Figure 6 is a flowchart of another data access method for a phase-change memory provided in an embodiment of this application;

[0026] Figure 7 is a flowchart of another data access method for a phase-change memory provided in an embodiment of this application;

[0027] Figure 8 is a flowchart of another data access method for a phase-change memory provided in an embodiment of this application;

[0028] Figure 9 is a flowchart of another data access method for a phase-change memory provided in an embodiment of this application;

[0029] Figure 10 is a flowchart of another data access method for a phase-change memory provided in an embodiment of this application;

[0030] Figure 11 is a flowchart of another data access method for a phase-change memory provided in an embodiment of this application;

[0031] Figure 12 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application;

[0032] Figure 13 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application;

[0033] Figure 14 is a schematic diagram of another process for data access of phase-change memory provided in an embodiment of this application;

[0034] Figure 15 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application;

[0035] Figure 16 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application;

[0036] Figure 17 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application;

[0037] Figure 18 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application;

[0038] Figure 19 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application;

[0039] Figure 20 is a schematic diagram of the structure of another phase-change memory provided in an embodiment of this application. Detailed Description

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments of this application and corresponding accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] In the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the access relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. In the text description on page 4 / 31 of this application specification, 10 CN 120526820 A, the character " / " generally indicates that the associated objects before and after are in an "or" relationship. In addition, in the embodiments of this application, "first", "second", "third", etc. are only used to distinguish the contents of different objects and have no other special meaning.

[0042] Figure 1 is a schematic diagram of the read voltage drift of the phase change memory. In the coordinate system shown in Figure 1, the horizontal axis corresponds to time t, and the vertical axis corresponds to the read voltage Vt. When data is written into a cell of a phase-change memory, the read voltage (drift) used to read the correct data from the cell drifts over time. The dashed line corresponding to a 0-bit drift represents the curve of the read voltage changing over time when the correct 0-bit is read from the cell; the solid line corresponding to a drift represents the curve of the read voltage changing over time when the correct 1-bit is read from the cell. If data is read from a cell in the phase-change memory at different times according to a given read voltage Vread, it is easy to read incorrect data.

[0043] In practical applications, to address the read voltage drift issue, multiple read voltage levels are typically designed. Each read voltage corresponds to a write-to-read delay time range, and the write-to-read delay time ranges covered by multiple read voltage levels may partially overlap. Write-to-read delay refers to the length of time between data writing and data reading. For example, if data is written at 18:14:30 on 2023 / 11 / 29 and read at 18:14:31 on 2023 / 11 / 29, the write-to-read delay is 1 second. Table 1 lists the write-to-read delays corresponding to successful and failed reads at different read voltages. Taking multiple read voltage levels, denoted as Vread1, Vread2, and Vread3, as an example, the write-after-read latency range for Vread1 is 1µs to 1000ms; for Vread2, it's 100ms to 1000s; and for Vread3, it's 100s to 12 hours. For each read voltage, for read I / O requests triggered within the corresponding write-after-read latency range, using that voltage guarantees the correctness of the read data (i.e., a successful read), ensuring the correctness of read I / O requests triggered within that time range. Conversely, for read I / O requests triggered outside the corresponding write-after-read latency range, using that voltage will fail to read the correct data (i.e., a read failure).

[0044] Table 1

[0045] Write TO Read Delay (ms) Vread1 Vread2 Vread3 0.001 Read passed Read failed Read failed 0.01 Read passed Read failed Read failed 0,1 Read passed Read failed Read failed 1 Read passed Read failed Read failed 10 Read passed Read failed Read failed 100 Read passed Read passed Read failed 1000 Read passed Read passed Read failed 10000 Read passed Read passed Read failed 100000 Read failed Read passed Read passed 1000000 Read failed Read passed Read passed 10800000 Read failed Read failed Read passed 43200000 Read failed Read failed Read passed

[0046] In practical applications, by covering the time range of the post-write read delay by multiple read voltage levels, the read correctness of all I / O requests within a certain range of post-write read time width can be guaranteed. The write-after-read latency refers to the overall time range defined by the write-after-read delay covered by all read voltage levels. For example, Vread1 corresponds to the write-after-read latency...Page 5 / 31, CN 120526820 A: The read latency range is 1µs to 1000ms; the write-after-read latency range for Vread2 is 100ms to 1000s, and the write-after-read latency range for Vread3 is 100s to 12h (hours), so the write-after-read time width is 1µs to 12h.

[0047] When the write-after-read time width is exceeded, the Retention mechanism is used to ensure that all storage units of the PCM can be refreshed once within the write-after-read time width, thereby ensuring that the time interval between the write operation time and the read operation time of all storage units of the PCM will not exceed the write-after-read time width. Among them, Retention (retention time) is generally used to represent the time range within which the storage medium can be correctly read after erasing and writing. The longer the better, it is one of the important indicators of storage medium reliability.

[0048] The read voltage drift problem can be better solved by using multiple levels of read voltage. In practical applications, when a phase-change memory (PCM) responds to a read I / O request, it uses a read voltage level to initiate a read operation on the storage cell in the PCM's storage medium to read data, and performs ECC (Error Checking and Correcting) processing on the read data. If the ECC result indicates that the read data is incorrect, a new read voltage level is used, and a new read voltage level is used to re-initiate a read operation on the storage cell in the PCM's storage medium to read data; the above steps are repeated until the correct data is read. The above data reading method can be understood as a Read Retry method, which uses different read voltage levels to continuously re-attempt to initiate a read operation on the storage cell in the PCM's storage medium until the correct read voltage is found and the correct data is read using the correct read voltage.

[0049] However, if most read I / O requests need to go through multiple Read Retry operations to find the correct read voltage, then the I / O latency will increase, which will greatly degrade the QoS (Quality of Service) of the service system using the phase-change memory.

[0050] To this end, embodiments of this application provide a data access method, related devices, and storage medium for a phase-change memory (PCM). In this embodiment, a small amount of SRAM resources are added to the PCM controller. During the write phase, the bitmap provided by the SRAM can be used to record whether a write operation has occurred at each coarse-grained unit of time; the Bloom filter provided by the SRAM can be used to record whether a write operation has occurred at each fine-grained unit of time. Thus, in the subsequent read phase, even with a large bandwidth...In this case, the bitmap and Bloom filter provided by SRAM resources can correctly distinguish the read voltage of the three levels of the phase-change memory design, so as to find the correct read voltage to respond to the read I / O request with a high probability at one time, significantly reduce the number of read retry, and greatly optimize the QoS of the service system using the phase-change memory without affecting the latency and bandwidth of the overall system.

[0051] The technical solutions provided by the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0052] Figure 2 is a schematic diagram of the structure of a phase-change memory provided by an embodiment of this application. Referring to Figure 2, the phase-change memory includes at least a controller and a storage medium. The controller of the PCM includes, but is not limited to, MCU (Microcontroller), CPU (Central Processing Unit) and MPU (Microprocessor Unit). The storage space of the storage medium provides multiple storage cells, and the storage cells can store 0 bits or 1 bits.

[0053] During the data writing phase, the host sends a write I / O request including the write address to the phase-change memory (PCM). The PCM writes the data requested by the write I / O request into the storage cell corresponding to the write address in the PCM's storage medium. During the data reading phase, the host sends a read I / O request including the read address to the PCM. The PCM initiates a read operation on the storage cell corresponding to the read address in the PCM's storage medium according to the read voltage to read the written data and returns it to the host. In addition, the host can receive write I / O requests or read I / O requests from service systems using the PCM and forward them to the PCM. Service systems using the PCM are, for example, cloud service products, including but not limited to: cloud servers, cloud database systems, or cloud desktop systems, etc.

[0054] In this embodiment, the host includes, for example, but is not limited to: computer systems in any device form such as laptops, desktop computers, smartphones, tablets, industrial computers, servers, etc. The host system and the phase-change memory can be located in the same device or in different devices; there is no restriction on this.

[0055] In practical applications, the PCM controller can also include more functional modules. For example, the PCM controller may also include: a front-end control module, an address mapping module, an ECC module, a media manager module, and a global timer, etc., without restriction.

[0056] Among them, the front-end control module completes the parsing of read I / O requests and write I / O requests transmitted from the host and sends them to the subsequent levels, such as to the address mapping module and the ECC module.

[0057] The address mapping module is used to convert the logical address (LA) sent by the host into a physical address (PA). Specifically, it converts the read address in LA form in the read I / O request into a read address in PA form; and it converts the write address in LA form in the write I / O request into a write address in PA form. The read address refers to the address information of the storage unit to be read during the data reading phase; the write address refers to the address information of the storage unit to be written during the data writing phase.

[0058] The ECC module encodes the write data requested by the write I / O request, and the ECC module also uses the ECC algorithm to determine the redundancy check bits of the write data. The encoded write data and its redundancy check bits are written into the storage unit corresponding to the write address in the PCM storage medium. During the data reading phase, the encoded write data and its redundancy check bits are read from the PCM's storage medium. The ECC module decodes the encoded write data to obtain the write data. The ECC module also uses the ECC algorithm to re-determine the redundancy check bits of the read write data. Based on the comparison between the redundancy check bits re-determined using the ECC algorithm and the redundancy check bits read from the storage medium, it determines whether the encoded write data read from the PCM's storage medium is correct. For more information on the ECC module, please refer to the relevant technologies.

[0059] The Media Manager module is used for storage medium management, such as, but not limited to, using a Retention mechanism to refresh the PCM's storage medium.

[0060] A global timer is used for timing, with no restriction on the timing start point; for example, timing begins after the PCM starts.

[0061] In this embodiment, the PCM controller includes at least a first SRAM and a second SRAM; the first SRAM is an SRAM (Static Random Access Memory) that provides a bitmap; the second SRAM is an SRAM that provides a Bloom filter.

[0062] A bitmap is a commonly used data structure used to represent a set, where each element corresponds to a binary bit, that is, a bit is used to mark the value corresponding to an element, and the key is the element. If the element exists in the set, the corresponding binary bit is 1, otherwise it is 0. In short, a bit (0 or 1) is used to indicate whether an element has appeared. Since data is stored in units of bits, storage space can be greatly saved.

[0063] A Bloom filter is a special Hash Table used to quickly check whether an element belongs to a set.In a certain set. It can quickly determine whether an element is in a large set, and the judgment speed is fast and does not occupy too much memory space. The main principle of the Bloom filter is to use a set of hash functions to map the elements to the index positions in a set of bit arrays. When checking whether an element is in the set, the element is hashed, and then the value of the bit array corresponding to the hash value is checked to see if it is 1. If the value of the bit array corresponding to the hash value is 1, then the element may be in the set; otherwise, the element is definitely not in the set. Since the mapping of hash functions may collide, the Bloom filter may make a false judgment, that is, judge an element that is not in the set as being in the set. However, the Bloom filter will not miss a judgment, that is, it will not judge an element that is in the set as not being in the set.

[0064] In this embodiment, the first SRAM can provide two bitmaps, namely the first bitmap and the second bitmap. The second SRAM can provide two Bloom filters, namely the first Bloom filter and the second Bloom filter. Thus, even with a large bandwidth (page 7 / 31, CN 120526820 A in the specification), using two bitmaps and two Bloom filters with less SRAM resources, the three read voltage levels of the phase-change memory design can be correctly distinguished. This allows for a higher probability of finding the correct read voltage to respond to read I / O requests in one go, significantly reducing the number of read retries. This greatly optimizes the QoS of the service system using the phase-change memory without significantly affecting the overall system latency and bandwidth.

[0065] When the phase-change memory controller includes at least a first SRAM and a second SRAM, the three read voltage levels can be correctly distinguished. The time range of the read voltage's post-write read latency falls between the minimum and maximum post-write read latency, meaning the post-write read latency of the read voltage is greater than or equal to the minimum post-write read latency and less than or equal to the maximum post-write read latency.

[0066] Specifically, the phase-change memory is configured with a first read voltage, a second read voltage, and a third read voltage, with the minimum post-write read latency increasing from smallest to largest. It is understood that, ordered by minimum post-write read latency from smallest to largest, they are: first read voltage, second read voltage, and third read voltage. In practical applications, the time ranges of the post-write read latency corresponding to any two read voltages may not overlap. Further optionally, the time range of the post-write read latency covered by the first read voltage partially overlaps with the time range of the post-write read latency covered by the second read voltage, and / or, the time range of the post-write read latency covered by the second read voltage partially overlaps with the time range of the post-write read latency covered by the third read voltage. It is understood that the minimum post-write read latency of the second read voltage is less than the maximum post-write read latency of the first read voltage, and / or, the minimum post-write read latency of the third read voltage is less than the maximum post-write read latency of the second read voltage. For example, the post-write read latency corresponding to the first read voltage Vread1...The read latency ranges from 1µs to 1000ms; the write-after-read latency corresponding to the second read voltage Vread2 ranges from 100ms to 1000s, and the write-after-read latency corresponding to the third read voltage Vread3 ranges from 100s to 12 hours. The minimum write-after-read latency of 100ms for the second read voltage Vread2 is less than the maximum write-after-read latency of 1000ms for the first read voltage Vread1. The minimum write-after-read latency of 100s for the third read voltage Vread3 is less than the maximum write-after-read latency of 1000s for the second read voltage Vread2.

[0067] In this embodiment, two unit times with different granularities are defined: coarse-grained unit time and fine-grained unit time. The duration of the coarse-grained unit time is related to the minimum write-after-read delay of the third read voltage. For example, the duration of the coarse-grained unit time is equal to the minimum write-after-read delay of the third read voltage, or the duration of the coarse-grained unit time is obtained by increasing or decreasing the minimum write-after-read delay of the third read voltage. There is no limitation on this. The duration of the fine-grained unit time is related to the minimum write-after-read delay of the second read voltage. For example, the duration of the fine-grained unit time is equal to the minimum write-after-read delay of the second read voltage, or the duration of the fine-grained unit time is obtained by increasing or decreasing the minimum write-after-read delay of the second read voltage. There is no limitation on this.

[0068] In this embodiment, two bitmaps provided by the first SRAM can be used to record whether a write operation occurs in each coarse-grained unit time; two Bloom filters provided by the second SRAM can be used to record whether a write operation occurs in each fine-grained unit time. The two bitmaps provided by the first SRAM can distinguish between (Vread1 / Vread2) and Vread3, that is, determine that the required read voltage is either the third read voltage Vread3, the second read voltage Vread2, or the first read voltage Vread1. The two Bloom filters provided by the second SRAM can distinguish between Vread1 and (Vread2 / Vread3), that is, determine that the required read voltage is either the first read voltage Vread1, the second read voltage Vread2, or the third read voltage Vread3. Combining the first SRAM and the second SRAM can correctly distinguish the three read voltage levels.

[0069] The write process of the phase-change memory is described below with reference to FIG3. FIG3 is a flowchart of a data access method for a phase-change memory provided in an embodiment of this application. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a first SRAM and a second SRAM. The phase-change memory is configured with a first read voltage, a second read voltage, and a third read voltage, with the minimum write-after-read latency increasing from small to large. The method is executed by the controller. Referring to Figure 3, the method may include the following steps:

[0070] 301. In response to a write I / O request including a write address, the method is configured according to the parity class of the current time unit.Page 8 / 31, CN 120526820 Type A, selects the target bitmap from the first bitmap and the second bitmap included in the first SRAM, wherein the duration of the coarse-grained unit time is related to the minimum post-write read delay of the third read voltage, and the first bitmap and the second bitmap are used to select the third read voltage during the read phase.

[0071] Specifically, the PCM controller receives and responds to the write I / O request including the write address sent by the host. During the response process, the write address in the form of LA in the write I / O request can be converted into the write address in the form of PA; the ECC module can also be called to encode the write data requested by the write I / O request, and the redundancy check bit of the write data can be determined using the ECC algorithm, but it is not limited to this.

[0072] In this embodiment, when the PCM controller responds to the write I / O request, it determines which coarse-grained unit time and parity type the current timing coarse-grained unit time is based on the current timing and the timing start time. The timing start time can be flexibly set as needed. For example, the timing start time is the PCM startup time.

[0073] If the current coarse-grained unit time is of odd type, it means that the current coarse-grained unit time is the odd-numbered coarse-grained unit time; if the current coarse-grained unit time is of even type, it means that the current coarse-grained unit time is the even-numbered coarse-grained unit time. Taking a coarse-grained unit time of 100s as an example, the time ranges corresponding to the odd-numbered coarse-grained unit time are: 0~100s, 200s~300s, 400s~500s…; the time ranges corresponding to the even-numbered coarse-grained unit time are: 100s~200s, 300s~400s, 500s~600s….

[0074] For example, the implementation of selecting the target bitmap from the first bitmap and the second bitmap included in the first SRAM according to the parity type of the current coarse-grained unit time is as follows: if the parity type indicates that the current coarse-grained unit time is the odd-numbered coarse-grained unit time, the first bitmap is selected from the first bitmap and the second bitmap included in the first SRAM as the target bitmap, and the first bitmap is related to the odd-numbered coarse-grained unit time; if the parity type indicates that the current coarse-grained unit time is the even-numbered coarse-grained unit time, the second bitmap is selected from the first bitmap and the second bitmap included in the first SRAM as the target bitmap, and the second bitmap is related to the even-numbered coarse-grained unit time.

[0075] 302. Save the first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier indicates that the target storage cell corresponding to the write address in the storage medium has performed a write operation.

[0076] Specifically, when saving the first write operation identifier of the write address in the target bitmap, the write address is used as the key to callThe mapping position of the write address in the target bitmap is determined by various mapping functions such as Hash function in the target bitmap. The value of the bit at the mapping position of the write address in the bit array of the target bitmap is set to 1. 1 bit in the bit array of the target bitmap represents the first write operation identifier of the write address, so as to save the first write operation identifier of the write address in the target bitmap. It can be understood that if 0 bit in the bit array of the target bitmap, it means that no write address has been recorded.

[0077] For coarse-grained unit time, since the time range of coarse-grained unit time is relatively large, it is difficult to record each write address without affecting the bandwidth and latency of the service system using PCM. Therefore, a mapping table-like approach is adopted to expand the granularity of each bit recorded in the bit array of the target bitmap. That is, each bit can be used to determine whether the target storage unit corresponding to the write address within a certain address range has performed a write operation. From the perspective of the entire PCM, the probability of correctly distinguishing the read voltage can be improved.

[0078] Based on the above, optionally, when saving the first write operation identifier of the write address in the target bitmap, the write address can be shifted right by M bits, where M is a positive integer; the first mapping position corresponding to the write address in the bit array of the target bitmap is determined based on the right-shifted write address; the value of the bit at the first mapping position is set as the first write operation identifier of the write address, so as to save the first write operation identifier of the write address in the target bitmap.

[0079] Specifically, the write address after shifting right by M bits is used as the Key, and various mapping functions such as the Hash function in the target bitmap are called to determine the mapping position corresponding to the write address in the bit array of the target bitmap (here referred to as the first mapping bit setting), and the value of the bit at the first mapping position corresponding to the write address in the bit array of the target bitmap is set to 1. 1 bit in the bit array of the target bitmap represents the first write operation identifier of each write address within the range of 2^M, so as to save the first write operation identifier of the write address in the target bitmap.

[0080] Further optionally, before saving the first write operation flag of the write address in the target bitmap, the above method further includes: if the current time is the start time of the current coarse-grained unit time, then the target bitmap is cleared, that is, the value of each bit in the bit array of the target bitmap is set to 0. If the current time is not the start time of the current coarse-grained unit time, the first write operation flag of the write address is directly saved in the target bitmap. In this way, it can be ensured that the first write operation flag of the write address within the time range corresponding to the current coarse-grained unit time is stored well in the target bitmap, and the read correctness of the I / O request is better guaranteed.

[0081] For better understanding, it is explained in conjunction with Figure 4. Referring to Figure 4, if the time of the odd-numbered coarse-grained unit time is...Within the specified time range, when the PCM controller receives a write I / O request from the host, it shifts the write address to the right by M bits, uses the shifted write address as the key, and calls the hash function of the first bit diagram to map the key, obtaining the mapping position corresponding to the write address in the bit array of the first bit diagram. Taking a bit array of the first bit diagram with a length of 12 bits as an example, the mapping position corresponding to the write address in the bit array of the first bit diagram is the 4th bit. Then, the value of the 4th bit in the bit array of the first bit diagram is set to 1 to indicate that the write address corresponding to the write I / O request has been written; each bit in the bit array of the first bit diagram represents whether the address within the range of 2^M has been written.

[0082] In addition, after the PCM controller receives a write I / O request from the host, if the current time is the start time of the odd-numbered coarse-grained unit time, it can first clear the first bit diagram and then call the first bit diagram. If the current time is not the start time of the odd-numbered coarse-grained unit time, it can directly call the first bit diagram.

[0083] Referring to Figure 4, if the PCM controller receives a write I / O request from the host within the even-numbered coarse-grained unit time range, it shifts the write address to the right by M bits, uses the write address after the M-bit shift as the Key, and calls the Hash function of the second bitmap to map the Key, obtaining the mapping position corresponding to the write address in the bit array of the second bitmap. Taking the length of the bit array of the second bitmap as 12 bits as an example, the mapping position corresponding to the write address in the bit array of the second bitmap is the 6th bit. Then, the value of the 6th bit in the bit array of the second bitmap is set to 1 to indicate that the write address corresponding to the write I / O request has been written; each bit in the bit array of the second bitmap represents whether the address within the range of 2^M has been written.

[0084] In addition, after the PCM controller receives the write I / O request from the host, if the current time is the start time of the even-numbered coarse-grained unit time, it can first clear the second bitmap and then call the second bitmap. If the current time is not the start time of the even-numbered coarse-grained unit time, the second bitmap can be directly called.

[0085] 303. According to the parity type of the fine-grained unit time of the current timing, a target Bloom filter is selected from the first Bloom filter and the second Bloom filter included in the second SRAM. The duration of the fine-grained unit time is related to the minimum write-after-read delay of the second read voltage. The first Bloom filter and the second Bloom filter are used to select the first read voltage or the second read voltage during the read phase.

[0086] Specifically, during the response to the write I / O request, the PCM controller also determines which fine-grained unit time and parity type the current timing fine-grained unit time is based on the current timing and the timing start point. If the current timing fine-grained unit time is of the odd type, it means that the current timing fine-grained unit time is the odd-numbered fine-grained unit time.Time; if the current fine-grained unit of time is of even type, it means that the current fine-grained unit of time is the even-numbered fine-grained unit of time. Taking a fine-grained unit of time of 100ms as an example, the time ranges corresponding to the odd-numbered fine-grained units of time are: 0~100ms, 200ms~300ms, 400ms~500ms…; the time ranges corresponding to the even-numbered fine-grained units of time are: 100ms~200ms, 300ms~400ms, 500ms~600ms… Instruction manual, page 10 / 31, 16 CN 120526820 A

[0087] For example, the implementation of selecting a target Bloom filter from the first Bloom filter and the second Bloom filter included in the second SRAM according to the parity type of the fine-grained unit time of the current timing is as follows: if the parity type indicates that the fine-grained unit time of the current timing is the odd-numbered fine-grained unit time, the first Bloom filter is selected as the target Bloom filter from the first Bloom filter and the second Bloom filter included in the second SRAM, and the first Bloom filter is associated with the odd-numbered fine-grained unit time;

[0088] if the parity type indicates that the fine-grained unit time of the current timing is the even-numbered fine-grained unit time, the second Bloom filter is selected as the target Bloom filter from the first Bloom filter and the second Bloom filter included in the second SRAM, and the second Bloom filter is associated with the even-numbered fine-grained unit time.

[0089] 304. A second write operation identifier of the write address is stored in the target Bloom filter, wherein the second write operation identifier indicates that the target memory cell has performed a write operation.

[0090] For example, the implementation of storing the second write operation identifier of the write address in the target Bloom filter is as follows: determine the second mapping position of the write address in the bit array of the target Bloom filter; set the value of the bit at the second mapping position to the second write operation identifier of the write address, so as to store the second write operation identifier of the write address in the target Bloom filter.

[0091] Specifically, using the write address as the key, call multiple mapping functions such as the Hash function in the target Bloom filter to determine multiple mapping positions of the write address in the bit array of the target Bloom filter (here referred to as the second mapping position), set the value of the bit at the multiple mapping positions of the write address in the bit array of the target Bloom filter to 1, and the corresponding 1 bit in the bit array of the target Bloom filter represents the first write operation identifier of the write address, so as to store the first write operation identifier of the write address in the target Bloom filter. It can be understood that if 0 bit in the bit array of the target Bloom filter, it means that no write address has been recorded.

[0092] Further optionally, before storing the second write operation identifier of the write address in the target Bloom filter, the above method further includes: if the current time is the start time of the fine-grained unit time of the current timing, then performing a write operation on the target Bloom filter.The row is cleared, that is, the value of each bit in the bit array of the target Bloom filter is set to 0. If the current time is not the start time of the fine-grained unit time of the current timekeeping, the operation of storing the second write operation identifier of the write address in the target Bloom filter is directly executed. In this way, it can be ensured that the second write operation identifier of the write address corresponding to the time range of the fine-grained unit time of the current timekeeping is stored in the target Bloom filter, and the read correctness of the I / O request is better guaranteed.

[0093] For better understanding, it is explained in conjunction with Figure 5. Referring to Figure 5, if the PCM controller receives a write I / O request sent by the host in the time range of the odd-numbered fine-grained unit time, the write address is used as the key, and multiple Hash functions of the first Bloom filter are called to map the key to obtain multiple mapping positions corresponding to the write address in the bit array of the first Bloom filter. The multiple Hash functions are denoted as Hash 00, Hash 01 and Hash 02 respectively. Taking a 12-bit length bit array of the first Bloom filter as an example, the mapping positions corresponding to the write address in the bit array of the first Bloom filter are the 2nd bit, the 4th bit, and the 9th bit. Therefore, the values ​​of the 4th bit and the 9th bit in the bit array of the first Bloom filter are both set to 1 to indicate that a write operation has been performed on the write address corresponding to the write I / O request.

[0094] Furthermore, after the PCM controller receives the write I / O request sent by the host, if the current time is the start time of the odd-numbered fine-grained unit time, the first Bloom filter can be cleared first, and then invoked. If the current time is not the start time of the odd-numbered fine-grained unit time, the first Bloom filter can be invoked directly.

[0095] If, within an even-numbered fine-grained unit time interval, the PCM controller receives a write I / O request from the host, using the write address as the key, it calls multiple hash functions of the second Bloom filter to map the key, obtaining multiple mapping positions corresponding to the write address in the bit array of the second Bloom filter. These hash functions are denoted as Hash 10, Hash 11, and Hash 12, respectively. Taking a bit array of the second Bloom filter with a length of 12 bits as an example, the mapping positions corresponding to the write address in the bit array of the second Bloom filter are the 1st bit, the 6th bit, and the 10th bit. Then, the values ​​of the 1st bit, the 6th bit, and the 10th bit in the bit array of the second Bloom filter are all set to 1 to indicate that a write operation has been performed on the write address corresponding to the write I / O request.

[0096] In addition, after the PCM controller receives a write I / O request sent by the host, if the current time is the even-numbered granular...If the current time is not the start time of the even-numbered fine-grained unit time, the second Bloom filter can be cleared first and then called. If the current time is not the start time of the even-numbered fine-grained unit time, the second Bloom filter can be called directly.

[0097] 305. Write the data requested by the write I / O request into the target storage unit.

[0098] In practical applications, the data requested by the write I / O request can be directly written into the target storage unit, or the ECC module can be called to encode the write data requested by the write I / O request, and the redundancy check bit of the write data can be determined using the ECC algorithm. The encoded write data and its redundancy check bit can be written into the target storage unit. There are no restrictions on this.

[0099] The technical solution provided in this application embodiment adds a small amount of SRAM resources to the PCM controller. During the write phase, the bitmap provided by the SRAM can be used to record whether a write operation has occurred in each coarse-grained unit time; the Bloom filter provided by the SRAM can be used to record whether a write operation has occurred in each fine-grained unit time. Thus, in the subsequent read phase, even under high bandwidth conditions, the bitmap and Bloom filter provided by SRAM resources can correctly distinguish the three read voltage levels of the phase-change memory design, achieving a high probability of finding the correct read voltage to respond to the read I / O request in one go, significantly reducing the number of read retryes, and greatly optimizing the QoS of the service system using the phase-change memory without significantly affecting the overall system latency and bandwidth.

[0100] To better understand the write process, a specific write process is described below with reference to Figure 6. Figure 6 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application. Referring to Figure 6, the method may include the following steps:

[0101] S1. In response to a write I / O request, determine whether the current coarse-grained unit time belongs to the odd-numbered coarse-grained unit time; if yes, execute S2; if no, execute S3;

[0102] S2. If the current time is the start time of the current coarse-grained unit time, first clear the first bit map; then shift the write address to the right by M bits, and update the first bit map based on the write address after shifting M bits, and execute S4.

[0103] Updating the first bit map based on the write address after shifting M bits means recording the write operation identifier corresponding to the write address in the first bit map.

[0104] S3. If the current time is the start time of the current coarse-grained unit time, first clear the second bit map; then shift the write address to the right by M bits, and update the second bit map based on the write address after shifting M bits, and execute S4.

[0105] Updating the second bit map based on the write address after shifting M bits means recording the write operation identifier corresponding to the write address in the second bit map.

[0106] S4. Determine whether the current fine-grained unit time belongs to the odd-numbered fine-grained unit time; if yes, execute S5; if no, execute S6.

[0107] S5. If the current time is the start time of the fine-grained unit time of the current timing, the first Bloom filter is cleared first; then the first Bloom filter is updated based on the write address, and S7 is executed.

[0108] Updating the first Bloom filter based on the write address means recording the write operation identifier corresponding to the write address in the first Bloom filter.

[0109] S6. If the current time is the start time of the fine-grained unit time of the current timing, the second Bloom filter is cleared first; then the second Bloom filter is updated based on the write address, and S7 is executed.

[0110] Updating the second Bloom filter based on the write address means recording the write operation identifier corresponding to the write address in the second Bloom filter.

[0111] S7. The data requested by the write I / O request is written into the storage unit.

[0112] After writing data based on the above write process, the read process of the phase change memory is described below with reference to Figure 7. Figure 7 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a first SRAM and a second SRAM. The phase-change memory is configured with a first read voltage, a second read voltage, and a third read voltage, with the minimum write-to-read latency increasing from small to large. The method is executed by the controller. Referring to Figure 7, the method may include the following steps:

[0113] 701. In response to a read I / O request including a read address, a first write operation identifier of the read address is searched in the first bit map and the second bit map included in the first SRAM.

[0114] 702. If the first write operation identifier of the read address is not found in either the first bit map or the second bit map, the third read voltage is selected as the target read voltage, and step 704 is executed.

[0115] 703. If the first write operation identifier of the read address is found in the first bit map and / or the second bit map, based on the existence of the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter included in the second SRAM, one of the first read voltage and the second read voltage is selected as the target read voltage, and step 704 is executed.

[0116] For example, step 703 is implemented as follows: The second write operation identifier of the read address is searched in the first Bloom filter and the second Bloom filter; if the second write operation identifier of the read address is not found, the second read voltage is selected from the first read voltage and the second read voltage as the target read voltage; if the second write operation identifier of the read address is found, the first read voltage is selected from the first read voltage and the second read voltage as the target read voltage.

[0117] 704. A read operation is performed on the storage cell corresponding to the read address in the storage medium according to the target read voltage.

[0118] In this embodiment, the first bitmap is related to the odd-numbered coarse-grained unit time, and the second bitmap is related to the even-numbered unit time.The coarse-grained unit time is related to the duration of the coarse-grained unit time, which is related to the minimum write-read delay of the third read voltage; the first Bloom filter is related to the odd-numbered fine-grained unit time, the second Bloom filter is related to the even-numbered fine-grained unit time, and the duration of the fine-grained unit time is related to the minimum write-read delay of the second read voltage.

[0119] In this embodiment, the PCM controller receives and responds to the read I / O request including the read address sent by the host. During the response process, the read address in the LA form in the read I / O request can also be converted to the read address in the PA form, but it is not limited to this.

[0120] During the write phase, the bitmap provided by the SRAM can be used to record whether a write operation has occurred in each coarse-grained unit time. Specifically, for a write operation initiated within the time range of the odd-numbered coarse-grained unit time, the first bitmap included in the first SRAM has saved at least one first write operation identifier corresponding to a write address; for a write operation initiated within the time range of the even-numbered coarse-grained unit time, the second bitmap included in the first SRAM has saved at least one first write operation identifier corresponding to a write address.

[0121] Therefore, when the PCM controller responds to a read I / O request, it first searches for the first write operation identifier of the read address in the first bit map and the second bit map included in the first SRAM.

[0122] As an example, using the read address as the key, various mapping functions such as the Hash function in the target bit map are called to determine the mapping position of the read address in the target bit map. The value of the bit at the mapping position of the read address in the bit array of the target bit map is queried. If the value of the bit at the mapping position of the read address in the bit array of the target bit map is 1, it means that the first write operation identifier of the read address has been found; if the value of the bit at the mapping position of the read address in the bit array of the target bit map is 0, it means that the first write operation identifier of the read address has not been found. Here, the target bit map is either the first bit map or the second bit map. Instruction manual, page 13 / 31, 19 CN 120526820 A

[0123] As another example, the read address is shifted right by M bits, where M is a positive integer; the read address after shifting right by M bits is used as the key, and various mapping functions such as Hash function in the target bitmap are called to determine the mapping position of the read address in the target bitmap. The value of the bit at the mapping position of the read address in the bit array of the target bitmap is queried. If the value of the bit at the mapping position of the read address in the bit array of the target bitmap is 1, it means that the first write operation identifier of the read address has been found; if the value of the bit at the mapping position of the read address in the bit array of the target bitmap is 0, it means that the first write operation identifier of the read address has not been found. The target bitmap is either the first bitmap or the second bitmap.

[0124] For better understanding, Figure 4 is used as an example for explanation. All read I / O requests received by the PCM controller.In both bitmaps, it is determined whether the first write operation identifier of the read address is in either bitmap. If it is not in either bitmap, the third read voltage is selected as the target read voltage; if it is in either bitmap, the read voltage differentiation needs to continue.

[0125] It is worth noting that, according to the access locality principle of the actual host, differentiating the third read voltage from the time dimension of coarse-grained unit time (duration is, for example, 100s) can maintain a relatively large probability of correctly reading data. Taking M as 16 as an example, the address granularity recorded by each bit in the bit array of the bitmap is 64K (kilobytes). Specifically, taking the PCM capacity as 256GB (gigabytes) as an example, only 256G / 64K*2=8Mbit=1MB (megabytes) of SRAM resources are needed. The PCM controller can provide 1MB of SRAM resources, which has almost no impact on the latency and bandwidth of the overall system. If the PCM capacity is larger, the address granularity represented by each bit can be appropriately increased.

[0126] In this embodiment, if the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, it indicates that the memory cell corresponding to the read address has not been written within the time range corresponding to the coarse-grained unit time. In this case, the third read voltage is selected as the target read voltage. If the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, it indicates that the memory cell corresponding to the read address has a high probability of being written within the time range corresponding to the coarse-grained unit time. In this case, it is necessary to use the first Bloom filter and the second Bloom filter to distinguish whether the first read voltage or the second read voltage should be selected as the target read voltage.

[0127] When selecting the target read voltage using the first Bloom filter and the second Bloom filter, the second write operation identifier of the read address is searched in the first Bloom filter and the second Bloom filter. Specifically, using the read address as the key, various mapping functions such as the Hash function in the target Bloom filter are called to determine multiple mapping positions of the read address in the target Bloom filter. The values ​​of the bits at the multiple mapping positions of the read address in the bit array of the target Bloom filter are queried. If the values ​​of the bits at the multiple mapping positions of the read address in the bit array of the target Bloom filter are all 1, it means that the second write operation identifier of the read address has been found; if the values ​​of one or more bits at the multiple mapping positions of the read address in the bit array of the target Bloom filter are 0, it means that the second write operation identifier of the read address has not been found. Here, the target Bloom filter is either the first Bloom filter or the second Bloom filter.

[0128] In this embodiment, if the second write operation identifier of the read address is not found in either the first Bloom filter or the second Bloom filter, the second read voltage is selected as the target read voltage from the first read voltage and the second read voltage; if the second write operation identifier of the read address is found in the first Bloom filter and / or the second Bloom filter, it means that the second write operation identifier of the read address has been found in the fine-grained Bloom filter.Within the time range corresponding to the unit of time, the memory cell corresponding to the read address has been written. The first read voltage is selected as the target read voltage from the first read voltage and the second read voltage.

[0129] For better understanding, Figure 5 is used as an example. All read I / O requests received by the PCM controller are judged in both Bloom filters to determine whether the second write operation identifier of the read address is in either Bloom filter. Specifically, the read address is shifted right by M bits, and the read address after shifting right by M bits is used as the key. Multiple Hash functions of the target Bloom filter are called to map the key to obtain multiple mapping positions of the read address in the bit array of the target Bloom filter. The multiple Hash functions are denoted as Hash 10, Hash 11 and Hash 12 respectively. If one or more bits at multiple mapping positions of the read address in the target Bloom filter bit array (page 14 / 31, CN 120526820 A group) are 0, it indicates that the second write operation identifier of the read address has not been found; if the bits at multiple mapping positions of the read address in the target Bloom filter bit array are all 1, it indicates that the second write operation identifier of the read address has been found. If not found in any Bloom filter, the second read voltage is selected as the target read voltage; if found in any Bloom filter, the first read voltage is selected as the target read voltage.

[0130] Since Bloom filters have a certain degree of misjudgment, the probability of misjudgment is related to the size of the bit array in the Bloom filter and the number of mapping functions. Research has shown that if the design bandwidth is 8GB / s, with 4 hash functions, the probability of reading incorrect data is less than 0.0561, and the PCM controller only needs 9.6MB of SRAM resources, which is the resource that the PCM controller can provide. This greatly reduces the probability of Read Retry, and multiple mapping functions can be calculated and checked simultaneously, so it has almost no impact on the delay and bandwidth of the PCM controller. In practical applications, the bandwidth and the number of mapping functions can be flexibly designed without limitation.

[0131] In this embodiment, after selecting the target read voltage, a read operation is performed on the storage unit corresponding to the read address in the storage medium according to the target read voltage to read data from the storage unit and return the read data to the host. In practical applications, if encoded data is written to the storage unit during the writing stage, the ECC module can be called to decode the read encoded data and return the decoded data to the host.

[0132] In some optional embodiments, in order to improve the reliability of reading the correct data, after performing a read operation on the storage unit corresponding to the read address in the storage medium according to the target read voltage, if the target read voltage is the first read voltage, error checking and correction ECC processing is performed on the read data; if the ECC processing result indicates that the read data is incorrect, then the data is processed in sequence.Select one of the second and third read voltages as the target read voltage, and execute the step of reading data from the storage cell corresponding to the read address in the storage medium according to the target read voltage, until the ECC processing result indicates that the read data is correct.

[0133] Because the Bloom filter has a false positive rate, that is, if the judgment result is that an element exists, the element may not exist, but if the judgment result is that it does not exist, it definitely does not exist. Considering that the Bloom filter has this characteristic, when the first read voltage is selected as the target read voltage, after reading data from the storage cell of the PCM storage medium according to the first read voltage, it is necessary to perform ECC processing on the read data to check whether the read data is correct. If the read data is correct, the read data is returned to the host, and the read process ends. If the read data is incorrect, the Read Retry mechanism is used to select one of the second and third read voltages as the new target read voltage, and the data is reread according to the new target read voltage. If the newly read data is incorrect, the Read Retry mechanism is used to select the unselected read voltage from the second and third read voltages as the new target read voltage, and the data is reread according to the new target read voltage. If the newly read data is incorrect, an error message is returned to the host; if the newly read data is correct, the correct newly read data is returned to the host.

[0134] In practical applications, when performing ECC processing on the read data, the ECC module uses the ECC algorithm to redetermine the redundancy check bits of the read data. If the redundancy check bits redetermined by the ECC algorithm are the same as the redundancy check bits read from the storage medium, the data read from the PCM's storage medium is correct. If the redundancy check bits redetermined by the ECC algorithm are different from the redundancy check bits read from the storage medium, the data read from the PCM's storage medium is incorrect.

[0135] It is understood that the Read Retry mechanism will only be used to try to find the correct read voltage if the target read voltage is the first read voltage and the data read by the first read voltage is incorrect. The probability of this situation is very small, which greatly reduces the probability of Read Retry and has almost no impact on the latency and bandwidth of the PCM controller.

[0136] The technical solution provided in this application adds a small amount of SRAM resources to the PCM controller. In the write stage specification, page 15 / 31, paragraph 21 CN 120526820 A, the bitmap provided by SRAM can be used to record whether a write operation has occurred in each coarse-grained unit of time; the Bloom filter provided by SRAM can be used to record whether a write operation has occurred in each fine-grained unit of time. In this way, during the read stage,Even under high bandwidth conditions, the bitmap and Bloom filter provided by SRAM resources can correctly distinguish the three read voltage levels of the phase-change memory design, enabling the correct read voltage to be found in response to the read I / O request with a high probability in one go, significantly reducing the number of read retryes, and greatly optimizing the QoS of the service system using the phase-change memory without affecting the latency and bandwidth of the overall system.

[0137] To better understand the read process, a specific read process is described below with reference to Figure 8. Figure 8 is a flowchart of another data access method for phase-change memory provided by an embodiment of this application. Referring to Figure 8, the method may include the following steps:

[0138] S1. In response to a read I / O request including a read address, the first write operation identifier of the read address is searched in the first bitmap and the second bitmap included in the first SRAM, and step S2 or S3 is executed.

[0139] S2. If the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, the third read voltage is selected as the target read voltage, and step S6 is executed.

[0140] S3. If the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, then the second write operation identifier of the read address is searched in the first Bloom filter and the second Bloom filter, and step S4 or S5 is executed.

[0141] S4. If the second write operation identifier of the read address is not found, then the second read voltage is selected from the first read voltage and the second read voltage as the target read voltage, and step S6 is executed.

[0142] S5. If the second write operation identifier of the read address is found, then the first read voltage is selected from the first read voltage and the second read voltage as the target read voltage, and step S6 is executed.

[0143] S6. The read operation is performed on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0144] The foregoing embodiment describes the case where the phase change memory is configured with three levels of read voltage. The following describes the case where the phase change memory is configured with two levels of read voltage.

[0145] In one case, the two Bloom filters included in the SRAM provided by the controller are used for data access, as described in conjunction with FIG9 and FIG10.

[0146] Figure 9 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with a fourth read voltage and a fifth read voltage, increasing in minimum post-write read latency. The method is executed by the controller. Referring to Figure 9, the method may include the following steps:

[0147] S1. In response to a write I / O request including a write address, a target Bloom filter is selected from the third Bloom filter and the fourth Bloom filter included in the third SRAM according to the parity type of the current unit time. The third Bloom filter...The filter is associated with the odd-numbered unit time, the fourth Bloom filter is associated with the even-numbered unit time, and the duration of the unit time is associated with the minimum post-write read delay of the fifth read voltage.

[0148] In this embodiment, when the phase-change memory controller includes at least the third SRAM, the two read voltage levels can be correctly distinguished. Here, the two read voltage levels to be distinguished are referred to as the fourth read voltage and the fifth read voltage, respectively. The minimum post-write read delay of the fourth read voltage is less than the minimum post-write read delay of the fifth read voltage. In practical applications, the time ranges of the post-write read delays corresponding to the fourth read voltage and the fifth read voltage may not overlap. Further optionally, the time ranges of the post-write read delays corresponding to the fourth read voltage and the fifth read voltage may partially overlap. It is understood that the minimum post-write read delay of the fifth read voltage is less than the maximum post-write read delay of the fourth read voltage.

[0149] In this embodiment, the unit time is associated with the minimum post-write read delay of the fifth read voltage. For example, the duration of a unit time is equal to the minimum write-after-read delay of the fifth read voltage, or the duration of a unit time is obtained by increasing or decreasing the minimum write-after-read delay of the fifth read voltage (see page 16 / 31 of CN 120526820 A). There are no restrictions on this.

[0150] In this embodiment, two Bloom filters provided by the third SRAM can be used to record whether a write operation occurs in each unit time.

[0151] Specifically, the PCM controller receives and responds to a write I / O request including a write address sent by the host. During the response process, the write address in LA form in the write I / O request can be converted to a write address in PA form; the ECC module can also be called to encode the write data requested in the write I / O request, and the ECC algorithm can be used to determine the redundancy check bits of the write data, but this is not limited to these methods.

[0152] In this embodiment, when the PCM controller responds to a write I / O request, it determines the current unit time and its odd / even type based on the current timing and the timing start point. The timing start point is flexibly set as needed. For example, the timing starts when the PCM starts, meaning the timing start point is the PCM's startup time.

[0153] If the current unit time is odd, it means the current unit time is the odd-numbered unit time, and the third Bloom filter from the third and fourth Bloom filters included in the third SRAM is used as the target Bloom filter; if the current unit time is even, it means the current unit time is the even-numbered unit time, and the fourth Bloom filter from the third and fourth Bloom filters included in the third SRAM is used as the target Bloom filter.

[0154] Taking a unit time duration of 100s as an example, the time ranges corresponding to the odd-numbered unit time are: 0~100s, 200s~300s, 400s~500s……; the time ranges corresponding to the even-numbered units of time are respectively: 100s~200s, 300s~400s, 500s~600s…….

[0155] S2. Save the write operation identifier of the write address in the target Bloom filter, wherein the write operation identifier indicates that the target storage cell corresponding to the write address in the storage medium has performed a write operation.

[0156] For example, the implementation method of saving the write operation identifier of the write address in the target Bloom filter is: determine the mapping position of the write address in the bit array of the target Bloom filter; set the value of the bit at the second mapping position to the write operation identifier of the write address, so as to save the write operation identifier of the write address in the target Bloom filter.

[0157] Specifically, using the write address as the key, multiple mapping functions such as the Hash function in the target Bloom filter are called to determine multiple mapping positions of the write address in the bit array of the target Bloom filter. The values ​​of the bits at the multiple mapping positions of the write address in the bit array of the target Bloom filter are set to 1. The corresponding 1 bit in the bit array of the target Bloom filter represents the write operation identifier of the write address, so as to save the write operation identifier of the write address in the target Bloom filter. It can be understood that if 0 bits in the bit array of the target Bloom filter, it means that no write address has been recorded.

[0158] Further optionally, before saving the write operation identifier of the write address in the target Bloom filter, the above method further includes: if the current time is the start time of the current time unit, then the target Bloom filter is cleared, that is, the values ​​of each bit in the bit array of the target Bloom filter are set to 0. If the current time is not the start time of the current time unit, then the operation of saving the write operation identifier of the write address in the target Bloom filter is directly executed. In this way, it can be ensured that the write operation identifier of the write address corresponding to the current unit time is well stored in the target Bloom filter, and the read correctness of the I / O request is better guaranteed.

[0159] S3. Write the data requested by the write I / O request into the target storage unit.

[0160] In practical applications, the data requested by the write I / O request can be directly written into the target storage unit, or the ECC module can be called to encode the write data requested by the write I / O request, and the redundancy check bit of the write data can be determined by the ECC algorithm. The encoded write data and its redundancy check bit are then written into the target storage unit. There are no restrictions on this. Specification 17 / 31 pages 23 CN 120526820 A

[0161] The technical solution provided by the embodiments of this application adds a small amount of SRAM resources to the PCM controller. During the write phase, the Bloom filter provided by the SRAM can be used to record whether a write operation occurs in each unit time. In this way, in the laterIn the subsequent read phase, even under high bandwidth conditions, the Bloom filter provided by SRAM resources can correctly distinguish the two read voltage levels of the phase-change memory design, and find the correct read voltage to respond to the read I / O request with a high probability in one go, significantly reducing the number of read retryes. Under the condition of almost no impact on the latency and bandwidth of the overall system, the QoS of the service system using the phase-change memory is greatly optimized.

[0162] After writing data based on the above write process, the read process of the phase-change memory is described below with reference to Figure 10. Figure 10 is a flowchart of another phase-change memory data access method provided by the embodiment of this application. The phase-change memory includes at least: a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with a fourth read voltage and a fifth read voltage with the minimum write read latency from small to large. The method is executed by the controller. Referring to Figure 10, the method may include the following steps:

[0163] S1. In response to a read I / O request including a read address, the write operation identifier of the read address is searched in the third Bloom filter and the fourth Bloom filter.

[0164] In this embodiment, the PCM controller receives and responds to a read I / O request including a read address sent by the host. During the response process, the read address in LA form in the read I / O request can also be converted to a read address in PA form, but it is not limited thereto.

[0165] During the write phase, the Bloom filter provided by the SRAM can be used to record whether a write operation has occurred in each unit of time. Specifically, for write operations initiated within the time range of the odd-numbered unit of time, the third Bloom filter included in the third SRAM has already stored at least one write operation identifier corresponding to a write address; for write operations initiated within the time range of the even-numbered unit of time, the fourth Bloom filter included in the third SRAM has already stored at least one write operation identifier corresponding to a write address.

[0166] Therefore, when responding to a read I / O request, the PCM controller searches for the write operation identifier of the read address in the third Bloom filter and the fourth Bloom filter. Specifically, using the read address as the key, various mapping functions such as the Hash function in the target Bloom filter are called to determine multiple mapping positions of the read address in the target Bloom filter. The values ​​of the bits at the multiple mapping positions of the read address in the bit array of the target Bloom filter are queried. If the values ​​of the bits at the multiple mapping positions of the read address in the bit array of the target Bloom filter are all 1, it means that the write operation identifier of the read address has been found; if the values ​​of one or more bits at the multiple mapping positions of the read address in the bit array of the target Bloom filter are 0, it means that the write operation identifier of the read address has not been found. Among them, the target Bloom filter is the third Bloom filter or the fourth Bloom filter.

[0167] S2. If the write operation identifier of the read address is not found in either the third Bloom filter or the fourth Bloom filter,Then the fifth read voltage is selected as the target read voltage;

[0168] S3. If the write operation identifier of the read address is found in the third Bloom filter and the fourth Bloom filter, the fourth read voltage is selected as the target read voltage.

[0169] S4. The read operation is performed on the storage cell corresponding to the read address in the storage medium according to the target read voltage.

[0170] The specific implementation of the read operation is similar to the specific implementation of the read operation in the aforementioned embodiment, and will not be repeated here.

[0171] In some optional embodiments, considering the false judgment rate of the Bloom filter, in order to improve the reliability of reading the correct data, after the read operation is performed on the storage cell corresponding to the read address in the storage medium according to the target read voltage, if the target read voltage is the fourth read voltage, the read data is subjected to error checking and correction ECC processing; if the result of the ECC processing specification 18 / 31 page 24 CN 120526820 A indicates that the read data is incorrect, the fifth read voltage is used as the target read voltage, and the step of reading data from the storage cell corresponding to the read address in the storage medium according to the target read voltage is re-executed.

[0172] It is understood that the Read Retry mechanism will only be used to try to find the correct read voltage if the target read voltage is the fourth read voltage and the data read by the fourth read voltage is incorrect. The probability of this situation is very small, which greatly reduces the probability of Read Retry and has almost no impact on the latency and bandwidth of the PCM controller.

[0173] The technical solution provided by the embodiments of this application adds a small amount of SRAM resources to the PCM controller. During the write phase, the Bloom filter provided by the SRAM can be used to record whether a write operation occurs in each unit of time. In this way, during the read phase, even in the case of large bandwidth, the Bloom filter provided by the SRAM resources can correctly distinguish the two read voltage levels of the phase change memory design, and find the correct read voltage to respond to the read I / O request with a high probability at one time, significantly reducing the number of Read Retry. Under the condition of almost no impact on the latency and bandwidth of the overall system, the QoS of the service system using the phase change memory is greatly optimized.

[0174] In another case, the two bitmaps included in the SRAM provided by the controller are described in conjunction with FIG11 and FIG12.

[0175] Figure 11 is a flowchart of another data access method for phase-change memory provided in an embodiment of this application. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with a fourth read voltage and a fifth read voltage, which increase in magnitude of the minimum write-after-read latency. The method is executed by the controller. Referring to Figure 11, the method may include the following steps:

[0176] S1. In response to a write I / O request including a write address, a target bitmap is selected from the third bitmap and the fourth bitmap included in the third SRAM according to the parity type of the current unit time. The third bitmap is associated with the odd-numbered unit time, and the fourth bitmap is associated with the even-numbered unit time. The duration of the unit time is associated with the minimum post-write read latency of the fifth read voltage.

[0177] In this embodiment, when the controller of the phase-change memory includes at least the third SRAM, the read voltages of the two levels can be correctly distinguished. Here, the two levels of read voltages to be distinguished are referred to as the fourth read voltage and the fifth read voltage, respectively. The minimum post-write read latency of the fourth read voltage is less than the minimum post-write read latency of the fifth read voltage. In practical applications, the time ranges of the post-write read latency corresponding to the fourth read voltage and the fifth read voltage may not overlap. Further optionally, the time ranges of the post-write read latency corresponding to the fourth read voltage and the fifth read voltage may partially overlap. It is understood that the minimum post-write read latency of the fifth read voltage is less than the maximum post-write read latency of the fourth read voltage.

[0178] In this embodiment, the unit time is related to the minimum write-after-read latency of the fifth read voltage. For example, the duration of the unit time is equal to the minimum write-after-read latency of the fifth read voltage, or the duration of the unit time is obtained by increasing or decreasing the minimum write-after-read latency of the fifth read voltage, and there is no limitation on this.

[0179] In this embodiment, the two bitmaps provided by the third SRAM can be used to record whether a write operation occurs in each unit time.

[0180] Specifically, the PCM controller receives and responds to the write I / O request including the write address sent by the host. During the response process, the write address in LA form in the write I / O request can be converted to the write address in PA form; the ECC module can also be called to encode the write data requested by the write I / O request, and the redundancy check bit of the write data can be determined using the ECC algorithm, but it is not limited to this.

[0181] In this embodiment, when the PCM controller responds to a write I / O request, it determines the current timing unit time and its odd / even type based on the current timing time and timing start point. The timing start point is flexibly set as needed. For example, timing begins when the PCM starts, meaning the timing start point is the PCM's startup time.

[0182] If the current timing unit time is odd, it means the current timing unit time is the odd-numbered unit time, and the target bitmap is the third bitmap from the third bitmap and fourth bitmap included in the third SRAM; if the current timing unit time is even, it means the current timing unit time is the even-numbered unit time, and the target bitmap is the fourth bitmap from the third bitmap and fourth bitmap included in the third SRAM.

[0183] S2. Save the write operation identifier of the write address in the target bitmap, wherein the write operation identifier indicates that the target storage unit corresponding to the write address in the storage medium has performed a write operation.

[0184] Specifically, when saving the write operation identifier of the write address in the target bitmap, the write address is used as the key, and various mapping functions such as Hash function in the target bitmap are called to determine the mapping position of the write address in the target bitmap. The value of the bit at the mapping position of the write address in the bit array of the target bitmap is set to 1. 1 bit in the bit array of the target bitmap represents the write operation identifier of the write address, so as to save the write operation identifier of the write address in the target bitmap. It can be understood that if 0 bit in the bit array of the target bitmap, it means that no write address has been recorded.

[0185] For a unit of time, since the time range of the unit of time is relatively large, it is difficult to achieve the recording of each write address without affecting the bandwidth and latency of the service system using PCM. Therefore, by adopting a mapping table-like approach, the granularity of each bit record in the bit array of the target bitmap is expanded. That is, each bit can be used to determine whether the target memory cell corresponding to the write address within a certain address range has performed a write operation. From the perspective of the entire PCM, this can improve the probability of correctly distinguishing the read voltage.

[0186] Based on the above, optionally, when storing the write operation identifier of the write address in the target bitmap, the write address can be shifted right by M bits, where M is a positive integer; the mapping position corresponding to the write address in the bit array of the target bitmap is determined based on the right-shifted write address; the value of the bit at the mapping position is set as the write operation identifier of the write address, so as to store the write operation identifier of the write address in the target bitmap.

[0187] Specifically, the write address after right shifting by M bits is used as the Key. Various mapping functions, such as the Hash function, in the target bitmap are called to determine the mapping position corresponding to the write address in the bit array of the target bitmap. The value of the bit at the mapping position corresponding to the write address in the bit array of the target bitmap is set to 1. 1 bit in the bit array of the target bitmap represents the write operation identifier of each write address within a range of 2^M, so as to save the write operation identifier of the write address in the target bitmap.

[0188] Further optionally, before saving the write operation identifier of the write address in the target bitmap, the above method further includes: if the current time is the start time of the current time unit, then the target bitmap is cleared, that is, the value of each bit in the bit array of the target bitmap is set to 0. If the current time is not the start time of the current time unit, the write operation identifier of the write address is directly saved in the target bitmap. In this way, it can be ensured that the write operation identifier of the write address within the time range corresponding to the current time unit is well stored in the target bitmap, and the read correctness of the I / O request is better guaranteed.

[0189] S3. Write the data requested by the write I / O request into the target storage unit.

[0190] The specific implementation of the write operation is similar to that of the write operation in the aforementioned embodiments, and will not be repeated here.

[0191] The technical solution provided in this application adds a small amount of SRAM resources to the PCM controller. During the write phase, the bitmap provided by the SRAM can be used to record whether a write operation occurs at each unit of time. In this way, during the read phase, even under the condition of large bandwidth, the bitmap provided by the SRAM resources can correctly distinguish the two read voltage levels of the phase change memory design, so as to find the correct read voltage to respond to the read I / O request with a high probability at one time, significantly reducing the number of read retry, and greatly optimizing the QoS of the service system using the phase change memory without affecting the latency and bandwidth of the overall system.

[0192] After writing data based on the above write process, the read process of the phase change memory is described below with reference to Figure 12. Specification 20 / 31 pages 26 CN 120526820 A

[0193] Figure 12 is a flowchart of another phase change memory data access method provided in the embodiment of this application. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with a fourth read voltage and a fifth read voltage, which are arranged in ascending order of minimum write-to-read latency. The method is executed by the controller. Referring to Figure 12, the method may include the following steps:

[0194] S1. In response to a read I / O request including a read address, the write operation identifier of the read address is searched in the third bitmap and the fourth bitmap.

[0195] In this embodiment, the PCM controller receives and responds to a read I / O request including a read address sent by the host. During the response process, the read address in the form of LA in the read I / O request may also be converted to the read address in the form of PA, but it is not limited to this.

[0196] During the write phase, the bitmap provided by the SRAM can be used to record whether a write operation has occurred in each unit of time. Specifically, for a write operation initiated within the time range of the odd-numbered unit time, the third bitmap included in the third SRAM has saved at least one write operation identifier corresponding to a write address; for a write operation initiated within the time range of the even-numbered unit time, the fourth bitmap included in the third SRAM has saved at least one write operation identifier corresponding to a write address.

[0197] Therefore, when the PCM controller responds to a read I / O request, it searches for the write operation identifier of the read address in the third and fourth bitmaps.

[0198] As an example, using the read address as the key, various mapping functions such as the Hash function in the target bitmap are called to determine the mapping position of the read address in the target bitmap. The value of the bit at the mapping position of the read address in the bit array of the target bitmap is queried. If the value of the bit at the mapping position of the read address in the bit array of the target bitmap is 1,If the value of the bit at the mapping position of the read address in the bit array of the target bitmap is 0, it means that the write operation identifier of the read address has not been found. The target bitmap is either the third bitmap or the fourth bitmap.

[0199] As another example, the read address is shifted right by M bits, where M is a positive integer; using the read address after the right shift by M bits as the Key, various mapping functions such as the Hash function in the target bitmap are called to determine the mapping position of the read address in the target bitmap. The value of the bit at the mapping position of the read address in the bit array of the target bitmap is then queried. If the value of the bit at the mapping position of the read address in the bit array of the target bitmap is 1, it means that the write operation identifier of the read address has been found; if the value of the bit at the mapping position of the read address in the bit array of the target bitmap is 0, it means that the write operation identifier of the read address has not been found. The target bitmap is either the third bitmap or the fourth bitmap.

[0200] S2. If no write operation identifier for the read address is found in either the third or fourth bitmap, then the fifth read voltage is selected as the target read voltage.

[0201] S3. If a write operation identifier for the read address is found in the third and / or fourth bitmap, then the fourth read voltage is selected as the target read voltage.

[0202] S4. Perform a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0203] The specific implementation of the read operation is similar to that of the read operation in the aforementioned embodiments, and will not be repeated here.

[0204] The technical solution provided in this application adds a small amount of SRAM resources to the PCM controller. During the write phase, the bitmap provided by the SRAM can be used to record whether a write operation occurs at each unit of time. Thus, during the read phase, even under high bandwidth conditions, the bitmap provided by the SRAM resources can correctly distinguish the two read voltage levels of the phase-change memory design, achieving a high probability of finding the correct read voltage to respond to the read I / O request in one go, significantly reducing the number of read retryes, and greatly optimizing the QoS of the service system using the phase-change memory without significantly affecting the overall system latency and bandwidth.

[0205] The following describes the application of Bloom filter groups for the three-level read voltage configuration and the two-level read voltage configuration of the phase-change memory.

[0206] For the case of the three-level read voltage configuration of the phase-change memory, in practical applications, the two bitmaps provided by the first SRAM can be used to record whether a write operation has occurred at each coarse-grained unit of time; the Bloom filter group provided by the second SRAM can be used to record whether a write operation has occurred at each fine-grained unit of time.The two bitmaps can distinguish (Vread1 / Vread2) and Vread3, that is, determine that the required read voltage is either the third read voltage Vread3, or the second read voltage Vread2 or the first read voltage Vread1. The Bloom filter set provided by the second SRAM can distinguish Vread1 and (Vread2 / Vread3), that is, determine that the required read voltage is either the first read voltage Vread1, or the second read voltage Vread2 or the third read voltage Vread3. The first SRAM and the second SRAM can be combined to correctly distinguish the three read voltage levels.

[0207] Therefore, for the case where the phase change memory is configured with 3 read voltage levels, the write process using the two bitmaps provided by the first SRAM and the Bloom filter set provided by the second SRAM is described below with reference to FIG13.

[0208] FIG13 is a flowchart of another phase change memory data access method provided in the embodiment of this application. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a first SRAM and a second SRAM. The phase-change memory is configured with a first read voltage, a second read voltage, and a third read voltage, with the minimum write-after-read latency increasing from small to large. The method is executed by the controller. Referring to Figure 13, the method may include the following steps:

[0209] 801. In response to a write I / O request including a write address, a target bitmap is selected from the first bitmap and the second bitmap included in the first SRAM according to the parity type of the current coarse-grained unit time. The duration of the coarse-grained unit time is related to the minimum write-after-read latency of the third read voltage. The first bitmap and the second bitmap are used to select the third read voltage during the read phase.

[0210] The implementation of step 801 can be found in the implementation of step 301 in the foregoing embodiment, and will not be repeated here.

[0211] 802. A first write operation identifier of the write address is stored in the target bitmap. The first write operation identifier indicates that the target storage cell corresponding to the write address in the storage medium has performed a write operation.

[0212] The implementation method of step 802 can be referred to the implementation method of step 302 in the foregoing embodiment, and will not be repeated here.

[0213] 803. According to the target arrangement position of the sub-unit time to which the current time belongs in the fine-grained unit time of the current timing, select the target Bloom filter located at the target arrangement position in the Bloom filter group included in the second SRAM. The fine-grained unit time includes n sub-unit times divided in sequence. The duration of the fine-grained unit time is related to the minimum write-after-read delay of the second read voltage. The Bloom filter group is used to select the first read voltage or the second read voltage in the reading stage. The Bloom filter group includes n Bloom filters arranged in sequence.

[0214] In this embodiment, the Bloom filter group included in the second SRAM includes n Bloom filters arranged in sequence.The value is a positive integer greater than or equal to 3. Each fine-grained unit of time consists of n sub-units of time divided in sequence. Thus, the write address corresponding to a write I / O request in one sub-unit of time for each fine-grained unit of time is recorded in a Bloom filter. For example, a Bloom filter array includes 10 Bloom filters. Taking a fine-grained unit time of 100ms as an example, a certain fine-grained unit time is divided into 10 sub-unit time periods, each with a duration of 10ms. The time range of the first sub-unit time period is 0-10ms, the second sub-unit time period is 10-20ms, the third sub-unit time period is 20-30ms, the fourth sub-unit time period is 30-40ms, the fifth sub-unit time period is 40-50ms, the sixth sub-unit time period is 50-60ms, the seventh sub-unit time period is 60-70ms, and the eighth sub-unit time period is 70-10ms. 80ms, the time range corresponding to the 9th sub-unit time is 80~90ms, and the time range corresponding to the 10th sub-unit time is 90~100ms.

[0215] Specifically, during the response to the write I / O request, the PCM controller also determines which fine-grained unit time the current timing is based on the current timing and the timing start point, and determines the target arrangement position of the sub-unit time to which the current time belongs in the current fine-grained unit time. The target arrangement position is, for example, any one of the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, etc. The target Bloom filter located at the target arrangement position is selected from the Bloom filter group included in the second SRAM. For example, the target Bloom filter is any one of the 1st Bloom filter, the 2nd Bloom filter, ... the 10th Bloom filter.

[0216] 804. Save the second write operation identifier of the write address in the target Bloom filter, wherein the second write operation identifier indicates that the target memory cell has performed a write operation.

[0217] For example, the implementation of saving the second write operation identifier of the write address in the target Bloom filter is as follows: determine the second mapping position of the write address in the bit array of the target Bloom filter; set the value of the bit at the second mapping position to the second write operation identifier of the write address, so as to save the second write operation identifier of the write address in the target Bloom filter.

[0218] For the implementation of step 804, please refer to the implementation of step 304 in the foregoing embodiment, which will not be repeated here.

[0219] Further optional, before saving the second write operation identifier of the write address in the target Bloom filter, the above methodThe method also includes: if the current timing is not the first fine-grained unit time, then the target Bloom filter is cleared, that is, the value of each bit in the bit array of the target Bloom filter is set to 0. If the current timing is the first fine-grained unit time, then the operation of storing the second write operation identifier of the write address in the target Bloom filter is directly executed. In this way, it can be ensured that the second write operation identifier of the write address in the sub-unit time of the current fine-grained unit time is stored well in the target Bloom filter, and the read correctness of I / O requests is better guaranteed.

[0220] For better understanding, it will be explained with reference to Figure 14. Referring to Figure 14, if the PCM controller receives a write I / O request from the host within a certain fine-grained unit time range, using the write address as the key, and if the current time falls within the first sub-unit time range of that fine-grained unit time, it calls multiple hash functions of the first Bloom filter in the Bloom filter group to map the key, obtaining multiple mapping positions corresponding to the write address in the bit array of the first Bloom filter. These hash functions are denoted as Hash 00, Hash 01, and Hash 02, respectively. Taking a 12-bit length for the bit array of the first Bloom filter as an example, the mapping positions corresponding to the write address in the bit array of the first Bloom filter are the 2nd bit, the 4th bit, and the 9th bit. Therefore, the values ​​of the 4th and 9th bits in the bit array of the first Bloom filter are both set to 1 to indicate that a write operation has been performed on the write address corresponding to the write I / O request.

[0221] If the current time falls within the time range of the second sub-unit of a certain fine-grained unit of time, multiple hash functions of the second Bloom filter in the Bloom filter group are called to map the Key, obtaining multiple mapping positions corresponding to the write address in the bit array of the second Bloom filter. The multiple hash functions are denoted as Hash 10, Hash 11, and Hash 12, respectively. Taking the bit array of the second Bloom filter as having a length of 12 bits as an example, the mapping positions corresponding to the write address in the bit array of the first Bloom filter are the 1st bit, the 6th bit, and the 10th bit. Then, the values ​​of the 1st bit, the 6th bit, and the 10th bit in the bit array of the second Bloom filter are all set to 1 to indicate that the write address corresponding to the write I / O request has performed a write operation.

[0222] Similarly, if the current time falls within the time range of the nth sub-unit time of a certain fine-grained unit time (page 23 / 31, CN 120526820 A), multiple Hash functions of the nth Bloom filter in the Bloom filter group are called to map the Key, obtaining multiple mapping positions corresponding to the write address in the bit array of the nth Bloom filter. The multiple Hash functions are respectively denoted as Hash n0, ...n1 and Hash n2. Taking the length of the bit array of the nth Bloom filter as 12 bits as an example, the mapping positions corresponding to the write address in the bit array of the nth Bloom filter are the 1st bit, the 6th bit, and the 10th bit. Then, the values ​​of the 1st bit, the 6th bit, and the 10th bit in the bit array of the nth Bloom filter are all set to 1 to indicate that the write address corresponding to the write I / O request has been written.

[0223] In addition, after the PCM controller receives the write I / O request sent by the host, if the current time is not the first fine-grained unit time, the target Bloom filter is cleared first, and then the target Bloom filter is called. If the current time is the first fine-grained unit time, the target Bloom filter can be called directly.

[0224] 805. Write the data requested by the write I / O request into the target storage unit.

[0225] The implementation method of step 805 can be referred to the implementation method of step 305 in the above embodiment, and will not be repeated here.

[0226] The technical solution provided in this application embodiment adds a small amount of SRAM resources to the PCM controller. During the write phase, the bitmap provided by SRAM can be used to record whether a write operation has occurred in each coarse-grained unit of time; the Bloom filter group provided by SRAM can be used to record whether a write operation has occurred in multiple sub-units of time included in each fine-grained unit of time. In this way, in the subsequent read phase, even in the case of large bandwidth, the bitmap and Bloom filter provided by SRAM resources can correctly distinguish the three levels of read voltage in the phase change memory design, so as to find the correct read voltage to respond to the read I / O request with a high probability at one time, significantly reducing the number of read retry, and greatly optimizing the QoS of the service system using phase change memory without affecting the latency and bandwidth of the overall system. In addition, it is worth noting that compared with the case where SRAM provides two Bloom filters, the Bloom filter group provided by SRAM saves more SRAM resources, and the advantage is more obvious.

[0227] In order to better understand the write process, a specific write process is described below with reference to Figure 15. Figure 15 is a flowchart of another data access method of phase change memory provided in this application embodiment. Referring to Figure 15, the method may include the following steps:

[0228] S1. In response to a write I / O request, determine whether the current coarse-grained unit time belongs to the odd-numbered coarse-grained unit time; if yes, execute S2; if no, execute S3;

[0229] S2. If the current time is the start time of the current coarse-grained unit time, first clear the first bit diagram; then shift the write address to the right by M bits, and update the first bit diagram based on the write address after shifting to the right by M bits, and execute S4.

[0230] Updating the first bit diagram based on the write address after shifting to the right by M bits means recording the write operation identifier corresponding to the write address in the first bit diagram.

[0231] S3. If the current time is the start time of the coarse-grained unit time of the current timing, the second bitmap is cleared first; then the write address is shifted right by M bits, and the second bitmap is updated based on the write address after the right shift by M bits, and S4 is executed.

[0232] Updating the second bitmap based on the write address after the right shift by M bits means recording the write operation identifier corresponding to the write address in the second bitmap.

[0233] S4. According to the target arrangement position of the sub-unit time to which the current time belongs in the fine-grained unit time of the current timing, the target Bloom filter located at the target arrangement position is selected in the Bloom filter group included in the second SRAM. The fine-grained unit time includes n sub-unit times divided in sequence. The duration of the fine-grained unit time is related to the minimum write-read delay of the second read voltage. The Bloom filter group is used to select the first read voltage or the second read voltage in the reading stage. The Bloom filter group includes n Bloom filters arranged in sequence. Instruction manual, pages 24 / 31, 30 CN 120526820 A

[0234] S5. If the current fine-grained unit time is not the first fine-grained unit time, first clear the target Bloom filter, and then update the target Bloom filter based on the write address; if the current fine-grained unit time is the first fine-grained unit time, update the target Bloom filter based on the write address.

[0235] Wherein, updating the target Bloom filter based on the write address means recording the write operation identifier corresponding to the write address in the target Bloom filter.

[0236] S6. Write the data requested by the write I / O request into the storage unit.

[0237] After writing the data based on the above write process, the read process of the phase change memory is described below with reference to FIG16. FIG16 is a flowchart of another data access method of phase change memory provided in the embodiment of this application. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a first SRAM and a second SRAM. The phase-change memory is configured with a first read voltage, a second read voltage, and a third read voltage, with the minimum write-to-read latency increasing from small to large. The method is executed by the controller. Referring to Figure 16, the method may include the following steps:

[0238] 901. In response to a read I / O request including a read address, a first write operation identifier of the read address is searched in the first bit map and the second bit map included in the first SRAM.

[0239] The implementation of step 901 can be found in the implementation of step 701 in the embodiment shown in Figure 7, and will not be repeated here.

[0240] 902. If the first write operation identifier of the read address is not found in either the first bit map or the second bit map, the third read voltage is selected as the target read voltage.

[0241] The implementation of step 902 can be found in the implementation of step 702 in the embodiment shown in Figure 7, and will not be repeated here.

[0242] 903. If a first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, then based on the existence of a second write operation identifier of the read address in the Bloom filter group included in the second SRAM, select one of the first read voltage and the second read voltage as the target read voltage.

[0243] For example, step 903 is implemented as follows: searching for the second write operation identifier of the read address in the Bloom filter group; if the second write operation identifier of the read address is not found, then selecting the second read voltage as the target read voltage from the first read voltage and the second read voltage; if the second write operation identifier of the read address is found in the target Bloom filter in the Bloom filter group, then selecting the first read voltage as the target read voltage from the first read voltage and the second read voltage.

[0244] When selecting the target read voltage using the Bloom filter group, the second write operation identifier of the read address is searched in each Bloom filter included in the Bloom filter group. Specifically, using the read address as the key, various mapping functions such as the Hash function in any Bloom filter are called to determine multiple mapping positions of the read address in the Bloom filter. The values ​​of the bits at the multiple mapping positions of the read address in the bit array of the Bloom filter are queried. If the values ​​of the bits at the multiple mapping positions of the read address in the bit array of the Bloom filter are all 1, it means that the second write operation identifier of the read address has been found; if the values ​​of one or more bits at the multiple mapping positions of the read address in the bit array of the Bloom filter are 0, it means that the second write operation identifier of the read address has not been found.

[0245] In this embodiment, if the second write operation identifier of the read address is not found in the Bloom filter group, the second read voltage is selected as the target read voltage from the first read voltage and the second read voltage; if the second write operation identifier of the read address is found in the Bloom filter group, it means that the first read voltage is selected as the target read voltage from the first read voltage and the second read voltage.

[0246] For better understanding, Figure 14 is used as an example for explanation. For all read I / O received by the PCM controller, please refer to page 31 of the manual (CN 120526820 A). The task is to determine whether the second write operation identifier of the read address exists in any Bloom filter within the Bloom filter group. Specifically, the read address is right-shifted by M bits, and the M-bit-shifted read address is used as the key. Multiple hash functions of each Bloom filter are called to map the key, obtaining multiple mapped positions of the read address in the bit array of the Bloom filter. For example, the multiple hash functions of the first Bloom filter are denoted as Hash 10, Hash 11, and Hash 12. If one or more bits at multiple mapped positions of the read address in the bit array of the first Bloom filter are found...If the value of the bit is 0, it means that the second write operation identifier of the read address has not been found; if the value of the bit at multiple mapping positions of the read address in the bit array of the first Bloom filter is 1, it means that the second write operation identifier of the read address has been found. Similarly, for all read I / O requests received by the PCM controller, the Bloom filter group is judged in each Bloom filter. If the second write operation identifier of the read address is not found in any Bloom filter, the second read voltage is selected as the target read voltage; if the second write operation identifier of the read address is found in any Bloom filter, the first read voltage is selected as the target read voltage.

[0247] 904. Perform a read operation on the storage cell corresponding to the read address in the storage medium according to the target read voltage.

[0248] The implementation of step 904 can be found in the implementation of step 704 in the embodiment shown in Figure 7, and will not be repeated here.

[0249] In some optional embodiments, in order to improve the reliability of reading correct data, after performing a read operation on the storage cell corresponding to the read address in the storage medium according to the target read voltage, if the target read voltage is the first read voltage, the read data is subjected to error checking and correction ECC processing; if the ECC processing result indicates that the read data is incorrect, then a second read voltage and a third read voltage are selected sequentially as the target read voltage, and the step of reading data from the storage cell corresponding to the read address in the storage medium according to the target read voltage is executed until the ECC processing result indicates that the read data is correct.

[0250] Since Bloom filters have a false positive rate, that is, if the judgment result is that an element exists, the element may not exist, but if the judgment result is that it does not exist, it definitely does not exist. Considering that Bloom filters have this characteristic, when the first read voltage is selected as the target read voltage, after reading data from the storage cell of the PCM storage medium according to the first read voltage, the read data needs to be processed by ECC to check whether the read data is correct. If the read data is correct, the read data is returned to the host, and the read process ends. If the read data is incorrect, the Read Retry mechanism is used to select one of the second and third read voltages as the new target read voltage, and the data is reread according to the new target read voltage. If the newly read data is incorrect, the Read Retry mechanism is used to select the unselected read voltage from the second and third read voltages as the new target read voltage, and the data is reread according to the new target read voltage. If the newly read data is incorrect, an error message is returned to the host; if the newly read data is correct, the correct newly read data is returned to the host.

[0251] In practical applications, when performing ECC processing on the read data, the ECC module uses the ECC algorithm to re-determine the target read voltage.If the redundancy check bit of the read data is the same as the redundancy check bit read from the storage medium, the data read from the PCM's storage medium is correct. If the redundancy check bit is different from the redundancy check bit read from the storage medium, the data read from the PCM's storage medium is incorrect.

[0252] It is understood that the Read Retry mechanism will only be used to try to find the correct read voltage if the target read voltage is the first read voltage and the data read by the first read voltage is incorrect. The probability of this situation is very small, which greatly reduces the probability of Read Retry and has almost no impact on the delay and bandwidth of the PCM controller.

[0253] The technical solution provided in this application adds a small amount of SRAM resources to the PCM controller. In the write-stage specification, page 26 / 31, section 32 CN 120526820 A, the bitmap provided by SRAM can be used to record whether a write operation occurs at each coarse-grained unit of time; the Bloom filter provided by SRAM can be used to record whether a write operation occurs at each fine-grained unit of time. Thus, in the read stage, even under high bandwidth conditions, the bitmap and Bloom filter provided by SRAM resources can correctly distinguish the three read voltage levels of the phase-change memory design, achieving a high probability of finding the correct read voltage to respond to the read I / O request at once, significantly reducing the number of read retryes, and greatly optimizing the QoS of the service system using the phase-change memory without affecting the overall system latency and bandwidth.

[0254] To better understand the read process, a specific read process is described below with reference to Figure 17. Figure 17 is a flowchart of another data access method for phase-change memory provided in this application embodiment. Referring to Figure 17, the method may include the following steps:

[0255] S1. In response to a read I / O request including a read address, a first write operation identifier of the read address is searched in the first bit map and the second bit map included in the first SRAM, and step S2 or S3 is executed.

[0256] S2. If the first write operation identifier of the read address is not found in either the first bit map or the second bit map, a third read voltage is selected as the target read voltage, and step S6 is executed.

[0257] S3. If the first write operation identifier of the read address is found in the first bit map and / or the second bit map, a second write operation identifier of the read address is searched in the Bloom filter group, and step S4 or S5 is executed.

[0258] S4. If the second write operation identifier of the read address is not found, a second read voltage is selected from the first read voltage and the second read voltage as the target read voltage, and step S6 is executed.

[0259] S5. If the second write operation identifier of the read address is found, a third write voltage is selected from the first read voltage and the second read voltage.The target read voltage is used as the read voltage, and step S6 is executed.

[0260] S6: Perform a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0261] The following describes the case where the phase change memory is configured with two levels of read voltage based on the Bloom filter group included in the SRAM. The write process is described with reference to FIG18, and the read process is described with reference to FIG19.

[0262] FIG18 is a flowchart of another phase change memory data access method provided in the embodiment of this application. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with a fourth read voltage and a fifth read voltage with a minimum write-after-read latency that are arranged from smallest to largest. The method is executed by the controller. See Figure 18. The method may include the following steps:

[0263] S1. In response to a write I / O request including a write address, according to the target arrangement position of the sub-unit time to which the current time belongs in the current time unit, a target Bloom filter located at the target arrangement position is selected in the Bloom filter group included in the third SRAM. The unit time includes n sub-unit times divided in sequence. The duration of the unit time is related to the minimum write-after-read latency of the fifth read voltage. The Bloom filter group includes n Bloom filters arranged in sequence.

[0264] In this embodiment, when the controller of the phase-change memory includes at least a third SRAM, the read voltages of the two levels can be correctly distinguished. Here, the read voltages of the two levels to be distinguished are referred to as the fourth read voltage and the fifth read voltage, respectively. The minimum write-after-read latency of the fourth read voltage is less than the minimum write-after-read latency of the fifth read voltage. In practical applications, the time ranges of the write-after-read delay corresponding to the fourth read voltage and the fifth read voltage may not overlap. Further optionally, the time ranges of the write-after-read delay corresponding to the fourth read voltage and the fifth read voltage may partially overlap. It is understood that the minimum write-after-read delay of the fifth read voltage is less than the maximum write-after-read delay of the fourth read voltage.

[0265] In this embodiment, the unit time is related to the minimum write-after-read delay of the fifth read voltage. For example, the duration of the unit time is equal to the minimum write-after-read delay of the fifth read voltage, or the duration of the unit time is obtained by increasing or decreasing the minimum write-after-read delay of the fifth read voltage; this is not limited. Specification 27 / 31 pages 33 CN 120526820 A

[0266] Specifically, the PCM controller receives and responds to a write I / O request including a write address sent by the host. During the response process, the write address in LA format in the write I / O request can be converted to the write address in PA format; the ECC module can also be called to encode the write data requested in the write I / O request, and the ECC algorithm can be used to determine the redundancy check bits of the write data, but it is not limited to these.

[0267] In this embodiment, the third SRAM includes a Bloom filter group comprising n sequentially arranged Bloom filters, where n is a positive integer greater than or equal to 3. Each unit time comprises n sequentially divided sub-unit time, so that the write address corresponding to a write I / O request in one sub-unit time of each unit time is recorded in a Bloom filter. For example, a Bloom filter bank consists of 10 Bloom filters. Taking a unit time of 100ms as an example, a unit time is divided into 10 sub-units, each with a duration of 10ms. The time range of the first sub-unit is 0-10ms, the second sub-unit is 10-20ms, the third sub-unit is 20-30ms, the fourth sub-unit is 30-40ms, the fifth sub-unit is 40-50ms, the sixth sub-unit is 50-60ms, the seventh sub-unit is 60-70ms, the eighth sub-unit is 70-80ms, the ninth sub-unit is 80-90ms, and the tenth sub-unit is 90-100ms.

[0268] Specifically, during the response to a write I / O request, the PCM controller also determines which unit time the current timing unit is based on the current timing and the timing start point, and determines the target arrangement position of the sub-unit time to which the current time belongs within the current timing unit time. The target arrangement position is, for example, any one of the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, etc. The target Bloom filter located at the target arrangement position is selected from the Bloom filter group included in the third SRAM. For example, the target Bloom filter is any one of the 1st Bloom filter, the 2nd Bloom filter, ..., the 10th Bloom filter.

[0269] S2. The write operation identifier of the write address is stored in the target Bloom filter, wherein the write operation identifier indicates that the target memory cell corresponding to the write address in the storage medium has performed a write operation.

[0270] For example, the implementation of storing the write operation identifier of the write address in the target Bloom filter is as follows: determine the mapping position of the write address in the bit array of the target Bloom filter; set the value of the bit at the second mapping position to the write operation identifier of the write address, so as to store the write operation identifier of the write address in the target Bloom filter.

[0271] Specifically, using the write address as the key, call multiple mapping functions such as the Hash function in the target Bloom filter to determine multiple mapping positions of the write address in the bit array of the target Bloom filter, set the value of the bit at the multiple mapping positions of the write address in the bit array of the target Bloom filter to 1, and store the corresponding bit in the bit array of the target Bloom filter.1 bit represents the write operation identifier of the write address, so as to save the write operation identifier of the write address in the target Bloom filter. It can be understood that if 0 bits in the bit array of the target Bloom filter, it means that no write address has been recorded.

[0272] Further optionally, before saving the write operation identifier of the write address in the target Bloom filter, the above method further includes: if the current time is not the first unit time, then the target Bloom filter is cleared, that is, the value of each bit in the bit array of the target Bloom filter is set to 0. If the current time is the first unit time, then the operation of saving the write operation identifier of the write address in the target Bloom filter is directly executed. In this way, the read correctness of the I / O request can be better guaranteed.

[0273] S3, Write the data requested by the write I / O request into the target storage unit.

[0274] In practical applications, the data requested by the write I / O request can be directly written to the target storage unit, or the ECC module can be called to encode the write data requested by the write I / O request, and the redundancy check bit of the write data can be determined using the ECC algorithm. The encoded write data and its redundancy check bit are then written to the target storage unit. This is not limited.

[0275] The technical solution provided in this application adds a small amount of SRAM resources to the PCM controller. During the write phase, the Bloom filter provided by the SRAM can record whether a write operation has occurred at each unit of time. In this way, during the subsequent read phase, even under high bandwidth conditions, the Bloom filter provided by the SRAM resources can correctly distinguish the two read voltage levels of the phase change memory design, and find the correct read voltage to respond to the read I / O request with a high probability at once, significantly reducing the number of read retryes. Under the condition of almost no impact on the latency and bandwidth of the overall system, the QoS of the service system using the phase change memory is greatly optimized.

[0276] After writing data based on the above write process, the read process of the phase-change memory is described below with reference to Figure 19. Figure 19 is a flowchart of another data access method of phase-change memory provided in the embodiment of this application. The phase-change memory includes at least: a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with a fourth read voltage and a fifth read voltage with the minimum write-to-read latency increasing from small to large. The method is executed by the controller. Referring to Figure 19, the method may include the following steps:

[0277] S1. In response to a read I / O request including a read address, the write operation identifier of the read address is searched in the Bloom filter group.

[0278] In this embodiment, the PCM controller receives and responds to a read I / O request including a read address sent by the host. During the response process, the read address in the form of LA in the read I / O request may also be converted to the read address in the form of PA, but it is not limited thereto.

[0279] During the write phase, the Bloom filter provided by SRAM can be used to record whether a write operation has occurred at each unit of time. When the PCM controller responds to a read I / O request, it searches for the write operation identifier of the read address in the Bloom filter group. Specifically, using the read address as the key, various mapping functions such as Hash functions in any Bloom filter are called to determine multiple mapping positions of the read address in the Bloom filter. The values ​​of the bits at the multiple mapping positions of the read address in the bit array of the Bloom filter are queried. If the values ​​of the bits at the multiple mapping positions of the read address in the bit array of the Bloom filter are all 1, it means that the write operation identifier of the read address has been found; if the values ​​of one or more bits at the multiple mapping positions of the read address in the bit array of the Bloom filter are 0, it means that the write operation identifier of the read address has not been found.

[0280] S2. If no write operation identifier for the read address is found in the Bloom filter group, the fifth read voltage is selected as the target read voltage.

[0281] S3. If a write operation identifier for the read address is found in the Bloom filter group, the fourth read voltage is selected as the target read voltage.

[0282] S4. Perform a read operation on the storage cell corresponding to the read address in the storage medium according to the target read voltage.

[0283] The specific implementation of the read operation is similar to that of the read operation in the aforementioned embodiment, and will not be repeated here.

[0284] In some optional embodiments, considering the false positive rate of the Bloom filter, in order to improve the reliability of reading the correct data, after performing a read operation on the storage cell corresponding to the read address in the storage medium according to the target read voltage, if the target read voltage is the fourth read voltage, the read data is subjected to error checking and correction ECC processing; if the ECC processing result indicates that the read data is incorrect, the fifth read voltage is used as the target read voltage, and the step of reading data from the storage cell corresponding to the read address in the storage medium according to the target read voltage is re-executed.

[0285] It is understood that the Read Retry mechanism will only be used to try to find the correct read voltage if the target read voltage is the fourth read voltage and the data read by the fourth read voltage is incorrect. The probability of this situation occurring is extremely small, greatly reducing the probability of Read Retry and having almost no impact on the latency and bandwidth of the PCM controller.

[0286] The technical solution provided in this application adds a small amount of SRAM resources to the PCM controller. During the write phase, the Bloom filter provided by the SRAM can be used to record whether a write operation occurs at each unit of time. In this way, during the read phase, even under high bandwidth conditions, the Bloom filter provided by the SRAM resources can correctly distinguish phase change memory.The two-stage read voltage design of the device enables the correct read voltage to be found in response to the read I / O request with a high probability in one go, significantly reducing the number of read retryes and greatly optimizing the QoS of the service system using the phase-change memory without affecting the latency and bandwidth of the overall system.

[0287] Figure 20 is a schematic diagram of another phase-change memory structure provided in the embodiment of this application. As shown in Figure 20, the phase-change memory includes: a controller 11 and a storage medium 12; the controller includes at least one SRAM; the controller is used to execute the steps in the data access method of the phase-change memory.

[0288] Further optionally, as shown in Figure 20, the phase-change memory also includes: a communication component 13, a display 14, a power supply component 15 and other components. Only some components are schematically shown in Figure 20, and it does not mean that the phase-change memory only includes the components shown in Figure 13. In addition, the components in the dashed box in Figure 20 are optional components, not mandatory components, and the specific components depend on the product form of the phase-change memory.

[0289] The embodiment of this application also provides a memory database system, which includes at least: the phase-change memory provided in the embodiment of this application.

[0290] This application embodiment also provides a cloud service product, including at least: the memory database system provided in this application embodiment.

[0291] This application embodiment also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to implement the steps in the phase-change memory data access method.

[0292] This application embodiment also provides a computer program product, including a computer program / instruction, which, when executed by a processor, enables the processor to implement the steps in the phase-change memory data access method.

[0293] The above-mentioned communication components are configured to facilitate wired or wireless communication between the device containing the communication components and other devices. The device containing the communication components can access wireless networks based on communication standards, such as WiFi (Wireless Fidelity), 2G (2nd Generation), 3G (3rd Generation), 4G (4th Generation) / LTE (long Term Evolution), 5G (5th Generation), or combinations thereof. In one exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In another exemplary embodiment, the communication component further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module may be based on Radio Frequency Identification (RFID).The display is implemented using Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0294] The above-mentioned display includes a screen, which may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a Touch Panel, the screen may be implemented as a touch screen to receive input signals from the user. The Touch Panel includes one or more touch sensors to sense touch, swipe, and gestures on the Touch Panel. The touch sensors may not only sense the boundaries of the touch or swipe action, but also detect the duration and pressure associated with the touch or swipe operation.

[0295] The above-mentioned power supply component provides power to various components of the device in which the power supply component is located. The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply component is located. (Pages 30 / 31 of Specification 36 CN 120526820 A)

[0296] It should be noted that the execution subject of each step of the method provided in the above embodiments can be the same device, or the method can be executed by different devices. Furthermore, some processes described in the above embodiments and accompanying drawings include multiple operations appearing in a specific order. However, it should be clearly understood that these operations may not be executed in the order they appear in this document, or may be executed in parallel. The operation numbers, such as 301, 302, etc., are merely used to distinguish different operations; the numbers themselves do not represent any execution order. Additionally, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first," "second," etc., in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to different types.

[0297] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0298] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusivity.The term "comprises" implies that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0299] The above are merely embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application. Instruction Manual Page 31 / 31 37 CN 120526820 A Figure 1 Figure 2 Instruction Manual Figure 1 / 13 Page 38 CN 120526820 A Figure 3 Instruction Manual Figure 2 / 13 Page 39 CN 120526820 A Figure 4 Figure 5 Instruction Manual Figure 3 / 13 Page 40 CN 120526820 A Figure 6 Instruction Manual Figure 4 / 13 Page 41 CN 120526820 A Figure 7 Figure 8 Instruction Manual Figure 5 / 13 Page 42 CN 120526820 A Figure 9 Figure 10 Instruction Manual Figure 6 / 13 Page 43 CN 120526820 A Figure 11 Figure 12 Instruction Manual Figure 7 / 13 Page 44 CN 120526820 A Figure 13 Instruction Manual Figure 8 / 13 Page 45 CN 120526820 A Figure 14 Instruction Manual Figure 9 / 13 Page 46 CN 120526820 A Figure 15 Instruction Manual Drawings 10 / 13 Page 47 CN 120526820 A Figure 16 Figure 17 Instruction Manual Drawings 11 / 13 Page 48 CN 120526820 A Figure 18 Figure 19 Instruction Manual Drawings 12 / 13 Page 49 CN 120526820 A Figure 20 Instruction Manual Drawings 13 / 13 Page 50 CN 120526820 A Abstract The embodiment of the invention provides a data access method of a phase change memory, related device and a storage medium. In the embodiment of the invention, a smallamount of SRAM (Static Random Access Memory) resources are added in a PCM (Pulse Code Modulation) controller, and in a writing stage, whether a writing operation occurs in each coarse-grained unit time or not can be recorded by utilizing a bitmap provided by the SRAM; and a Bloom filter provided by the SRAM can be used for recording whether a writing operation occurs in each fine-grained unit time or not. Therefore, in the subsequent reading stage, even under the condition of large bandwidth, the bitmap and the Bloom filter provided by the SRAM resource can be utilized to correctly distinguish the reading voltage of three gears designed for the phase change memory, so that the correct reading voltage in response to a read I / O request can be found at one time with a relatively large probability, and the number of Read Retry times is significantly reduced. And the QoS of a service system using the phase change memory is greatly optimized under the condition that the time delay andbandwidth of the whole system are hardly influenced.

Claims

1. A data access method for a phase change memory, characterized in that: The phase change memory comprises at least: a controller and a storage medium, the controller comprises at least a first static random access memory SRAM and a second SRAM, the phase change memory is configured with a first read voltage, a second read voltage and a third read voltage with a minimum read-after-write delay in ascending order; the method is executed by the controller, the method comprising: In response to a write I / O request including a write address, selecting a target bitmap from a first bitmap and a second bitmap included in a first SRAM according to a parity type of a coarse-grained unit time currently being counted, wherein a duration of the coarse-grained unit time is related to a minimum read-after-write delay of the third read voltage, and the first bitmap and the second bitmap are used to select the third read voltage during a read phase; storing a first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; selecting, according to a parity type of a fine-grained unit time currently being counted, a target Bloom filter from a first Bloom filter and a second Bloom filter included in the second SRAM, wherein the duration of the fine-grained unit time is related to a minimum read-after-write delay of the second read voltage, and the first Bloom filter and the second Bloom filter are used to select the first read voltage or the second read voltage during a read phase; storing a second write operation identifier of the write address in the target Bloom filter, wherein the second write operation identifier indicates that a write operation has been performed on the target storage unit; The data requested to be written by the write I / O request is written into the target storage unit.

2. The method according to claim 1, characterized in that Selecting a target bitmap from a first bitmap and a second bitmap included in the first SRAM according to a parity type of a coarse-grained unit time of current timing, comprising: If the parity type indicates that the coarse-grained unit time of the current timing is an odd-numbered coarse-grained unit time, selecting the first bitmap as the target bitmap from the first bitmap and the second bitmap included in the first SRAM, the first bitmap being associated with the odd-numbered coarse-grained unit time; If the parity type indicates that the coarse-grained unit time of the current timing is an even-numbered coarse-grained unit time, the second bitmap is selected as the target bitmap from the first bitmap and the second bitmap included in the first SRAM, and the second bitmap is associated with the even-numbered coarse-grained unit time.

3. The method according to claim 1, characterized in that Saving the first write operation identifier of the write address in the target bitmap includes: Shifting the write address right by M bits, where M is a positive integer; Determining a first mapping position corresponding to the write address in the bit array of the target bitmap based on the right-shifted write address; The value of the bit at the first mapping position is set as the first write operation identifier of the write address, so as to save the first write operation identifier of the write address in the target bitmap.

4. The method according to any one of claims 1 to 3, characterized in that Before storing the first write operation identifier of the write address in the target bitmap, the method further includes: If the current time is the start time of the coarse-grained unit time of the current timing, the target bitmap is cleared.

5. The method according to claim 1, wherein Selecting a target Bloom filter from a first Bloom filter and a second Bloom filter included in the second SRAM according to a parity type of a fine-grained unit time currently being counted includes: If the parity type indicates that the fine-grained unit time of the current timing is an odd-numbered fine-grained unit time, selecting the first Bloom filter as the target Bloom filter from a first Bloom filter and a second Bloom filter included in the second SRAM, the first Bloom filter being associated with the odd-numbered fine-grained unit time; If the parity type indicates that the fine-grained unit time of the current timing is an even-numbered fine-grained unit time, the second Bloom filter is selected as the target Bloom filter from the first Bloom filter and the second Bloom filter included in the second SRAM, and the second Bloom filter is associated with the even-numbered fine-grained unit time.

6. The method according to claim 1, characterized in that Saving the second write operation identifier of the write address in the target Bloom filter includes: determining a second mapping location of a write address in the bit array of the target Bloom filter; The value of the bit at the second mapping position is set as the second write operation identifier of the write address, so as to store the second write operation identifier of the write address in the target Bloom filter.

7. The method according to any one of claims 1 to 3, 5 and 6, characterized in that Before storing the second write operation identifier of the write address in the target Bloom filter, the method further includes: If the current time is the start time of the fine-grained unit time of the current timing, the target Bloom filter is cleared.

8. A data access method for a phase change memory, characterized in that: The phase change memory comprises at least: a controller and a storage medium, the controller comprises at least a first SRAM and a second SRAM, the phase change memory is configured with a first read voltage, a second read voltage and a third read voltage with a minimum read-after-write delay in ascending order; the method is executed by the controller, the method comprising: In response to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bitmap and a second bitmap included in the first SRAM; If the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, selecting the third read voltage as the target read voltage; If a first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, selecting one of the first read voltage and the second read voltage as the target read voltage based on the existence of a second write operation identifier of the read address in the first Bloom filter and the second Bloom filter included in the second SRAM; A read operation is performed on a storage unit corresponding to the read address in the storage medium according to a target read voltage.

9. The method according to claim 8, characterized in that Selecting one of the first read voltage and the second read voltage as the target read voltage based on the existence of the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter included in the second SRAM includes: searching the first Bloom filter and the second Bloom filter for a second write operation identifier of the read address; If the second write operation identifier of the read address is not found, selecting the second read voltage from the first read voltage and the second read voltage as the target read voltage; If the second write operation identifier of the read address is found, the first read voltage is selected as the target read voltage from the first read voltage and the second read voltage.

10. The method according to claim 9, characterized in that After performing a read operation on the storage unit corresponding to the read address in the storage medium according to the target read voltage, the method further includes: If the target read voltage is the first read voltage, performing error checking and correction (ECC) processing on the read data; If the ECC processing result indicates that the read data is incorrect, the second read voltage and the third read voltage are used as target read voltages in sequence, and the step of reading data from the storage unit corresponding to the read address in the storage medium according to the target read voltages is performed until the ECC processing result indicates that the read data is correct.

11. A data access method for a phase change memory, characterized in that: The phase change memory comprises at least: a controller and a storage medium, the controller comprises at least a third SRAM, the phase change memory is configured with a fourth read voltage and a fifth read voltage with a minimum read-after-write delay from small to large; the method is executed by the controller, the method comprising: In response to a write I / O request including a write address, selecting a target bitmap from a third bitmap and a fourth bitmap included in the third SRAM according to a parity type of a currently counted unit time, wherein the third bitmap is associated with an odd-numbered unit time, the fourth bitmap is associated with an even-numbered unit time, and the duration of the unit time is associated with a minimum read-after-write delay of the fifth read voltage; storing a write operation identifier of the write address in the target bitmap, wherein the write operation identifier indicates that a write operation has been performed on the target storage unit corresponding to the write address in the storage medium; The data requested to be written by the write I / O request is written into the target storage unit.

12. The method according to claim 11, characterized in that Also includes: In response to a read I / O request including a read address, searching for a write operation identifier of the read address in the third bitmap and the fourth bitmap; If the write operation identifier of the read address is not found in the third bitmap and the fourth bitmap, selecting the fifth read voltage as the target read voltage; If the write operation identifier of the read address is found in the third bitmap and / or the fourth bitmap, selecting the fourth read voltage as the target read voltage; A read operation is performed on a storage unit corresponding to the read address in the storage medium according to a target read voltage.

13. A data access method for a phase change memory, characterized in that: The phase change memory comprises at least: a controller and a storage medium, the controller comprises at least a third SRAM, the phase change memory is configured with a fourth read voltage and a fifth read voltage with a minimum read-after-write delay from small to large; the method is executed by the controller, the method comprising: In response to a write I / O request including a write address, selecting a target Bloom filter from a third Bloom filter and a fourth Bloom filter included in the third SRAM according to a parity type of a currently counted unit time, wherein the third Bloom filter is associated with an odd-numbered unit time, the fourth Bloom filter is associated with an even-numbered unit time, and a duration of the unit time is associated with a minimum read-after-write delay of the fifth read voltage; Saving a write operation identifier of the write address in the target Bloom filter, wherein the write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; The data requested to be written by the write I / O request is written into the target storage unit.

14. The method according to claim 13, characterized in that Also includes: In response to a read I / O request including a read address, searching for a write operation identifier of the read address in the third Bloom filter and the fourth Bloom filter; If the write operation identifier of the read address is not found in the third Bloom filter and the fourth Bloom filter, selecting the fifth read voltage as the target read voltage; If a write operation identifier of the read address is found in the third Bloom filter and the fourth Bloom filter, selecting the fourth read voltage as the target read voltage; A read operation is performed on a storage unit corresponding to the read address in the storage medium according to a target read voltage.

15. The method according to claim 14, characterized in that After performing a read operation on the storage unit corresponding to the read address in the storage medium according to the target read voltage, the method further includes: If the target read voltage is the fourth read voltage, performing error checking and correction (ECC) processing on the read data; If the ECC processing result indicates that the read data is erroneous, the fifth read voltage is used as the target read voltage, and the step of reading data from the storage unit corresponding to the read address in the storage medium according to the target read voltage is re-executed.

16. A data access method for a phase change memory, characterized in that: The phase change memory comprises at least: a controller and a storage medium, the controller comprises at least a first SRAM and a second SRAM, the phase change memory is configured with a first read voltage, a second read voltage, and a third read voltage with a minimum read-after-write delay in ascending order; the method is executed by the controller, the method comprising: In response to a write I / O request including a write address, selecting a target bitmap from a first bitmap and a second bitmap included in the first SRAM according to a parity type of a coarse-grained unit time currently being counted, wherein the duration of the coarse-grained unit time is related to a minimum read-after-write delay of the third read voltage, and the first bitmap and the second bitmap are used to select the third read voltage during a read phase; storing a first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; selecting, from a Bloom filter group included in the second SRAM, a target Bloom filter located at the target arrangement position according to a target arrangement position of a sub-unit time to which the current time belongs in a fine-grained unit time currently being counted, wherein the fine-grained unit time includes n sub-unit times divided in sequence, the duration of the fine-grained unit time is related to a minimum read-after-write delay of the second read voltage, the Bloom filter group is used to select the first read voltage or the second read voltage during a read phase, and the Bloom filter group includes n Bloom filters arranged in sequence; storing a second write operation identifier of the write address in the target Bloom filter, wherein the second write operation identifier indicates that a write operation has been performed on the target storage unit; The data requested to be written by the write I / O request is written into the target storage unit.

17. A data access method for a phase change memory, characterized in that: The phase change memory comprises at least: a controller and a storage medium, the controller comprises at least a first SRAM and a second SRAM, the phase change memory is configured with a first read voltage, a second read voltage and a third read voltage with a minimum read-after-write delay in ascending order; the method is executed by the controller, the method comprising: In response to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bitmap and a second bitmap included in the first SRAM; If the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, selecting the third read voltage as the target read voltage; If a first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, selecting one of the first read voltage and the second read voltage as the target read voltage based on the existence of a second write operation identifier of the read address in the Bloom filter group included in the second SRAM; A read operation is performed on a storage unit corresponding to the read address in the storage medium according to a target read voltage.

18. A data access method for a phase change memory, characterized in that: The phase change memory comprises at least: a controller and a storage medium, the controller comprises at least a third SRAM, the phase change memory is configured with a fourth read voltage and a fifth read voltage with a minimum read-after-write delay from small to large; the method is executed by the controller, the method comprising: In response to a write I / O request including a write address, selecting a target Bloom filter located at a target arrangement position in a Bloom filter group included in the third SRAM according to a target arrangement position of a sub-unit time to which the current time belongs in a unit time currently being counted, wherein the unit time includes n sub-unit times divided in sequence, a duration of the unit time is related to a minimum read-after-write delay of a fifth read voltage, and the Bloom filter group includes n Bloom filters arranged in sequence; storing a write operation identifier of the write address in the target Bloom filter, wherein the write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; The data requested to be written by the write I / O request is written into the target storage unit.

19. A data access method for a phase change memory, characterized in that: The phase change memory comprises at least: a controller and a storage medium, the controller comprises at least a third SRAM, the phase change memory is configured with a fourth read voltage and a fifth read voltage with a minimum read-after-write delay from small to large; the method is executed by the controller, the method comprising: In response to a read I / O request including a read address, searching for a write operation identifier of the read address in a Bloom filter group included in the third SRAM; If no write operation identifier of the read address is found in the Bloom filter group, selecting the fifth read voltage as the target read voltage; If a write operation identifier of the read address is found in the Bloom filter group, selecting the fourth read voltage as the target read voltage; A read operation is performed on a storage cell corresponding to a read address in a storage medium according to the target read voltage.

20. A phase change memory, characterized in that: At least: A controller and a storage medium, wherein the controller includes at least one SRAM; The controller is used to execute the steps in the method according to any one of claims 1 to 19.

21. A memory database system, characterized in that: At least: The phase change memory according to claim 20.

22. A cloud service product, characterized in that: At least: The in-memory database system of claim 21.

23. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the processor is enabled to implement the steps of the method according to any one of claims 1 to 19.

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