Electro-optical device and electronic apparatus

Abstract

To reduce the electric power consumed in the parasitic capacitance of data lines in an electro-optical device.SOLUTION: A pixel circuit 110 includes an OLED that emits light with a luminance corresponding to the current flowing from the anode to the cathode, and a transistor that flows a current to the OLED that corresponds to the voltage between the gate node and the source node. A control circuit 30 supplies a potential corresponding to the grayscale level to the gate node via a data line 14 in a first frame write period, supplies a potential Vel for placing the transistor 121 in an off state to the gate node via the data line 14 in a first initialization period prior to the write period, executes a reset operation in odd-numbered rows in a second initialization period, and executes a non-reset operation in even-numbered rows. The reset operation involves supplying a potential Vorst via the data line 14, and the non-reset operation involves raising or lowering the potential of the data line 14 and the anode potential to a potential between the potential Vel and the potential Vorst.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] In recent years, various electro-optical devices (display devices) using light-emitting elements such as organic light-emitting diodes (hereinafter referred to as "OLEDs") have been proposed. In electro-optical devices, a pixel circuit including the light-emitting elements and driving transistors is generally provided at the intersections of scanning lines and data lines, corresponding to the pixels of an image to be displayed.

[0003] In such a configuration, when a data signal having a potential corresponding to the grayscale level of a pixel is supplied to the gate node of the driving transistor, the driving transistor supplies a current corresponding to the voltage between the gate node and the source node to the light-emitting element, causing the light-emitting element to emit light with a brightness corresponding to the grayscale level. A pixel circuit having four transistors including a drive transistor is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-179628 Summary of the Invention [Problem to be solved by the invention]

[0005] When an electro-optical device is miniaturized and applied to a portable device, there is a strong demand for low power consumption due to battery etc. However, the above-described configuration has a problem in that the power consumption is not sufficiently low. [Means for solving the problem]

[0006] In order to solve the above problems, an electro-optical device according to one aspect of the present disclosure includes: [Brief description of the drawings]

[0007] [Figure 1] 1 is a perspective view of an electro-optical device according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing an electrical configuration of the electro-optical device. [Diagram 3] FIG. 2 is a diagram illustrating a pixel circuit of the electro-optical device. [Figure 4] 4 is a timing chart showing the operation of the electro-optical device. [Diagram 5] 4 is a timing chart showing the operation of the electro-optical device. [Figure 6] 5A to 5C are diagrams illustrating the operation of the electro-optical device. [Figure 7] 5A to 5C are diagrams illustrating the operation of the electro-optical device. [Figure 8] 5A to 5C are diagrams illustrating the operation of the electro-optical device. [Figure 9] 5A to 5C are diagrams illustrating the operation of the electro-optical device. [Figure 10] 5A to 5C are diagrams illustrating the operation of the electro-optical device. [Figure 11] 5A to 5C are diagrams illustrating the operation of the electro-optical device. [Figure 12] 5A to 5C are diagrams illustrating the operation of the electro-optical device. [Figure 13] 1A and 1B are diagrams for explaining advantages of an electro-optical device. [Figure 14] FIG. 1 is a perspective view showing a head mounted display using an electro-optical device. [Figure 15] FIG. 2 is a diagram showing an optical configuration of a head mounted display. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, electro-optical devices according to embodiments will be described with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred specific examples, and therefore various technically preferable limitations are attached, but the scope of the present disclosure is not limited to these forms unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0009] FIG. 1 is a perspective view showing an electro-optical device 10 according to an embodiment. The electro-optical device 10 is a micro display panel that displays an image in, for example, a head mounted display. The electro-optical device 10 includes a pixel circuit including an OLED, a drive circuit that drives the pixel circuit, and the like. The pixel circuit, the drive circuit, and the like are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

[0010] The electro-optical device 10 is housed in a frame-shaped case 192 that opens in the display region 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 194 is provided with a plurality of terminals 196 that are connected to a host device (not shown). When the plurality of terminals 196 are connected to the host device, video data, synchronization signals, and the like are supplied to the electro-optical device 10 from the host device via the FPC board 194.

[0011] In the figure, the X direction indicates the extension direction of the scanning lines in the electro-optical device 10, and the Y direction indicates the extension direction of the data lines. The two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and is the emission direction of the light emitted from the OLED.

[0012] 2 is a block diagram showing an electrical configuration of the electro-optical device 10. As shown in the figure, the electro-optical device 10 includes a control circuit 30, a data signal output circuit 50, an auxiliary circuit 60, n capacitive elements 70, an initialization circuit 80, a display area 100, and a scanning line driving circuit 120. In the display area 100, m rows of scanning lines 12 are provided along the X direction in the drawing, and n columns of data lines 14 are provided along the Y direction so as to be electrically insulated from each of the scanning lines 12. Here, m and n are integers of 2 or more.

[0013] In the display region 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scanning lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix of m rows and n columns. In order to distinguish the rows of the matrix arrangement, they may be referred to as 1, 2, 3, ..., (m-1), mth row from the top in the figure. Similarly, in order to distinguish the columns of the matrix, they may be referred to as 1, 2, 3, ..., (n-1), nth column from the left in the figure. Integers (i-1) and i, which are 1 to m, are used to generally describe the scan lines 12. In particular, (i-1) may be used as an odd number to generally describe odd-numbered (1, 3, 5, ...) rows, and i may be used as an even number to generally describe even-numbered (2, 4, 6, ...) rows. In addition, an integer j, which is 1 to n, is used to generally describe the data lines 14.

[0014] The control circuit 30 controls each unit based on video data Vid and a synchronous signal Sync supplied from a host device. The video data Vid specifies the gradation level of pixels in an image to be displayed, for example, in 8 bits. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data.

[0015] In this embodiment, the pixels of an image to be displayed and the pixel circuits 110 in the display area 100 correspond one-to-one. The brightness characteristic indicated by the grayscale level in the video data Vid supplied from the host device does not necessarily match the luminance characteristic of the OLED included in the pixel circuit 110. Therefore, in order to make the OLED emit light at a brightness corresponding to the grayscale level specified by the video data Vid, the control circuit 30 up-converts the 8 bits of the video data Vid to, for example, 10 bits in the embodiment and outputs it as the video data Vdata. Therefore, the 10-bit video data Vdata also specifies a grayscale level. In other words, the video data Vdata specifies a grayscale level obtained by converting the grayscale level specified by the video data Vid.

[0016] For the up-conversion, a look-up table is used that stores in advance the correspondence between the 8-bit input video data Vid and the 10-bit output video data Vdata. The control circuit 30 generates various control signals to control each unit, as will be described in detail later.

[0017] The scanning line driving circuit 120 is a circuit for outputting various signals to drive the pixel circuits 110 arranged in m rows and n columns, row by row, under the control of the control circuit 30. For example, the scanning line driving circuit 120 supplies scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), / Gwr(m) to the 1st, 2nd, 3rd, ..., (m-1), mth scanning lines 12 in order. In general, the scanning signal supplied to the (i-1)th scanning line 12 is represented as / Gwr(i-1). The scanning line driving circuit 120 outputs various control signals in addition to the scanning signals / Gwr(1) to / Gwr(m), which will be described in detail later.

[0018] The data signal output circuit 50 is a circuit that outputs a signal of a voltage according to luminance to the pixel circuits 110 located in a row selected by the scanning line driving circuit 120. In detail, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, and n DA conversion circuits 500. The selection circuit group 52 includes selection circuits 520 in one-to-one correspondence with the n columns, the first latch circuit group 54 includes first latch circuits L1 in one-to-one correspondence with the n columns, and the second latch circuit group 56 includes second latch circuits L2 in one-to-one correspondence with the n columns. Also, the n DA conversion circuits 500 are in one-to-one correspondence with the n columns.

[0019] That is, a set of a selection circuit 520, a first latch circuit L1, a second latch circuit L2, and a DA conversion circuit 500 is provided corresponding to each example. Here, the selection circuit 520 of the jth column instructs the first latch circuit L1 of the jth column to select the video data of the jth column from the video data Vdata output from the control circuit 30, and the first latch circuit L1 of the jth column latches the video data Vdata according to the instruction. The second latch circuit L2 of the jth column outputs the video data Vdata latched by the first latch circuit L1 of the jth column to the DA conversion circuit 500 of the jth column in a writing period (C) described later according to the control of the control circuit 30.

[0020] The j-th column DA conversion circuit 500 converts the 10-bit video data Vdata output from the j-th column second latch circuit L2 into an analog signal and outputs it to the j-th column data signal output line 14c. In other words, the data signal output line 14c is provided in one-to-one correspondence with the data line 14, and the output terminal of the j-th column DA conversion circuit 500 is connected to the j-th column data signal output line 14c.

[0021] The auxiliary circuit 60 is a collection of transistors 62 provided in one-to-one correspondence with the data signal output lines 14c. The source node of the transistor 62 corresponding to the jth column is connected to a power supply line of potential Vref, and the drain node of the transistor 62 is connected to the jth data signal output line 14c. A control signal / Gref output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 62 in each column.

[0022] The n capacitive elements 70 are provided in one-to-one correspondence with pairs of data signal output lines 14c and data lines 14. In particular, one end of the capacitive element 70 in the jth column is connected to the data signal output line 14c in the jth column, and the other end of the capacitive element 70 in the jth column is connected to the data line 14 in the jth column. The video data Vdata corresponds to a gradation level specified by the video data Vid, and the DA conversion circuit 500 converts the video data Vdata into an analog signal, which is supplied as a data signal to the data line 14 via the capacitive element 70. Therefore, the potential of the data signal supplied to the data line 14 corresponds to the gradation level specified by the video data Vid and the video data Vdata.

[0023] The initialization circuit 80 is a collection of pairs of transistors 82 , 84 and 86 provided in one-to-one correspondence with the data lines 14 . A source node of the transistor 82 corresponding to the j-th column is connected to a power supply line of potential Vel, and a drain node of the transistor 82 is connected to the data line 14 of the j-th column. A control signal / Drst output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 82 in each column. The potential Vel is used as a high-level potential of the power supply voltage.

[0024] A source node of the transistor 84 corresponding to the j-th column is connected to a power supply line of potential Vini, and a drain node of the transistor 84 is connected to the j-th column data line 14. A control signal / Gini output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 84 in each column.

[0025] The source node of the transistor 86 corresponding to the j-th column is connected to a power supply line of the potential Vorst, and the drain node of the transistor 86 is connected to the data line 14 of the j-th column. A control signal / Grst output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 86 in each column. The potential Vorst is, for example, the potential Gnd or a low potential close to the potential Gnd. Specifically, the potential Vorst is a potential at which no current flows through the OLED if power is supplied to the anode of the OLED.

[0026] A capacitance component parasitic on each data line 14 of each column. In the figure, the capacitance component is represented as a parasitic capacitance 72. That is, the parasitic capacitance 72 is represented electrically as a capacitance element having one end connected to the data line 14 and the other end connected to a power supply line having a constant potential. In addition, in the figure, the potentials of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are denoted as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n), respectively. In general, the potential of the data line 14 in the jth column is denoted as Vd(j).

[0027] 3 is a circuit diagram showing a pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to one another. For this reason, the pixel circuits 110 will be described by taking the pixel circuit 110 located in the (i-1)th row and jth column as a representative.

[0028] As shown in the figure, the pixel circuit 110 includes an OLED 130, p-type transistors 121 to 124, and a capacitance element 140. The transistors 121 to 124 are, for example, MOS type. Note that MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor. In addition, the pixel circuit 110 in the (i-1)th row is supplied with the control signals / Gel(i-1) and / Gcmp(i-1) from the scanning line driving circuit 120 in addition to the scanning signal / Gwr(i-1) corresponding to the (i-1)th row.

[0029] Control signal / Gel(i-1) is a generalized representation of control signals / Gel(1), / Gel(2), ..., / Gel(m-1), / Gel(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows. Similarly, control signal / Gcmp(i-1) is a generalized representation of control signals / Gcmp(1), / Gcmp(2), ..., / Gcmp(m-1), / Gcmp(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows.

[0030] The OLED 130 is a light-emitting element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is optically transparent. In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby emitting white light.

[0031] In the case of color display, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), and B (blue). A color filter corresponding to the color is provided on the light emission side from the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and the color filter in order, and is visually recognized by the observer. Note that the optical resonator is omitted. In addition, when the electro-optical device 10 simply displays a monochromatic image of light and dark only, the optical resonator and the color filter are omitted.

[0032] In the transistor 121 of the pixel circuit 110 in the (i-1)th row and jth column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply line 116 to which the potential Vel is supplied, and the drain node d is connected to the source node of the transistor 123 and the source node of the transistor 124. In the capacitance element 140, one end is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116. Therefore, the capacitance element 140 holds the voltage between the gate node g and the source node s of the transistor 121. The other end of the capacitive element 140 may be connected to a power supply line of a different potential other than the power supply line 116 of the potential Vel, as long as the potential is kept substantially constant.

[0033] In the embodiment, a so-called MOS capacitance formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer (lower electrode) and a gate electrode layer (upper electrode) of a transistor is used as the capacitance element 140. Note that a parasitic capacitance of the gate node g of the transistor 121 may be used as the capacitance element 140, or a so-called metal capacitance formed by sandwiching an insulating layer between different conductive layers in a semiconductor substrate may be used.

[0034] In the transistor 122 of the pixel circuit 110 in the (i-1)th row and jth column, a gate node is connected to the (i-1)th row scanning line 12, and a source node is connected to the jth column data line 14. In the transistor 123 of the pixel circuit 110 in the (i-1)th row and jth column, a control signal / Gcmp(i-1) is supplied to a gate node, and a drain node is connected to the jth column data line 14. In the transistor 124 of the pixel circuit 110 in the (i-1)th row and jth column, a control signal / Gel(i-1) is supplied to a gate node, and a drain node is connected to the pixel electrode 131 which is the anode of the OLED 130. A potential Vct is supplied to the common electrode 133 that functions as the cathode of the OLED 130. Note that the potential Vct is, for example, the potential Gnd or a low potential close to the potential Gnd.

[0035] In this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, coupling between two or more elements in a semiconductor substrate through different wiring layers and contact holes even if the elements are not directly connected to each other.

[0036] The control circuit 30 controls driving of the pixel circuit 110 via the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scanning line drive circuit 120. For this reason, the control circuit 30, the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scanning line drive circuit 120 may be collectively referred to as a control circuit in a broad sense that controls the pixel circuit 110.

[0037] Next, the operation of the electro-optical device 10 will be described.

[0038] 4 and 5 are timing charts illustrating the operation of the electro-optical device. Of these, FIG. 4 is a timing chart for an odd-numbered frame (V_odd), and FIG. 5 is a timing chart for an even-numbered frame (V_even).

[0039] In this description, an odd frame (V_odd) refers to the frame that precedes the other of two consecutive frames, and an even frame (V_even) refers to the frame that follows the other of two consecutive frames. One frame refers to the period required to display one frame of an image specified by video data Vid. When the time length of one frame is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal.

[0040] In the electro-optical device 10, in each of the odd-numbered frames (V_odd) and even-numbered frames (V_odd), m scanning lines 12 are selected one by one in the order of 1st, 2nd, 3rd, ..., mth row and horizontally scanned. The period required for horizontal scanning of one row is the horizontal scanning period (H).

[0041] In the electro-optical device 10, the horizontal scanning period (H) is divided, in order of time, into an initialization period (A), a compensation period (B), and a writing period (C). Of these, the initialization period (A) is further divided into three initialization periods (A1), (A2), and (A3). In addition to the initialization period (A), the compensation period (B), and the writing period (C), the operation of the pixel circuit 110 further includes a light emission period (D).

[0042] The initialization period (A1) is a period for setting the transistor 121 to an off state. The initialization period (A2) is a period for resetting the anode potential of the OLED 130 for either the odd-numbered rows or the even-numbered rows. Note that in the initialization period (A2), the anode potential of the OLED 130 is not reset for the other of the odd-numbered rows or the even-numbered rows. The initialization period (A3) is a period for supplying the potential Vini for turning on the transistor 121 to the gate node g. The compensation period (B) is a period for causing the gate node g of the transistor 121 to converge to a potential corresponding to the threshold voltage of the transistor 121. The write period (C) is a period during which a potential corresponding to the gradation level is held (written) at the gate node g of the transistor 121, and more specifically, is a period during which the gate node g of the transistor 121 is changed from a potential corresponding to the threshold voltage by an amount corresponding to a voltage corresponding to the current flowing through the OLED 130. The light emitting period (D) is a period for causing a current corresponding to the potential of the gate node g held in the writing period (C) to flow through the OLED 130 to emit light.

[0043] As described above, in the embodiment, there is a division into odd frames (V_odd) and even frames (V_odd). In addition, the operation of each row in the horizontal scanning period (H) is common except that it differs between odd-numbered rows and even-numbered rows in the initialization period (A2), and the operation of the pixel circuits 110 in columns 1 to n of a row scanned in a certain horizontal scanning period (H) is almost common. Therefore, in the following, the operation of the odd frame (V_odd) will be described first, and then the operation of the even frame (V_even) will be described. Also, in each frame, the operation of the odd (i-1)th row horizontal scanning period (H_odd) and the pixel circuit 110 in the (i-1)th row and jth column will be described first, and then the operation of the even ith row horizontal scanning period (H_even) and the pixel circuit 110 in the ith row and jth column will be described.

[0044] In an odd-numbered frame (V_odd), in the initialization period (A1) of each horizontal scanning period (H), the control signal / Drst is at L level, the control signal / Gini is at H level, and the control signal / Gref is at L level. Therefore, the transistors 82 in each column are turned on, the transistors 84 in each column are turned off, and the transistors 62 in each column are turned on. In addition, in the initialization period (A1) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row in the odd-numbered frame (V_odd), the control signal / Grst is at H level, so that the transistors 86 in each column are turned off.

[0045] In the initialization period (A1) of the horizontal scanning period (H_odd) in the odd-numbered (i-1)th row, the scanning signal / Gwr(i-1) is at the L level, the control signal / Gcmp(i-1) is at the H level, and the control signal / Gel(i-1) is at the H level. Therefore, in the initialization period (A1), in the pixel circuit 110 in the (i-1)th row and jth column, the transistor 122 is in the ON state, the transistor 123 is in the OFF state, and the transistor 124 is in the OFF state. The initialization period (A1) of the horizontal scanning period (H_odd) corresponds to the "first gate node initialization period" in the claims.

[0046] 6, in the pixel circuit 110 in the (i-1)th row and jth column, a potential Vel is supplied to one end of the capacitance element 140 and to the gate node g of the transistor 121 via the transistor 82, the jth column data line 14, and the transistor 122 in that order. When the gate node g reaches the potential Vel, the voltage between the gate node g and the source node s becomes zero, and the transistor 121 is forced to enter an off state. In this embodiment, the transistor 121 is set to the off state in the initialization period (A1), but this is not limiting, and the initialization period (A1) may be omitted. That is, the transistor 121 may not be set to the off state in the initialization period (A1), and the anode potential of the OLED 130 may be reset in the initialization period (A2). Also, the transistor 122 may be set to the off state to reset the anode potential of the OLED 130.

[0047] In the initialization period (A1) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row in the odd-numbered frame (V_odd), the transistor 82 is in the on state in each column, and the transistor 62 is in the on state in each column. Therefore, in the initialization period (A1) of the horizontal scanning period (H_odd), the data line 14 is at the potential Vel, and the data signal output line 14c is at the potential Vref in each column. Therefore, in each column, the voltage across the capacitive element 70 becomes |Vel-Vref|, and one end of the parasitic capacitance 72 is held at the potential Vel. Since the potential Vel is the higher level of the power supply voltage, in each column, the capacitive element 70 and the parasitic capacitance 72 are charged.

[0048] In an odd frame (V_odd), during the initialization period (A2) of each horizontal scanning period (H), the control signal / Drst changes to H level, the control signal / Gini maintains H level, and the control signal / Gref maintains L level. As a result, the transistors 82 in each column change to the OFF state, the transistors 84 in each column maintain the OFF state, and the transistors 62 in each column maintain the ON state. In addition, in the initialization period (A2) of the horizontal scanning period (H_odd) of the odd-numbered (i-1) row, the control signal / Grst changes to the L level, so that the transistors 86 in each column change to the ON state.

[0049] In the initialization period (A2) of the horizontal scanning period (H_odd) in the odd-numbered (i-1)th row, the scanning signal / Gwr(i-1) changes to H level, the control signal / Gcmp(i-1) changes to L level, and the control signal / Gel(i-1) changes to L level. Therefore, in the initialization period (A2), in the pixel circuit 110 in the (i-1)th row and jth column, the transistor 122 changes to the OFF state, the transistor 123 changes to the ON state, and the transistor 124 changes to the ON state.

[0050] 7, in the initialization period (A2), an operation is performed in which the anode of the OLED 130 in the pixel circuit 110 in the (i-1)th row and jth column is reset to the potential Vorst via the transistors 124, 123, the jth column data line 14, and the transistor 86 in that order, that is, a reset operation is performed. The initialization period (A2) of the horizontal scanning period (H_odd) corresponds to the "first initialization period" in the claims, and the reset operation corresponds to the "first operation" in the claims.

[0051] In the initialization period (A2) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row in the odd-numbered frame (V_odd), the transistor 86 in each column is in the on state, and the transistor 62 in each column maintains the on state. Therefore, in the initialization period (A2) of the horizontal scanning period (H_odd), the data line 14 in each column becomes the potential Vorst, and the data signal output line 14c maintains the potential Vref from the initialization period (A1). Therefore, in each column, the voltage across the capacitive element 70 becomes |Vorst-Vref|, and one end of the parasitic capacitance 72 is held at the potential Vorst. The potentials Vel and Vorst are expressed as follows: Vel>Vorst Since this relationship holds, the capacitive element 70 and the parasitic capacitance 72 in the j-th column are discharged.

[0052] In an odd frame (V_odd), during the initialization period (A3) of each horizontal scanning period (H), the control signal / Drst maintains the H level, the control signal / Gini changes to the L level, and the control signal / Gref maintains the L level. As a result, the transistors 82 in each column maintain the OFF state, the transistors 84 in each column change to the ON state, and the transistors 62 in each column maintain the ON state. In addition, in the initialization period (A3) of the horizontal scanning period (H_odd) of the odd-numbered (i-1) row, the control signal / Grst changes to H level. As a result, the transistors 86 of each column change to the off state. The initialization period (A3) of the horizontal scanning period (H_odd) corresponds to the "third initialization period" in the claims.

[0053] In the initialization period (A3) of the horizontal scanning period (H_odd) in the odd-numbered (i-1)th row, the scanning signal / Gwr(i-1) changes to the L level, the control signal / Gcmp(i-1) changes to the H level, and the control signal / Gel(i-1) changes to the H level. Therefore, in the initialization period (A3), in the pixel circuit 110 in the (i-1)th row and jth column, the transistor 122 changes to the ON state, the transistor 123 changes to the OFF state, and the transistor 124 changes to the OFF state.

[0054] Therefore, during the initialization period (A3), as shown in FIG. 9, in the pixel circuit 110 in the (i-1)th row and jth column, the potential Vini is supplied to one end of the capacitance element 140 and to the gate node g of the transistor 121 via the transistor 84, the jth column data line 14, and the transistor 122, in that order.

[0055] In the initialization period (A3) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row in the odd-numbered frame (V_odd), the transistor 84 in each column is in the on state, and the transistor 62 in each column maintains the on state. Therefore, in the initialization period (A3) of the horizontal scanning period (H_odd), the data line 14 in each column becomes the potential Vini, and the data signal output line 14c maintains the potential Vref from the initialization period (A1). Therefore, in each column, the voltage across the capacitive element 70 is |Vini-Vref|, and one end of the parasitic capacitance 72 is held at the potential Vini. The potentials Vini and Vorst are expressed as follows: (Vel>)Vini>Vorst This is the relationship. As a result, the capacitive element 70 and the parasitic capacitance 72 become charged.

[0056] In the odd frame (V_odd), in the compensation period (B) of each horizontal scanning period (H), the control signal / Drst maintains the H level, the control signal / Gini changes to the H level, and the control signal / Gref maintains the L level. As a result, the transistors 82 in each column maintain the OFF state, the transistors 84 in each column change to the OFF state, and the transistors 62 in each column maintain the ON state. Furthermore, in the compensation period (B) of the horizontal scanning period (H_odd) of the odd-numbered (i-1) row, the control signal / Grst is maintained at the H level, so that the transistors 86 in each column are maintained in the off state.

[0057] In the compensation period (B) of the horizontal scanning period (H_odd) of the odd-numbered (i-1) row, the scanning signal / Gwr(i-1) maintains the L level, the control signal / Gcmp(i-1) changes to the L level, and the control signal / Gel(i-1) maintains the H level. As a result, in the pixel circuit 110 in the (i-1) row and j column, the transistor 122 maintains the ON state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

[0058] At the start of the compensation period (B), in the (i-1)th row pixel circuit 110, the gate node g of the transistor 121 is at the potential Vini. When the gate node g is at the potential Vini and the transistor 123 is turned on, the transistor 121 is diode-connected.

[0059] 10, in the compensation period (B), the voltage between the gate node g and the source node s of the transistor 121 converges to (a voltage close to) the threshold voltage Vth of the transistor 121. That is, the potentials of the gate node g of the transistor 121 and the data line 14 converge to a potential equivalent to the threshold (Vel-Vth).

[0060] During the compensation period (B) of the (i-1)th row, the transistors 62 in each column are maintained in the on state, so that the data signal output lines 14c in each column are maintained at the potential Vref. Furthermore, since the data line 14 converges to the potential equivalent to the threshold voltage (Vel-Vth), the voltage across the capacitive element 70 becomes |Vel-Vth-Vref|, and one end of the parasitic capacitance 72 is held at the potential equivalent to the threshold voltage (Vel-Vth).

[0061] In an odd frame (V_odd), in a writing period (C) of each horizontal scanning period (H), the control signal / Drst maintains the H level, the control signal / Gini maintains the H level, and the control signal / Gref changes to the H level. As a result, the transistors 82 in each column maintain the off state, the transistors 84 in each column maintain the off state, and the transistors 62 in each column change to the off state. In addition, in the writing period (C) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row in the odd-numbered frame (V_odd), the control signal / Grst is maintained at the H level, so that the transistor 86 in each column is maintained in the off state.

[0062] In the writing period (C) of the horizontal scanning period (H_odd) of the (i-1)th row, the scanning signal / Gwr(i-1) maintains the L level, the control signal / Gcmp(i-1) changes to the H level, and the control signal / Gel(i-1) maintains the H level. As a result, in the pixel circuit 110 of the (i-1)th row and column j, the transistor 122 maintains the ON state, the transistor 123 changes to the OFF state, and the transistor 124 maintains the OFF state.

[0063] During the writing period (C), the transistors 62 in each column are turned off. The DA conversion circuit 500 in each column is supplied with 10-bit video data Vdata corresponding to the (i-1)th row and column. Therefore, the DA conversion circuit 500 in the jth column outputs a signal of a potential corresponding to the grayscale level of the (i-1)th row and jth column to the data signal output line 14c.

[0064] 11, one end of the capacitive element 70 in the jth column rises from a potential Vref to a potential of a gradation level corresponding to the (i-1)th row and the jth column. This potential rise reaches the gate node g of the transistor 121 via the capacitive element 70, the data line 14, and the transistor 122 in this order.

[0065] The potential change amount of the gate node g in the writing period (C) is a value obtained by multiplying the potential rise amount at one end of the capacitance element 70 by the ratio of the capacitance value of the capacitance element 70 to the "composite capacitance value." The "composite capacitance value" here is the capacitance value of the composite capacitance of the capacitance element 70, the parasitic capacitance 72, and the capacitance element 140. Note that the capacitance value of the capacitance element 140 can be ignored if it is sufficiently small compared with the other capacitance values.

[0066] When the scanning signal / Gwr(i-1) changes to the H level, the writing period (D) of the (i-1)th row ends, that is, the horizontal scanning period (H_odd) of the (i-1)th row ends. When the scanning signal / Gwr(i-1) becomes the H level, the transistor 122 in the pixel circuit 110 in the (i-1)th row and column j is turned off, but the voltage difference between the potential of the gate node g and the potential Vel of the source node s is held in the capacitance element 140.

[0067] After the writing period (C) ends, a light emitting period (D) begins. When the light emission period (E) of the (i-1)th row is reached, the control signal / Gel(i-1) is inverted to the L level, so that the transistor 124 is turned on. 12, in the light emission period (D), a current Iel according to the potential of the gate node g held by the capacitance element 140 flows through the OLED 130 in the pixel circuit 110 in the (i-1)th row and jth column through the transistor 121. As a result, the OLED 130 emits light with a luminance according to the current Iel.

[0068] In an odd frame (V_odd), the operation of the horizontal scanning period (H_even) of the even-numbered i-th row next to the odd-numbered (i-1)-th row is the same as the operation of the horizontal scanning period (H_odd) of the odd-numbered (i-1)-th row, except that the control signal / Grst is maintained at H level during the initialization period (A2), as shown in Figure 4. Therefore, the operation of the horizontal scanning period (H_even) of the even-numbered i-th row will be explained with emphasis on the initialization period (A2).

[0069] In the initialization period (A2) of the horizontal scanning period (H_even) of the even-numbered i-th row, the transistors 82 of each column change to the off state, the transistors 84 of each column maintain the off state, and the transistors 62 of each column maintain the on state, which is common to the initialization period (A2) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)-th row. The initialization period (A2) of the horizontal scanning period (H_even) corresponds to the "second initialization period" in the claims. It should be noted here that in the initialization period (A2) of the horizontal scanning period (H_even) of the even-numbered i-th row, the control signal / Grst is maintained at the H level, so that the transistors 86 of each column are maintained in the off state.

[0070] In the immediately preceding initialization period (A 1 ), the data line 14 is at the potential Vel, and the potential Vel is held at the other end of the capacitive element 70 and one end of the parasitic capacitance 72 . In addition, in the initialization period (A2) of the horizontal scanning period (H_even), in the pixel circuit 110 at row i and column j, the transistor 122 changes to an OFF state, the transistor 123 changes to an ON state, and the transistor 124 changes to an ON state. The initialization period (A1) of the horizontal scanning period (H_even) corresponds to the "second gate node initialization period" in the claims. 8, in the OLED 130 in the pixel circuit 110 in the i-th row and j-th column, charges flow out from the capacitive element 70 and the parasitic capacitance 72 and are directed to the OLED 130 via the data line 14 and the transistors 123 and 124 in this order, that is, a non-reset operation is performed. The non-reset operation corresponds to the "second operation" in the claims.

[0071] When the parasitic capacitance of the OLED 130 is fully charged due to the charge flowing out from the capacitive element 70 and the parasitic capacitance 72, the charge overflows and flows into (the light-emitting functional layer 132 of) the OLED 130, causing the OLED 130 to emit light.

[0072] In addition, the charge outflow causes the capacitive element 70 and the parasitic capacitance 72 in the jth column to discharge, and the data line 14 drops from the potential Vel. This discharge is only a small amount, and is only sufficient to distribute the charge to the parasitic capacitance of the OLED 130 via the jth data line 14. For this reason, during the initialization period (A2) of the horizontal scanning period of the i-th row, the anode of the j-th data line 14 and the i-th column pixel circuit 110 drops slightly from potential Vel to a potential between potential Vorst and potential Vel, but it is safe to say that it is approximately at potential Vel.

[0073] In this way, in an odd frame (V_odd), during the initialization period (A2) of the horizontal scanning period (H_odd) of the odd (i-1)th row, a reset operation is performed to discharge the anode of the OLED 130, and during the initialization period (A2) of the horizontal scanning period (H_even) of the even i-th row, a non-reset operation is performed, and the reset operation is not performed.

[0074] The main reason why a reset operation for discharging the anode of the OLED 130 is performed is as follows. In the OLED 130, the light-emitting functional layer 132 is sandwiched between the pixel electrode 131, which is the anode, and the common electrode 133, which is the cathode, so that the OLED 130 has a parasitic capacitance. As described above, in the compensation period (B), the gate node g and the drain node d (the source node of the transistor 124) of the transistor 121 are at a potential equivalent to the threshold value. Next, in the writing period (C), a potential corresponding to the grayscale level is supplied to the gate node g of the transistor 121.

[0075] If a data signal corresponding to the black level of the lowest gradation (the darkest level) is supplied to the gate node g, the gate node g should ideally be at the potential Vel, but in reality, the potential is lower than the potential Vel. Therefore, when the transistor 124 is turned on during the light emission period (D), a leakage current flows from the source node s to the drain node d in the transistor 121. If the charge accumulated in the parasitic capacitance of the OLED 130 is not reset in advance, the leakage current will eventually fully charge the parasitic capacitance, causing a current to start flowing through the OLED 130, resulting in light emission. This phenomenon is called black floating, because even though the black level, i.e., a luminance at which no light is emitted, is specified, a slight light is emitted, and it is visually perceived as if the black is floating.

[0076] Therefore, in the initialization period (A2), the anode of the OLED 130 is set to the potential Vorst to discharge the anode in advance and reset the charge accumulated in the parasitic capacitance of the OLED 130. As a result, even if a leakage current flows through the transistor 121 in the light emission period (D), the leakage current does not fully charge the parasitic capacitance of the OLED 130, and light is not emitted, so that the so-called black floating can be suppressed.

[0077] However, a configuration in which a reset operation is performed can be a factor that hinders low power consumption. When a reset operation is performed, the other end of the capacitive element 70 and one end of the parasitic capacitance 72 are at a potential Vel in the initialization period (A1), at a potential Vorst in the initialization period (A2), and at a potential Vini in the initialization period (A3).

[0078] As described above, the potentials Vel, Vorst, and Vini are expressed as follows: Vel>Vini>Vorst (≒Vct) This is the relationship. Of these, the potential Vel is a high level of the power supply voltage, and the potential Vorst is a low level of the power supply voltage, Gnd, or a potential close to the potential Gnd. Therefore, when a reset operation is performed, the capacitive element 70 and the parasitic capacitance 72 are charged in the initialization period (A1), discharged in the initialization period (A2), and charged in the initialization period (A3). Since such a charge->discharge->charge cycle of the capacitive element 70 and the parasitic capacitance 72 is performed for each column, the power consumed becomes large. Note that the initialization period (A3) after the initialization period (A2) of the horizontal scanning period (H_even) corresponds to the "fourth initialization period" in the claims.

[0079] The non-reset operation is common to the reset operation in that the other end of the capacitive element 70 and one end of the parasitic capacitance 72 are charged to the potential Vel in the initialization period (A1). However, in the non-reset operation, an operation of distributing charge is performed in the initialization period (A2), so the discharge of the capacitive element 70 and the parasitic capacitance 72 can be ignored compared to when the reset operation is performed. Furthermore, in the reset operation and the non-reset operation, the other end of the capacitive element 70 and one end of the parasitic capacitance 72 both become the potential Vini in the initialization period (A3), but in the reset operation, charging is from the potential Vorst, whereas in the non-reset operation, discharging is from the potential Vel.

[0080] That is, in the reset operation, the capacitive element 70 and the parasitic capacitance 72 go through the following states during the initialization period (A1)→(A2)→(A3): charge→discharge→charge; whereas in the non-reset operation, they go through the following states: charge→almost no change→discharge. Therefore, in the non-reset operation, the power consumed by charging and discharging the capacitive element 70 and the parasitic capacitance 72 in each column can be reduced compared to the reset operation.

[0081] However, it should be noted that the non-reset operation causes the so-called black floating, as described above. That is, in an odd frame (V_odd), the reset operation is performed in the horizontal scanning period (H_odd) of the odd (i-1)th row, whereas the non-reset operation is performed in the horizontal scanning period (H_even) of the even i-th row, causing the black floating.

[0082] Therefore, in the embodiment, in the even frame (V_even) following the odd frame (V_odd), a non-reset operation is performed during the horizontal scanning period (H_odd) of the odd (i-1)th row, and a reset operation is performed during the horizontal scanning period (H_even) of the even i-th row, so that the row performing the reset operation and the row performing the non-reset operation are interchanged.

[0083] 5, in an even frame (V_even), the control signal / Grst is at H level during the initialization period (A2) of the horizontal scanning period (H_odd), and is at L level during the initialization period (A2) of the horizontal scanning period (H_even). The other control signals / Drst, / Gini, and / Gref are common to each horizontal scanning period in an odd frame (V_odd). Therefore, in an even frame (V_even), the odd-numbered (i-1)th row is in a non-reset operation, and the even-numbered i-th row is in a reset operation.

[0084] In order to explain the advantages of low power consumption and the reduction in display quality in this embodiment, a comparative example will be described. The comparative example is configured to perform a reset operation in the initialization period (A2) without distinguishing between odd-numbered rows and even-numbered rows.

[0085] 13 is a diagram showing four consecutive frames in which all pixels are displayed in black when the lowest grayscale black level is specified, and all pixels are displayed in white when the highest grayscale white level is specified, in a comparative example and an embodiment. In the diagram, the four frames are the first, second, third, and fourth frames in chronological order. Of the four frames, the first and third frames are odd-numbered frames (V_odd), and the second and fourth frames are even-numbered frames (V_even).

[0086] In the comparative example, when all black is displayed, the reset operation is performed on all rows (Reset: Yes), so that black floating does not occur. However, the reset operation causes power to be consumed by the capacitive element 70 and the parasitic capacitance 72.

[0087] In contrast, in the embodiment, when displaying all black, in an odd frame (V_odd), a reset operation is performed on odd rows, and a non-reset operation is performed on even rows (reset: none). Therefore, while no black float occurs on odd rows, black float occurs on even rows. Note that black float is represented as a hatched area in FIG. 13. In the embodiment, when displaying all black, a non-reset operation is performed on odd-numbered rows and a reset operation is performed on even-numbered rows in an even-numbered frame (V_even). As a result, black floating occurs in the odd-numbered rows but not in the even-numbered rows. In the embodiment, the black floating occurs for each row in one frame, so there is a difference between odd and even rows. However, the black floating occurs alternately between odd frames (V_odd) and even frames (V_even), so there is no difference between odd and even rows in two frame periods, so it is difficult to be visually recognized as black floating. In the embodiment, in one frame, the non-reset operation is performed on half of all the rows, so that the power consumed by the capacitive element 70 and the parasitic capacitance 72 can be reduced as compared to the comparative example.

[0088] In addition, when all white display is performed in the comparative example, the reset operation is performed on all rows, so that no adverse effects due to black floating occur. On the other hand, in the embodiment, when displaying all white, the reset operation is not performed on either the odd-numbered rows or the even-numbered rows. In the rows where the reset operation is not performed, floating black occurs, but even if the rows emit light at a slightly brighter luminance when the rows are already emitting light at a bright luminance, the difference cannot be visually recognized. Therefore, when displaying all white, there is no difference in the display between the comparative example and the embodiment. However, in the embodiment, the reset operation is not performed on half of the rows, so that the power consumed by the capacitive element 70 and the parasitic capacitance 72 can be reduced.

[0089] The above-described embodiment can be modified or applied in various ways as follows.

[0090] In the embodiment, the horizontal scanning period is divided into odd-numbered rows and even-numbered rows for each row, but the present invention is not limited to this configuration. For example, the horizontal scanning period may be divided into two or more consecutive rows.

[0091] In the embodiment and the like, the OLED 130 has been described as an example of the light-emitting element, but other light-emitting elements may be used. For example, the light-emitting element may be an LED, or a liquid crystal element combined with an illumination mechanism. In other words, the light-emitting element may be an electro-optical element that changes its optical state according to the voltage of the data line 14. In the embodiment and the like, a 10-bit conversion example is shown as the DA conversion circuit 500, but the present invention is not limited to this.

[0092] The channel types of the transistors 64, 82, 84, 86, 121 to 124, etc. are not limited to those in the embodiment, etc. Furthermore, the channels of these transistors, etc. may be changed as appropriate, or may be replaced with transmission gates as appropriate.

[0093] Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, a head-mounted display will be taken as an example of the electronic device.

[0094] FIG. 14 is a diagram showing the appearance of a head mounted display, and FIG. 15 is a diagram showing the optical configuration thereof. First, as shown in Fig. 14, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to general eyeglasses. Also, as shown in Fig. 15, the head mounted display 300 has an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye provided near the bridge 320 and on the rear side of the lenses 301L and 301R (the lower side in the figure). The image display surface of the electro-optical device 10L is disposed to the left in FIG. 15. As a result, the image displayed by the electro-optical device 10L is output in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed to the right, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is output in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction.

[0095] In this configuration, a person wearing the head mounted display 300 can observe images displayed by the electro-optical devices 10L and 10R in a see-through state in which the images are superimposed on the outside world. Furthermore, in this head mounted display 300, when the electro-optical device 10L displays an image for the left eye and the electro-optical device 10R displays an image for the right eye among the binocular images with parallax, the wearer can perceive the displayed image as if it had depth and a three-dimensional effect.

[0096] In addition, electronic devices including the electro-optical device 10 can be applied to electronic viewfinders in video cameras and interchangeable lens digital cameras, portable information terminals, display units of wristwatches, light bulbs of projection projectors, and the like, in addition to the head mounted display 300.

[0097] From the above-mentioned exemplary embodiments, the following aspects can be understood, for example.

[0098] An electro-optical device according to one aspect (Aspect 1) includes a first pixel circuit provided in correspondence with a data line and a first scanning line, a second pixel circuit provided in correspondence with the data line and a second scanning line, and a control circuit that controls the first pixel circuit and the second pixel circuit; the first pixel circuit includes a first light emitting element that emits light with a luminance corresponding to a current flowing between two electrodes, and a first drive transistor that causes a current corresponding to a voltage between a potential of a gate node and a potential of a source node to flow to the first light emitting element, the second pixel circuit includes a second light emitting element that emits light with a luminance corresponding to a current flowing between two electrodes, and a second drive transistor that causes a current corresponding to a voltage between a potential of a gate node and a potential of a source node to flow to the second light emitting element, and the control circuit supplies a potential corresponding to a gradation level to the gate node of the first drive transistor via the data line in a first write period of a first horizontal scanning period in which the first scanning line is selected in a first frame, During the initialization period, a first operation is performed, and during the second horizontal scanning period in which the second scanning line is selected, a potential corresponding to the gradation level is supplied to the gate node of the second driving transistor via the data line during a second write period, and during the second initialization period before the second write period, a second operation is performed, and the first operation is an operation of supplying a first potential different from the potential corresponding to the gradation level to one of the two electrodes via the data line, and the second operation is an operation of setting the potential of the data line and the potential at the one electrode to a potential between the first potential and the second potential, and the second potential is a potential that, when supplied to the gate node, turns off the first driving transistor and the second transistor.

[0099] According to the first aspect, when the first operation is performed in the first pixel circuit, the second operation is performed in the second pixel circuit. In the first operation, the amount of discharge in the parasitic capacitance of the data line is increased, whereas in the second operation, the amount of discharge in the parasitic capacitance of the data line is reduced.

[0100] Note that the odd-numbered frame (V_odd) is an example of a first frame, the (i-1)th scanning line 12 is an example of a first scanning line, and the i-th scanning line 12 is an example of a second scanning line. The pixel circuit 110 in the (i-1)th row and jth column is an example of a first pixel circuit, and the pixel circuit 110 in the i-th row and jth column is an example of a second pixel circuit. The LED 130 is an example of a light-emitting element, the pixel electrode 131 is an example of one of the two electrodes, the transistor 121 is an example of a drive transistor, the potential Vorst is an example of a first potential, and the potential Vel is an example of a second potential that is an off potential. A potential slightly lower than the potential Vel, specifically, in the off state, a potential after the charge accumulated in the parasitic capacitance of the data line held at the off potential during the first initialization period is distributed to one electrode of the light-emitting element, is an example of a potential between the first potential and the second potential. Moreover, the horizontal scanning period (H_odd) is an example of a first horizontal scanning period, and the horizontal scanning period (H_even) is an example of a second horizontal scanning period.

[0101] An electro-optical device according to a specific aspect 2 of aspect 1 has a first switching element having one end and another end, the one end being electrically connected to the data line and the other end being electrically connected to the power supply line of the first potential, and the control circuit controls the first switching element to an on state during the first initialization period. According to the second aspect, the first switching element is turned on in the first initialization period, causing the data line to have the first potential. The transistor 86 is an example of a first switching element.

[0102] An electro-optical device according to a specific aspect 3 of aspect 2 has a second switching element having one end and the other end, the one end being electrically connected to the data line and the other end being electrically connected to a power supply line that supplies an on potential, and the control circuit controls the second switching element to an on state during a third initialization period after the first initialization period and before the first write period, and during a fourth initialization period after the second initialization period and before the second write period, and the on potential is a potential that, when supplied to the gate node, turns the first drive transistor and the second drive transistor to an on state. According to the third aspect, in the third and fourth reset periods, the second switching element is in an on state, so that the potential of the data line and the potential of the gate node become the on potential. The transistor 84 is an example of a second switching element.

[0103] In an electro-optical device relating to a specific aspect 4 of aspect 3, the control circuit supplies the on potential to the gate node via the data line during the third initialization period and the fourth initialization period, and causes the gate node of the first drive transistor and the gate node of the second drive transistor to converge to a potential corresponding to the threshold value of the first drive transistor and the second drive transistor during a first compensation period after the third initialization period and before the first write period, and a second compensation period after the fourth initialization period and before the second write period. In order to converge the gate node to a potential corresponding to the threshold of the first (second) drive transistor during the first (second) compensation period, it is necessary to turn the first (second) drive transistor on before the first (second) compensation period. According to aspect 4, the data line in the first operation changes from the second potential to the first potential and then changes to the on potential, so that power is consumed by the parasitic capacitance of the data line, whereas the data line in the second operation changes from the second potential to the on potential, so that the power consumed by the parasitic capacitance of the data line is reduced compared to the first operation.

[0104] In an electro-optical device according to another specific aspect 5 of aspect 1, the control circuit performs the second operation in the first initialization period and performs the first operation in the second initialization period in a second frame following the first frame. According to aspect 5, the scanning lines on which the first operation is performed and the scanning lines on which the second operation is performed in the second frame are swapped and averaged from the first frame, so that degradation of display quality due to the second operation can be made less noticeable. The even frame (V_even) is an example of the second frame.

[0105] In another specific aspect 6 of aspect 1, the control circuit supplies a potential according to a grayscale level to the gate node via a coupling capacitance and the data line in the first write period and the second write period. According to the sixth aspect, it is possible to suppress not only the parasitic capacitance of the data line but also the discharge amount of the coupling capacitance. Note that the capacitive element 70 is an example of a coupling capacitance.

[0106] In another specific aspect 7 of aspect 1, the control circuit supplies the second potential to the gate node of the first driving transistor via the data line during a first gate node initialization period before the first initialization period during the first horizontal scanning period, and supplies the second potential to the gate node of the second driving transistor via the data line during a second gate node initialization period before the second initialization period during the second horizontal scanning period.

[0107] An electronic device according to an eighth aspect includes the electro-optical device according to any one of the first to seventh aspects. [Explanation of symbols]

[0108] 10...electro-optical device, 12...scanning line, 14...data line, 14c...data signal output line, 30...control circuit, 50...data signal output circuit, 60...auxiliary circuit, 62...transistor, 70...capacitive element, 72...parasitic capacitance, 80...initialization circuit, 82, 84, 86...transistor, 110...pixel circuit, 120...scanning line driving circuit, 121-124...transistor, 130...OLED.

Claims

1. A first pixel circuit is provided corresponding to the data line and the first scan line, A second pixel circuit is provided corresponding to the data line and the second scan line, A control circuit for controlling the first pixel circuit and the second pixel circuit, Includes, The first pixel circuit is, A first light-emitting element that emits light with brightness corresponding to the current flowing between the two electrodes, A first drive transistor that supplies a current to the first light-emitting element corresponding to the voltage between the potential of the gate node and the potential of the source node, Includes, The second pixel circuit is, A second light-emitting element that emits light with brightness corresponding to the current flowing between the two electrodes, A second drive transistor that supplies a current to the second light-emitting element corresponding to the voltage between the potential of the gate node and the potential of the source node, Includes, The aforementioned control circuit is During the first horizontal scanning period in which the first scan line is selected in the first frame, During the first writing period, A potential corresponding to the grayscale level is supplied to the gate node of the first drive transistor via the data line. During the first initialization period prior to the first write period, Perform the first action, During the second horizontal scanning period in which the second scan line is selected, During the second writing period, A potential corresponding to the grayscale level is supplied to the gate node of the second drive transistor via the data line. During the second initialization period prior to the second write period, Perform the second action, The first operation is, This operation involves supplying a first potential, different from the potential corresponding to the grayscale level, to one of the two electrodes via the data line. The second operation is to bring the potential of the data line and the potential at one of the electrodes to a potential between the first potential and the second potential. The second potential, when supplied to the gate node, is a potential that will turn off the first drive transistor and the second drive transistor. Electro-optical device.

2. A first switching element having one end and the other end, one end being electrically connected to the data line and the other end being electrically connected to the power supply line of the first potential, The aforementioned control circuit is During the first initialization period, Control the first switching element to the ON state. The electro-optical apparatus according to claim 1.

3. A second switching element having one end and the other end, one end being electrically connected to the data line and the other end being electrically connected to a power supply line that supplies an ON potential, The aforementioned control circuit is In the third initialization period after the first initialization period and before the first write period, and in the fourth initialization period after the second initialization period and before the second write period, The second switching element is controlled to the ON state, The aforementioned ON potential is This potential, when supplied to the gate node, will turn on the first drive transistor and the second drive transistor. The electro-optical apparatus according to claim 2.

4. The aforementioned control circuit is During the third and fourth initialization periods, The ON potential is supplied to the gate node via the data line. In the first compensation period after the third initialization period and before the first write period, and in the second compensation period after the fourth initialization period and before the second write period, The gate nodes of the first drive transistor and the second drive transistor are brought to converge to a potential corresponding to the threshold of the first drive transistor and the second drive transistor. The electro-optical apparatus according to claim 3.

5. The aforementioned control circuit is In the second frame following the first frame, During the first initialization period, the second operation is performed. During the second initialization period, the first operation is performed. The electro-optical apparatus according to claim 1.

6. The aforementioned control circuit is During the first write period and the second write period, A potential corresponding to the grayscale level is supplied to the gate node via the coupling capacitor and the data line. The electro-optical apparatus according to claim 1.

7. The aforementioned control circuit is During the first horizontal scanning period, During the first gate node initialization period prior to the first initialization period, the second potential is supplied to the gate node of the first drive transistor via the data line. During the second horizontal scanning period, During the second gate node initialization period prior to the second initialization period, the second potential is supplied to the gate node of the second drive transistor via the data line. The electro-optical apparatus according to claim 1.

8. An electronic device having an electro-optical device according to any one of claims 1 to 7.

Images