Row hammer refresh address calculation method, calculation circuit, and semiconductor memory device having the same
By designing a low hammer refresh address (RHA) calculation circuit for dynamic random access memory (DRAM), the problems of slow computing speed and large circuit scale in the prior art are solved, and computing efficiency at high speed and small circuit scale are achieved.
JP2025037325AActive Publication Date: 2025-03-18WINBOND ELECTRONICS CORP
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Patent Information
- Application Number
- JP2023144183
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-09-06
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2043-09-06
AI Technical Summary
Technical Problem
When calculating low hammer refresh address (RHA), the calculation speed is slow and the circuit scale is large, making it difficult to meet the needs of high speed and small circuit scale.
Method used
An RHA calculation circuit is designed to calculate the adjacent RHA addresses on the upper and lower sides through various operating methods based on seed addresses, and optimize the calculation process to improve speed and reduce the circuit scale through the coordinated work of control units and calculation units.
Benefits of technology
It realizes high-speed calculation of low hammer refresh addresses on small circuit scale, improving computing efficiency and system performance.
✦ Generated by Eureka AI based on patent content.
Abstract
To provide a row hammer refresh address (RHA) calculation method, a calculation circuit, and a semiconductor memory device having the same, capable of RHA calculation at high speed with a small circuit scale.SOLUTION: As an opportunity at the time of updating a seed address, a control unit of a RHA calculation circuit performs an order control of a calculation unit so as to preferentially calculate an address obtained by an operation with a small amount of calculation (inverting only a least significant bit) as an adjacent RHA among adjacent RHAs on both sides based on the updated seed address, or preferentially calculates an address obtained by an operation with a small amount of calculation (inverting only a second least significant bit) as an adjacent RHA among the adjacent RHAs on both sides, based on the updated seed address. On the other hand, in the calculation unit of the RHA calculation circuit, a calculation circuit is implemented in which the possibility that the physical arrangement of the word lines and the row addresses assigned to them are finally refined to a specified logic is found, and based on that, the calculation logic of the adjacent RHA and the adjoining adjacent RHA with the minimum amount of calculation is found, and the calculation order control is also optimized.SELECTED DRAWING: Figure 3
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