Semiconductor device and manufacturing method thereof

The semiconductor device addresses the issue of peeling between the die bond material and the die pad by using a die pad with strategically designed regions and grooves, enhancing adhesion and improving reliability and performance.

JP2025043480APending Publication Date: 2025-04-01RENESAS ELECTRONICS CORP
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Patent Information

Application Number
JP2023150785
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-09-19
Publication Date
2025-04-01

AI Technical Summary

Technical Problem

The reliability of semiconductor devices is compromised due to peeling between the die bond material and the die pad, which affects the device's ability to maintain performance over time.

Method used

The semiconductor device incorporates a die pad with specific regions and grooves designed to enhance the adhesion between the die bond material and the die pad, including a first region at the center, a second region around the first region with grooves, and a third region further around. The grooves in the second region terminate before reaching the first and third regions, allowing the die bond material to spread effectively and anchor securely.

Benefits of technology

This design improves the reliability and performance of semiconductor devices by preventing peeling between the die bond material and the die pad, ensuring consistent function over time.

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Abstract

To improve the performance of a semiconductor device.SOLUTION: The upper surface of a die pad 20 includes a region R1, a region R2 including points overlapping with each of the four corners 10c of a semiconductor chip 10, and a region R3 located around the region R2. The die pad 20 has a plurality of grooves TR formed in the region R2. Each of the plurality of grooves TR terminates at a position not reaching the region R1 or the region R3. The plurality of grooves TR includes a plurality of grooves TR1 extending along one of the two diagonals 10D of the semiconductor chip 10 and a plurality of grooves TR2 extending along the other of the two diagonals 10D. Each of the plurality of grooves TR1 is arranged so as to intersect with one or more of the plurality of grooves TR2.SELECTED DRAWING: Figure 7
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