Noise detection circuit and display panel driving device

Abstract

To provide a noise detection circuit and a display panel driving device which can avoid wrong operations of a control target of a logic circuit.SOLUTION: The noise detection circuit includes: a noise output unit for inputting a first noise overlapped with a first voltage of a specific potential, converting the first noise to a second noise lower than the first noise, overlapping the second noise with a second voltage with a potential lower than the specific potential, and outputting a second noise overlapped with the second voltage as a noise signal; and a noise detection signal output unit for outputting a detection signal showing that the first noise is detected, while keeping the level of the detection signal, when the noise signal is input.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a noise detection circuit and a display panel driving device. [Background technology]

[0002] The device disclosed in Patent Document 1 prevents noise transmission by activating a noise canceller when a power supply noise detection circuit detects either noise superimposed on a high-potential power supply voltage (HVDD) or noise superimposed on a low-potential power supply voltage (VSS1).

[0003] An example of such a device that uses multiple power supply systems (power supply voltages with different potentials) is a driver for driving a liquid crystal panel. If an overvoltage state continues for a specific period of time (such as 10 us), the driver can protect the semiconductor device that constitutes the liquid crystal panel from the overvoltage by forcibly turning off the power. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-103490 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, conventional technology that uses multiple power supply systems cannot detect noise in logic circuits that are driven by low-potential power supply voltages, and as a result, noise superimposed on a high-potential power supply voltage can cause malfunctions such as flickering and freezing in the display panel that is controlled by the logic circuit.

[0006] In consideration of the above circumstances, an object of the present disclosure is to provide a noise detection circuit and a display panel driving device that can prevent malfunction of an object controlled by a logic circuit. [Means for solving the problem]

[0007] In order to solve the above problems, the noise detection circuit of the present disclosure includes a noise output unit that inputs a first noise to be superimposed on a first voltage of a specific potential, converts the first noise into a second noise having a lower potential than that of the first noise, superimposes the second noise on a second voltage having a lower potential than the specific potential, and outputs the second noise superimposed on the second voltage as a noise signal, and a noise detection signal output unit that, when the noise signal is input, outputs a detection signal indicating that the first noise has been detected while maintaining the level of the detection signal. Effect of the Invention

[0008] The present disclosure provides an effect of providing a noise detection circuit and a display panel driving device that can prevent malfunction of a controlled object of a logic circuit. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a configuration of a display panel according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a timing chart for explaining an example of control when noise is detected. [Diagram 3] FIG. 3 is a diagram showing a schematic configuration of the noise detection circuit. [Figure 4] FIG. 4 is a diagram showing a configuration example of a noise detection circuit for VGOUT. [Diagram 5] FIG. 5 is a diagram for explaining the operation of the VGOUT noise detection circuit shown in FIG. [Figure 6] FIG. 6 is a diagram showing a first modified example of the VGOUT noise detection circuit. [Figure 7] FIG. 7 is a diagram for explaining the operation of the VGOUT noise detection circuit shown in FIG. [Figure 8] FIG. 8 is a diagram showing a second modified example of the VGOUT noise detection circuit. [Figure 9] FIG. 9 is a diagram for explaining the operation of the VGOUT noise detection circuit shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and the description thereof will be omitted as appropriate.

[0011] [Embodiment] (display device) 1 is a diagram showing a configuration of a display panel according to an embodiment of the present disclosure. The display panel 100 may be interpreted as a vehicle display device mounted on an automobile or the like. A control board 200 may be connected to the display panel 100. The control board 200 may include a main processor 10, a first power supply circuit 11, and a second power supply circuit 12. The main processor 10 may transmit digital video data, timing signals synchronized therewith, and the like. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, and the like.

[0012] The display panel 100 may include a display unit 110, a gate control unit 120, and a display panel driving device 130.

[0013] (Display section 110) The display unit 110 may be construed as an image display device such as a liquid crystal display unit or an organic EL (Electro Luminescence) unit.

[0014] (Gate control unit 120) The gate control unit 120 may be interpreted as a gate driver. Specifically, the gate control unit 120 may generate a gate signal based on a signal supplied from the timing controller 3 of the display panel driving device 130, and supply the generated gate signal to the display panel 100.

[0015] (Display panel driving device 130) The display panel driving device 130 may be interpreted as a device for controlling the lighting state of a plurality of light-emitting elements provided in the display panel 100. The display panel driving device 130 may include a GOUT control circuit 1, an SOUT control circuit 2, a timing controller 3, and a noise detection circuit 4.

[0016] (GOUT control circuit 1) The GOUT control circuit 1 may be interpreted as a gate driver that generates the gate signal GOUT. The GOUT control circuit 1 may generate the gate signal GOUT based on a first voltage of a specific potential, and output the generated gate signal GOUT to the gate control unit 120.

[0017] The first voltage may be interpreted as the power supply voltage VGOUT output from the first power supply circuit 11. The specific potential may be interpreted as a high potential (for example, 20 [V]).

[0018] The first power supply circuit 11 may be interpreted as a circuit for generating a power supply voltage VGOUT. The first power supply circuit 11 may be provided on the control board 200.

[0019] The gate signal GOUT may be interpreted as a signal that controls the scanning direction of the display unit 110. The GOUT control circuit 1 may sequentially output the gate signal GOUT to the gate lines under the control of the timing controller 3. Specifically, the GOUT control circuit 1 may shift the gate signal GOUT using a shift register, thereby sequentially supplying the signals to the gate lines.

[0020] (SOUT control circuit 2) The SOUT control circuit 2 may be interpreted as a source driver that generates a source signal SOUT. The SOUT control circuit 2 may generate the source signal SOUT based on a first voltage of a specific potential, and output the generated source signal SOUT to a source bus line of the display unit 110.

[0021] The first voltage may be interpreted as a power supply voltage VSOUT output from the second power supply circuit 12. The specific potential is, for example, 7 [V]. The second power supply circuit 12 may be interpreted as a circuit for generating the power supply voltage VSOUT. The second power supply circuit 12 may be provided on the control board 200.

[0022] The source signal SOUT may be interpreted as a driving voltage applied to a plurality of source bus lines provided in the display unit 110.

[0023] (Timing Controller 3) The timing controller 3 may control the display timing of an image on the display panel 100. Specifically, the timing controller 3 may perform a rearrangement process of image data, horizontal synchronization control of the SOUT control circuit 2, vertical synchronization control of the GOUT control circuit 1, and the like.

[0024] (Noise detection circuit 4) When the noise detection circuit 4 detects noise superimposed on at least one of the power supply voltage VGOUT and the power supply voltage VSOUT, it may output a detection signal indicating that noise has been detected. The noise detection circuit 4 may include a VGOUT noise detection circuit 4a that detects noise superimposed on the power supply voltage VGOUT, and a VSOUT noise detection circuit 4b that detects noise superimposed on the power supply voltage VSOUT. In this way, the noise detection circuit 4 may include a plurality of circuits for detecting noise superimposed on each of the power supply voltage VGOUT and the power supply voltage VSOUT.

[0025] The detection results of noise detected by these circuits may be transmitted as detection signals VGDET and VSDET to the timing controller 3. The timing controller 3 may control the operations of the GOUT control circuit 1 and the SOUT control circuit 2 based on these signals, and may notify the main processor 10 of these signals.

[0026] Next, an example of noise superimposed on the power supply voltage VGOUT and an example of control when this noise is detected will be described with reference to Fig. 2. Fig. 2 is a timing chart for explaining an example of control when noise is detected.

[0027] FIG. 2 shows noise superimposed on the power supply voltage VGOUT, the gate signal GOUT (frame start signal VST), the gate signal GOUT (clock signal CLK), the detection signal VGDET, and the display state.

[0028] (1) When noise is superimposed on the power supply voltage VGOUT at time t1 during display on the display panel 100, for example, the potential level of the power supply voltage VGOUT drops instantaneously, (2) a detection signal VGDET is generated at the timing when the potential level drops. In other words, the potential of the detection signal VGDET changes from an L level (low level) to an H level (high level).

[0029] (3) The timing controller 3 controls the GOUT control circuit 1 to interrupt the generation of the gate signal GOUT at the timing when the potential level of the detection signal VGDET changes. This resets the operation of the gate control unit 120, that is, the operation of the gate drive circuit integrated in the display panel 100, and holds (fixes) the display image.

[0030] (4) Since the signal input from the main processor 10 (host) to the timing controller 3 continues, when the timing controller 3 receives the next frame start signal VST at time t2, it resets the detection signal VGDET. This causes display to start from the frame start signal VST.

[0031] A similar operation may be performed when noise is superimposed on the power supply voltage VSOUT. That is, when noise is detected in the power supply voltage VSOUT, the timing controller 3 may control the GOUT control circuit 1 to interrupt the generation of the gate signal GOUT. If the generation of the gate signal GOUT continues even when the generation of the source signal SOUT is interrupted, writing to the pixels will be performed, resulting in an abnormal display. However, by interrupting the generation of the gate signal GOUT, the TFT (Thin Film Transistor) that writes to the pixels will not be turned on, and the pixel data will maintain the state of the previous frame.

[0032] In this disclosure, an example has been described in which the timing controller 3 controls the GOUT control circuit 1 based on the detection signal VGDET, etc., but the main processor 10 may control the operation after noise detection based on the detection signal VGDET, etc.

[0033] Next, an overview of the operation of the noise detection circuit 4 when detecting noise will be described with reference to Fig. 3. Fig. 3 is a diagram showing a schematic configuration of the noise detection circuit. The display panel driving device 130 includes a VDD / VSS system circuit in addition to the VGOUT / VSSS system that is the detection target. Fig. 3 shows the noise detection circuit 4, which is an example of a VDD / VSS system circuit. The noise detection circuit 4 operates at a second potential (e.g., 3 [V]) that is lower than a first voltage of a specific potential.

[0034] The power supply for the control board 200 is a loop via the bypass capacitor Cb, so when the control board 200 receives EMS (Electro Magnetic Susceptibility) noise, positive or negative noise may be superimposed on the power supply.

[0035] Specifically, as shown in FIG. 3, noise may be superimposed on each of the power supply voltage VGOUT (e.g., 20 V) which is the first voltage output from the control board 200, and the power supply voltage VSSS (e.g., 0 V or ground potential).

[0036] When the noise detection circuit 4 operates in common mode, the noise detection circuit 4 operating at the second potential (for example, 3 V) cannot detect noise, and therefore the anticipated noise route and the power supply of the noise detection circuit 4 are completely separated.

[0037] The noise detection circuit 4 directly inputs the power supply of the control board 200 to the clock input terminals of two HVFFs (high voltage flip-flops) included in the noise detection circuit 4. One HVFF operates at the falling edge of VGOUT, and the other HVFF operates at the rising edge of VSSS. This makes it possible to detect noise superimposed on a first voltage of a specific potential. In other words, the noise detection circuit 4 may detect noise superimposed on a power supply voltage VGOUT (e.g., 20 [V]) or may detect noise superimposed on a power supply voltage VSSS (e.g., 0 V).

[0038] It is preferable that the transistors used in the noise detection circuit 4 have a withstand voltage that matches the specifications of the power supply arranged in the expected noise transmission route.

[0039] Next, the configuration of the VGOUT noise detection circuit 4a will be specifically described with reference to Fig. 4. Fig. 4 is a diagram showing an example of the configuration of the VGOUT noise detection circuit. The VGOUT noise detection circuit 4a may be interpreted as an example of the HVFF shown in Fig. 3. In Fig. 4, the VSOUT noise detection circuit 4b is omitted. The VSOUT noise detection circuit 4b may be configured similarly to the VGOUT noise detection circuit 4a.

[0040] The VGOUT noise detection circuit 4a may include a noise output section 41 and a noise detection signal output section .

[0041] (Noise output unit 41) The noise output unit 41 may input a first noise to be superimposed on a first voltage of a specific potential (e.g., 20 [V]), convert the first noise into a second noise having a potential lower than that of the first noise, and input the second noise into a circuit (e.g., wiring nd2) to which a second voltage (e.g., VDD=3 [V]) is applied, thereby superimposing the second noise. Note that the transistor MP0 at this time may be interpreted as being in an OFF state. The second voltage may be interpreted as a voltage whose potential is lower than the above-mentioned specific potential. The noise output unit 41 may output the second noise to be superimposed on the second voltage as a noise signal.

[0042] The noise output section 41 may include a capacitor C1, a line nd2, and a transistor MP0 which is a P-channel MOSFET.

[0043] (Capacitor C1) A first end of the capacitor C1 may be connected to the wiring nd1. A second end of the capacitor C1 opposite to the first end may be connected to the drain of the transistor MP0 and the wiring nd2. A power supply voltage VGOUT, which is a first voltage, is applied to the wiring nd1. The capacitor C1 may pass AC components (noise) superimposed on the power supply voltage VGOUT.

[0044] (Wiring nd2) The wiring nd2 may be interpreted as a wiring that transmits noise (noise signal) that has passed through the capacitor C1 to the noise detection signal output unit 42. A first end of the wiring nd2 may be connected to the capacitor C1 and the drain of the transistor MP0. A second end of the wiring nd2 opposite to the first end may be connected to the noise detection signal output unit 42.

[0045] (Transistor MP0) The drain of the transistor MP0 may be connected to the capacitor C1 and a wiring nd2. The gate of the transistor MP0 may be connected to the timing controller 3 via a wiring nd3. A second voltage may be applied to the source of the transistor MP0.

[0046] The noise detection signal output section 42 may be considered as a flip-flop (FF) circuit. When the noise detection signal output section 42 receives a noise signal from the noise output section 41, the noise detection signal output section 42 may output a detection signal VGDET indicating that a first noise superimposed on a first voltage (e.g., 20 V) has been detected. The noise detection signal output section 42 may output the detection signal VGDET while maintaining the potential level of the detection signal VGDET for a certain period of time.

[0047] (operation) Fig. 5 is a diagram for explaining the operation of the VGOUT noise detection circuit shown in Fig. 4. When the display panel driving device 130 is powered on, a signal with a potential of L level is input to the line nd3, so that the transistor MP0 is in the ON state. Therefore, a second voltage (for example, VDD=3 [V]) is applied to the line nd2 (time t1).

[0048] When the potential of the line nd3 becomes H level (time t2) before the display panel 100 starts operating, the line nd2 becomes floating. However, the potential of the line nd2 is maintained at 3 [V] by the capacitor C1 and the line nd1.

[0049] When noise is superimposed on the power supply voltage VGOUT, the potential of the line nd2 drops by approximately the same amount as the noise potential due to capacitive coupling. This potential difference becomes FF, that is, the clock of the noise detection signal output unit 42, and the noise detection signal output unit 42 outputs the detection signal VGDET (time t3). Specifically, the noise detection signal output unit 42 outputs a signal with a potential of H level as the detection signal VGDET. While the potential of the line nd3 is at H level, the H-level detection signal VGDET continues to be output. The potential of the line nd3 may periodically become L level.

[0050] (First Modification) Next, a first modified example of the VGOUT noise detection circuit 4a will be described with reference to Fig. 6. Fig. 6 is a diagram showing a first modified example of the VGOUT noise detection circuit. The VGOUT noise detection circuit 4a1 according to the first modified example may include a noise output unit 41A instead of the noise output unit 41 shown in Fig. 1.

[0051] (Noise output section 41A) The noise output unit 41A may input a first noise to be superimposed on a first voltage of a specific potential (e.g., 20 [V]) in the same manner as the noise output unit 41, convert the first noise into a second noise having a potential lower than that of the first noise, and superimpose the second noise on a second voltage (e.g., VDD=3 [V]) having a potential lower than the specific potential, similar to the noise output unit 41. The noise output unit 41A may output the second noise to be superimposed on the second voltage as a noise signal in the same manner as the noise output unit 41.

[0052] The noise output section 41A may include a voltage dividing circuit 5 and a resistor R1.

[0053] (Voltage divider circuit 5) The voltage dividing circuit 5 may be interpreted as a circuit that divides the first voltage and outputs the divided voltage. The voltage dividing circuit 5 may include a capacitor C1 and a capacitor C2 connected in series to the capacitor C1. The capacitor C1 may be interpreted as a first capacitor. The capacitor C2 may be interpreted as a second capacitor.

[0054] A first end of the capacitor C1 may be connected to a wiring nd1 to which a power supply voltage VGOUT is applied. A second end of the capacitor C1 opposite to the first end may be connected to a resistor R1, a capacitor C2, and a wiring nd2.

[0055] A first end of the capacitor C2 may be connected to the capacitor C1, the resistor R1, and the wiring nd2. A second end of the capacitor C2 opposite to the first end may be grounded.

[0056] A first voltage is applied to the voltage divider circuit 5, and the potential of the AC component (noise) superimposed on the first voltage is set by the capacitance ratio of the capacitors C1 and C2. That is, the sensitivity of the noise detection can be adjusted by the ratio of the capacitors C1 and C2. For example, when the second voltage VDD is 3 [V], when the power supply voltage VGOUT, which is the first voltage, drops instantaneously from 20 [V] to 10 [V] due to power supply noise, the input of the FF drops to -7 [V], and the element may be damaged. By adjusting the sensitivity of the noise detection by the voltage divider circuit 5, that is, by adjusting the input voltage of the noise detection signal output unit 42, which is the FF, it is possible to prevent the noise detection signal output unit 42 from being damaged even when such a fluctuation in the power supply voltage VGOUT occurs.

[0057] Voltage V generated on wire nd2 C1 can be calculated by the following (1). 1 is the capacitance of capacitor C1, C 2 represents the capacitance of the capacitor C2, and V represents the voltage applied to both ends of the voltage divider circuit 5. V C1 =C 1 / (C 1 +C 2 )·V··(1)

[0058] For example, the voltage V is 20 [V], C 1 is 17[pF], C 2 is 3 pF, the voltage V C1 is 3[V].

[0059] (Resistor R1) A first end (one end) of the resistor R1 may be connected to the connection point of the capacitor C1 and the capacitor C2. A second voltage (for example, VDD=3 [V]) may be applied to a second end (the other end) of the resistor R1, which is opposite to the first end. The resistor R1 may be interpreted as a resistor for fixing the potential of the wiring nd2. Without the resistor R1, the wiring nd2 becomes floating, so the potential is indefinite, and it is unclear how much the potential of the wiring nd2 changes when the potential of the wiring nd1 changes. In the configuration shown in FIG. 4, the potential is controlled using the transistor MP0, but in the configuration shown in FIG. 6, the voltage is divided by C1 / C2, so the voltage of the VDD1 system will not become abnormal even if Tr (the transistor MP0 shown in FIG. 4) is not turned off.

[0060] The wiring nd2 may be interpreted as a wiring that transmits a noise signal superimposed on the voltage output from the voltage dividing circuit 5 to the noise detection signal output unit 42. A first end of the wiring nd2 may be connected to the connection point between the capacitors C1 and C2. A second end of the wiring nd2 opposite to the first end may be connected to the noise detection signal output unit 42.

[0061] Fig. 7 is a diagram for explaining the operation of the VGOUT noise detection circuit shown in Fig. 6. In the VGOUT noise detection circuit 4a1 shown in Fig. 6, the potential of the line nd2 is fixed to a second voltage (for example, VDD=3 [V]) by the high resistance resistor R1 (time t1).

[0062] When noise is superimposed on the power supply voltage VGOUT, the voltage generated on the line nd2 changes according to the ratio of the capacitors C1 and C2, and this voltage becomes a noise signal and serves as the clock for the noise detection signal output unit 42. As a result, the noise detection signal output unit 42 outputs the detection signal VGDET (time t2).

[0063] (Second Modification) Next, a second modified example of the VGOUT noise detection circuit 4a will be described with reference to Fig. 8. Fig. 8 is a diagram showing a second modified example of the VGOUT noise detection circuit. The VGOUT noise detection circuit 4a2 according to the second modified example may include a noise output unit 41B instead of the noise output unit 41 shown in Fig. 1.

[0064] (Noise output section 41B) The noise output unit 41B may input a first noise to be superimposed on a first voltage of a specific potential (e.g., 20 [V]) in the same manner as the noise output unit 41, convert the first noise into a second noise having a potential lower than that of the first noise, and superimpose the second noise on a second voltage (e.g., VDD=3 [V]) having a potential lower than the specific potential, similar to the noise output unit 41. The noise output unit 41B may output the second noise to be superimposed on the second voltage as a noise signal in the same manner as the noise output unit 41.

[0065] The noise output section 41B may include an integrating circuit 6, a transistor MP0 which is a P-channel MOSFET, a resistor R1, a wiring nd2, and a wiring nd3.

[0066] (Integrator circuit 6) The integrating circuit 6 may be interpreted as a circuit including a capacitor C1 and a resistor R1, which integrates the first voltage and outputs the integrated voltage, or as a delay circuit having a predetermined time constant.

[0067] (Resistor R1) The resistor R1 may be interpreted as a first resistor. A first end of the resistor R1 may be connected to a wiring nd1 to which a power supply voltage VGOUT is applied. A second end of the resistor R1, which is opposite to the first end, may be connected to a wiring nd2 and a transistor MP0.

[0068] (Wiring nd2) A first end of the wiring nd2 may be connected to the resistor R1 and the source of the transistor MP0. A second end of the wiring nd2 opposite to the first end may be connected to the capacitor C1.

[0069] (Capacitor C1) A first end of the capacitor C1 may be connected to the wiring nd2. A second end of the capacitor C1 opposite to the first end may be grounded.

[0070] (Transistor MP0) The source of the transistor MP0 may be connected to the integrating circuit 6. The voltage integrated by the integrating circuit 6 may be applied to the source of the transistor MP0. The drain of the transistor MP0 may be connected to a resistor R2 and a wiring nd3. The gate of the transistor MP0 may be connected to a wiring nd1 and a resistor R1. A first voltage may be applied to the gate of the transistor MP0. The L length of the transistor MP0 may be set according to a noise detection level, or the transistor MP0 may be configured in a vertical stacked configuration.

[0071] (Resistor R2) Resistor R2 may be considered as a second resistor with one end connected to the drain of transistor MP0 and the other end grounded. The other end of resistor R2 may be considered as being connected to the reference power supply terminal (GND). If resistor R2 is not present and wiring nd3 is floating, the potential of wiring nd3 will not become L level when transistor MP0 is turned OFF. If resistor R2 is not present and wiring nd3 is shorted to GND, the potential of wiring nd3 will not become H level even when transistor MP0 is turned ON.

[0072] One end of the wiring nd3 may be connected to the connection point between the drain and the resistor R2. The other end of the wiring nd3 may be connected to the noise detection signal output unit 42. The wiring nd3 may be interpreted as a wiring that transmits a noise signal superimposed on the voltage integrated by the integration circuit 6 to the noise detection signal output unit 42.

[0073] In the noise output unit 41B, the sensitivity of noise detection can be adjusted by setting the time constant of the integrating circuit 6 which is a delay circuit, setting the L length of the transistor MP0, stacking the transistor MP0 vertically, etc. By adjusting the sensitivity of noise detection, that is, by adjusting the input voltage of the noise detection signal output unit 42 which is an FF, it is possible to prevent the noise detection signal output unit 42 from being damaged even if a fluctuation occurs in the power supply voltage VGOUT.

[0074] Fig. 9 is a diagram for explaining the operation of the VGOUT noise detection circuit shown in Fig. 8. When instantaneous noise is superimposed on the wiring nd1 (time t1), the voltage applied to the wiring nd2 has a waveform obtained by integrating the voltage applied to the wiring nd1 due to the time constant of the resistor R1 and the capacitor C1 of the integrating circuit 6.

[0075] As a result of the integration of the voltage, a potential difference occurs between the voltage applied to the wiring nd1 and the voltage applied to the wiring nd2 (i.e., the voltage integrated by the integrator circuit 6) (time t2). Due to this potential difference, the gate-source voltage Vgs of the transistor MP0 becomes equal to the voltage applied to the wiring nd1 (V nd1 ) to the wire nd2 (V nd2 ) is subtracted, that is, the difference between these voltages (Vgs=V nd1 -V nd2 ) when the gate-source voltage Vgs exceeds the gate threshold voltage, the transistor MP0 temporarily enters the ON state. That is, the transistor MP0 is in the ON state from the point when the gate-source voltage Vgs exceeds the gate threshold voltage to the point when the gate-source voltage Vgs becomes smaller than the gate threshold voltage. Therefore, the potential of the line nd3 temporarily becomes H level. This H level potential serves as the clock for the noise detection signal output unit 42, which outputs the detection signal VGDET (time t3).

[0076] (Action and effect) According to the noise detection circuit 4 of the present disclosure, a noise signal indicating noise whose potential has been converted is used to output a detection signal VGDET (EMS detection signal) as a logical value, thereby making it possible to detect momentary fluctuations in the power supply voltage as noise. Also, the noise signal can be latched as a clock.

[0077] Furthermore, even if the display panel driving device 130 or the display panel 100 has a power supply configuration in which the voltages of a power supply that may be a noise source (e.g., the first power supply circuit 11) and the power supply of the noise detection circuit 4 do not fluctuate at the same time, a logic circuit (e.g., the timing controller 3) that is driven by a low-potential power supply voltage can detect noise superimposed on a high-potential power supply voltage.

[0078] Therefore, it is possible to suppress malfunctions such as flickering and freezing of the display unit 110, which is the object of control of the logic circuit, caused by noise superimposed on the high-potential power supply voltage. In other words, a normal display state can be maintained. Furthermore, by accurately detecting noise that occurs instantaneously by the noise detection circuit 4, the logic circuit (for example, the timing controller 3) shared with the noise detection circuit 4 can eliminate the effect on the display or limit the effect to one frame.

[0079] By changing the target power supply and the arrangement of the noise detection circuit 4, it is possible to detect power supply systems that are susceptible to noise due to the influence of devices incorporated in the display panel 100, and also to make it easier to detect power supply noise near circuits that are prone to malfunction.

[0080] In addition, the following supplementary notes are provided in relation to the above description.

[0081] (Appendix 1) a noise output unit that receives a first noise to be superimposed on a first voltage of a specific potential, converts the first noise into a second noise having a potential lower than that of the first noise, superimposes the second noise on a second voltage having a potential lower than the specific potential, and outputs the second noise superimposed on the second voltage as a noise signal; a noise detection signal output unit that, when the noise signal is input, outputs a detection signal indicating that the first noise has been detected while maintaining the level of the detection signal; A noise detection circuit comprising:

[0082] (Appendix 2) The noise output unit is a capacitor having a first end to which the first voltage is applied; a P-channel transistor having a drain connected to a second end of the capacitor opposite to the first end and having a source to which the second voltage is applied; a wiring connected to the drain, the second end, and the noise detection signal output unit, the wiring transmitting the noise signal to the noise detection signal output unit; 2. The noise detection circuit of claim 1, comprising:

[0083] (Appendix 3) The noise output unit is a voltage dividing circuit including a first capacitor and a second capacitor connected in series to the first capacitor, dividing the first voltage and outputting the divided voltage; a resistor having one end connected to a connection point between the first capacitor and the second capacitor and having the second voltage applied to the other end; a wiring connected to the connection point, the wiring transmitting the noise signal superimposed on the voltage output from the voltage divider circuit to the noise detection signal output unit; 2. The noise detection circuit of claim 1, comprising:

[0084] (Appendix 4) the noise output unit includes an integration circuit including a capacitor and a first resistor, and integrates and outputs the first voltage; a P-channel transistor having a source to which the voltage integrated by the integrating circuit is applied and a gate to which the first voltage is applied; a second resistor having one end connected to the drain of the P-channel transistor and the other end grounded; a wiring connected to a connection point between the drain and the second resistor, the wiring transmitting the noise signal superimposed on the voltage integrated by the integration circuit to the noise detection signal output unit; 2. The noise detection circuit of claim 1, comprising:

[0085] (Appendix 5) A noise detection circuit according to any one of claims 1 to 4; a driver that generates at least one of a gate signal and a source signal based on the first voltage and supplies the signal to a display panel; A timing controller for controlling the driver; Equipped with The timing controller holds the potential level of the signal at a low level when the detection signal is input, and resumes supply of the signal after a certain period of time has elapsed since the input of the detection signal. [Explanation of symbols]

[0086] 1 GOUT control circuit 2 SOUT control circuit 3 Timing Controller 4 Noise detection circuit 4a Noise detection circuit for GOUT 4a1 Noise detection circuit for GOUT 4a2 Noise detection circuit for GOUT 4b Noise detection circuit for SOUT 5 Voltage divider circuit 6 Integrator circuit 10. Main Processor 11 1st power supply circuit 12 2nd power supply circuit 41 Noise output section 41A Noise output section 41B Noise output section 42 Noise detection signal output section 100 Display Panel 110 Display section 120 Gate control section 130 Display panel driver 200 Control Board

Claims

1. a noise output unit that receives a first noise to be superimposed on a first voltage of a specific potential, converts the first noise into a second noise having a potential lower than that of the first noise, superimposes the second noise on a second voltage having a potential lower than the specific potential, and outputs the second noise superimposed on the second voltage as a noise signal; a noise detection signal output unit that, when the noise signal is input, outputs a detection signal indicating that the first noise has been detected while maintaining a level of the detection signal; A noise detection circuit comprising:

2. The noise output unit is a capacitor having a first end to which the first voltage is applied; a P-channel transistor having a drain connected to a second end of the capacitor opposite to the first end and having a source to which the second voltage is applied; a wiring connected to the drain, the second end, and the noise detection signal output unit, the wiring transmitting the noise signal to the noise detection signal output unit; 2. The noise sensing circuit of claim 1, comprising:

3. The noise output unit is a voltage dividing circuit including a first capacitor and a second capacitor connected in series to the first capacitor, dividing the first voltage and outputting the divided voltage; a resistor having one end connected to a connection point between the first capacitor and the second capacitor and having the second voltage applied to the other end; a wiring connected to the connection point, the wiring transmitting the noise signal superimposed on the voltage output from the voltage divider circuit to the noise detection signal output unit; 2. The noise sensing circuit of claim 1, comprising:

4. the noise output unit includes an integration circuit including a capacitor and a first resistor, and integrates and outputs the first voltage; a P-channel transistor having a source to which the voltage integrated by the integrating circuit is applied and a gate to which the first voltage is applied; a second resistor having one end connected to the drain of the P-channel transistor and the other end grounded; a wiring connected to a connection point between the drain and the second resistor, the wiring transmitting the noise signal superimposed on the voltage integrated by the integration circuit to the noise detection signal output unit; 2. The noise sensing circuit of claim 1, comprising:

5. A noise detection circuit according to any one of claims 1 to 4; a driver that generates at least one of a gate signal and a source signal based on the first voltage and supplies the signal to a display panel; A timing controller for controlling the driver; Equipped with The timing controller holds the potential level of the signal at a low level when the detection signal is input, and resumes supply of the signal after a certain period of time has elapsed since the input of the detection signal.

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