Display device

Abstract

To provide a display device capable of holding uniform display quality.SOLUTION: A display device includes: a pixel including a light emitting element that emits light on the basis of a received data voltage; a first scanning drive section for providing a first scanning signal at a turn-on level for determining a point of time when the pixel receives a data voltage; and a second scanning drive section for providing a second scanning signal at a turn-on level for determining timing for initializing an anode voltage of the light emitting element. Each frame period includes an active period and a blank period; the active period is a period from when the pixel receives the first scanning signal at a first turn-on level to when it receives the first scanning signal at the last turn-on level; the blank period is a period from when the pixel receives the first scanning signal at the last turn-on level to when it receives the first scanning signal at the first turn-on level in the next frame period; and the length of the blank period is equal to or more than a period when each pixel receives the second scanning signal at a turn-on level.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] With the development of information technology, the importance of display devices, which are a connection medium between users and information, is becoming more and more apparent. Accordingly, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0003] A display device displays an image using a plurality of pixels. The plurality of pixels may receive individual voltages or a common voltage. In this case, the voltage level of the common voltage may be changed by varying the load of an electric element capacitively coupled to the common voltage over time.

[0004] For example, if the voltage level of the common voltage is applied differently to each pixel, it may affect the brightness of the pixel, resulting in a displayed image that differs from the desired image. [Patent Document 1] Korean Patent Publication No. 10-2022-0097824 Summary of the Invention [Problem to be solved by the invention]

[0005] One of the technical problems to be solved by the present invention is to provide a display device capable of maintaining uniform display quality. [Means for solving the problem]

[0006] According to an embodiment of the present invention, a display device includes a pixel including a light emitting element that emits light with a luminance based on a received data voltage, a first scan driver that provides a first scan signal of a turn-on level that determines a time when the pixel receives the data voltage, and a second scan driver that provides a second scan signal of a turn-on level that determines a timing of initializing an anode voltage of the light emitting element, each frame period including an active period and a blank period, the active period being a period from a time when the pixel receives an initial first scan signal of a turn-on level to a time when the pixel receives a last first scan signal of a turn-on level, the blank period being a period from a time when the pixel receives the last first scan signal of a turn-on level to a time when the pixel receives a first first scan signal of a turn-on level of a next frame period, and a length of the blank period being equal to or longer than a cycle in which each pixel receives the second scan signal of the turn-on level.

[0007] The length of the blank period may be an integer multiple of a period during which each of the pixels receives the second scan signal of the turn-on level.

[0008] Each of the pixels may receive the first scanning signal of the turn-on level once during one frame period, and each of the pixels may receive the second scanning signal of the turn-on level N times during the one frame period, where N is an integer greater than 3.

[0009] The length of the blank period may be (N-3) times the period during which each of the pixels receives the second scan signal of the turn-on level.

[0010] The N may be 4, and the length of the blank period may be 1 time the period during which each of the pixels receives the second scanning signal at the turn-on level.

[0011] The N may be 5, and the length of the blank period may be twice the period during which each of the pixels receives the second scanning signal at the turn-on level.

[0012] The number of pixels that simultaneously receive the second scan signal of the turn-on level may be maintained the same during the frame period.

[0013] According to an embodiment of the present invention, a display device includes a pixel including a light emitting element that emits light with a luminance based on a received data voltage; a first scan driver that provides a first scan signal of a turn-on level that determines a time when the pixel receives the data voltage; and a second scan driver that provides a second scan signal of a turn-on level that determines a timing of initializing an anode voltage of the light emitting element, each frame period including an active period and a blank period, the active period being a period from a time when the pixel receives a first first scan signal of the turn-on level to a time when the pixel receives a last first scan signal of the turn-on level, the blank period being a period from a time when the pixel receives the last first scan signal of the turn-on level to a time when the pixel receives a first first scan signal of the turn-on level of a next frame period, and a length of the blank period being equal to or greater than half of a corresponding frame period.

[0014] Each of the frame periods may include one address scan period and one self-scan period for each of the pixels, and during the address scan period, each of the pixels may receive a first scan signal at a turn-on level and a second scan signal at a turn-on level, and during the self-scan period, each of the pixels may receive the second scan signal at a turn-on level without receiving the first scan signal at a turn-on level.

[0015] The second scan signal of a turn-on level received by the pixels of the last pixel row among the pixels during the self-scan period may not overlap with the first scan signal of a turn-on level received by the pixels of the first pixel row among the pixels during the address scan period.

[0016] According to an embodiment of the present invention, a display device includes pixels including light emitting elements emitting light with a luminance based on a received data voltage; a first scan driver providing a first scan signal of a turn-on level determining a time point at which the pixels receive the data voltage; and a second scan driver providing a second scan signal of a turn-on level determining a timing at which an anode voltage of the light emitting elements is initialized, each frame period may include an address scan period and a self-scan period for each of the pixels, during the address scan period, each of the pixels receives the first scan signal of the turn-on level and the second scan signal of the turn-on level, during the self-scan period, each of the pixels receives the second scan signal of the turn-on level without receiving the first scan signal of the turn-on level, during each of the frame periods, a self-scan period of a first pixel row is started before an address scan period of a last pixel row is ended, and during each of the frame periods, the second scan signal of the turn-on level supplied during the address scan period of the pixels may not overlap with the second scan signal of the turn-on level supplied during the self-scan period of the pixels.

[0017] During each of the frame periods, the second scan signals of the turn-on level supplied during the address scan periods of the pixels may be superimposed in units of M adjacent pixel rows, where M is an integer greater than one.

[0018] During each of the frame periods, the second scan signals of the turn-on level supplied during the self-scan periods of the pixels may be superimposed on each of the M adjacent pixel rows.

[0019] The width of the second scanning signal of the turn-on level may be P horizontal periods, where P is an integer greater than 0, and M is 2×P.

[0020] The P may be 4 and the M may be 8.

[0021] The P may be 3 and the M may be 6.

[0022] The P may be 2 and the M may be 4.

[0023] During each of the frame periods, each of the second scan signals at the turn-on level supplied during the address scan periods of the pixels may include Q pulses, and a first pulse of the Q pulses supplied to a first pixel row may overlap with R pulses supplied to other pixel rows, and each of the Q and R may be an integer greater than 0.

[0024] A second of the Q pulses supplied to the first row of pixels may overlap with S pulses supplied to another row of pixels, where S is R+(R+1).

[0025] A third of the Q pulses provided to the first row of pixels may overlap with T pulses provided to other rows of pixels, where T is S+(R+1). Effect of the Invention

[0026] The display device according to the present invention can maintain uniform display quality. [Brief description of the drawings]

[0027] [Figure 1] 1 is a diagram illustrating a display device according to an embodiment of the present invention; [Diagram 2] 2 is a diagram illustrating a pixel according to an embodiment of the present invention; FIG. [Figure 3a] FIG. 11 is a diagram for explaining a change in display frequency according to an embodiment of the present invention. [Figure 3b] FIG. 11 is a diagram for explaining a change in display frequency according to an embodiment of the present invention. [Figure 4] FIG. 11 is a diagram illustrating an address scan period according to an embodiment of the present invention. [Diagram 5] FIG. 11 is a diagram illustrating a self-scan period according to an embodiment of the present invention. [Figure 6]1 is a diagram illustrating a method of driving a display device according to an embodiment of the present invention; [Figure 7] 7 is a diagram for explaining an image displayed when following the driving method of FIG. 6. FIG. [Figure 8] 7 is a diagram for explaining an image displayed when following the driving method of FIG. 6. FIG. [Figure 9] 11A to 11C are diagrams illustrating a method of driving a display device according to another embodiment of the present invention. [Figure 10] 11A to 11C are diagrams illustrating a method of driving a display device according to another embodiment of the present invention. [Figure 11] 11A to 11C are diagrams illustrating a method of driving a display device according to another embodiment of the present invention. [Figure 12] 11A to 11C are diagrams illustrating a method of driving a display device according to another embodiment of the present invention. [Figure 13] 11A to 11C are diagrams illustrating a method of driving a display device according to another embodiment of the present invention. [Figure 14] 11A to 11C are diagrams illustrating a method of driving a display device according to another embodiment of the present invention. [Figure 15] 11A to 11C are diagrams illustrating a method of driving a display device according to another embodiment of the present invention. [Figure 16] 11A to 11C are diagrams illustrating a method of driving a display device according to another embodiment of the present invention. [Figure 17] 11 is a diagram illustrating a display device according to another embodiment of the present invention; [Figure 18] FIG. 13 is a diagram illustrating a pixel according to another embodiment of the present invention. [Figure 19] FIG. 11 is a diagram illustrating an address scan period according to another embodiment of the present invention. [Figure 20] FIG. 11 is a diagram illustrating a self-scan period according to another embodiment of the present invention. [Figure 21] 11 is a diagram illustrating a driving method of a display device according to still another embodiment of the present invention; [Figure 22] 11 is a diagram illustrating a driving method of a display device according to still another embodiment of the present invention; [Diagram 23] FIG. 13 is a diagram illustrating a pixel according to still another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention may be embodied in various different forms and is not limited to the embodiments set forth below.

[0029] In order to clearly explain the present invention, parts that are not related to the present invention will be described as necessary. Also, the same reference numerals will be used throughout the specification to refer to the same or similar components. Therefore, the above reference numerals can be used in other drawings.

[0030] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of each component shown in the drawings. In the drawings, thicknesses may be exaggerated to clearly show multiple layers and regions.

[0031] In addition, when the expression "same" is used in the description, it may mean "substantially the same." In other words, it may mean that it is the same to the extent that a person with ordinary skill in the art would understand it to be the same. Other expressions may also mean expressions in which "substantially" is omitted.

[0032] FIG. 1 is a diagram illustrating a display device according to an embodiment of the present invention.

[0033] Referring to FIG. 1, a display device 10 according to an embodiment of the present invention may include a timing controller 11, a data driver 12, a scan driver 13, a pixel unit 14, and a light emitting driver 15.

[0034] The timing controller 11 may receive a gray scale for an input image (or an input frame). The gray scale may include a first color gray scale, a second color gray scale, and a third color gray scale. The first color gray scale may be a gray scale for expressing a first color, the second color gray scale may be a gray scale for expressing a second color, and the third color gray scale may be a gray scale for expressing a third color.

[0035] Furthermore, the timing controller 11 may receive a control signal for the image. Such control signal may include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a data enable signal. The vertical synchronization signal may include a plurality of pulses, and may indicate that a previous frame period ends and a current frame period starts based on a time point when each pulse occurs. An interval between adjacent pulses of the vertical synchronization signal may correspond to one frame period. The horizontal synchronization signal may include a plurality of pulses, and may indicate that a previous horizontal period ends and a new horizontal period starts based on a time point when each pulse occurs. An interval between adjacent pulses of the horizontal synchronization signal may correspond to one horizontal period. The data enable signal may have an enable level for a specific horizontal period and a disable level for the remaining period. When the data enable signal is at an enable level, it may indicate that a color gradation is supplied in the corresponding horizontal period.

[0036] The timing controller 11 may provide a gray scale that is rendered or corrected according to the specifications of the display device 10 to the data driver 12. In addition, the timing controller 11 may provide a clock signal, a scan start signal, etc. to the scan driver 13. The timing controller 11 may provide a clock signal, a light emission stop signal, etc. to the light emission driver 15.

[0037] The data driver 12 may generate data voltages to be provided to the data lines DL1, ..., DLj, ..., DLq using the gray scale and control signal received from the timing controller 11. For example, the data driver 12 may sample the gray scale using a clock signal and apply data voltages corresponding to the gray scale to the data lines in units of pixel rows. q may be an integer greater than 1, and j may be an integer greater than 0 and less than q.

[0038] The scan driver 13 may include first to fourth scan drivers 13GW, 13GB, 13GI, and 13GC. The first scan driver 13GW may provide first scan signals to the first scan lines GW1, ..., GWi, ..., GWp. p may be an integer greater than 1, and i may be an integer greater than 0 and less than p. The second scan driver 13GB may provide second scan signals to the second scan lines GB1, ..., GBi, ..., GBp. The third scan driver 13GI may provide third scan signals to the third scan lines G1, ..., GIi, ..., GIp. The fourth scan driver 13GC may provide first scan signals to the fourth scan lines GC1, ..., GCi, ..., GCp.

[0039] For example, the first scan driver 13GW may receive at least one scan clock signal and a scan start signal from the timing controller 11 to generate first scan signals to be provided to the first scan lines GW1 to GWp. The first scan driver 13GW may sequentially provide the first scan signals having a pulse of a turn-on level to the first scan lines GW1 to GWp. For example, the first scan driver 13GW may be configured in the form of a shift register, and may generate the first scan signals in a manner of sequentially transmitting a pulse-shaped scan start signal of a turn-on level to the next scan stage in response to control of the scan clock signal.

[0040] The second scan driver 13GB, the third scan driver 13GI, and the fourth scan driver 13GC may be configured similarly to the first scan driver 13GW, and therefore a duplicated description will be omitted. According to an embodiment of the present invention, at least some of the first to fourth scan drivers 13GW, 13GB, 13GI, and 13GC may be integrated. For example, if the polarity and width of the pulses are the same, two or more scan drivers may be integrated. For example, referring to FIG. 4, the third scan driver 13GI and the fourth scan driver 13GC may be integrated because the polarity and width of the pulse of the turn-on level applied to the third scan line GIi at time t2a and the pulse of the turn-on level applied to the fourth scan line GCi at time t3a are the same.

[0041] The light emission driver 15 may receive at least one light emission clock signal and a light emission stop signal from the timing controller 11 and generate light emission signals to be provided to the light emission lines EM1, ..., EMi, ..., EMp. The light emission driver 15 may sequentially provide light emission signals having pulses of a turn-off level to the light emission lines EM1 to EMp. For example, the light emission driver 15 may be configured as a shift register and may generate light emission signals in a manner of sequentially transmitting a pulsed light emission stop signal of a turn-off level to the next light emission stage in response to control of the light emission clock signal.

[0042] In FIG. 1, the first scanning lines GW1-GWp, the second scanning lines GB1-GBp, the third scanning lines GI1-GIp, the fourth scanning lines GC1-GCp, and the emission lines EM1-EMp are each shown as p in number. However, in other embodiments, at least one of the second scanning lines GB1-GBp, the third scanning lines GI1-GIp, the fourth scanning lines GC1-GCp, and the emission lines EM1-EMp may be configured with p / 2 or less in number. For example, two adjacent pixel rows can share one second scanning line. Similarly, two adjacent pixel rows can share one third scanning line, fourth scanning line, or emission line. The same pixel row means pixels connected to the same first scanning line.

[0043] The pixel unit 14 includes pixels. Each pixel PXij can be connected to a corresponding data line DLj, scan lines GWi, GBi, GIi, GCi, and emission line EMi. Each pixel PXij can include a light emitting element that emits light based on a received data voltage.

[0044] The pixel unit 14 may include a first pixel emitting light of a first color, a second pixel emitting light of a second color, and a third pixel emitting light of a third color. The first color, the second color, and the third color may be different colors. For example, the first color may be one of red, green, and blue, the second color may be one of red, green, and blue that is not the first color, and the third color may be the remaining color of red, green, and blue that is not the first color or the second color. Also, magenta, cyan, and yellow may be used as the first to third colors instead of red, green, and blue.

[0045] The pixel unit 14 may be arranged in various forms such as diamond PENTILE™, RGB-Stripe, S-stripe, real RGB, and normal PENTILE™.

[0046] FIG. 2 is a diagram illustrating a pixel according to an embodiment of the present invention.

[0047] 2, the pixel PXij includes a pixel circuit PXC and a light emitting element LD. The pixel circuit PXC includes transistors T1, T2, T3, T4, T5, T6, T7, T8, and a storage capacitor Cst.

[0048] The pixel PXij may be located in the i-th pixel row and the j-th pixel column. The pixel PXij may be a first pixel for expressing a first color. A second pixel for expressing a second color and a third pixel for expressing a third color may be configured in the same manner as the first pixel, and therefore a duplicated description will be omitted.

[0049] The P-type transistor may be a polysilicon semiconductor transistor. The channel of the active layer of the polysilicon semiconductor transistor may include a polysilicon semiconductor. For example, the polysilicon semiconductor transistor may be a low temperature polysilicon (LTPS) thin film transistor. The polysilicon semiconductor transistor has high electron mobility and thus has fast driving characteristics.

[0050] The N-type transistor may be an oxide semiconductor transistor. In the oxide semiconductor transistor, a channel of an active layer may include an oxide semiconductor. For example, the oxide semiconductor transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor. The oxide semiconductor transistor has a lower charge mobility than a polysilicon semiconductor transistor. For example, the oxide semiconductor transistor may have a smaller amount of leakage current generated in a turned-off state than a polysilicon semiconductor transistor.

[0051] The first transistor T1 may have a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may be a P-type transistor. According to an embodiment of the present invention, the first transistor T1 may include a sub-gate electrode (or a back-gate electrode, a body electrode), and the sub-gate electrode may receive a first power supply voltage ELVDD.

[0052] The second transistor T2 may have a gate electrode connected to the first scan line GWi, a first electrode connected to the data line DLj, and a second electrode connected to the second node N2. The second transistor T2 may be a switching transistor. The second transistor T2 may be a P-type transistor.

[0053] The first scan driver 13GW may provide a first scan signal having a turn-on level that determines when the pixel PXij receives a data voltage. For example, the second transistor T2 may be turned on upon receiving the first scan signal having a turn-on level, and the second transistor T2 may apply the data voltage applied to the data line DLj to the second node N2.

[0054] The third transistor T3 may have a gate electrode connected to the fourth scan line GCi, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may be a diode-connected transistor. The third transistor T3 may be an N-type transistor.

[0055] The fourth transistor T4 has a gate electrode connected to the third scan line GIi, a first electrode connected to the first node N1, and a second electrode receiving the first initialization voltage VINT. The fourth transistor T4 may be a gate initialization transistor. The fourth transistor T4 may be an N-type transistor.

[0056] The fifth transistor T5 may have a gate electrode connected to the emission line EMi, a first electrode receiving the first power supply voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 may be a first emission control transistor. The fifth transistor T5 may be a P-type transistor.

[0057] The sixth transistor T6 may have a gate electrode connected to the emission line EMi, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The sixth transistor T6 may be a second emission control transistor. The sixth transistor T6 may be a P-type transistor.

[0058] The seventh transistor T7 may have a gate electrode connected to the second scan line GBi, a first electrode receiving the second initialization voltage VAINT, and a second electrode connected to the fourth node N4. The seventh transistor T7 may be an anode initialization transistor. The seventh transistor T7 may be a P-type transistor.

[0059] The second scan driver 13GB may provide a second scan signal of a turn-on level that determines a timing for initializing the anode voltage of the light emitting device LD. For example, the seventh transistor T7 that receives the second scan signal of the turn-on level is turned on, and the second initialization voltage VAINT is applied to the anode of the light emitting device LD, so that the anode voltage of the light emitting device LD may be initialized to the second initialization voltage VAINT.

[0060] The eighth transistor T8 may have a gate electrode connected to the second scan line GBi, a first electrode receiving the bias voltage VOBS, and a second electrode connected to the second node N2. The eighth transistor T8 may be a bias transistor. The eighth transistor T8 may be a P-type transistor.

[0061] The storage capacitor Cst may have a first electrode receiving a first power supply voltage ELVDD and a second electrode coupled to a first node N1.

[0062] The light emitting element LD has an anode connected to the fourth node N4 and a cathode receiving the second power supply voltage ELVSS. The light emitting element LD can emit light in one of a first color, a second color, and a third color. The light emitting element LD may be a light emitting diode. The light emitting element LD may be an organic light emitting element, an inorganic light emitting element, a quantum dot / well light emitting diode, or the like. In one embodiment of the present invention, only one light emitting element LD is provided in each pixel, but in other embodiments, each pixel may be provided with a plurality of light emitting elements. In this case, the plurality of light emitting elements may be connected in series, in parallel, in series-parallel, or the like.

[0063] 3a and 3b are diagrams for explaining a display frequency change according to an embodiment of the present invention.

[0064] The display device 10 can support a variable refresh rate (VRR). The refresh rate is the frequency at which a data voltage is written to the pixel PXij, and is also called a screen scanning rate or a screen reproduction rate, and can represent the number of image frames reproduced per second.

[0065] For example, the pixel unit 14 can display an image at a first frequency AHz in a first mode (see FIG. 3a) and display an image at a second frequency BHz lower than the first frequency AHz in a second mode (see FIG. 3b).

[0066] For example, in the first mode, each frame period 1F may include one address scan period AS and one self scan period SS for each pixel PXij. For example, in the second mode, each frame period 1F may include one address scan period AS and multiple self scan periods SS for each pixel PXij. The smaller the second frequency BHz, the more the number of self scan periods SS included in one frame period 1F may increase. In another embodiment, in the third mode, each frame period 1F may include only one address scan period AS for each pixel PXij, and may not include a self scan period SS.

[0067] The address scan period AS is a period for writing data voltages to the pixels PXij. The address scan period AS can also be called a data programming period for receiving data voltages from the data lines DLj.

[0068] The self-scan period SS is a period during which no data voltage is written to the pixel PXij. During the light emission period of the self-scan period SS, the pixel PXij can emit light using the data voltage written in the address scan period AS. The length of the self-scan period SS may be the same as the length of the address scan period AS.

[0069] 4 is a diagram for explaining an address scan period according to an embodiment of the present invention, and the pixel PXij in FIG.

[0070] At time t1a, a light emission signal of a turn-off level (high level) is applied to the emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 are turned off and the pixel PXij is brought into a non-light emitting state.

[0071] At time t2a, the third scan signal of the turn-on level (high level) is applied to the third scan line GIi, thereby turning on the fourth transistor T4. This causes the first initialization voltage VINT to be applied to the first node N1. The first initialization voltage VINT is a sufficiently low voltage to on-bias the first transistor T1.

[0072] At time t3a, a fourth scan signal of a turn-on level (high level) is applied to the fourth scan line GCi, turning on the third transistor T3, and thus the first transistor T1 is brought into a diode-connected state in which the drain electrode and gate electrode are connected.

[0073] At time t4a, a scan signal of a turn-on level (low level) is applied to the first scan line GWi, thereby turning on the second transistor T2. Thus, the data voltage of the data line DLj may be applied to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3, which are in a turned-on state. At this time, the voltage of the first node N1 may be a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The storage capacitor Cst may hold the difference between the first power supply voltage ELVDD and the compensation voltage.

[0074] At time t5a, a scan signal of a turn-on level (low level) is applied to the second scan line GBi, so that the seventh transistor T7 and the eighth transistor T8 are turned on. When the seventh transistor T7 is turned on, the second initialization voltage VAINT is applied to the anode of the light emitting element LD, so that the light emitting element LD can be initialized to a charge amount corresponding to a voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. This makes it easy to express low gray scales in the light emitting element LD.

[0075] Also, by turning on the eighth transistor T8, the voltage of the second node N2 can be set to the bias voltage VOBS, and thus, the bias voltage VOBS, not the data voltage of the previous frame period, is applied to the source electrode of the first transistor T1, thereby preventing the hysteresis phenomenon and ensuring the on-bias state.

[0076] At time t6a, a turn-on level (low level) light emission signal is applied to the light emission line EMi, thereby turning on the fifth transistor T5 and the sixth transistor T6. Therefore, a path of a driving current is formed that flows from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element LD.

[0077] The amount of driving current can be adjusted according to the voltage stored in the storage capacitor Cst. The light emitting device LD emits light with a luminance corresponding to the amount of driving current. The light emitting device LD can emit light before a light emitting signal of a turn-off level is applied to the emission line EMi.

[0078] 5 is a diagram for explaining a self-scan period according to an embodiment of the present invention, and the explanation of FIG. 5 will be made with reference to pixel PXij of FIG.

[0079] At time t7a, a light emission signal of a turn-off level (high level) is applied to the emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 are turned off and the pixel PXij enters a non-light emitting state.

[0080] During the period t7a to t8a, the first scan line GWi, the third scan line GIi, and the fourth scan line GCi are held with the scan signals at the turn-off level, so the voltage of the first node N1 does not fluctuate.

[0081] At time t8a, a scan signal of a turn-on level (low level) is applied to the second scan line GBi, so that the seventh transistor T7 and the eighth transistor T8 are turned on. When the seventh transistor T7 is turned on, the second initialization voltage VAINT is applied to the anode of the light emitting element LD, so that the light emitting element LD can be initialized to a charge amount corresponding to a voltage difference between the second initialization voltage VAINT and the second power supply voltage ELVSS. This makes it easy to express low gray scales in the light emitting element LD.

[0082] Also, by turning on the eighth transistor T8, the voltage of the second node N2 can be set to the bias voltage VOBS, and thus, the bias voltage VOBS, not the data voltage of the previous frame period, is applied to the source electrode of the first transistor T1, thereby preventing the hysteresis phenomenon and ensuring the on-bias state.

[0083] At time t9a, a turn-on level (low level) light emission signal is applied to the light emission line EMi, so that the fifth transistor T5 and the sixth transistor T6 can be turned on. Therefore, a path of a driving current is formed that flows from the first power supply voltage ELVDD to the second power supply voltage ELVSS via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element LD.

[0084] The amount of driving current can be adjusted according to the voltage held in the storage capacitor Cst. Since the voltage of the first node N1 written during the address scan period AS is held during the self-scan period SS, the luminance of the pixel PXij during the self-scan period SS is the same as the luminance of the pixel PXij during the address scan period AS.

[0085] Fig. 6 is a diagram for explaining a driving method of a display device according to an embodiment of the present invention, and Figs. 7 and 8 are diagrams for explaining images displayed when following the driving method of Fig. 6.

[0086] 6, each of the frame periods FRMP1, FRMP2, ... may include an active period and a blank period. For example, the first frame period FRMP1 may include an active period ACTP1 and a blank period BNKP1. The second frame period FRMP2 may include an active period ACTP2 and a blank period (not shown). The blank period may be a porch period.

[0087] The active period ACTP1 or ACTP2 may be a period from when the pixel of the pixel unit 14 receives the first scan signal of the turn-on level for the first time to when it receives the last first scan signal of the turn-on level.

[0088] The first scan driver 13GW may sequentially apply first scan signals of a turn-on level (low level) to the first scan lines GW1 to GWp. For example, the first scan driver 13GW may apply a first scan signal of a first turn-on level to the first scan line GW1. For example, the first scan driver 13GW may apply a first scan signal of a last turn-on level to the first scan line GWp. During the active period ACTP1 or ACTP2, the data driver 12 may apply data voltages to the data lines DL1 to DLq in pixel row units at timings corresponding to the first scan signals of the turn-on level.

[0089] The blank period BNKP1 may be a period from when the pixels of the pixel unit 14 receive the last first scan signal of the turn-on level to when they receive the first first scan signal of the turn-on level of the next frame period FRMP2. During the blank period BNKP1, the data driver 12 may not apply data voltages to the data lines DL1 to DLq. According to an embodiment of the present invention, during the blank period BNKP1, the data driver 12 may hold a reference voltage of a particular level on the data lines DL1 to DLq. According to an embodiment of the present invention, during the blank period BNKP1, the data driver 12 may not supply voltages to the data lines DL1 to DLq.

[0090] The second scan driver 13GB can sequentially apply the second scan signal of the turn-on level to the second scan lines GB1 to GBp. In the embodiment shown in FIG. 6, the second scan signal of the turn-on level is sequentially applied in units of two second scan lines. For example, the first stage of the second scan driver 13GB can simultaneously apply the second scan signal of the turn-on level (low level) to the second scan lines GB1 and GB2. Then, the second stage of the second scan driver 13GB can simultaneously apply the second scan signal of the turn-on level to the second scan lines GB3 and GB4. Then, the third stage of the second scan driver 13GB can simultaneously apply the second scan signal of the turn-on level to the second scan lines GB5 and GB6. In another embodiment, the second scan signal of the turn-on level can be sequentially applied in units of one second scan line (see FIGS. 9 and 10).

[0091] Each pixel may receive the first scan signal of the turn-on level once during one frame period FRMP1. Each pixel may receive the second scan signal of the turn-on level N times during one frame period FRMP1. N may be an integer greater than 1. In the embodiment shown in FIG. 6, each pixel is shown receiving the second scan signal of the turn-on level four times during one frame period FRMP1. The second scan driver 13GB may provide the second scan signal of the turn-on level to each pixel at a constant cycle GB1CYC. Referring to the description of FIGS. 3a to 5, in the embodiment shown in FIG. 6, one frame period FRMP1 may include one address scan period AS and three self-scan periods SS for each pixel PXij. The address scan periods AS of pixels located in the same pixel row may be the same as each other. Similarly, the self-scan periods SS of pixels located in the same pixel row may be the same as each other.

[0092] In the embodiment shown in FIG. 6, it is assumed that the pulse width of the first scan signal of the turn-on level corresponds to one horizontal period, and the pulse width of the second scan signal of the turn-on level corresponds to four horizontal periods. In this case, the time interval between the second scan signals of the turn-on level that are sequentially applied may be two horizontal periods. For example, the second scan signals of the turn-on level may be simultaneously applied to the second scan lines GB1 and GB2, and then, two horizontal periods later, the second scan signals of the turn-on level may be simultaneously applied to the second scan lines GB3 and GB4. In another embodiment, when the second scan signals of the turn-on level are sequentially applied in units of one second scan line (see FIG. 9 and FIG. 10), the time interval between the second scan signals of the turn-on level that are sequentially applied may be set to one horizontal period.

[0093] 6, the length of the blank period BNKP1 is shorter than the period GB1CYC in which each pixel receives the second scan signal of the turn-on level. In this case, the number of second scan lines to which the second scan signal of the turn-on level is applied in each horizontal period of the specific periods swp1, swp2, and swp3 may be 12. The pixels connected to such second scan lines are located in second areas AR21, AR22, and AR23.

[0094] Meanwhile, the number of second scan lines to which the second scan signals of the turn-on level are applied in each horizontal period of the remaining periods except for the specific periods swp1, swp2, and swp3 may be 16. The pixels connected to such second scan lines are located in first areas AR11, AR12, AR13, and AR14.

[0095] However, the number of second scan lines to which the second scan signal of the turn-on level is applied in each of the two horizontal periods before and after the specific periods swp1, swp2, and swp3 may be 14. For convenience of explanation, the explanation of this is omitted in FIGS. 7 and 8.

[0096] 7, there is shown a photograph in which a monochrome image frame is input to the pixel unit 14. It can be seen that even though a monochrome image frame is input to the pixel unit 14, a darker striped pattern is displayed in the second regions AR21, AR22, and AR23 compared to the first regions AR11, AR12, AR13, and AR14.

[0097] 8, the emission line EMi, the second scan line GBi, the fourth node voltage N4V, and the second initialization voltage VAINT in the address scan period AS described with reference to FIG. 4 are illustrated.

[0098] At time t5a, the second scan signal having a turn-on level may be applied to the second scan line GBi, and the seventh transistor T7 may be turned on to apply the second initialization voltage VAINT to the fourth node N4, which is the anode of the light emitting element LD (see FIG. 2).

[0099] The second initialization voltage VAINT may be a common voltage commonly supplied to all pixels of the pixel unit 14. The second initialization voltage VAINT may be supplied as a DC voltage. However, the voltage level of the second initialization voltage VAINT may be changed by being capacitively coupled with the anodes of the light emitting elements LD of the plurality of pixels via the seventh transistors T7 that are turned on.

[0100] As described above, the second initialization voltage VAINT may be capacitively coupled to 16 pixel rows during one horizontal period in the first regions AR11, AR12, AR13, and AR14. Meanwhile, the second initialization voltage VAINT may be capacitively coupled to 14 pixel rows during one horizontal period in the second regions AR21, AR22, and AR23. Due to such a difference in load, the voltage level of the second initialization voltage VAINT supplied to the second regions AR21, AR22, and AR23 may be lower than the voltage level of the second initialization voltage VAINT supplied to the first regions AR11, AR12, AR13, and AR14.

[0101] Due to the difference in the voltage level of the second initialization voltage VAINT, a difference also occurs in the fourth node voltage N4V of the fourth node N4. Therefore, after time point t6a, the light-emitting elements LD in the second areas AR21, AR22, and AR23 emit light with a lower luminance than the light-emitting elements LD in the first areas AR11, AR12, AR13, and AR14.

[0102] 9 to 16 are diagrams illustrating a method of driving a display device according to another embodiment of the present invention.

[0103] 9 and 10, each of the frame periods FRMP1, FRMP2, ... may include an active period and a blank period. For example, the first frame period FRMP1 may include an active period ACTP1 and a blank period BNKP1. The second frame period FRMP2 may include an active period ACTP2 and a blank period (not shown).

[0104] The active period ACTP1 or ACTP2 may be a period from when the pixel of the pixel unit 14 receives the first scan signal of the first turn-on level to when it receives the last first scan signal of the last turn-on level.

[0105] The first scan driver 13GW may sequentially apply first scan signals of a turn-on level (low level) to the first scan lines GW1 to GWp. For example, the first scan driver 13GW may apply a first scan signal of a first turn-on level to the first scan line GW1. For example, the first scan driver 13GW may apply a first scan signal of a last turn-on level to the first scan line GWp. During the active period ACTP1 or ACTP2, the data driver 12 may apply data voltages to the data lines DL1 to DLq in pixel row units at timings corresponding to the first scan signals of the turn-on level.

[0106] The blank period BNKP1 may be a period from when the pixels of the pixel unit 14 receive the last first scan signal of the turn-on level to when they receive the first first scan signal of the turn-on level of the next frame period FRMP2. During the blank period BNKP1, the data driver 12 may not apply data voltages to the data lines DL1 to DLq. According to an embodiment of the present invention, during the blank period BNKP1, the data driver 12 may hold a reference voltage of a particular level on the data lines DL1 to DLq. According to an embodiment of the present invention, during the blank period BNKP1, the data driver 12 may not supply voltages to the data lines DL1 to DLq.

[0107] The second scan driver 13GB may sequentially apply the second scan signal of the turn-on level to the second scan lines GB1 to GBp. In the embodiment shown in FIG. 6, the second scan signal of the turn-on level is sequentially applied in units of one second scan line. For example, the first stage of the second scan driver 13GB may apply the second scan signal of the turn-on level (low level) to the second scan line GB1. Then, the second stage of the second scan driver 13GB may apply the second scan signal of the turn-on level to the second scan line GB2. Then, the third stage of the second scan driver 13GB may apply the second scan signal of the turn-on level to the second scan line GB3. In another embodiment, the second scan signal of the turn-on level may be sequentially applied in units of two second scan lines (see FIG. 6).

[0108] Each pixel may receive the first scan signal at a turn-on level once during one frame period FRMP1. Each pixel may receive the second scan signal at a turn-on level N times during one frame period FRMP1, where N may be an integer greater than 3. In the embodiment shown in FIG. 9, each pixel is shown receiving the second scan signal at a turn-on level four times during one frame period FRMP1. In the embodiment shown in FIG. 10, each pixel is shown receiving the second scan signal at a turn-on level five times during one frame period FRMP1.

[0109] The second scan driver 13GB may provide a second scan signal of a turn-on level to each pixel at a constant period GB1CYC. Referring to the description of Figs. 3a to 5, in the embodiment shown in Fig. 9, one frame period FRMP1 may include one address scan period AS and three self-scan periods SS for each pixel PXij. In the embodiment shown in Fig. 10, one frame period FRMP1 may include one address scan period AS and four self-scan periods SS for each pixel PXij. The address scan periods AS of pixels located in the same pixel row may be the same as each other. Similarly, the self-scan periods SS of pixels located in the same pixel row may be the same as each other.

[0110] 9 and 10, it is assumed that the pulse width of the first scan signal at the turn-on level corresponds to one horizontal period, and the pulse width of the second scan signal at the turn-on level corresponds to three horizontal periods. In this case, the time interval between the second scan signals at the turn-on level that are sequentially applied may be one horizontal period.

[0111] 9 and 10, the length of the blank period BNKP1 may be greater than or equal to the period GB1CYC in which each pixel receives the second scanning signal at the turn-on level. For example, the length of the blank period BNKP1 may be an integer multiple of the period GB1CYC in which each pixel receives the second scanning signal at the turn-on level. For example, the length of the blank period BNKP1 may be (N-3) times the period in which each pixel receives the second scanning signal at the turn-on level.

[0112] For example, in the embodiment shown in Fig. 9, N corresponds to 4, so the length of the blank period may be 1 time the period in which each pixel receives the second scan signal of the turn-on level. For example, in the embodiment shown in Fig. 10, N corresponds to 5, so the length of the blank period may be 2 times the period in which each pixel receives the second scan signal of the turn-on level.

[0113] According to an embodiment of the present invention, the number of pixels that simultaneously receive the second scan signal of the turn-on level may be maintained the same during the frame periods FRMP1 and FRMP2, i.e., the number of pixels that simultaneously receive the second scan signal of the turn-on level during each horizontal period of the frame periods FRMP1 and FRMP2 may be the same.

[0114] For example, in the case of the embodiment shown in FIG. 9, the number of pixels receiving the second scan signal of the turn-on level at successive time points t1b, t2b, t3b, and t4b corresponding to four successive horizontal periods may be the same. For example, the number of pixel rows receiving the second scan signal of the turn-on level at successive time points t1b, t2b, t3b, and t4b may be nine. For example, at time point t1b, nine pixel rows including three pixel rows connected to the second scan lines GB(p-2), GB(p-1), and GBp may receive the second scan signal of the turn-on level. At time point t2b, nine pixel rows including three pixel rows connected to the second scan lines GB(p-1), GBp, and GB1 may receive the second scan signal of the turn-on level. At time point t3b, nine pixel rows including three pixel rows connected to the second scan lines GBp, GB1, and GB2 may receive the second scan signal of the turn-on level. At time t4b, nine pixel rows, including the three pixel rows connected to the second scan lines GB1, GB2, and GB3, can receive the second scan signal at a turn-on level.

[0115] For example, in the case of the embodiment shown in FIG. 10, the number of pixels receiving the second scan signal of the turn-on level at successive time points t1c, t2c, t3c, and t4c corresponding to four successive horizontal periods may be the same. For example, the number of pixel rows receiving the second scan signal of the turn-on level at successive time points t1c, t2c, t3c, and t4c may be nine. For example, at time point t1c, nine pixel rows including three pixel rows connected to the second scan lines GB(p-2), GB(p-1), and GBp may receive the second scan signal of the turn-on level. At time point t2c, nine pixel rows including three pixel rows connected to the second scan lines GB(p-1), GBp, and GB1 may receive the second scan signal of the turn-on level. At time point t3c, nine pixel rows including three pixel rows connected to the second scan lines GBp, GB1, and GB2 may receive the second scan signal of the turn-on level. At time t4c, nine pixel rows, including the three pixel rows connected to the second scan lines GB1, GB2, and GB3, can receive the second scan signal at a turn-on level.

[0116] 9 and 10, the voltage level of the second initialization voltage VAINT does not fluctuate due to differences in load, and the display device 10 can maintain uniform display quality without stripes or unevenness.

[0117] Each of the frame periods FRMP1, FRMP2, ... in Figures 11 to 16 can include an active period and a blank period. For example, the first frame period FRMP1 can include an active period ACTP1 and a blank period BNKP1. The second frame period FRMP2 can include an active period ACTP2 and a blank period (not shown).

[0118] Each frame period FRMP1, FRMP2, ... may include an address scan period and a self-scan period for each pixel. For example, in the embodiment shown in Figures 11 to 13, each frame period FRMP1, FRMP2, ... includes one address scan period and one self-scan period for each pixel. For example, in the embodiment shown in Figures 14 to 16, each frame period FRMP1, FRMP2, ... includes one address scan period and three self-scan periods for each pixel.

[0119] During the address scan period, each pixel may receive a first scan signal at a turn-on level and a second scan signal at a turn-on level, and during the self-scan period, each pixel may receive a second scan signal at a turn-on level without receiving the first scan signal at a turn-on level.

[0120] During each of the frame periods FRMP1, FRMP2, ..., the self-scan period of the first pixel row (i.e., the pixel row connected to the second scan line GB1) may start before the address scan period of the last pixel row (i.e., the pixel row connected to the second scan line GBp) ends. Also, during each of the frame periods FRMP1, FRMP2, ..., the second scan signal of the turn-on level supplied during the pixel address scan period may not overlap with the second scan signal of the turn-on level supplied during the pixel self-scan period.

[0121] 11 to 13, the second scanning signals of the turn-on level supplied during the pixel address scan periods during each of the frame periods FRMP1, FRMP2, ... may be superimposed in units of M adjacent pixel rows. In this case, M may be an integer greater than 1. Also, the second scanning signals of the turn-on level supplied during the pixel self-scan periods during each of the frame periods FRMP1, FRMP2, ... may be superimposed in units of M adjacent pixel rows.

[0122] In one embodiment of the present invention, the width of the second scanning signal at the turn-on level may be P horizontal periods, where P may be an integer greater than 0. In this case, M may be twice P. In the embodiment shown in FIG. 11, P may be 4 and M may be 8. In the embodiment shown in FIG. 12, P may be 3 and M may be 6. In the embodiment shown in FIG. 13, P may be 2 and M may be 4.

[0123] In each of the embodiments shown in FIGS. 11 to 13, the number of pixels that simultaneously receive the second scanning signal of the turn-on level may be kept the same during the frame periods FRMP1 and FRMP2. That is, the number of pixels that simultaneously receive the second scanning signal of the turn-on level in each horizontal period of the frame periods FRMP1 and FRMP2 may be the same. In the embodiment shown in FIG. 11, the number of pixel rows that simultaneously receive the second scanning signal of the turn-on level in each horizontal period may be eight. In the embodiment shown in FIG. 12, the number of pixel rows that simultaneously receive the second scanning signal of the turn-on level in each horizontal period may be six. In the embodiment shown in FIG. 13, the number of pixel rows that simultaneously receive the second scanning signal of the turn-on level in each horizontal period may be four. Therefore, according to the embodiments shown in FIGS. 11 to 13, the voltage level of the second initialization voltage VAINT does not fluctuate due to the load difference. Therefore, the display device 10 can maintain a uniform display quality without stripes or unevenness.

[0124] In the embodiments shown in Figures 14 to 16, each of the second scanning signals at a turn-on level supplied during the pixel address scan period during each of the frame periods FRMP1 and FRMP2 may include Q pulses. Q may be an integer greater than 0. For example, Q may be 3 in Figure 14, Q may be 2 in Figure 15, and Q may be 1 in Figure 16. Also, each of the second scanning signals at a turn-on level supplied during the pixel self-scan period during each of the frame periods FRMP1 and FRMP2 may include Q pulses.

[0125] At this time, the first pulse of the Q pulses supplied to the first pixel row (for example, pixels connected to the first scanning line GW1 and the second scanning line GB1) may be superimposed on the R pulses supplied to the other pixel rows. At this time, R may be an integer greater than 1. For example, R may be 3 in FIG. 14, FIG. 15, and FIG. 16. With reference to FIG. 14, FIG. 15, and FIG. 16, it can be seen that the first pulse of the Q pulses supplied to the second scanning line GB1 is superimposed on the pulses supplied to the second scanning lines GB2, GB3, and GB4. In the case of the embodiment shown in FIG. 14 and FIG. 15, four pulses supplied to the second scanning line may be superimposed on the first region AR11 of the pixel unit 14 corresponding to the period swp1. Also, in the case of the embodiment shown in FIG. 14 and FIG. 15, four pulses supplied to the second scanning line may be superimposed on the first region AR12, which is symmetrical to the first region AR11 from the center of the pixel unit 14. In the case of the embodiment shown in FIG. 16, four pulses supplied to the second scanning line may be superimposed on the entire region of the pixel section 14.

[0126] Also, the second pulse of the Q pulses supplied to the first pixel row (for example, pixels connected to the first scanning line GW1 and the second scanning line GB1) may be superimposed on the S pulses supplied to other pixel rows. In this case, S may be R+(R+1). For example, S may be 7. With reference to FIG. 14 and FIG. 15, it can be seen that the second pulse of the Q pulses supplied to the second scanning line GB1 is superimposed on the pulses supplied to the second scanning lines GB2, GB3, GB4, GB5, GB6, . . . In the case of the embodiment shown in FIG. 14, eight pulses supplied to the second scanning line may be superimposed on the second region AR21 of the pixel unit 14 corresponding to the period swp2. Also, in the case of the embodiment shown in FIG. 14, eight pulses supplied to the second scanning line may be superimposed on the second region AR22 located symmetrically to the second region AR21 from the center of the pixel unit 14. In the embodiment shown in FIG. 15, eight pulses supplied to the second scanning line may be superimposed on each of the remaining second areas AR2 excluding the first areas AR11 and AR12.

[0127] Also, the third pulse of the Q pulses supplied to the first pixel row (e.g., pixels connected to the first scan line GW1 and the second scan line GB1) may be overlapped with the T pulses supplied to other pixel rows. In this case, T may be S+(R+1). For example, T may be 11. Referring to FIG. 14, it can be seen that the third pulse of the Q pulses supplied to the second scan line GB1 is overlapped with the pulses supplied to the second scan lines GB2, GB3, GB4, GB5, GB6, .... In the case of the embodiment shown in FIG. 14, 12 pulses supplied to the second scan line may be overlapped with each other for the remaining third region AR3 excluding the first regions AR11, AR12 and the second regions AR21, AR22.

[0128] According to the embodiment shown in FIG. 16, the entire region of the pixel unit 14 can exhibit uniform display quality. According to the embodiment shown in FIG. 15, the start region AR11 and the end region AR12 of the pixel unit 14 may exhibit lower luminance than intended, but the middle region AR2 can exhibit uniform display quality. According to the embodiment shown in FIG. 14, the start regions AR11 and AR21 and the end regions AR12 and AR22 of the pixel unit 14 may exhibit lower luminance than intended, but the middle region AR3 can exhibit uniform display quality. In the case of the embodiments shown in FIG. 14 and FIG. 15, the luminance reduction of the edge regions AR11, AR12, AR21, and AR22 can be hardly recognized by the user. Also, the luminance reduction of the edge regions AR11, AR12, AR21, and AR22 can be made invisible by covering the edge regions AR11, AR12, AR21, and AR22 with a black matrix. According to one embodiment of the present invention, dummy pixel rows may be added to the display device 10 before the first pixel row and after the last pixel row, thereby preventing luminance reduction in the edge regions AR11, AR12, AR21, and AR22.

[0129] FIG. 17 is a diagram illustrating a display device according to another embodiment of the present invention.

[0130] 17, a display device 10a may include a scan driver 13a and a light emission driver 15a. Other configurations of the display device 10a are the same as those of the display device 10 of FIG. 1, so duplicated descriptions will be omitted.

[0131] The scan driver 13a may include first to third scan drivers 13GWa, 13GIa, and 13GRa. The first scan driver 13GWa may provide first scan signals to the first scan lines GWa1, ..., GWai, ..., GWap. p may be an integer greater than 1, and i may be an integer greater than 0 and less than p. The second scan driver 13GIa may provide second scan signals to the second scan lines GIa1, ..., GIai, ..., GIap. The third scan driver 13GRa may provide third scan signals to the third scan lines GRa1, ..., GRai, ..., GRap.

[0132] For example, the first scan driver 13GWa may receive at least one scan clock signal and a scan start signal from the timing controller 11 to generate a first scan signal to be provided to the first scan lines GWa1 to GWap. The first scan driver 13GWa may sequentially provide the first scan signal having a pulse of a turn-on level to the first scan lines GWa1 to GWap. For example, the first scan driver 13GWa may be configured as a shift register, and may generate the first scan signal by sequentially transmitting a pulse-shaped scan start signal of a turn-on level to the next scan stage according to the control of the scan clock signal. The second scan driver 13GIa and the third scan driver 13GRa may be configured substantially the same as the first scan driver 13GWa, and therefore a duplicated description will be omitted.

[0133] The light emission driver 15a may include a first light emission driver 15EMa and a second light emission driver 15EMBa. The first light emission driver 15EMa may provide a first light emission signal to the first light emission lines EMa1, ..., EMai, ..., EMap. The second light emission driver 15EMBa may provide a second light emission signal to the second light emission lines EMBa1, ..., EMBai, ..., EMBap.

[0134] For example, the first light-emitting driver 15EMa may receive at least one light-emitting clock signal and a light-emitting stop signal from the timing controller 11 and generate a first light-emitting signal to be provided to the first light-emitting lines EMa1 to EMap. The first light-emitting driver 15EMa may sequentially provide light-emitting signals having pulses of a turn-off level to the first light-emitting lines EMa1 to EMap. For example, the first light-emitting driver 15EMa may be configured as a shift register and may generate the first light-emitting signal by sequentially transmitting a pulse-shaped light-emitting stop signal of a turn-off level to the next light-emitting stage according to control of the light-emitting clock signal. The second light-emitting driver 15EMBa may be configured substantially the same as the first light-emitting driver 15EMa, and therefore a duplicated description will be omitted.

[0135] The pixel section 14a includes pixels. Each pixel PXija may be connected to a corresponding data line DLaj, a scanning line GWai, GIai, GRai, and an emission line EMai, EMBai. Each pixel PXija may include a light-emitting element that emits light based on a received data voltage.

[0136] FIG. 18 is a diagram for explaining a pixel according to another embodiment of the present invention.

[0137] 18, a pixel PXija according to an embodiment of the present invention may include a pixel circuit PXCa and a light emitting element LDa. The pixel circuit PXCa may include transistors T1a, T2a, T3a, T4a, T5a, and T6a, a first capacitor Csta, and a second capacitor Cholda.

[0138] In the following, a circuit composed of N-type transistors will be described as an example. However, a person skilled in the art would be able to design a circuit composed of P-type transistors by changing the polarity of the voltage applied to the gate terminal. Similarly, a person skilled in the art would be able to design a circuit composed of a combination of P-type transistors and N-type transistors. A P-type transistor refers to a transistor in which the amount of current increases when the voltage difference between the gate electrode and the source electrode increases in the negative direction. An N-type transistor refers to a transistor in which the amount of current increases when the voltage difference between the gate electrode and the source electrode increases in the positive direction. The transistor may be configured in various forms such as a thin film transistor (TFT), a field effect transistor (FET), and a bipolar junction transistor (BJT).

[0139] In the following, the transistors T1a, T2a, T3a, T4a, T5a, and T6a are configured as N-type oxide thin film transistors. In other embodiments, the transistors T1a, T2a, T3a, T4a, T5a, and T6a may be P-type silicon thin film transistors. In other embodiments, some of the transistors T1a, T2a, T3a, T4a, T5a, and T6a may be N-type oxide thin film transistors, and the other parts may be P-type silicon thin film transistors.

[0140] The oxide thin film transistor may be a low temperature polycrystalline oxide (TPO) thin film transistor in which an active pattern (semiconductor layer) includes an oxide. However, the transistors shown here are merely examples, and the N-type transistor is not limited to the examples shown here. For example, the active pattern (semiconductor layer) included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polysilicon) or an organic semiconductor. The silicon thin film transistor may be a low temperature poly-silicon (LTPS) thin film transistor in which an active pattern (semiconductor layer) includes amorphous silicon, polysilicon, etc.

[0141] The first transistor T1a may have a first gate electrode connected to the first node N1a and a second gate electrode connected to the third node N3a. The second gate electrode of the first transistor T1a may be for adjusting the characteristics of the output current with respect to the input voltage of the first transistor T1a. For example, the first transistor T1a mainly operates in a saturation state. In this case, if the second gate electrode of the first transistor T1a does not exist, the magnitude of the output current may change according to the change in the drain-source voltage even though the gate-source voltage is the same. According to an embodiment of the present invention, the characteristics of the first transistor T1a are adjusted to be insensitive to the change in the drain-source voltage, so that the first transistor T1a can output substantially the same current for the same gate-source voltage. The first transistor T1a may control the amount of driving current flowing from the first power line ELVDDL to the second power line ELVSSL. Therefore, the first transistor T1a may be referred to as a driving transistor. The first electrode of the first transistor T1a may be connected to the second node N2a and the second electrode may be connected to the third node N3a.

[0142] The second transistor T2a may have a gate electrode connected to the first scan line GWai, a first electrode connected to the data line DLaj, and a second electrode connected to the first node N1a. The second transistor T2a may receive a data voltage applied to the data line DLaj. Therefore, the second transistor T2a may be referred to as a data write transistor.

[0143] The first scan driver 13GWa may provide a first scan signal having a turn-on level that determines when the pixel PXija receives a data voltage. For example, the second transistor T2a may be turned on upon receiving the first scan signal having a turn-on level, and the second transistor T2a may apply the data voltage applied to the data line DLaj to the first node N1a.

[0144] The third transistor T3a may have a gate electrode connected to the third scan line GRai, a first electrode receiving a reference voltage VREFa, and a second electrode connected to the first node N1a. The reference voltage VREFa may be supplied from a reference voltage source. The third transistor T3a may apply the reference voltage VREFa to the first node N1a to initialize the voltage of the first node N1a to the reference voltage VREFa. Therefore, the third transistor T3a may be referred to as a first initialization transistor.

[0145] The fourth transistor T4a may have a gate electrode connected to the second scan line GIai, a first electrode receiving an initialization voltage VAINTa, and a second electrode connected to a fourth node N4a. The initialization voltage VAINTa may be supplied from an initialization voltage source. The fourth transistor T4a may apply the initialization voltage VAINTa to the fourth node N4a to initialize the voltage of the fourth node N4a to the initialization voltage VAINTa. Therefore, the fourth transistor T4a may be referred to as a second initialization transistor.

[0146] The second scan driver 13GIa may provide a second scan signal of a turn-on level that determines the timing of initializing the anode voltage of the light emitting element LDa. For example, upon receiving the second scan signal of the turn-on level, the fourth transistor T4a is turned on and the initialization voltage VAINTa is applied to the anode of the light emitting element LDa, so that the anode voltage of the light emitting element LDa may be initialized to the initialization voltage VAINTa.

[0147] The fifth transistor T5a may have a gate electrode connected to the first light emitting line EMai, a first electrode receiving the first power supply voltage ELVDDa, and a second electrode connected to the second node N2a. The fifth transistor T5a can adjust the opening and closing of a driving current path connecting the first power supply voltage ELVDDa to the second power supply voltage ELVSSa. Therefore, the fifth transistor T5a can be called a first light emitting control transistor.

[0148] The sixth transistor T6a may have a gate electrode connected to the second light emission line EMBai, a first electrode connected to the third node N3a, and a second electrode connected to the fourth node N4a. The sixth transistor T6a can adjust the opening and closing of a driving current path connecting from the first power supply voltage ELVDDa to the second power supply voltage ELVSSa. Therefore, the sixth transistor T6a can be called a second light emission control transistor.

[0149] The first capacitor Csta may connect the first node N1a and the third node N3a. A first electrode of the second capacitor Cholda may receive the first power supply voltage ELVDDa and a second electrode may be connected to the third node N3a.

[0150] The light emitting element LDa has an anode connected to the fourth node N4a and a cathode receiving the second power supply voltage ELVSSa. The light emitting element LDa may be a light emitting diode. The light emitting element LDa may be an organic light emitting diode, an inorganic light emitting diode, a quantum dot / well light emitting diode, or the like. In one embodiment of the present invention, only one light emitting element LDa is provided in each pixel, but in other embodiments, each pixel may be provided with a plurality of light emitting elements. In this case, the plurality of light emitting elements may be connected in series, in parallel, in series-parallel, or the like. The light emitting element LDa of each pixel PXaij may emit light in one of a first color, a second color, and a third color.

[0151] FIG. 19 is a diagram for explaining an address scan period according to another embodiment of the present invention.

[0152] The address scan period in Figure 19 is an example of the address scan period AS in Figures 3a and 3b. In the following, a pixel row connected to the i-th scan lines GWai, GIai, GRai and the i-th emission lines EMai, EMBai will be described as a reference.

[0153] First, at time t1d, a first light-emitting signal having a turn-off level (e.g., a low level) may be applied to the first light-emitting line EMai, which turns off the fifth transistor T5a and ends the light-emitting period based on the data voltage written in the previous frame period.

[0154] Next, at time t2d, a second scan signal of a turn-on level (e.g., high level) is applied to the second scan line GIai, thereby turning on the fourth transistor T4a. As a result, the initialization voltage VAINTa can be applied to the fourth node N4a. Thus, the anode voltage of the light emitting element LDa can be initialized. At this time, since the sixth transistor T6a is in a turned-on state, the initialization voltage VAINTa can also be applied to the third node N3a. Thus, the voltage of the second electrode of the second capacitor Cholda can be initialized.

[0155] Next, at time t3d, a third scan signal having a turn-on level is applied to the third scan line GRai, thereby turning on the third transistor T3a, and applying the reference voltage VREFa to the first node N1a, thereby initializing the voltage across the first capacitor Csta.

[0156] Next, at time t4d, the second light-emitting signal having a turn-off level is applied to the second light-emitting line EMBai, thereby turning off the sixth transistor T6a, and thus electrically isolating the third node N3a and the fourth node N4a.

[0157] Next, at time t5d, the first light-emitting signal of the turn-on level is applied to the first light-emitting line EMai, so that the fifth transistor T5a can be turned on. As described above, the voltage across the first capacitor Csta is initialized, and at time t5d, the first capacitor Csta can be in a state in which the voltage difference between the gate electrode (first node N1a) and the source electrode (third node N3a) of the first transistor T1a is kept higher than the threshold voltage of the first transistor T1a. Therefore, at time t5d, the first transistor T1a can be in a turned-on state. At this time, a current is supplied from the first power supply voltage ELVDDa through the turned-on fifth transistor T5a and the first transistor T1a, so that the voltage of the third node N3a can gradually rise. When the voltage difference between the gate electrode (first node N1a) and the source electrode (third node N3a) of the first transistor T1a reaches the threshold voltage of the first transistor T1a, the first transistor T1a is turned off, and the voltage of the third node N3a can be maintained. This allows the first capacitor Csta to hold a voltage corresponding to the threshold voltage of the first transistor T1a. The period during which the first capacitor Csta holds a voltage corresponding to the threshold voltage of the first transistor T1a can be called a compensation period. At time t6d, the first light-emitting signal of the turn-off level is supplied to the first light-emitting line EMai, and the compensation period ends.

[0158] Next, at time t7d, the first scan signal having a turn-on level is applied to the first scan line GWai, thereby turning on the second transistor T2a. At this time, the data voltage is applied to the data line DLaj, and the data voltage is written to the first node N1a. The voltage of the third node N3a may vary depending on the capacitance ratio of the capacitors Csta and Cholda and the voltage of the third node N3a previously held during the compensation period.

[0159] Next, at time t8d, the second scan signal having a turn-on level is applied to the second scan line GIai, thereby turning on the fourth transistor T4a, and thus initializing the anode voltage of the light emitting element LDa to the initialization voltage VAINTa, which is effective for expressing low gradations such as black gradations.

[0160] Next, at time t9d, the second light-emitting signal of the turn-on level is applied to the second light-emitting line EMBai, so that the sixth transistor T6a can be turned on, thereby connecting the first transistor T1a to the anode of the light-emitting element LDa.

[0161] Next, at time t10d, the first light-emitting signal having a turn-on level is applied to the first light-emitting line EMai, thereby turning on the fifth transistor T5a, thereby generating a driving current path that connects the first power supply voltage ELVDDa, the fifth transistor T5a, the first transistor T1a, the sixth transistor T6a, and the second power supply voltage ELVSSa, and the light-emitting element LDa can emit light with a luminance that corresponds to the amount of driving current flowing along the driving current path.

[0162] FIG. 20 is a diagram for explaining a self-scan period according to another embodiment of the present invention.

[0163] The self-scan period of FIG. 20 is an example of the self-scan period SS of FIG. 3a and FIG. 3b. During the self-scan period of FIG. 20, the first emission line EMai, the second emission line EMBai, and the second scan line GIai may be applied with signals having the same waveforms as those of the address scan period of FIG. 19. The first scan line GWai and the third scan line GRai may be held with a scan signal of a turn-off level. As a result, the first node N1a is in a floating state, and the difference in voltage between both ends of the first capacitor Csta may be held. Therefore, the luminance of the light emitting element LDa after the self-scan period of FIG. 20 may be the same as the luminance of the light emitting element LDa after the immediately preceding address scan period.

[0164] 21 and 22 are diagrams illustrating a method of driving a display device according to still another embodiment of the present invention.

[0165] 21 and 22, each of the frame periods FRMP1, FRMP2, ... may include an active period and a blank period. For example, the first frame period FRMP1 may include an active period ACTP1 and a blank period BNKP1. The second frame period FRMP2 may include an active period ACTP2 and a blank period (not shown).

[0166] The active period ACTP1 or ACTP2 may be a period from when the pixel of the pixel unit 14a receives the first scan signal GWa1 of the initial turn-on level to when it receives the first scan signal GWap of the final turn-on level.

[0167] The first scan driver 13GWa may sequentially apply first scan signals of a turn-on level (e.g., high level) to the first scan lines GWa1 to GWap. For example, the first scan driver 13GWa may apply a first scan signal of a first turn-on level to the first scan line GWa1. For example, the first scan driver 13GWa may apply a first scan signal of a last turn-on level to the first scan line GWap. During the active period ACTP1 or ACTP2, the data driver 12a may apply data voltages to the data lines DLa1 to DLaq in pixel row units at timings corresponding to the first scan signals of the turn-on level.

[0168] The blank period BNKP1 may be a period from when the pixels of the pixel unit 14a receive the last first scan signal of the turn-on level to when they receive the first first scan signal of the turn-on level of the next frame period FRMP2. During the blank period BNKP1, the data driver 12a may not apply data voltages to the data lines DLa1 to DLaq. According to an embodiment of the present invention, during the blank period BNKP1, the data driver 12a may hold a reference voltage of a particular level on the data lines DLa1 to DLaq. According to an embodiment of the present invention, during the blank period BNKP1, the data driver 12a may not supply voltages to the data lines DLa1 to DLaq.

[0169] The second scan driver 13GBa may sequentially apply second scan signals of a turn-on level to the second scan lines GB1 to GBp. Here, each of the second scan signals of the turn-on level may include one or more pulses. For example, referring to FIG. 19, a first pulse of the second scan signal may occur at time t2d, and a second pulse of the second scan signal may occur at time t8d. In another embodiment, the first pulse of the second scan signal may not occur at time t2d and the second pulse of the second scan signal may not occur at time t8d as shown in FIG. 19. In this case, each of the second scan signals of the turn-on level includes one pulse. The waveform of the second scan signal in the self-scan period may be set to be the same as the waveform of the second scan signal in the address scan period (see FIG. 19 and FIG. 20).

[0170] Referring to the description of Figs. 3a to 5, one frame period FRMP1 in the embodiment shown in Figs. 21 and 22 may include one address scan period AS and one self-scan period SS for each pixel PXija. The address scan periods AS of pixels located in the same pixel row may be the same as each other. Similarly, the self-scan periods SS of pixels located in the same pixel row may be the same as each other. During the address scan period AS, each pixel may receive a first scan signal of a turn-on level and a second scan signal of a turn-on level. During the self-scan period SS, each pixel may receive a second scan signal of a turn-on level without receiving a first scan signal of a turn-on level.

[0171] The pixel unit 14a may sequentially include a first region AR1a, a second region AR2a, a third region AR3a, and a fourth region AR4a. It is assumed that the first pixel row of the first region AR1a is connected to the second scanning line GIa1, and the last pixel row of the first region AR1a is connected to the second scanning line GIa(1+r). r may be an integer greater than 0. It is assumed that one pixel row of the second region AR2a is connected to the second scanning line GIas, and another pixel row of the second region AR2a is connected to the second scanning line GIa(s+r). s may be an integer greater than 1+r. It is assumed that one pixel row of the third region AR3a is connected to the second scanning line GIat, and another pixel row of the third region AR3a is connected to the second scanning line GIa(t+r). t may be an integer greater than s+r. Assume that one pixel row of the fourth area AR4a is connected to the second scan line GIa(pr) and another pixel row of the fourth area AR4a is connected to the second scan line GIap, where pr may be an integer greater than t+r.

[0172] Here, it is assumed that a specific image pattern is input to the first region AR1a of the pixel unit 14a, and a monochromatic image pattern is input to the other regions AR2a, AR3a, and AR4a. With reference to the data voltages applied to the data lines DLa1 to DLaq, it can be seen that the data voltage corresponding to the first region AR1a is applied for a period t1e to t2e.

[0173] When the first frame period FRMP1 is defined as a period from time t1e to time t5e, time t3e may be the middle time of the first frame period FRMP1. That is, the period t1e to t3e may correspond to half of the first frame period FRMP1. Also, the period t3e to t5e may correspond to half of the first frame period FRMP1.

[0174] In the embodiment shown in FIG. 21, the length of the blank period BNKP1 may be less than half the length of the corresponding first frame period FRMP1. That is, the length of the active period ACTP1 may be greater than the blank period BNKP1. In this case, in the third area AR3a, the second scanning signal of the turn-on level applied to the second scanning lines GIat to GIa(t+r) is applied before time t2e. That is, the anode voltage of the light-emitting element LDa of the pixel connected to the second scanning lines GIat to GIa(t+r) is initialized to the initialization voltage VAINTa before time t2e.

[0175] Depending on the layout of the pixel circuit PXaij, the anode electrode of the light-emitting element LDa may form a parasitic capacitance with the adjacent data lines DLa1 to DLaq. Therefore, when the data voltage changes at time t2e, the anode voltage N4a_AR3a of the light-emitting element LDa in the third region AR3a may change according to the data voltage. On the other hand, the anode voltage of the light-emitting element LDa of the pixel in the fourth region AR4a may be initialized to the initialization voltage VAINTa after time t2e. As a result, the anode voltage N4a_AR4a of the light-emitting element LDa in the fourth region AR4a is not affected by the change in the data voltage at time t2e.

[0176] In the embodiment shown in FIG. 21, even though a monochromatic image pattern is input to the third area AR3a, a copy image pattern of a specific image pattern in the first area AR1a can be displayed.

[0177] Meanwhile, in the embodiment shown in FIG. 22, the length of the blank period BNKP1 may be more than half of the corresponding first frame period FRMP1. Referring to FIG. 22, an example is shown in which the length of the blank period BNKP1 is greater than half of the corresponding first frame period FRMP1. In another embodiment, as described above, the first pulse of the second scan signal may not occur at time t2d and the second pulse of the second scan signal may not occur at time t8d as shown in FIG. 19. In such an embodiment, the length of the blank period BNKP1 may be equal to half of the corresponding first frame period FRMP1. That is, the end time of the first scan signal at the turn-on level of the first scan line GWap may be time t3e.

[0178] In the embodiment shown in FIG. 22, the second scan signal of the turn-on level received by the pixels of the last pixel row (i.e., pixels connected to the first scan line GWap and the second scan line GIap) during the self-scan period may not overlap with the first scan signal of the turn-on level received by the pixels of the first pixel row (i.e., pixels connected to the first scan line GWa1 and the second scan line GIa1) during the address scan period. For example, the second scan signal of the turn-on level received by the pixels of the last pixel row (i.e., pixels connected to the first scan line GWa1 and the second scan line GIa1) during the self-scan period may end before time t1e. In this case, the first scan signal of the turn-on level received by the pixels of the first pixel row (i.e., pixels connected to the first scan line GWa1 and the second scan line GIa1) during the address scan period may be received after time t1e. Even if the data voltage rises at time t1e and falls at time t2e, the rising and falling edges cancel each other out, so that the copy image pattern as shown in FIG. 21 is not displayed in the third area AR3a.

[0179] FIG. 23 is a diagram illustrating a pixel according to still another embodiment of the present invention.

[0180] The pixel PXbij in Fig. 23 has a pixel circuit PXCb that is partially modified compared to the pixel PXaij in Fig. 18. Specifically, the fifth transistor T5b and the sixth transistor T6b are changed to P-type transistors.

[0181] In this case, the embodiments shown in FIGS. 17 to 22 can be similarly applied by reversing the polarity of the light emission signals applied to the first emission lines EMbi and the second emission lines EMBbi.

[0182] The drawings and detailed description of the invention referred to above are merely illustrative of the present invention, and are used only for the purpose of explaining the present invention, and are not intended to limit the meaning or the scope of the present invention described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the technical scope of the present invention should be determined by the appended claims. [Explanation of symbols]

[0183] 13GW 1st Scan Driver 13GB 2nd scan driver 14 Pixel section PXij pixel AS address scan period SS Self-scan period FRMP1, FRMP2 frame period ACTP1, ACTP2 active period

Claims

1. A pixel including a light-emitting element that emits light at a luminance based on a received data voltage; a first scan driver for providing a first scan signal having a turn-on level that determines a time point at which the pixel receives the data voltage; a second scan driver for providing a second scan signal having a turn-on level that determines a timing for initializing an anode voltage of the light emitting device; Each frame period includes an active period and a blank period, The active period is a period from when the pixel receives a first scan signal having an initial turn-on level to when the pixel receives a first scan signal having a last turn-on level, the blank period is a period from when the pixel receives the last first scan signal of the turn-on level to when the pixel receives the first first scan signal of the turn-on level in a frame period following a frame period including the blank period, The length of the blank period is equal to or longer than a cycle during which each of the pixels receives the second scanning signal of the turn-on level.

2. The display device of claim 1 , wherein the length of the blank period is an integer multiple of a period during which each of the pixels receives the second scanning signal of the turn-on level.

3. Each of the pixels receives the first scan signal of the turn-on level once during one frame period; Each of the pixels receives the second scan signal of the turn-on level N times during the one frame period; The display device according to claim 2 , wherein N is an integer greater than 3.

4. 4. The display device of claim 3, wherein the length of the blank period is (N-3) times the period during which each of the pixels receives the second scanning signal of the turn-on level.

5. said N being 4; The display device according to claim 4 , wherein the length of the blank period is equal to one period during which each of the pixels receives the second scanning signal of the turn-on level.

6. N is 5; The display device according to claim 4 , wherein the length of the blank period is twice the period during which each of the pixels receives the second scanning signal of the turn-on level.

7. 7. The display device of claim 1, wherein the number of pixels simultaneously receiving the second scanning signal of the turn-on level is kept the same during the frame period.

8. A pixel including a light-emitting element that emits light at a luminance based on a received data voltage; a first scan driver for providing a first scan signal having a turn-on level that determines a time point at which the pixel receives the data voltage; a second scan driver for providing a second scan signal having a turn-on level that determines a timing for initializing an anode voltage of the light emitting device; Each frame period includes an active period and a blank period, The active period is a period from when the pixel receives a first scan signal of a turn-on level to when the pixel receives a last first scan signal of a turn-on level, the blank period is a period from when the pixel receives the last first scan signal of the turn-on level to when the pixel receives the first first scan signal of the turn-on level in a frame period following a frame period including the blank period, A display device, wherein the length of the blank period is equal to or greater than half of the corresponding frame period.

9. each of the frame periods includes one address scan period and one self-scan period for each of the pixels; During the address scan period, each of the pixels receives a first scan signal of a turn-on level and a second scan signal of a turn-on level; The display device of claim 8 , wherein during the self-scan period, each of the pixels does not receive a first scanning signal of a turn-on level but receives a second scanning signal of a turn-on level.

10. 10. The display device of claim 9, wherein a second scan signal of a turn-on level received by pixels of a last pixel row among the pixels during the self-scan period does not overlap with a first scan signal of a turn-on level received by pixels of a first pixel row among the pixels during the address scan period.

Images