Quantum calculation device and controller

Abstract

To realize a larger filling rate than in an existing technique, in a technique of correcting a quantum errors by using cells aligned in a two-dimensional lattice grating.SOLUTION: In a quantum calculation device including a controller and a quantum processor, the quantum processor includes: a passage part; a scan storage part; and a computation region, the passage part, the scan storage part, and the computation region each having one or more cells. The controller includes an operation unit configured to move a computation target cell stored in the scan storage part to the computation region via the passage part and to perform computation in the computation region.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to quantum error correction in quantum computers. [Background technology]

[0002] Quantum computers are a technology that performs calculations by utilizing the principle of superposition in quantum mechanics. Quantum computers are expected to be able to solve important scientific problems, such as prime factorization and quantum chemistry calculations, faster than conventional computers, and their development is being actively pursued around the world. Because the superposition state of quantum bits is sensitive to environmental noise, naive calculations destroy the superposition state, making reliable calculations impossible.

[0003] To suppress noise, quantum error correction is an effective method, in which information for one quantum bit is encoded using multiple quantum bits in a certain region of multiple quantum bits spread on a two-dimensional plane, and the effective error rate is significantly reduced by error correction. The encoded quantum bit is called a logical quantum bit.

[0004] Currently, in typical quantum error correction, it is common to abstract the quantum bit area on a plane by dividing it into cells arranged in a two-dimensional lattice, with each cell being an area capable of encoding one quantum bit (Non-Patent Documents 1 to 4). In this case, cells in which data (information) is embedded are called data cells, and cells without embedded data are called free cells. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] Beverland, Michael, Vadym Kliuchnikov, and Eddie Schoute. "Surface code compilation via edge-disjoint paths." PRX Quantum 3.2 (2022): 020342. [Non-patent document 2] Chamberland, Christopher, and Earl T. Campbell. "Universal quantum computing with twist-free and temporally encoded lattice surgery." PRX Quantum 3.1 (2022): 010331. [Non-patent document 3] Beverland, Michael E., et al. "Assessing requirements to scale to practical quantum advantage." arXiv preprint arXiv:2211.07629 (2022). [Non-patent document 4] Lee, Joonho, et al. "Even more efficient quantum computations of chemistry through tensor hypercontraction." PRX Quantum 2.3 (2021): 030305. [Non-Patent Document 5] Litinski, Daniel. "A game of surface codes: Large-scale quantum computing with lattice surgery." Quantum 3 (2019): 128. Summary of the Invention [Problem to be solved by the invention]

[0006] In quantum error correction technology using cells arranged in a two-dimensional lattice, a certain number of empty cells must be allocated in order to perform operations on data cells. If the total number of cells is n and the number of data cells is m, m / n means the proportion of the computer's memory space that is effectively used to store data, and this value is called the filling factor. The conventional technologies disclosed in Non-Patent Documents 1 to 4 have the problem of a small filling factor.

[0007] The present invention has been made in consideration of the above points, and aims to provide a technology for achieving a filling factor greater than that of conventional technology in a technology for performing quantum error correction using cells arranged in a two-dimensional lattice. [Means for solving the problem]

[0008] According to the disclosed technology, there is provided a quantum computing device having a control device and a quantum processor, the quantum processor comprises a passageway, a scan storage unit, and an operation area, the passageway, the scan storage unit, and the operation area each having one or more cells; The control device an operation unit that moves the operation target cell stored in the scan storage unit to the operation area via the passage unit and performs the operation in the operation area; A quantum computing device is provided. [Effects of the Invention]

[0009] The disclosed technology provides a technology for achieving a filling factor greater than that of conventional technology in a technology for performing quantum error correction using cells arranged in a two-dimensional lattice. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 3 is a diagram illustrating an example of the configuration of a quantum computing device 300. [Figure 2] FIG. 2 is a diagram illustrating an example of a functional configuration of a control device 100. [Figure 3] FIG. 10 is a diagram showing a specific example of a cell layout. [Figure 4] FIG. 10 is a diagram showing typical rules for movement operations. [Figure 5] FIG. 10 is a diagram showing typical rules for movement operations. [Figure 6] FIG. 10 is a diagram showing typical rules for movement operations. [Figure 7]FIG. 10 is a diagram showing typical rules for movement operations. [Figure 8] FIG. 10 is a diagram showing typical rules for movement operations. [Figure 9] FIG. 10 is a diagram illustrating an example of an arrangement pattern. [Figure 10] FIG. 10 is a diagram illustrating an example of an arrangement pattern. [Figure 11] This is a diagram showing a Corridor 10, a Scan Storage 20, and a Compute Space 30. [Figure 12] FIG. 10 is a diagram illustrating an example of a block. [Figure 13] FIG. 1 is a diagram showing step 1 of the Point-Scan method. [Figure 14] FIG. 10 is a diagram showing step 2 of the Point-Scan method. [Figure 15] FIG. 10 is a diagram showing step 3 of the Point-Scan method. [Figure 16] FIG. 1 is a diagram illustrating step 1 of the Line-Scan method. [Figure 17] FIG. 10 is a diagram showing step 2 of the Line-Scan method. [Figure 18] 10 is a processing flow of the control device 100. [Figure 19] FIG. 2 is a diagram illustrating an example of a hardware configuration of a control device 100. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment of the present invention (the present embodiment) will be described with reference to the drawings. The embodiment described below is merely an example, and the embodiment to which the present invention is applied is not limited to the following embodiment.

[0012] (Device configuration example) 1 shows an example of the configuration of a quantum computing device 300 according to this embodiment. The "quantum computing device" may also be called a "quantum computer," a "quantum computer," or a "quantum computing system."

[0013] As shown in Fig. 1, quantum computing device 300 includes control device 100 and quantum processor 200. Control device 100 performs quantum computation by transmitting control signals and the like to quantum processor 200, operating and measuring quantum processor 200, and obtaining computation results (measurement results). Control device 100 can be realized by, for example, a classical computer. Hereinafter, "computer" means "classical computer."

[0014] The quantum processor 200 has a plurality of quantum bits as a physical quantum system. In this embodiment, for example, a two-level quantum bit or a bosonic quantum bit capable of performing continuous quantum computation can be used as the quantum system. For example, a superconducting circuit, an ion trap, a quantum dot, a microwave photon, or the like can be used as a physical system for realizing the quantum bit.

[0015] The multiple quantum bits in quantum processor 200 are basically laid out on a two-dimensional plane, divided into areas, and arranged in a two-dimensional lattice pattern to form multiple cells, similar to the prior art.

[0016] (Example of functional configuration of control device 100)

[0017] An example of the functional configuration of the control device 100 of this embodiment is shown in Fig. 2. As shown in Fig. 2, the control device 100 has a setting unit 110, an input unit 120, and an operation unit 130. The setting unit 110, for example, sets the initial quantum state in the quantum processor 200. The input unit 120 inputs information to be used for the operation (computation). The operation unit 130 performs the operation described below on the cells in the quantum processor 200.

[0018] It should be noted that the quantum bits in this embodiment are not limited to those using actual physical systems. For example, the quantum bits may be on a simulator realized by software. In this case, the quantum processor 200 functions as a quantum bit simulator. This simulator may be provided inside the control device 100. Furthermore, this simulator may be provided on the cloud.

[0019] (About operation) First, the basic operation of this embodiment will be explained. As mentioned above, currently, in typical quantum error correction, it is common to perform abstraction by dividing a quantum bit region on a plane into cells arranged in a two-dimensional lattice, with each cell being an area capable of encoding one quantum bit (Non-Patent Documents 1 to 4). Cells in which information is embedded are called data cells, and cells in which no information is embedded are called free cells.

[0020] A specific example of a layout of closely packed cells is shown in Fig. 3. In this embodiment, quantum processor 200 realizes such a cell layout.

[0021] Three types of operations can be performed on data cells that contain encoded logical quantum bit information: "single quantum bit operations," "multi-quantum lattice surgery operations," and "movement." An overview of these operations is provided below. These operations themselves are existing technologies and are described, for example, in Non-Patent Document 5.

[0022] It should be noted that the “operation” is a process that the operation unit 130 in the control device 100 performs on the quantum processor 200.

[0023] A "single quantum bit operation" can be performed by temporarily occupying free cells around the target data cell. This occupancy time is calculated in units called code beats, and the required time and the number of free cells to occupy vary depending on the operation.

[0024] A multi-qubit lattice surgery operation is an operation on multiple target data cells. This operation is performed by occupying one code beat of an empty cell that connects the target data cells on a two-dimensional plane.

[0025] "Move" is an operation that moves the quantum bit information embedded in a data cell to an empty cell at a different coordinate without performing any calculations. This operation occupies one code beat of the empty cell that connects the source cell to the destination cell. After the move is performed, the source cell has no embedded information. This move operation is used frequently in this embodiment.

[0026] (About movement operations) Typical rules for movement operations (movement examples) are shown in FIGS.

[0027] In the example shown in Figure 4, information in cell 1 is moved to cell 3. At this time, cell 2 is occupied for one code beat. It is possible to specify the movement route during the movement, and in the example of Figure 5, information in cell 1 is moved to cell 4 along the route shown in the figure.

[0028] In addition, when moving information, it is possible to move information from multiple cells at the same time. In the example of Figure 6, information A in cell 5 is moved to cell 6, and information B in cell 1 is moved to cell 3.

[0029] Figure 7 shows that the entire path for movement must be empty cells. In other words, in the example of Figure 7, because cell 2 is a data cell, information from cell 1 cannot be moved to cell 3 via cell 2. On the other hand, information from cell 1 can be moved to cell 3 by passing through an empty cell.

[0030] Figure 8 shows that an occupied cell for a move can only be used in one path at most. In other words, when performing an operation to move information A from cell 5 to cell 8 and an operation to move information B from cell 1 to cell 3, cell 2 cannot be included in both paths. The above two operations can be performed only if there is no overlap between the two paths.

[0031] As described above, both single-qubit and multi-qubit operations require free cells around the target data cell in order to perform the operation. Therefore, to perform an operation in quantum computing device 300, a certain number of free cells must be allocated in quantum processor 200.

[0032] (About the assignment) Here, we will explain the problem in more detail. As mentioned above, if the total number of cells is n and the number of data cells is m, then m / n means the percentage of the computer's memory space that is effectively used to store data. This value is called the filling rate. Since the number of data cells required is determined by the program to be executed, the higher the filling rate, the more likely it is that a large-scale program can be executed on a smaller quantum computing device.

[0033] In conventional technology, various logical quantum bit arrangement patterns have been considered. For example, the filling rate of logical quantum bits in the technology disclosed in Non-Patent Document 1 is 1 / 4. In Non-Patent Document 2, it is 4 / 9. In Non-Patent Document 3, it is 1 / 2. In Non-Patent Document 4, a filling rate of 2 / 3 is achieved by assuming that some lattice surgery operations are not performed.

[0034] However, all of the conventional technologies have only achieved a filling rate of a constant less than 1. Examples of these layout patterns are shown in Figures 9 and 10. For this reason, in the conventional technologies, it was unavoidable that a constant multiple of the amount of data actually required to execute an operation was required as surplus space.

[0035] As mentioned above, conventional quantum computing based on quantum error correction requires a constant multiple of the number of data cells required, which poses the problem that a desired program cannot be executed unless a large quantum computer is created.

[0036] In this embodiment, a technique is proposed to achieve a filling rate greater than that of the conventional technique and to solve the above-mentioned problems.

[0037] (Outline of the embodiment) In this embodiment, the scan method will be described. The scan method is a data cell arrangement and access method for performing quantum computing with a filling factor close to 1, which is higher than the filling factor in conventional techniques.

[0038] The technique according to this embodiment allows for a filling rate that asymptotically converges to 1 as the number of data cells m increases. However, this comes at the cost of requiring multiple steps to access a data cell. Long access times result in overhead in the computation time, but the trade-off between filling rate and access speed can be adjusted depending on the amount of overhead that can be tolerated.

[0039] Hereinafter, an example will be described as a detailed example of the technology according to the present embodiment. In the following description, for the sake of convenience, the expression "moving a cell in one area to another area" may be used to mean that data (which may also be called information) of a cell in a certain area is moved to a cell in another area.

[0040] (Example) In this embodiment, the multiple quantum bits in the quantum processor 200 are basically laid out on a two-dimensional plane, divided into areas, and form multiple cells arranged in a two-dimensional lattice, similar to conventional methods.

[0041] More specifically, in this embodiment, the quantum processor 200 (a device composed of "a plurality of cells arranged in a two-dimensional lattice") has three elements: Corridor 10, Scan Storage 20, and Compute Space 30. The relative arrangement of these elements is shown in FIG. 11. Corridor 10, Scan Storage 20, and Compute Space 30 may be referred to as passage section 10, scan storage section 20, and computing area 30, respectively.

[0042] In the example shown in FIG. 11, Corridor 10, six Scan Storages 20, and Compute Space 30 are provided.

[0043] The Scan Storage 20 is filled with data qubits. The Scan Storage 20 has a function to take out the data of the cells of the specified data qubits to Corridor 10 in a certain time by movement.

[0044] Corridor 10 is a set of empty cells for exchanging data taken out from Scan Storage 20 with Compute Space 30. Compute Space 30 is a set of empty cells of a constant size and is a space for performing operations using the cells moved here.

[0045] <Implementation method of Scan Storage 20> In this embodiment, as the implementation method of Scan Storage 20, either the Point-Scan method or the Line-Scan method can be used. In the quantum computing device 300, either one of the Point-Scan method and the Line-Scan method may be used, or both the Point-Scan method and the Line-Scan method may be used. Each method will be described below.

[0046] <Point-Scan method> In the Point-Scan method, all the required quantum bits are divided into blocks of k integers greater than or equal to 1. At this time, integers h and w are determined so that w×h-1≧n / k, and blocks are constructed by adding one or more blank cells to n / k data cells arranged in a shape of h×w.

[0047] FIG. 12(a) shows an example of a block in the Point-Scan method when h×w=5×5, n / k=24, and there is one blank cell.

[0048] In the Point-Scan arrangement, when the coordinates of a specified logical quantum bit are input, the logical quantum bit at the specified coordinates can be brought into the calculation area by the following procedure. The following procedure is executed by the operation unit 130 in the control device 100.

[0049] Step 1: The process of step 1 is called "Seek." The operation unit 130 first calculates the block in the quantum processor 200 that includes a cell that holds the specified logical quantum bit. If this cell is in contact with the corridor 10 from the beginning, the process moves to step 3. The blank cells in this block are set as scan cells.

[0050] An example of processing in step 1 after the above blocks are calculated is shown in Fig. 13. In Fig. 13 (and Figs. 14 to 18), processing progresses over time from left to right on the drawing. Note that in Figs. 15 and 17, for convenience of illustration, the processing is shown in two rows, one above the other.

[0051] As shown in Fig. 13, in this example, the scan cells are initially placed in the column adjacent to Corridor 10 in the center row. The cell containing the data to be moved (hereinafter referred to as the target cell) is the cell surrounded by a thick frame. As shown in Fig. 13, the operation unit 130 moves the scan cells one square at a time until they reach a position adjacent to the target cell.

[0052] Note that, as shown in FIG. 13, moving the scan cancel to a certain cell is equivalent to moving the data of the said cell to the scan cancel before the movement.

[0053] Step 2: The process of Step 2 is called Pick. As shown in FIG. 14, the operation unit 130 moves an empty cell (scan cancel) one grid at a time to bring the target cell closer to Corridor10. The operation unit 130 repeats this operation until the target cell can be directly taken out to Corridor10.

[0054] Step 3: The processes of Step 3 are called Load and Store. As shown in FIG. 15(a), first, the operation unit 130 moves the target cell to Compute Space30 via an empty cell. In (b) and (c), the operation unit 130 performs operations using the target cell in Compute Space30. During this period, as shown in (b), the operation unit 130 returns the positions of the scan cancel and the target cell from which data has been retrieved (= blank cell) to the central row. As shown in (c) and (d), after processing the operations on the target cell, the operation unit 130 returns the target cell to the central column.

[0055] <Line-Scan method> Next, the Line-Scan method will be described. In the Line-Scan method, the entire set of necessary qubits is divided into one or more integer k blocks. The number of cells for holding data in each block is n / k. Here, integers w and h are determined such that w×(h - 1)≧n / k, and the blocks are arranged in a shape where one blank row is placed in a w×h section.

[0056] FIG. 12(b) shows an example of blocks when w×h = 5×5, n / k = 20, and there are 5 blank cells.

[0057] In the Line-Scan arrangement, when the coordinates of a specified logical quantum bit are input, the logical quantum bit at the specified coordinates can be brought into the calculation domain by the following procedure. The following procedure is executed by the operation unit 130 in the control device 100.

[0058] Step 1: The process in step 1 is called "Seek." The operation unit 130 calculates the block that contains the cell that holds the specified logical quantum bit. The row of blank cells in this block is set as the scan row.

[0059] An example of processing in step 1 after the above blocks are calculated is shown in Figure 16. As shown in Figure 16, in this example, the scan row is located in the center row. The target cell having the data to be moved is the cell surrounded by a thick frame. As shown in Figure 16, the operation unit 130 moves the scan row until it becomes a row adjacent to the target cell.

[0060] Step 2: The processing in step 2 is called Load and Store. As shown in FIG. 17(a), the operation unit 13 moves the target cell to the Compute Space 30 by using the scan row and the Corridor 10. In (b) and (c), a calculation is performed in the Compute Space 30 using the target cell. During this time, as shown in (b), the operation unit 130 returns the scan row and the position of the blank cell created by removing the target cell to the center row. As shown in (c) and (d), after processing the calculation on the target cell, the operation unit 130 returns the target cell to the center column.

[0061] <Processing flow> A flowchart common to the two methods described above is shown in Fig. 18. The processing procedure of the quantum computing device 300 (particularly the control device 100) will be described with reference to Fig. 18.

[0062] In S101, the input unit 120 inputs to the control device 100 an operation command and a list of cells to be operated on.

[0063] In S102, the operation unit 130 seeks addresses of calculation targets that have not been loaded in order. Examples of seeking are as shown in Figures 13 and 16. When the Point-Scan method is used, the operation unit 130 also performs Picking (e.g., Figure 14).

[0064] In S103, the operation unit 130 loads the cell to be operated on into the Computation Space 30. Examples of loading are as shown in FIGS.

[0065] The processes of S102 and S103 are performed for each cell to be calculated. When all the cells to be calculated have been loaded (Yes in S104), the process proceeds to S105.

[0066] In S105, the operation unit 130 performs a calculation corresponding to the calculation command in the Computation Space 30.

[0067] In S106, the operation unit 130 stores the loaded cell. Storing means returning the cell to the Scan Storage 20. Examples of storing are as shown in FIGS.

[0068] <Features of the storage system according to this embodiment> Both of the above storage methods can be designed so that the filling rate asymptotically approaches 1 as n increases by setting appropriate values for w, h, and k relative to n. For example, this can be achieved by setting w=h and k to an appropriate constant. In practice, the parameters w, h, and k are optimized to satisfy the required access frequency and filling rate. This allows a higher filling rate to be achieved than when movement is not assumed in access, at the expense of access efficiency.

[0069] (Example of hardware configuration) The control device 100 described in this embodiment can be realized, for example, by causing a computer to execute a program. This computer may be a physical computer or a virtual machine on the cloud.

[0070] That is, the control device 100 can be realized by using hardware resources such as a CPU and memory built into a computer to execute a program corresponding to the processing performed by the control device 100. The program can be recorded on a computer-readable recording medium (such as a portable memory) and can be saved or distributed. The program can also be provided via a network such as the Internet or email.

[0071] Fig. 19 is a diagram showing an example of the hardware configuration of the computer. The computer in Fig. 19 includes a drive device 1000, an auxiliary storage device 1002, a memory device 1003, a CPU 1004, an interface device 1005, a display device 1006, an input device 1007, an output device 1008, and the like, all of which are interconnected by a bus BS. The computer may further include a GPU.

[0072] A program for realizing processing on the computer is provided by a recording medium 1001 such as a CD-ROM or a memory card. When the recording medium 1001 storing the program is set in the drive device 1000, the program is installed from the recording medium 1001 to the auxiliary storage device 1002 via the drive device 1000. However, the program does not necessarily have to be installed from the recording medium 1001, but may be downloaded from another computer via a network. The auxiliary storage device 1002 stores the installed program as well as necessary files, data, etc.

[0073] The memory device 1003 reads and stores the program from the auxiliary storage device 1002 when an instruction to start the program is received. The CPU 1004 realizes functions related to the control device 100 in accordance with the program stored in the memory device 1003. The interface device 1005 is used as an interface for connecting to the quantum processor 200, etc. The display device 1006 displays a GUI (Graphical User Interface) or the like according to the program. The input device 1007 is composed of a keyboard, mouse, buttons, a touch panel, etc., and is used to input various operation instructions. The output device 1008 outputs the calculation results.

[0074] (Effects of the embodiment) As described above, the technology described in this embodiment makes it possible to achieve a filling factor greater than that of conventional technology in a technology for performing quantum error correction using cells arranged in a two-dimensional lattice pattern.

[0075] The following additional notes are provided regarding the above-described embodiments.

[0076] <Additional Notes> (Additional note 1) 1. A quantum computing device having a controller and a quantum processor, the quantum processor comprises a passageway, a scan storage unit, and an operation area, the passageway, the scan storage unit, and the operation area each having one or more cells; The control device an operation unit that moves the operation target cell stored in the scan storage unit to the operation area via the passage unit and performs the operation in the operation area; Quantum computing device. (Additional note 2) the scan storage unit has a plurality of data cells and one or more blank cells; The operation unit moves the one or more blank cells in the scan storage unit so that the blank cells are adjacent to the operation target cell, and then moves the operation target cell to the operation area via the one or more blank cells and the passage unit. Item 1. The quantum computing device according to item 1. (Additional note 3) The operation unit returns the operation target cell to the scan storage unit after performing the operation in the operation area. Item 1. The quantum computing device according to item 1. (Additional note 4) The control device in the quantum computing device according to any one of appendixes 1 to 3.

[0077] Although the present embodiment has been described above, the present invention is not limited to such a specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0078] 100 control device 110 Setting section 120 Input section 130 Operation section 200 quantum processors 300 Quantum computing device 1000 Drive Device 1001 Recording media 1002 Auxiliary storage device 1003 Memory device 1004 CPU 1005 Interface device 1006 Display device 1007 Input Device 1008 Output Device

Claims

1. 1. A quantum computing device having a controller and a quantum processor, the quantum processor comprises a passageway, a scan storage unit, and an operation area, the passageway, the scan storage unit, and the operation area each having one or more cells; The control device an operation unit that moves the operation target cell stored in the scan storage unit to the operation area via the passage unit and performs an operation in the operation area; Quantum computing device.

2. the scan storage unit has a plurality of data cells and one or more blank cells; The operation unit moves the one or more blank cells in the scan storage unit so that the blank cells are adjacent to the operation target cell, and then moves the operation target cell to the operation area via the one or more blank cells and the passage unit. The quantum computing device of claim 1 .

3. The operation unit returns the operation target cell to the scan storage unit after performing the operation in the operation area. The quantum computing device of claim 1 .

4. The control device in the quantum computing device according to claim 1 .

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