Display driver and display device

Abstract

To provide a display driver and a display device capable of outputting a plurality of pixel driving signals at output timings that follow a quadratic curve-like delay characteristic, without display unevenness or noise.SOLUTION: A delay control circuit 43 that generates output timing signals for outputting pixel driving signals at respective different delay times comprises: first to s-th delay timing signal generation circuits 431 for generating first to k-th delay timing signals in which delay times increase toward first (k-th) to k-th (first) output channels; a control signal generation circuit 430 for supplying a start pulse signal that starts generation of the first to k-th delay timing signals to the first to s-th delay timing signal generation circuits; and a delay signal selection circuit 432 that, for each output channel, selects the earliest delay timing signal from among s delay timing signals with respect to first to s-th delay timing signal groups each consisting of the first to k-th delay timing signals, and sets the selected delay timing signals as first to k-th output timing signals.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a display driver that drives a display panel in response to a video signal, and to a display device that includes the display panel and the display driver. [Background technology]

[0002] A display panel, such as a liquid crystal display panel, that displays an image based on a video signal has a plurality of gate lines extending horizontally on a two-dimensional screen and a plurality of source lines extending vertically, arranged to intersect with each other. Furthermore, display cells, which serve as pixels, are formed at the intersections of each gate line and source line. The display panel is also connected to a source driver that applies a drive voltage, the voltage value of which corresponds to the luminance level of each pixel indicated by an input video signal, to each source line, and a gate driver that applies a gate signal to each gate line to select the gate line.

[0003] In response to the recent trend toward larger and higher-resolution display panels, a display device has been proposed in which the source driver is divided into multiple IC chips, the divided source driver group is arranged on one end side of each source line of the display panel, and gate drivers are arranged on one end side and the other end side of each gate line (see, for example, Patent Document 1).

[0004] As the number of source lines increases with the increase in resolution of display panels, the amount of current that flows simultaneously into the source lines when a drive voltage is applied increases accordingly, causing a problem of noise due to the sudden increase in the amount of current.

[0005] Furthermore, as display panels become larger, the length of gate lines increases, and the wiring resistance associated with this line length dulls the waveform of the gate signal. The degree of waveform dullness varies depending on the position of the display cell within the screen of the display panel. That is, the waveform dullness of the gate signal reaching the display cell formed in the center of the screen is greater than that reaching the display cell formed at both ends of the screen. As a result, the delay time between when the gate signal is output from the gate driver and when it reaches the display cell is longer in the center of the screen than at the edges of the screen.

[0006] Therefore, in the source driver described in Patent Document 1, in order to suppress a timing discrepancy between the drive voltage output from the source driver and the gate signal output from the gate driver, the output timing of the drive voltage applied to the source lines formed in the center of the screen is delayed more than the left and right ends of the screen. In other words, in Patent Document 1, the output timing is controlled so that the drive voltage is applied to each source line according to delay characteristics that increase the delay time from the both ends of the screen toward the center of the screen. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2022-40752 Summary of the Invention [Problem to be solved by the invention]

[0008] Incidentally, in order to precisely match the timing between the gate signal output from the gate driver and the drive voltage output from the source driver regardless of the position of the display cell within the screen, it is desirable for the delay characteristic to be a quadratic curve, i.e., one in which the rate of increase in delay time decreases from both the left and right ends of the screen toward the center of the screen.

[0009] However, with the source driver described in Patent Document 1, it is difficult to obtain output timing that follows such a quadratic curve-like delay characteristic.

[0010] Furthermore, in the source driver described in Patent Document 1, when the source driver is divided into multiple drivers each consisting of an independent IC chip, it is difficult to match the output timing of the drive voltage at the boundary between adjacent drivers, i.e., the output timing of the drive voltage at the end point of one driver, with the output timing of the drive voltage at the start point of the other driver. As a result, there is a possibility that the output timing of each drive voltage output from both drivers will be significantly different at the boundary between adjacent drivers, resulting in the risk of display unevenness.

[0011] Therefore, the present invention aims to provide a display driver and a display device that can output multiple pixel drive signals to a display panel at output timings that follow a quadratic curve-shaped delay characteristic in which the rate of increase in delay time decreases from the edges of the screen to the center, without causing display unevenness. [Means for solving the problem]

[0012] A display driver according to the present invention is a display driver having first to k-th output channels that output first to k-th (k is an integer of 2 or more) pixel drive signals respectively corresponding to pixels shown in a video signal, the display driver comprising: a delay control circuit that sequentially supplies first to k-th output timing signals corresponding to the first to k-th output channels, causing the first to k-th pixel drive signals to be output at timings after different delay times, and an output section that outputs the first to k-th pixel drive signals at output timings according to the supply timings of the first to k-th output timing signals, the delay control circuit comprising first to s-th (s is an integer of 2 or more) delay timing signal groups that generate first to s-th (s is an integer of 2 or more) delay timing signal groups that respectively correspond to the first to k-th output channels and that provide output timings in which the delay time increases for each output channel from the first output channel to the kth output channel or from the kth output channel to the first output channel, and in which the intervals between the output timings provided by the first to k-th delay timing signals are different from each other; a control signal generating circuit that individually supplies a start pulse signal indicating the timing for starting sequential generation of the 1st to kth delay timing signals to each of the 1st to sth delay timing signal generating circuits; and a delay signal selecting circuit that receives the 1st to sth delay timing signals generated by the 1st to sth delay timing signal generating circuits, selects, for each of the 1st to kth output channels, a delay timing signal with the earliest output timing from among the s delay timing signals corresponding to that output channel, and supplies the k delay timing signals selected for each of the 1st to kth output channels to the output section as the 1st to kth output timing signals.

[0013] Further, a display driver according to the present invention is a display driver including first to wth (w is an integer of 2 or more) drivers having first to kth output channels that output first to kth (k is an integer of 2 or more) pixel drive signals respectively corresponding to pixels shown in a video signal, and each of the first to wth drivers has a delay control circuit that sequentially supplies first to kth output timing signals corresponding to the first to kth output channels, causing the first to kth pixel drive signals to be output at timings with different delay times, and an output section that outputs the first to kth pixel drive signals at output timings according to the supply timings of the first to kth output timing signals, and the delay control circuits each provide the output timings corresponding to the first to kth output channels, and the delay time increases for each of the output channels from the first output channel to the kth output channel or from the kth output channel to the first output channel. The delay timing signal generating circuit includes: 1st to sth delay timing signal generating circuits that generate 1st to sth (s is an integer of 2 or more) delay timing signal groups that are made up of 1st to kth delay timing signals and in which the intervals between the output timings brought about by the 1st to kth delay timing signals are different from one another; a control signal generating circuit that supplies a start pulse signal that indicates the timing to start sequentially generating the 1st to kth delay timing signals to each of the 1st to sth delay timing signal generating circuits; and a delay signal selecting circuit that receives the 1st to sth delay timing signals generated by the 1st to sth delay timing signal generating circuits, selects, for each of the 1st to kth output channels, a delay timing signal with the earliest output timing from among the s delay timing signals corresponding to that output channel, and supplies the k delay timing signals selected for each of the 1st to kth output channels to the output section as the 1st to kth output timing signals.

[0014] A display device according to the present invention includes a display panel having a plurality of data lines and a plurality of gate lines arranged to intersect the plurality of data lines, and first to wth (w is an integer of 2 or more) drivers having first to kth output channels, each of which outputs first to kth (k is an integer of 2 or more) pixel drive signals corresponding to each pixel represented by a video signal to each of the data lines of the display panel, wherein each of the first to wth drivers has a delay control circuit which sequentially supplies first to kth output timing signals corresponding to the first to kth output channels, causing the first to kth pixel drive signals to be output at timings after respectively different delay times, and an output section which outputs the first to kth pixel drive signals at output timings according to the supply timings of the first to kth output timing signals, and the delay control circuit controls the delay control circuit to sequentially supply first to kth output timing signals corresponding to the first to kth output channels, each of which corresponds to the first to kth output channels, and the delay timing signal generating circuit for generating 1st to sth (s is an integer of 2 or more) delay timing signal groups, each consisting of 1st to kth delay timing signals that provide the output timing with an increasing delay time for each channel, and in which the intervals between the output timings provided by the 1st to kth delay timing signals are different from one another; a control signal generating circuit for individually supplying a start pulse signal, which indicates the timing at which to start sequentially generating the 1st to kth delay timing signals, to each of the 1st to sth delay timing signal generating circuits; and a delay signal selecting circuit for receiving the 1st to sth delay timing signals generated by the 1st to sth delay timing signal generating circuits, and for selecting, for each of the 1st to kth output channels, a delay timing signal with the earliest output timing from among the s delay timing signals corresponding to that output channel, and for supplying the k delay timing signals selected for each of the 1st to kth output channels to the output section as the 1st to kth output timing signals. [Effects of the Invention]

[0015] A display driver according to the present invention generates first to k-th output timing signals for outputting first to k-th pixel drive signals at timings with different delay times, respectively, as follows: First, s (s is an integer equal to or greater than 2) sets of delay timing signals are generated, each set consisting of first to k-th delay timing signals indicating output timings with increasing delay times toward the first (k-th) to k-th (first) output channels. Then, for the first to s-th delay timing signal sets each consisting of the above-mentioned first to k-th delay timing signals, a delay timing signal with the earliest output timing is selected from the s delay timing signals for each of the first to k-th output channels, and the selected k delay timing signals are set as the above-mentioned first to k-th output timing signals.

[0016] In this case, by changing the increase rate of the delay time due to the first to k-th delay timing signals and the generation start timing of the first to k-th delay timing signals in each of the s delay timing signal groups, it is possible to obtain the first to k-th output timing signals having a delay characteristic that resembles a quadratic curve. Furthermore, with this configuration, by determining a desired delay time as the delay time at the end (k-th) output channel of the first to k-th output timing signals, it is possible to calculate the delay time at the start (first) output channel of the display driver from the desired delay time. This makes it possible to easily synchronize the output timing of pixel drive signals at the boundaries between adjacent drivers when multiple drivers output pixel drive signals to multiple data lines of the display panel at output timings that follow the quadratic curve delay characteristic.

[0017] Therefore, according to the present invention, it is possible to output multiple pixel drive signals to a display panel at output timings that follow a quadratic curve-like delay characteristic in which the rate of increase in delay time decreases from the edge of the screen to the center, without causing display unevenness due to discrepancies in output timing at the boundaries between drivers. [Brief explanation of the drawings]

[0018] [Figure 1]1 is a block diagram showing a schematic configuration of a display device 100 including a display driver according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing the internal configuration of a driver 4a. [Figure 3] 4 is a block diagram showing the internal configuration of a delay control circuit 43. FIG. [Figure 4] 4 is a time chart showing the forms of clock signals CK1 to CK4. [Figure 5] FIG. 10 is a circuit diagram showing the internal configuration of a delay timing signal generating circuit 431_1. [Figure 6] FIG. 2 is a diagram showing delay forms of delayed signals d1 to dk. [Figure 7] FIG. 2 is a circuit diagram showing the configuration of a delay direction control circuit DCC. [Figure 8] FIG. 10 is a diagram showing delay characteristics of delay timing signals t1_1 to tk_1, t1_2 to tk_2, t1_3 to tk_3, and t1_s to tk_s when delayed in the positive direction. [Figure 9] 10 is a circuit diagram showing an example of the configuration of a delayed signal selection circuit 432. FIG. [Figure 10A] FIG. 10 is a diagram showing delay characteristics of each of delay timing signals t1_1 to tk_1 and t1_2 to tk_2, taking the case of s=2 and forward delay as an example. [Figure 10B] FIG. 10 is a diagram showing delay characteristics of output timing signals T1 to Tk generated by delayed timing signals t1_1 to tj_1 and t(j+1)_2 to tk_2, taking the case of s=2 and forward delay as an example. [Figure 11A] FIG. 10 is a diagram showing delay characteristics of each of delay timing signals t1_1 to tk_1, t1_2 to tk_2, and t1_3 to tk_3, taking the case of s=3 and forward delay as an example. [Figure 11B] FIG. 10 is a diagram showing delay characteristics of output timing signals T1 to Tk generated by delayed timing signals t1_1 to tp_1, t(p+1)_2 to tq_2, and t(q+1)_2 to tk_3, taking the case of s=3 and forward delay as an example. [Figure 12]10 is a diagram showing an example of delay characteristics of output timing signals T1 to Tk generated by drivers 4a to 4d. FIG. [Figure 13] FIG. 10 is a block diagram showing a schematic configuration of a display device 100A including a display driver according to a second embodiment of the present invention. [Figure 14] FIG. 4 is a block diagram showing the internal configuration of a delay control circuit 43A. [Figure 15] 10 is a flowchart showing the procedure of a delay timing adjustment process performed by a control signal generation circuit 430A. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0020] FIG. 1 is a diagram showing a schematic configuration of a display device 100 including a display driver according to the present invention.

[0021] As shown in Fig. 1, the display device 100 includes a drive control unit 20, gate drivers 30A and 30B, a source driver 40, and a display panel 10. The source driver 40 is composed of a plurality of semiconductor IC (Integrated Circuit) chips, each having the same configuration. For example, in the embodiment shown in Fig. 1, the source driver 40 is composed of drivers 4a to 4d, each of which is composed of an independent IC chip, arranged side by side on a substrate. Each driver has k (k is an integer greater than or equal to 2) output channels, obtained by dividing the n (n is a natural number greater than or equal to 2) output channels of the source driver 40 into four.

[0022] The display panel 10 is made of, for example, a liquid crystal or organic EL panel. The display panel 10 includes m (m is an integer of 2 or more) gate lines g1 to gm, each extending in the horizontal direction of the two-dimensional screen, and n data lines D1 to Dn, each extending in the vertical direction of the two-dimensional screen. Display cells, which serve as pixels, are formed at each intersection of the gate lines and the data lines.

[0023] The drive control unit 20 receives a video signal, detects a horizontal sync signal and a vertical sync signal from the video signal, and supplies the horizontal sync signal to the gate drivers 30A and 30B.

[0024] Based on this video signal, the drive control unit 20 generates a series of pixel data PD, which represents the luminance level of each pixel in, for example, 8 bits. Furthermore, the drive control unit 20 generates load signals LDa-LDd, each of which has a single pulse appearing at a different timing, in response to the horizontal synchronization signal. The load signals LDa-LDd are signals that individually instruct each of the drivers 4a-4d to acquire pixel data.

[0025] The drive control unit 20 then supplies the source driver 40 with a video data signal DVS including the above-mentioned sequence of pixel data PD, the reference clock signal CLK, and the load signals LDa to LDd.

[0026] The gate driver 30A is connected to one end of each of the gate lines g1 to gm, and the gate driver 30B is connected to the other end of each of the gate lines g1 to gm. The gate drivers 30A and 30B generate gate pulses in synchronization with a horizontal synchronization signal and apply these pulses sequentially to each of the gate lines g1 to gm of the display panel 10.

[0027] The source driver 40 receives the above-mentioned video data signal DVS, and extracts from the video data signal DVS a sequence of pixel data PD, a reference clock signal CLK, and load signals LDa to LDd.

[0028] Next, the source driver 40 takes in n pieces of pixel data PD from the series of pixel data PD in response to the load signals LDa to LDd.

[0029] The source driver 40 converts the n pieces of pixel data PD into n voltages having voltage values ​​corresponding to the respective brightness levels at different timings starting from the reference clock signal CLK. The source driver 40 then generates pixel drive signals G1 to Gn representing the n converted voltages, respectively, and outputs them to the data lines D1 to Dn of the display panel 10.

[0030] Specifically, driver 4a constituting source driver 40 takes in k pieces of pixel data PD from the sequence of pixel data PD in response to load signal LDa and converts each piece into k voltages at different timings starting from reference clock signal CLK. Driver 4a then generates pixel drive signals G1 to Gk representing the k converted voltages and outputs them to data lines D1 to Dk of display panel 10. Driver 4b takes in k pieces of pixel data PD from the sequence of pixel data PD in response to load signal LDb and converts each piece into k voltages at different timings starting from reference clock signal CLK. Driver 4b then generates pixel drive signals G(k+1) to Gr (r is 2·k) representing the k converted voltages and outputs them to data lines D(k+1) to Dr of display panel 10.

[0031] In response to the load signal LDc, the driver 4c takes in k pieces of pixel data PD from the sequence of pixel data PD and converts each piece into k voltages at different timings starting from the reference clock signal CLK. The driver 4c then generates pixel drive signals G(r+1) to Gy (y is 3·k) representing the k converted voltages and outputs them to the data lines D(r+1) to Dy of the display panel 10. The driver 4d takes in k pieces of pixel data PD from the sequence of pixel data PD in response to the load signal LDd and converts each piece into k voltages at different timings starting from the reference clock signal CLK. The driver 4d then generates pixel drive signals G(y+1) to Gn representing the k converted voltages and outputs them to the data lines D(y+1) to Dn of the display panel 10.

[0032] The drivers 4a to 4d have the same internal configuration.

[0033] FIG. 2 is a block diagram showing the internal configuration of each of the drivers 4a to 4d, with the driver 4a being selected.

[0034] As shown in FIG. 2, the driver 4a includes a receiving unit 400, a shift register 41, a first data latch unit 42, a delay control circuit 43, a second data latch unit 44, a level shift unit 45, a DA (digital to analog) conversion unit 46, and an output amplifier unit 47.

[0035] The receiving unit 400 receives the video data signal DVS and extracts a sequence of pixel data PD and a reference clock signal CLK from the video data signal DVS. Furthermore, the receiving unit 400 of the driver 4a extracts a load signal LDa from the video data signal DVS. The receiving unit 400 of the driver 4b extracts a load signal LDb from the video data signal DVS, the receiving unit 400 of the driver 4c extracts a load signal LDc, and the receiving unit 400 of the driver 4d extracts a load signal LDd.

[0036] The receiving unit 400 supplies the extracted reference clock signal CLK to the shift register 41 and the delay control circuit 43. Furthermore, in response to the extracted load signal LDa, the receiving unit 400 supplies a binary signal including, for example, a single pulse that transitions from logic level 0 to logic level 1 as the load signal LOAD to the shift register 41 and the delay control circuit 43. Furthermore, the receiving unit 400 supplies the extracted sequence of pixel data PD to the first data latch unit 42.

[0037] When the shift register 41 receives a single-pulse load signal LOAD, it captures the load signal LOAD in response to the clock signal CLK and sequentially shifts it at the timing of the clock signal CLK to generate k latch timing signals r1 to rk with different timings. The shift register 41 supplies the latch timing signals r1 to rk to the first data latch unit 42.

[0038] The first data latch unit 42 receives the sequence of pixel data PD, captures each pixel data piece at the timing of latch timing signals r1 to rk, and supplies the captured k pieces of pixel data PD to the second data latch unit 44 as pixel data P1 to Pk.

[0039] The delay control circuit 43 generates output timing signals T1 to Tk in which a single pulse signal appears after a stepwise increased delay, or output timing signals Tk to T1 in which a single pulse signal appears after a stepwise increased delay, in response to the single-pulse load signal LOAD and the clock signal CLK. The delay control circuit 43 supplies the generated output timing signals T1 to Tk to the second data latch unit 44.

[0040] The second data latch unit 44 takes in the pixel data P1 to Pk supplied from the first data latch unit 42, sets them as pixel data Q1 to Qk, and outputs them to the level shift unit 45 at the timing of the rising edge (or falling edge) of each of the output timing signals T1 to Tk.

[0041] That is, for example, the second data latch unit 44 outputs the captured pixel data P1 as pixel data Q1 at the rising edge of the output timing signal T1. Also, the second data latch unit 44 outputs the captured pixel data P2 as pixel data Q2 at the rising edge of the output timing signal T2. In this way, the second data latch unit 44 outputs the captured pixel data Pi (i is an integer from 1 to k) as pixel data Qi at the rising edge of the output timing signal Ti.

[0042] The level shift unit 45 performs level shift processing on each of the pixel data Q1 to Qk to increase the amplitude of the signal representing each bit of the pixel data, and supplies the result to the DA conversion unit 46 as high-voltage pixel data signals L1 to Lk.

[0043] The DA conversion unit 46 converts each of the pixel data signals L1 to Lk into a grayscale voltage having an analog voltage value corresponding to the brightness level represented by the pixel data signal, and supplies the converted grayscale voltages to the output amplifier unit 47 as the grayscale voltages V1 to Vk.

[0044] The output amplifier section 47 amplifies the grayscale voltages V1 to Vk individually and outputs the amplified voltages as pixel drive signals G1 to Gn.

[0045] FIG. 3 is a block diagram showing the internal configuration of the delay control circuit 43. As shown in FIG.

[0046] As shown in FIG. 3, the delay control circuit 43 includes a control signal generation circuit 430, delay timing signal generation circuits (DTSG) 431_1 to 431_s (s is an integer of 2 or more), and a delay signal selection circuit 432.

[0047] The control signal generation circuit 430 generates a delay direction control signal DIR that specifies the direction in which the output delay time is increased for the first to k-th output channels. Specifically, if the control signal generation circuit 430 belongs to driver 4a or 4b shown in FIG. 1, it generates a delay direction control signal DIR that specifies a forward delay that increases the output delay time from the first output channel toward the k-th output channel. On the other hand, if the control signal generation circuit 430 belongs to driver 4c or 4d, it generates a delay direction control signal DIR that specifies a backward delay that increases the output delay time from the k-th output channel toward the first output channel.

[0048] The control signal generating circuit 430 supplies the generated delay direction control signal DIR to the delay timing signal generating circuits 431_1 to 431_s.

[0049] 4, the control signal generation circuit 430 includes a clock generation circuit 60 that generates clock signals CK1 to CK4, each having a period Wc and with a phase difference between adjacent clock signals that is a unit delay time Ut. Note that the period Wc is equal to the length (4·Ut) obtained by multiplying Ut by 4, which is the number of clock signals, and the phase difference between the clock signals CK4 and CK1 is also the unit delay time Ut, as shown in FIG. 4. The clock generation circuit 60 generates s (s is an integer of 2 or greater) sets of clock signals CK1_1 to CK4_1, CK1_2 to CK4_2, CK1_3 to CK4_3, . . . , CK1_s to CK4_s, each having a different length of unit delay time Ut, based on the group of clock signals (CK1 to CK4) shown in FIG. Specifically, the length of the unit delay time Ut of each of the s groups of clock signals described above decreases in the order of CK1_1 to CK4_1, CK1_2 to CK4_2, CK1_3 to CK4_3, CK1_4 to CK4_4, . . . , CK1_s to CK4_s.

[0050] The control signal generation circuit 430 supplies clock signals CK1_1 to CK4_1, CK1_2 to CK4_2, CK1_3 to CK4_3, CK1_4 to CK4_4, . . . , CK1_s to CK4_s to delay timing signal generation circuits 431_1 to 431_s as shown in FIG.

[0051] Furthermore, the control signal generating circuit 430 generates start pulse signals ST1 to STs (s is an integer of 2 or greater) including a single pulse that starts the generation of the delay timing signals in response to the load signal LOAD.

[0052] The timing at which a single pulse appears in each of the start pulse signals ST1 to STs becomes later in the order of start pulse signals ST1, ST2, ST3, . . . , STs.

[0053] The control signal generating circuit 430 supplies the generated start pulse signals ST1 to STs to delay timing signal generating circuits 431_1 to 431_s as shown in FIG.

[0054] Each of the delay timing signal generating circuits 431_1 to 431_s generates delay timing signals t1 to tk indicating the output timing of the first to kth output channels in accordance with the delay direction control signal DIR, start pulse signal ST, and clock signals CK1 to CK4 received by itself.

[0055] That is, the delay timing signal generating circuit 431_1 generates delay timing signals t1_1 to tk_1 in response to the delay direction control signal DIR, the start pulse signal ST1, and the clock signals CK1_1 to CK4_1. The delay timing signal generating circuit 431_2 generates delay timing signals t1_2 to tk_2 in response to the delay direction control signal DIR, the start pulse signal ST2, and the clock signals CK1_2 to CK4_2. The delay timing signal generating circuit 431_3 generates delay timing signals t1_3 to tk_3 in response to the delay direction control signal DIR, the start pulse signal ST3, and the clock signals CK1_3 to CK4_3.

[0056] Similarly, the delay timing signal generating circuit 431_i (i is an integer from 4 to s) generates delay timing signals t1_i to tk_i in response to the delay direction control signal DIR, the start pulse signal STi, and the clock signals CK1_i to CK4_i.

[0057] The delay timing signal generating circuits 431_1 to 431_s have the same internal configuration.

[0058] FIG. 5 is a block diagram showing the internal configuration of each of the delay timing signal generating circuits 431_1 to 431_s, with the delay timing signal generating circuit 431_1 being selected.

[0059] As shown in FIG. 5, the delay timing signal generating circuit 431_1 includes a delay circuit DLC and a delay direction control circuit DCC.

[0060] The delay circuit DLC has flip-flops F1 to Fk (k is an integer of 2 or more) corresponding to the first to k-th output channels, respectively.

[0061] The delay circuit DLC is composed of a first shift register in which flip-flops (referred to as DFFs) of F(4x-3) (x is an integer greater than or equal to 1) among the flip-flops F1 to Fk are connected in series, a second shift register in which DFFs of F(4x-2) are connected in series, a third shift register in which DFFs of F(4x-1) are connected in series, and a fourth shift register in which DFFs of F(4x) are connected in series.

[0062] When the first shift register receives a start pulse signal ST1 at the first-stage flip-flop F1, it shifts a single pulse contained in the start pulse signal ST1 to the next-stage DFF in the order of F1, F5, F9, ..., F(k-7), and F(k-3) in accordance with the clock signal CK1_1, delaying each pulse by the period Wc.

[0063] When the first-stage flip-flop F2 of the second shift register receives the start pulse signal ST1, it shifts the single pulse contained in the start pulse signal ST1 to the next-stage DFF in the order of F2, F6, F10, ..., F(k-6), and F(k-2) in accordance with the clock signal CK2_1, delaying each pulse by the period Wc.

[0064] When the first-stage flip-flop F3 of the third shift register receives the start pulse signal ST1, it shifts the single pulse contained in the start pulse signal ST1 to the next-stage DFF in the order of F3, F7, F11, ..., F(k-5), and F(k-1) in accordance with the clock signal CK3_1, delaying each pulse by the period Wc.

[0065] When the fourth shift register receives the start pulse signal ST1 at the first-stage flip-flop F4, it shifts the single pulse contained in the start pulse signal ST1 to the next-stage DFF in the order of F4, F8, F12, ..., F(k-4), and Fk in accordance with the clock signal CK4_1, delaying each pulse by the period Wc.

[0066] Here, the delay circuit DLC supplies each of the binary signals output from the flip-flops F1 to Fk, each including a single pulse that transitions from logic level 0 to logic level 1, as delay signals d1 to dk to the delay direction control circuit DCC.

[0067] In the delay circuit DLC shown in Fig. 5, the circuit configuration is shown taking as an example the case where k is an integer divisible by 4, but the case where k is not divisible by 4 is also acceptable. In this case, if k is an integer not divisible by 4, for example (4x-1) (x is an integer of 1 or more), the flip-flop Fk in the final stage of the fourth shift register shown in Fig. 5 is deleted, and the flip-flops in the final stages of the first to third shift registers become F(k-2), F(k-1), and Fk, respectively.

[0068] FIG. 6 is a diagram showing delay forms of the delayed signals d1 to dk.

[0069] As shown in FIG. 6, the delay time between adjacent delayed signals d1 to dk increases in the order of d1, d2, d3, . . . , dk by the unit delay time Ut shown in FIG.

[0070] The delay direction control circuit DCC receives the delay direction control signal DIR together with the delay signals d1 to dk. When the delay direction control signal DIR indicates a forward delay, the delay direction control circuit DCC outputs the delay signals d1 to dk in the order shown below as delay timing signals t1_1 to tk_1.

[0071] d1:t1_1 d2:t2_1 d3:t3_1 · · · dk:tk_1 At this time, the delay times of the delay timing signals t1_1 to tk_1 increase by a unit delay time Ut for each output channel from the first output channel to the k-th output channel, similar to the delay signals d1 to dk shown in FIG.

[0072] On the other hand, when the delay direction control signal DIR indicates a backward delay, the following correspondence is satisfied, that is, the delay signals dk to d1 obtained by arranging the delay signals d1 to dk in descending order are output as delay timing signals t1_1 to tk_1, respectively.

[0073] dk:t1_1 d(k―1):t2_1 d(k―2):t3_1 · · · d3:t(k―2)_1 d2:t(k―1)_1 d1:tk_1 At this time, the delay timing signals t1_1 to tk_1 have a delay time that increases by a unit delay time Ut for each output channel, inversely to the delay signals d1 to dk shown in FIG. 6, that is, from the kth output channel to the first output channel.

[0074] FIG. 7 is a circuit diagram showing an example of the internal configuration of the delay direction control circuit DCC.

[0075] In the example shown in FIG. 7, the delay direction control circuit DCC is made up of selectors SD1 to SD(k / 2).

[0076] The selectors SD1 to SD(k / 2) commonly receive the delay direction control signal DIR, as shown in Fig. 7. Furthermore, the selectors SD1 to SD(k / 2) each receive a pair of delay signals d1 to dk as follows.

[0077] SD1:d1,dk SD2: d2, d(k-1) SD3:d3,d(k-2) SD4:d4,d(k-3) · · · SD(k / 2):d(k / 2), d[(k / 2)+1] Here, when the delay direction control signal DIR indicates a forward delay, the selectors SD1 to SD(k / 2) output the delay signals d1 to d(k / 2) as delay timing signals t1_1 to t(k / 2)_1, and output the delay signals dk to d[(k / 2)+1] as delay timing signals tk_1 to t[(k / 2)+1]_1.

[0078] On the other hand, when the delay direction control signal DIR indicates a reverse delay, the selectors SD1 to SD(k / 2) output the delay signals d1 to d(k / 2) as delay timing signals tk_1 to t[(k / 2)+1]_1 and output the delay signals dk to d[(k / 2)+1] as delay timing signals t1_1 to t(k / 2)_1.

[0079] For example, when the delay direction control signal DIR indicates a forward delay, the selector SD1 outputs the delay signal d1 as the delay timing signal t1_1 and outputs the delay signal dk as the delay timing signal tk_1. On the other hand, when the delay direction control signal DIR indicates a backward delay, the selector SD1 outputs the delay signal d1 as the delay timing signal tk_1 and outputs the delay signal dk as the delay timing signal t1_1.

[0080] Furthermore, for example, when the delay direction control signal DIR indicates a forward delay, the selector SD(k / 2) outputs the delay signal d(k / 2) as the delay timing signal t(k / 2)_1 and outputs the delay signal d[(k / 2)+1] as the delay timing signal t[(k / 2)+1]_1. On the other hand, when the delay direction control signal DIR indicates a backward delay, the selector SD(k / 2) outputs the delay signal d(k / 2) as the delay timing signal t[(k / 2)+1]_1 and outputs the delay signal d[(k / 2)+1] as the delay timing signal t(k / 2)_1.

[0081] Here, the delay timing signal generating circuits 431_1 to 431_s, each having an internal configuration as shown in Figures 5 and 7, supply s sets of delay timing signals consisting of the generated delay timing signals t1_1 to tk_1, t1_2 to tk_2, t1_3 to tk_3, ..., t1_s to tk_s to the delay signal selecting circuit 432.

[0082] FIG. 8 shows delay characteristics for each output channel at the time of forward delay, for four sets of delay timing signals t1_1 to tk_1, t1_2 to tk_2, t1_3 to tk_3, and t1_s to tk_s selected from the s sets of delay timing signals.

[0083] For example, the delay timing signal generating circuit 431_1 generates delay timing signals t1_1 to tk_1 in accordance with the delay characteristics represented by the slope of the dashed line in FIG. 8 from the first output channel (t1_1) to the kth output channel (tk_1) starting from the point when time ts1 has elapsed, in response to the start pulse signal ST1.

[0084] Furthermore, in response to the start pulse signal ST2 delayed relative to the start pulse signal ST1, the delay timing signal generating circuit 431_2 generates delay timing signals t1_2 to tk_2 that follow delay characteristics represented by the slope of the straight line shown by the dashed line in Fig. 8, starting from a point when a time ts2 longer than the time ts1 has elapsed. Note that the slope of the delay line formed by the delay timing signals t1_2 to tk_2 is gentler than the slope of the delay line formed by the delay timing signals t1_1 to tk_1 shown by the dashed line.

[0085] Furthermore, in response to the start pulse signal ST3 delayed with respect to the start pulse signal ST2, the delay timing signal generating circuit 431_3 generates delay timing signals t1_3 to tk_3 that follow delay characteristics represented by the slope of the solid line in Fig. 8, starting from a point when a time ts3 longer than the time ts2 has elapsed. Note that the slope of the delay line formed by the delay timing signals t1_3 to tk_3 is gentler than the slope of the delay line formed by the delay timing signals t1_2 to tk_2, represented by the dashed dotted line.

[0086] Similarly, the delay timing signal generating circuit 431_s generates delay timing signals t1_s to tk_s according to delay characteristics represented by the slope of the straight line shown by the two-dot chain line in Fig. 8, starting from a point when a time tss longer than the time ts(s-1) has elapsed, in response to the start pulse signal STs delayed relative to the start pulse signal ST(s-1). The slope of the delay line formed by the delay timing signals t1_s to tk_s is the gentlest among the delay timing signals generated in the delay control circuit 43.

[0087] That is, the rate of increase in delay time due to each delay timing signal from the first output channel to the kth output channel is a first group of delayed timing signals (t1_1 to tk_1); a second group of delayed timing signals (t1_2 to tk_2); a third group of delayed timing signals (t1_3 to tk_3); · · · s-th delayed timing signal group (t1_s to tk_s), The figures are decreasing in this order.

[0088] The delay signal selection circuit 432 selects, for each of the first to k-th output channels among the delay timing signals t1_1 to tk_1, t1_2 to tk_2, t1_3 to tk_3, ..., t1_s to tk_s, one delay timing signal with the earliest timing from among the s delay timing signals corresponding to that output channel. The delay signal selection circuit 432 outputs the delay timing signal selected for each of the first to k-th output channels as the above-mentioned output timing signals T1 to Tk.

[0089] FIG. 9 is a circuit diagram showing an example of the configuration of the delayed signal selection circuit 432. As shown in FIG.

[0090] As shown in FIG. 9, the delayed signal selection circuit 432 includes selection circuits SL1 to SLk corresponding to the first to k-th output channels, respectively.

[0091] The selection circuits SL1 to SLk have the same internal configuration, that is, they have an OR gate OR and an RS flip-flop RSF.

[0092] The OR gate OR included in each of the selection circuits SL1 to SLk receives s delayed timing signals corresponding to the same output channel, and supplies the logical sum result to the set terminal S of the RS flip-flop RSF.

[0093] For example, an OR gate OR included in the selection circuit SL1 receives delayed timing signals t1_1 to t1_s corresponding to the first output channel, and when any one of them reaches logic level 1, supplies a set signal of logic level 1 to the set terminal S of the RS flip-flop RSF included in the selection circuit SL1. On the other hand, when all of the delayed timing signals t1_1 to t1_s are logic level 0, the OR gate OR supplies a set signal of logic level 0 to the set terminal S of the RS flip-flop RSF. Also, for example, an OR gate OR included in the selection circuit SLk receives delayed timing signals tk_1 to tk_s corresponding to the kth output channel, and when any one of them reaches logic level 1, supplies a set signal of logic level 1 to the set terminal S of the RS flip-flop RSF included in the selection circuit SLk. On the other hand, when all of the delayed timing signals tk_1 to tk_s are logic level 0, the OR gate OR supplies a set signal of logic level 0 to the set terminal S of the RS flip-flop RSF.

[0094] The RS flip-flops RSF included in each of the selection circuits SL1 to SLk receive a load signal LOAD at their own reset terminals R, and are reset when the load signal LOAD indicates a logic level 1. As a result, the RS flip-flops RSF included in each of the selection circuits SL1 to SLk output output timing signals T1 to Tk that maintain a logic level 0 state.

[0095] Thereafter, when a set signal of logic level 1 is supplied to its set terminal S, the RS flip-flop RSF included in each of the selection circuits SL1 to SLk is set, and outputs an output timing signal that maintains the logic level 1 state.

[0096] For example, when the RS flip-flop RSF included in the selection circuit SL1 is in a reset state and receives a set signal of logic level 1 from the OR gate OR, it outputs an output timing signal T1 that transitions from logic level 0 to logic level 1 at that timing. That is, the RS flip-flop RSF included in the selection circuit SL1 outputs an output timing signal T1 that transitions from logic level 0 to logic level 1 at the timing of the delayed timing signal that first transitions from logic level 0 to logic level 1 among the delayed timing signals t1_1 to t1_s corresponding to the first output channel.

[0097] Furthermore, for example, when the RS flip-flop RSF included in the selection circuit SLk is in a reset state and receives a set signal of logic level 1 from the OR gate OR, it outputs an output timing signal Tk that transitions from logic level 0 to logic level 1 at that timing. In other words, the RS flip-flop RSF included in the selection circuit SLk outputs an output timing signal Tk that transitions from logic level 0 to logic level 1 at the timing of the delayed timing signal that first transitions from logic level 0 to logic level 1 among the delayed timing signals tk_1 to tk_s corresponding to the kth output channel. [Example of operation when s=2, DIR: forward delay] The operation of generating the output timing signals T1 to Tk by the delay control circuit 43 will be described below taking as an example the case where s=2, that is, where there are only two delay timing signal generating circuits 431_1 and 431_2 and the delay is in the forward direction.

[0098] 3 supplies a delay direction control signal DIR specifying a forward delay to the delay timing signal generating circuits 431_1 and 431_2. The control signal generating circuit 430 also supplies a start pulse signal ST1, in which a single pulse appears in response to the load signal LOAD, and clock signals CK1_1 to CK4_1 shown in FIG. 4 to the delay timing signal generating circuit 431_1.

[0099] Furthermore, the control signal generating circuit 430 supplies a start pulse signal ST2 in which a single pulse appears at a timing delayed from the start pulse signal ST1, and clock signals CK1_2 to CK4_2 shown in FIG. 4, to a delay timing signal generating circuit 431_2 in response to the load signal LOAD.

[0100] The unit delay time Ut of the clock signals CK1_2 to CK4_2 supplied to the delay timing signal generating circuit 431_2 is shorter than the unit delay time Ut of the clock signals CK1_1 to CK4_1 supplied to the delay timing signal generating circuit 431_1. In other words, the frequencies of the clock signals CK1_2 to CK4_2 are higher than the frequencies of the clock signals CK1_1 to CK4_1.

[0101] FIG. 10A is a diagram showing delay characteristics of the delay timing signals t1_1 to tk_1 and t1_2 to tk_2 generated by the delay timing signal generating circuits 431_1 and 431_2 under the control of the control signal generating circuit 430 described above.

[0102] The delay timing signal generating circuit 431_1 generates delay timing signals t1_1 to tk_1 whose delay times increase from a time delayed by time ts1 in response to the load signal LOAD as a starting point toward the first to k-th output channels, as shown by the dashed line in Fig. 10A. On the other hand, the delay timing signal generating circuit 431_2 generates delay timing signals t1_2 to tk_2 whose delay times increase from a time delayed by time ts2 in response to the load signal LOAD as a starting point toward the first to k-th output channels, as shown by the dashed line in Fig. 10A.

[0103] 10A, since the frequencies of clock signals CK1_2 to CK4_2 are higher than those of clock signals CK1_1 to CK4_1, the slope of the delay line (dash line) due to delayed timing signals t1_2 to tk_2 is smaller than the slope of the delay line (dashed line) due to delayed timing signals t1_1 to tk_1. In other words, the rate of increase in delay time due to delayed timing signals t1_2 to tk_2 is lower than the rate of increase in delay time due to delayed timing signals t1_1 to tk_1.

[0104] 10A, in the range of the 1st to jth (j is an integer less than k) output channels, the delay times between the same output channels are such that delay timing signals t1_1 to tk_1 are shorter than delay timing signals t1_2 to tk_2. However, in the range of the (j+1)th to kth output channels, as shown in FIG. 10A, the delay times between the same output channels are such that delay timing signals t1_2 to tk_2 are shorter than delay timing signals t1_1 to tk_1.

[0105] That is, as shown in FIG. 10A, the magnitude relationship between the delay times due to the delay timing signals t1_1 to tk_1 and the delay times due to the delay timing signals t1_2 to tk_2 is reversed at the inflection point tin between the jth and (j+1)th output channels.

[0106] 3 compares the delay timing signals t1_1 to tk_1 with t1_2 to tk_2 for the same output channel and selects the delay timing signal with the shorter delay time for each of the first to k-th output channels.The delay signal selection circuit 432 then outputs the selected delay timing signal for each of the first to k-th output channels as the output timing signals T1 to Tk.

[0107] As a result, as shown in FIG. 10B, the delayed timing signals t1_1 to tj_1 become T1 to Tj of the output timing signals T1 to Tk, and the delayed timing signals t(j+1)_2 to tk_2 become T(j+1) to tk of the output timing signals T1 to Tk. [Example of operation when s=3, DIR: forward delay] Next, the operation of generating the output timing signals T1 to Tk by the delay control circuit 43 will be described using the example where s=3, that is, where there are only three delay timing signal generating circuits 431_1 to 431_3 and the delay is in the forward direction.

[0108] At this time, the control signal generating circuit 430 supplies a delay direction control signal DIR specifying a forward delay to the delay timing signal generating circuits 431_1, 431_2 and 431_3.

[0109] Furthermore, the control signal generating circuit 430 supplies a start pulse signal ST1 in which a single pulse appears in response to the load signal LOAD, and clock signals CK1_1 to CK4_1 shown in FIG. 4 to the delay timing signal generating circuit 431_1. Moreover, the control signal generation circuit 430 supplies a start pulse signal ST2, in which a single pulse appears at a timing delayed from the start pulse signal ST1, and the clock signals CK1_2 to CK4_2 shown in Fig. 4, to a delay timing signal generation circuit 431_2 in response to the load signal LOAD. Furthermore, the control signal generation circuit 430 supplies a start pulse signal ST3, in which a single pulse appears at a timing delayed from the start pulse signal ST2, and the clock signals CK1_3 to CK4_3 shown in Fig. 4, to a delay timing signal generation circuit 431_3 in response to the load signal LOAD.

[0110] The unit delay time Ut of clock signals CK1_2 to CK4_2 is shorter than the unit delay time Ut of clock signals CK1_1 to CK4_1, and the unit delay time Ut of clock signals CK1_3 to CK4_3 is shorter than the unit delay time Ut of clock signals CK1_3 to CK4_3. In other words, the frequencies of clock signals CK1_2 to CK4_2 are higher than the frequencies of clock signals CK1_1 to CK4_1, and the frequencies of clock signals CK1_3 to CK4_3 are higher than the frequencies of clock signals CK1_2 to CK4_2.

[0111] FIG. 11A is a diagram showing delay characteristics of the delay timing signals t1_1 to tk_1, t1_2 to tk_2, and t1_3 to tk_3 generated by the delay timing signal generating circuits 431_1 to 431_3 under the control of the control signal generating circuit 430 described above.

[0112] The delay timing signal generating circuit 431_1 generates delay timing signals t1_1 to tk_1 whose delay times increase from a time ts1 delayed in response to the load signal LOAD as indicated by the dashed line in Fig. 11A toward the first to k-th output channels. The delay timing signal generating circuit 431_2 generates delay timing signals t1_2 to tk_2 whose delay times increase from a time ts2 delayed in response to the load signal LOAD as indicated by the dashed line in Fig. 11A toward the first to k-th output channels. The delay timing signal generating circuit 431_3 generates delay timing signals t1_3 to tk_3 whose delay times increase from a time ts3 delayed in response to the load signal LOAD as indicated by the solid line in Fig. 11A toward the first to k-th output channels.

[0113] Since the frequencies of clock signals CK1_2 to CK4_2 are higher than those of clock signals CK1_1 to CK4_1, the slope of the delay line (dash-dotted line) due to delayed timing signals t1_2 to tk_2 is smaller than the slope of the delay line (dashed line) due to delayed timing signals t1_1 to tk_1, as shown in Fig. 11A. Also, since the frequencies of clock signals CK1_3 to CK4_3 are higher than those of clock signals CK1_2 to CK4_2, the slope of the delay line (solid line) due to delayed timing signals t1_3 to tk_3 is smaller than the slope of the delay line (dashed-dotted line) due to delayed timing signals t1_2 to tk_2, as shown in Fig. 11A.

[0114] That is, the rate of increase in delay time due to delay timing signals t1_3 to tk_3 is lower than the rate of increase in delay time due to delay timing signals t1_2 to tk_2, and the rate of increase in delay time due to delay timing signals t1_2 to tk_2 is lower than the rate of increase in delay time due to delay timing signals t1_1 to tk_1.

[0115] 11A, in the range of the 1st to pth (p is an integer less than k) output channels, the delay time between the same output channels is shortest among the delay timing signals t1_1 to tk_1, t1_2 to tk_2, and t1_3 to tk_3, for the delay timing signals t1_1 to tk_1. Also, in the range of the (p+1)th to qth (q is an integer greater than p and less than k) output channels, the delay time between the same output channels is shortest among the delay timing signals t1_1 to tk_1, t1_2 to tk_2, and t1_3 to tk_3, for the delay timing signals t1_2 to tk_2. Furthermore, in the range of the (q+1)th to kth output channels, the delay time between the same output channels is shortest among the delay timing signals t1_1 to tk_1, t1_2 to tk_2, and t1_3 to tk_3, as shown in FIG. 11A.

[0116] That is, as shown in FIG. 11A, at the inflection point ti1 between the pth and (p+1)th output channels, the delay timing signal with the shortest delay time changes from t1_1 to tk_1 to t1_2 to tk_2, and at the inflection point ti2 between the qth and (q+1)th output channels, the delay timing signal with the shortest delay time changes from t1_2 to tk_2 to t1_3 to tk_3.

[0117] 3 compares the delay timing signals t1_1 to tk_1, t1_2 to tk_2, and t1_3 to tk_3 for the same output channel, and selects the delay timing signal with the shortest delay time for each of the first to k-th output channels.The delay signal selection circuit 432 then outputs the selected delay timing signal for each of the first to k-th output channels as the output timing signals T1 to Tk.

[0118] As a result, as shown in FIG. 11B, the delayed timing signals t1_1 to tp_1 become T1 to Tp of the output timing signals T1 to Tk, the delayed timing signals t(p+1)_2 to tq_2 become T(p+1) to Tq, and the delayed timing signals t(q+1)_3 to tk_3 become T(q+1) to Tk.

[0119] Therefore, as shown in FIG. 10B or 11B, the delay control circuit 43 can generate output timing signals T1 to Tk that follow a quadratic curve-like delay characteristic in which the rate of increase in delay time decreases when outputting pixel drive signals G1 to Gk from the first output channel to the kth output channel, respectively.

[0120] 1, the delay control circuits 43 included in each of the drivers 4a to 4d individually set the timing and delay direction of the start pulse signal group, thereby obtaining output timing signals T1 to Tk for all of the first to n-th output channels that follow a delay characteristic shaped like a quadratic curve, for example, as shown in Fig. 12. Note that Fig. 12 shows the delay characteristics for the first to k-th output channels, taking as an example a case where s=2, that is, the delay control circuit 43 includes only two delay timing signal generating circuits, 431_1 and 431_2.

[0121] This makes it possible to output pixel drive signals G1 to Gn for all output channels 1 to n at output timings that follow a quadratic curve-like delay characteristic in which the rate of increase in delay time decreases from both the left and right ends of the screen toward the center of the screen.

[0122] Here, the delay control circuit 43 of each of the drivers 4a to 4d has a built-in setting register (not shown) in which information specifying the delay time at the kth output channel, i.e., the end output channel (hereinafter referred to as end point delay time information) and delay direction information specifying the delay direction are pre-stored.

[0123] For example, in the example shown in Figure 12, the setting register of driver 4a stores delay direction information specifying a forward delay, as well as endpoint delay time information specifying a delay time at output timing teB1 shown in Figure 12 corresponding to the endpoint output channel. The setting register of driver 4b stores information specifying a forward delay, as well as endpoint delay time information specifying a delay time at output timing teB2 shown in Figure 12 corresponding to the endpoint output channel. The setting register of driver 4c stores information specifying a backward delay, as well as endpoint delay time information specifying an endpoint delay time at output timing teB2 shown in Figure 12 corresponding to the endpoint output channel. The setting register of driver 4d stores information specifying a backward delay, as well as endpoint delay time information specifying a delay time at output timing teB3 shown in Figure 12 corresponding to the endpoint output channel.

[0124] The control signal generating circuit 430 of each of the drivers 4a to 4d supplies a delay direction control signal DIR indicating the delay direction indicated by the delay direction information stored in the setting register to the delay timing signal generating circuits 431_1 to 431_s.

[0125] Furthermore, the control signal generating circuit 430 of each of the drivers 4a to 4d performs the following control based on the end point delay time information specified as above, so as to match the output timing of the end point output channel of one driver and the start point output channel of the other driver between a pair of adjacent drivers.

[0126] That is, in the delay control circuit 43, the output timing of the k-th output channel, that is, the output channel of the end point, is always the delay timing signal tk_s generated by the delay timing signal generating circuit 431_s. In this case, for example, when s=2, tk_2 of the delay timing signals t1_2 to tk_2 generated by the delay timing signal generating circuit 431_2 becomes the output timing of the k-th output channel (output channel of the end point) as shown in Fig. 10B. Also, for example, when s=3, tk_3 of the delay timing signals t1_3 to tk_3 generated by the delay timing signal generating circuit 431_3 becomes the output timing of the k-th output channel (output channel of the end point) as shown in Fig. 11B.

[0127] Furthermore, the delay timing signal generating circuit 431_s generates delay timing signals t1_s to tk_s including the above-mentioned tk_s based on the clock signals CK1_s to CK4_s. At this time, the delay time that changes between adjacent output channels in the delay timing signals t1_s to tk_s is the above-mentioned unit delay time Ut, and the total number of channels is k.

[0128] Therefore, by performing the following calculation using the delay time (end point delay time) of the delay timing signal tk_s representing the output timing of the end point output channel, the delay time of the delay timing signal t1_s corresponding to the start point output channel among the delay timing signals t1_s to tk_s including tk_s is obtained as the start point delay time.

[0129] Start delay time = End delay time - (k·Ut) Therefore, the control signal generating circuit 430 outputs the start pulse signal STs at a timing that will obtain the delay timing signal t1_s when the above-mentioned start point delay time has elapsed since receiving the load signal LOAD. At this time, the control signal generating circuit 430 sets the output timing of each of the other start pulse signals ST1 to ST(s-1) to be earlier than the start pulse signal STs, as shown in FIG.

[0130] For example, in the example shown in FIG. 12, s=2, so the delay timing signal that determines the end point delay time is the delay timing signal tk_2 generated by the delay timing signal generation circuit 431_2. Also, in the example shown in FIG. 12, the delay time at the output timing teB1 represented by the delay timing signal tk_2, i.e., the end point delay time, is specified as time tt1. Furthermore, the delay timing signal generation circuit 431_2 generates delay timing signals t1_2 to tk_2, including the above-mentioned tk_2, based on the clock signals CK1_2 to CK4_2. Therefore, the control signal generation circuit 430 of the driver 4a calculates the start point time ts2 of the first output channel, i.e., the start point output channel, by the following calculation based on the unit delay time Ut that increases between adjacent output channels in the delay timing signals t1_2 to tk_2, the total number of channels k, and the end point delay time tt1:

[0131] ts2=tt1-(k·Ut) Therefore, the control signal generating circuit 430 outputs the start pulse signal ST2 at a timing that will result in a delayed timing signal t1_2 when a time ts2 has elapsed since the load signal LOAD was received. Furthermore, the control signal generating circuit 430 outputs the start pulse signal ST1 at a time ts1 that is earlier than the start pulse signal ST2, as shown in FIG.

[0132] Therefore, according to the delay control circuit 43, by setting a delay time at the desired end point output channel for each driver (4a to 4d), as shown in FIG. 12, it is possible to match the output timing between the end point output channel of one driver and the start point output channel of the other driver between adjacent drivers.

[0133] This makes it possible to reduce the difference in output timing between pixel drive signals at the boundary between adjacent drivers (IC chips), thereby making it possible to reduce display unevenness caused by this.

[0134] Therefore, each of the above-described drivers 4a to 4d makes it possible to output pixel drive signals at output timings that follow a quadratic curve-like delay characteristic in which the rate of increase in delay time decreases from the edges of the screen toward the center, without causing display unevenness.

[0135] In the above embodiment, in order to match the output timing of the end point output channel of one driver and the start point output channel of the other driver between adjacent drivers, as described above, a calculation is performed for each driver using the delay time at the end point output channel (end point delay time), the total number of channels k, and the unit delay time Ut.

[0136] However, it is also possible to match the output timing of the output channel at the end of one driver with the output timing of the output channel at the start of the other driver between adjacent drivers without performing such calculations. [Example]

[0137] FIG. 13 is a block diagram showing the configuration of a display device 100A as another embodiment of the display device 100, which has been made in consideration of the above points.

[0138] The configuration shown in FIG. 13 is the same as that shown in FIG. 1 except that a source driver 40A is used instead of the source driver 40.

[0139] 13, the source driver 40A employs drivers 40a to 40d, each of which is made up of an independent IC chip, arranged in parallel, instead of the above-described drivers 4a to 4d. Note that the drivers 40a to 40d are each provided with an input terminal SI and an output terminal SO as external terminals of the IC chip, and are similar to the drivers 4a to 4d in that they also have other external terminals, i.e., k external terminals (not shown) for connecting to k data lines of the display panel 10.

[0140] In the source driver 40A, as shown in FIG. 13, the output terminal SO of the driver 40d is connected to the input terminal SI of the driver 40c, the output terminal SO of the driver 40c is connected to the input terminal SI of the driver 40b, and the output terminal SO of the driver 40b is connected to the input terminal SI of the driver 40a.

[0141] The internal configuration of each of the drivers 40a to 40d employs a delay control circuit 43A having the internal configuration shown in FIG. 14 instead of the delay control circuit 43 shown in FIG.

[0142] As shown in FIG. 14, the delay control circuit 43A employs a control signal generation circuit 430A instead of the control signal generation circuit 430 shown in FIG. 3, and the configuration is the same as that shown in FIG. 3 except that a comparator 433, an input terminal SI, and an output terminal SO are newly provided.

[0143] In the delay control circuit 43A, among the delay timing signals t1_1 to tk_1 generated by the delay timing signal generating circuit 431_1, t1_1 corresponding to the start point (first) output channel is output from the output terminal SO to the outside. That is, the driver 40d supplies the delay timing signal t1_1 generated by its own delay timing signal generating circuit 431_1 to the input terminal SI of the driver 40c connected to its own output terminal SO as shown in FIG. 13. Also, the driver 40c supplies the delay timing signal t1_1 generated by its own delay timing signal generating circuit 431_1 to the input terminal SI of the driver 40b connected to its own output terminal SO as shown in FIG. 13. Also, the driver 40b supplies the delay timing signal t1_1 generated by its own delay timing signal generating circuit 431_1 to the input terminal SI of the driver 40a connected to its own output terminal SO as shown in FIG.

[0144] Furthermore, the delay control circuit 43A supplies to a comparator 433 the delay timing signals tk_s corresponding to the end (k-th) output channel among the delay timing signals t1_s to tk_s generated by the delay timing signal generating circuit 431_s.

[0145] Furthermore, the delay control circuit 43A supplies the delay timing signal t1_1 received at its own input terminal SI from the adjacent driver to the comparator 433. That is, the driver 40c supplies the delay timing signal t1_1 received at its own input terminal SI from the driver 40d to the comparator 433. Furthermore, the driver 40b supplies the delay timing signal t1_1 received at its own input terminal SI from the driver 40c to the comparator 433. Furthermore, the driver 40a supplies the delay timing signal t1_1 received at its input terminal SI from the driver 40b to the comparator 433.

[0146] The comparator 433 compares the phase of the delay timing signal t1_1 generated by the delay timing signal generating circuit 431_1 of the adjacent driver with the phase of the delay timing signal tk_s generated by the delay timing signal generating circuit 431_2 of its own driver.

[0147] At this time, if the phase of the delayed timing signal tk_s is ahead of the phase of the delayed timing signal t1_1, the comparator 433 supplies an adjustment signal CM indicating a phase lead to the control signal generation circuit 430A. On the other hand, if the phase of the delayed timing signal tk_s is behind the phase of the delayed timing signal t1_1, the comparator 433 supplies an adjustment signal CM indicating a phase lag to the control signal generation circuit 430A.

[0148] Furthermore, if the phase difference between the phase of the delayed timing signal tk_s and the phase of the delayed timing signal t1_1 is within a predetermined allowable range centered around zero, the comparator 433 supplies an adjustment signal CM indicating phase agreement to the control signal generation circuit 430A.

[0149] The control signal generating circuit 430A performs a delay timing adjustment process based on the adjustment signal CM during the vertical blanking period of the video signal, between adjacent drivers, to match the output timing of the output channel at the end point of one driver with the output timing of the output channel at the start point of the other driver.

[0150] FIG. 15 is a flowchart showing the procedure of the delay timing adjustment process.

[0151] 15, the control signal generation circuit 430A first determines whether or not the adjustment signal CM indicates phase agreement (step S11). If it is determined in step S11 that the adjustment signal CM indicates phase agreement, the control signal generation circuit 430A ends this delay timing adjustment process and performs the same operation as the control signal generation circuit 430 shown in Fig. 3 described above. That is, the control signal generation circuit 430A supplies the delay direction control signal DIR, start pulse signals ST1 to STs, and clock signals CK1_1 to CK4_1, CK1_2 to CK4_2, CK1_3 to CK4_3, CK1_4 to CK4_4, . . . , CK1_s to CK4_s to the delay timing signal generation circuits 431_1 to 431_s.

[0152] If it is determined in step S11 that the adjusted signal CM does not indicate phase agreement, the control signal generating circuit 430A determines whether the adjusted signal CM indicates a phase delay (step S12). If it is determined in step S12 that the adjusted signal CM indicates a phase delay, the control signal generating circuit 430A advances the output timing of each of the start pulse signals ST1 to STs output in response to the load signal LOAD by a predetermined period of time compared to the previous output (step S13).

[0153] On the other hand, if it is determined in step S12 that the adjustment signal CM does not indicate a phase delay, that is, if the adjustment signal CM indicates a phase advance, the control signal generation circuit 430A uniformly delays the output timing of each of the start pulse signals ST1 to STs output in response to the load signal LOAD by a predetermined period from the previous output (step S14).

[0154] After executing step S13 or S14, the control signal generation circuit 430A goes to step S11 and executes the operations of steps S11 to S14 again. That is, the control signal generation circuit 430A adjusts (advance or delay) the output timing of each of the start pulse signals ST1 to STs until the output timing (tk_s) of the end (kth) output channel of its own driver coincides with the output timing (t1_1) of the start (first) output channel of the adjacent driver.

[0155] Therefore, according to the drivers 40a to 40d including the control signal generating circuit 430A, as shown in FIG. 12, at the boundary between adjacent drivers, an adjustment is automatically made to match the output timing of the end (kth) output channel of one driver with the output timing of the start (first) output channel of the other driver.

[0156] In the first and second embodiments described above, four shift registers and four clock signals CK1 to CK4 supplied to each shift register are used to generate the delay signals d1 to dk in the delay circuit DLC as shown in Fig. 5, but the configuration is not limited to this. For example, the delay circuit DLC may be configured with one shift register in which flip-flops F1 to Fk shown in Fig. 5 are cascade-connected, and one clock signal of a frequency (1 / Ut) with one cycle equal to the unit delay time Ut shown in Fig. 4 may be supplied to this one shift register.

[0157] Furthermore, in the delay circuit DLC of the above embodiment, delay signals d1 to dk are generated by a shift register consisting of k flip-flops (F1 to Fk), and by changing the frequency of the clock signals (CK1 to CK4) supplied to this shift register, various groups of delay timing signals with different delay characteristics are generated as shown in Fig. 8. However, the delay circuit DLC may employ a configuration in which k delay elements with variable delay times are cascaded instead of flip-flops, and the delay time of each delay element may be controlled by a delay time control signal.

[0158] In short, a display driver according to the present invention, which has first to kth output channels that output first to kth (k is an integer equal to or greater than 2) pixel drive signals corresponding to the pixels indicated by the video signal, may be configured to include the following delay control circuit and output section.

[0159] The output sections (44 to 47) output the first to k-th pixel drive signals (G1 to Gk) in response to the first to k-th output timing signals (T1 to Tk).

[0160] The delay control circuits (43, 43A) generate the first to k-th output timing signals that output the first to k-th pixel drive signals at timings that are different from each other after a different delay time. In this case, the delay control circuits include the following first to s-th (s is an integer of 2 or more) delay timing signal generating circuits, control signal generating circuits, and delay signal selecting circuits.

[0161] The first to s-th delay timing signal generating circuits (431_1 to 431_s) generate first to s-th (s is an integer of 2 or more) groups of delay timing signals (t1_1 to tk_1, t1_2 to tk_2, t1_3 to tk_3, ..., t1_s to tk_s) each of which corresponds to the first to k-th output channels and is made up of first to k-th delay timing signals which provide output timings in which the delay time increases for each output channel from the first output channel to the k-th output channel or from the k-th output channel to the first output channel, and in which the intervals between the output timings provided by the first to k-th delay timing signals are different from one another.

[0162] The control signal generating circuits (430, 430A) individually supply start pulse signals (ST1 to STk) indicating the timing to start sequentially generating the first to k-th delay timing signals to each of the first to s-th delay timing signal generating circuits.

[0163] The delay signal selection circuit (432) receives the first to s-th delay timing signals generated by the first to s-th delay timing signal generation circuits, selects, for each of the first to k-th output channels, a delay timing signal with the earliest output timing from among the s delay timing signals corresponding to that output channel, and supplies the k delay timing signals selected for each of the first to k-th output channels to the output sections (44 to 47) as the first to k-th output timing signals (T1 to Tk).

[0164] Here, by changing the increase rate of the delay time due to the first to k-th delay timing signals and the generation start timing of the first to k-th delay timing signals in each of the s delay timing signal groups, it is possible to obtain the first to k-th output timing signals having a delay characteristic that resembles a quadratic curve. Furthermore, with this configuration, by determining a desired delay time as the delay time at the end (k-th) output channel of the first to k-th output timing signals, it is possible to calculate the delay time at the start (first) output channel of the display driver from the desired delay time. This makes it possible to easily synchronize the output timing of pixel drive signals at the boundaries between adjacent drivers when multiple drivers output pixel drive signals to multiple data lines of the display panel at output timings that follow the quadratic curve delay characteristic.

[0165] Therefore, according to the present invention, it is possible to output multiple pixel drive signals to a display panel at output timings that follow a quadratic curve-like delay characteristic in which the rate of increase in delay time decreases from the edge of the screen to the center, without causing display unevenness due to discrepancies in output timing at the boundaries between drivers. [Explanation of symbols]

[0166] 4a~4d, 40a~40d drivers 10 Display panel 40 Source Driver 43, 43A Delay control circuit 44 Second data latch section 47 Output amplifier section 430, 430A Control signal generation circuit 431_1~431_s Delay timing signal generation circuit 432 Delay signal selection circuit

Claims

1. a display driver having first to k-th output channels for outputting first to k-th (k is an integer of 2 or more) pixel drive signals respectively corresponding to pixels indicated by a video signal, a delay control circuit that sequentially supplies first to k-th output timing signals corresponding to the first to k-th output channels, causing the first to k-th pixel drive signals to be output at timings after different delay times have passed; an output section that outputs the first to k-th pixel drive signals at output timings corresponding to supply timings of the first to k-th output timing signals; The delay control circuit includes: first to s-th (s is an integer of 2 or more) delay timing signal generating circuits that generate first to s-th (s is an integer of 2 or more) delay timing signal groups, each of which corresponds to the first to k-th output channels and includes first to k-th delay timing signals that provide output timings in which the delay time increases for each output channel from the first output channel to the k-th output channel or from the k-th output channel to the first output channel, and in which the intervals between the output timings provided by the first to k-th delay timing signals are different from one another; a control signal generating circuit that individually supplies a start pulse signal indicating a timing at which the sequential generation of the first to k-th delay timing signals should start to the first to s-th delay timing signal generating circuits; a delay signal selection circuit that receives the first to s-th delay timing signals generated by the first to s-th delay timing signal generation circuits, selects, for each of the first to k-th output channels, a delay timing signal with the earliest output timing from among the s delay timing signals corresponding to that output channel, and supplies the k delay timing signals selected for each of the first to k-th output channels to the output section as the first to k-th output timing signals.

2. The display driver according to claim 1, characterized in that the control signal generating circuit supplies the start pulse signal to each of the first to sth delay timing signal generating circuits in the order of the first to sth delay timing signal generating circuits, and controls the first to sth delay timing signal generating circuits to reduce the rate of increase in the delay time due to the first to kth delay timing signals belonging to the first to sth delay timing signal groups in the order of the first to sth delay timing signal groups.

3. the kth delayed timing signal in the sth delayed timing signal group becomes the kth output timing signal, the control signal generation circuit holds information specifying the delay time in the kth output channel as an end point output channel as an end point delay time, and calculates the delay time of the first delay timing signal in the sth delay timing signal group as a start point delay time by the following formula using the end point delay time: Start point delay time = End point delay time - (k x Ut) Ut: unit delay time for each output channel 3. The display driver according to claim 2, wherein the timing for supplying the start pulse signal to the sth delay timing signal generating circuit is determined based on the start point delay time.

4. Each of the first to s-th delay timing signal generating circuits comprises: a delay circuit including first to k-th flip-flops, which sequentially shifts the start pulse signal through each of the first to k-th flip-flops in response to a clock signal, and outputs signals output from each of the first to k-th flip-flops as first to k-th delayed signals; A display driver as described in any one of claims 1 to 3, characterized in that it includes a delay direction control circuit that receives a delay direction control signal that specifies a forward delay or a backward delay, and when the delay direction control signal indicates the forward delay, outputs the first to kth delay signals in the same order as the first to kth delay timing signals, while when the delay direction control signal indicates the backward delay, outputs the first to kth delay signals in descending order as the first to kth delay timing signals.

5. A display driver including first to w-th drivers (w is an integer of 2 or more) having first to k-th output channels, each of which outputs first to k-th pixel drive signals (k is an integer of 2 or more) corresponding to each pixel indicated by a video signal, Each of the first to wth drivers is a delay control circuit that sequentially supplies first to k-th output timing signals corresponding to the first to k-th output channels, causing the first to k-th pixel drive signals to be output at timings after different delay times have passed; an output section that outputs the first to k-th pixel drive signals at output timings corresponding to supply timings of the first to k-th output timing signals; The delay control circuit includes: first to s-th (s is an integer of 2 or more) delay timing signal generating circuits that generate first to s-th (s is an integer of 2 or more) delay timing signal groups, each of which corresponds to the first to k-th output channels and includes first to k-th delay timing signals that provide output timings in which the delay time increases for each output channel from the first output channel to the k-th output channel or from the k-th output channel to the first output channel, and in which the intervals between the output timings provided by the first to k-th delay timing signals are different from one another; a control signal generating circuit that individually supplies a start pulse signal indicating a timing at which the sequential generation of the first to k-th delay timing signals should start to the first to s-th delay timing signal generating circuits; a delay signal selection circuit that receives the first to s-th delay timing signals generated by the first to s-th delay timing signal generation circuits, selects, for each of the first to k-th output channels, a delay timing signal with the earliest output timing from among the s delay timing signals corresponding to that output channel, and supplies the k delay timing signals selected for each of the first to k-th output channels to the output section as the first to k-th output timing signals.

6. The display driver according to claim 5, wherein the control signal generating circuit supplies the start pulse signal to each of the first to sth delay timing signal generating circuits in the order of the first to sth delay timing signal generating circuits, and controls the first to sth delay timing signal generating circuits to reduce the rate of increase in the delay time due to the first to kth delay timing signals belonging to the first to sth delay timing signal groups in the order of the first to sth delay timing signal groups.

7. the first to wth drivers are each composed of an independent IC chip arranged side by side on a substrate, Each of the first to wth drivers is an output terminal for outputting the first delay timing signal included in the first delay timing signal group to the outside; an input terminal for externally inputting the first delay timing signal included in the first delay timing signal group of an adjacent driver; a comparator that compares the phase of the first delay timing signal externally input from the input terminal with the kth delay timing signal included in the sth delay timing signal group itself, and generates an adjustment signal that indicates a phase lead when the phase of the kth delay timing signal leads the phase of the first delay timing signal, and that indicates a phase lag when the phase of the kth delay timing signal lags the phase of the first delay timing signal; The control signal generating circuit of each of the first to wth drivers comprises: When the adjustment signal indicates a phase delay, the timing of each of the start pulse signals individually supplied to each of the first to s-th delay timing signal generating circuits is uniformly advanced, The display driver according to claim 6, characterized in that when the adjustment signal indicates a phase advance, the timing of each of the start pulse signals is uniformly delayed, thereby adjusting the kth output timing signal of one of the first to wth adjacent drivers to coincide with the first output timing signal of the other driver.

8. a display panel having a plurality of data lines and a plurality of gate lines arranged to cross the plurality of data lines; a display device including: first to w-th drivers (w is an integer of 2 or more) having first to k-th output channels, each of which outputs first to k-th pixel drive signals (k is an integer of 2 or more) corresponding to each pixel indicated by a video signal to each of the data lines of the display panel; Each of the first to wth drivers is a delay control circuit that sequentially supplies first to k-th output timing signals corresponding to the first to k-th output channels, causing the first to k-th pixel drive signals to be output at timings after different delay times have passed; an output section that outputs the first to k-th pixel drive signals at output timings corresponding to supply timings of the first to k-th output timing signals; The delay control circuit includes: first to s-th (s is an integer of 2 or more) delay timing signal generating circuits that generate first to s-th (s is an integer of 2 or more) delay timing signal groups, each of which corresponds to the first to k-th output channels and includes first to k-th delay timing signals that provide output timings in which the delay time increases for each output channel from the first output channel to the k-th output channel or from the k-th output channel to the first output channel, and in which the intervals between the output timings provided by the first to k-th delay timing signals are different from one another; a control signal generating circuit that individually supplies a start pulse signal indicating a timing at which the sequential generation of the first to k-th delay timing signals should start to the first to s-th delay timing signal generating circuits; a delay signal selection circuit that receives the first to s-th delay timing signals generated by the first to s-th delay timing signal generation circuits, selects, for each of the first to k-th output channels, a delay timing signal with the earliest output timing from among the s delay timing signals corresponding to that output channel, and supplies the k delay timing signals selected for each of the first to k-th output channels to the output section as the first to k-th output timing signals.

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