Level voltage generation circuit and display driver

Abstract

To provide a level voltage generation circuit and a display driver which can generate a plurality of highly accurate level voltages with a reduced circuit area.SOLUTION: A level voltage generation circuit employs an offset canceling amplifier that amplifies a reference voltage received by itself to generate an output voltage in an intermediate node included in itself and removes an offset occurred in the output voltage, as at least one gamma amplifier circuit among m gamma amplifier circuits individually amplifying m reference voltages respectively to generate m gamma voltages and outputting them to m taps of respective resistor strings. The offset cancelling amplifier carries out in order: a first step of detecting an offset voltage having occurred to the output voltage while shutting off connection between the own intermediate node and one tap among the m taps of the resistor string; and a second step of outputting an output voltage corrected for the offset voltage as a gamma voltage to the one tap while connecting the intermediate node to the one tap via an output node.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a voltage generating circuit that generates a plurality of voltages with different voltage levels, and a display driver. [Background technology]

[0002] A liquid crystal or organic EL display device includes a display panel on which a plurality of gate lines extending in the horizontal direction of a two-dimensional screen and a plurality of source lines extending in the vertical direction of the two-dimensional screen are arranged, a gate driver that drives the gate lines, and a source driver that drives the source lines.

[0003] The source driver includes a decoder that receives pixel data pieces representing the luminance level of each pixel based on a video signal and converts each of the pixel data pieces into a gradation voltage having a voltage value corresponding to the luminance level indicated by the pixel data piece. The decoder selects one of the gradation voltages generated by the gradation voltage generator that corresponds to the luminance level indicated by the pixel data piece and supplies the selected gradation voltage to a source line of the display panel.

[0004] As the above-mentioned grayscale voltage generating unit, one including first and second resistor strings each formed by connecting a plurality of resistors in series, a selector, and a group of gamma amplifiers has been proposed (see, for example, FIG. 3 of Patent Document 1). The selector shown in FIG. 3 of Patent Document 1 selects six voltages (V2 to V7) having voltage values ​​according to desired gamma characteristics from among the plurality of voltages generated by the first resistor string 107, and supplies each of the voltages to each of the gamma amplifiers (A1 to A6). Here, the group of voltages amplified by each gamma amplifier is applied to each of the desired taps in the second resistor string 153, and at this time, the voltages generated at each tap of the second resistor string are output as the above-mentioned plurality of grayscale voltages. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-8958 Summary of the Invention [Problem to be solved by the invention]

[0006] Incidentally, with the recent trend toward larger screens and higher definition display panels, source drivers are constructed by dividing them into multiple IC chips, each of which is arranged side by side along the horizontal direction of the two-dimensional screen of the display panel.

[0007] Here, if the amount of error with respect to the desired voltage value in each gradation voltage generated within each IC chip is different for each IC chip and the difference in the amount of error is large, there is a risk that this will be perceived as unevenness in the image display.

[0008] Therefore, it is desirable for the grayscale voltage generating section to generate highly accurate grayscale voltages with a small amount of error relative to the desired voltage value.

[0009] In order to improve the accuracy of the gradation voltage, it is conceivable to increase the size of the transistors that make up the gamma amplifiers described above, but this would result in a problem of an increase in the area within the IC chip required to construct multiple gamma amplifiers.

[0010] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a level voltage generating circuit and a display driver that can generate a plurality of highly accurate level voltages while reducing the circuit area. [Means for solving the problem]

[0011] A level voltage generation circuit according to the present invention includes a resistor string including a plurality of resistors connected in series with each other via a plurality of taps, and outputting n level voltages having different voltage levels from n (n is an integer of 2 or more) taps among the plurality of taps; a reference voltage generation unit that generates m (m is an integer of 2 or more) reference voltages according to desired gamma characteristics; and first to m-th gamma amplifier circuits that individually receive the m reference voltages, individually amplify the received reference voltages to generate m gamma voltages, and output the m gamma voltages to m taps among the plurality of taps via output nodes included in each of the first to m-th gamma amplifier circuits. At least one of the gamma amplifier circuits is an offset cancellation amplifier that generates an output voltage at an intermediate node included therein by amplifying the reference voltage received by the amplifier itself and removes an offset occurring in the output voltage, and the offset cancellation amplifier sequentially performs a first step of detecting an offset voltage occurring in the output voltage with the intermediate node of the amplifier itself disconnected from one of the m taps, and a second step of connecting the intermediate node to the one tap via the output node and outputting the output voltage, having been corrected for the offset voltage, as the gamma voltage to the one tap.

[0012] The display driver according to the present invention is a display driver including a level voltage generating circuit as a grayscale voltage generating circuit, and the first step is performed within a vertical blanking period of a frame period of a video signal. [Effects of the Invention]

[0013] In the present invention, an offset cancellation amplifier with an offset cancellation function is used as a gamma amplifier that generates a gamma voltage to be supplied to a resistor string by amplifying a reference voltage, which makes it possible to generate a gamma voltage having a desired voltage value with high precision without increasing the size of each transistor that constitutes the gamma amplifier.

[0014] Furthermore, this offset cancellation amplifier detects the offset occurring in the output voltage obtained by amplifying the reference voltage while the electrical connection to the resistor string is cut off, which makes it possible to detect the offset with high accuracy without being affected by the current flowing through the resistor string.

[0015] Therefore, according to the present invention, it is possible to suppress an increase in the circuit scale and to output a plurality of desired voltage levels from the resistor string with high precision. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a block diagram showing a schematic configuration of a display device 100 equipped with a display driver including a level voltage generating circuit according to the present invention. [Figure 2] 2 is a block diagram schematically showing the internal configuration of a data driver 103. FIG. [Figure 3] 3 is a circuit diagram showing an example of the internal configuration of a grayscale voltage generating circuit 122. FIG. [Figure 4] FIG. 2 is a circuit diagram showing an example of the internal configuration of a gamma amplifier circuit GB1. [Figure 5] 4 is a time chart showing waveforms of switch signals S1 and S2. [Figure 6A] FIG. 2 is a schematic circuit diagram showing the state of the gamma amplifier circuit GB1 in the first step. [Figure 6B] FIG. 10 is a schematic circuit diagram showing the state of the gamma amplifier circuit GB1 in the second step. [Figure 7] FIG. 10 is a circuit diagram showing another example of the internal configuration of the gamma amplifier circuit GB1. [Figure 8] FIG. 10 is a circuit diagram showing another example of the internal configuration of the gamma amplifier circuit GB1. [Figure 9] FIG. 2 is a circuit diagram showing an example of the internal configuration of a grayscale voltage generating circuit 122_a. [Figure 10] FIG. 2 is a circuit diagram showing an example of the internal configuration of a gamma amplifier circuit GB1_a. [Figure 11]FIG. 10 is a circuit diagram showing another example of the internal configuration of the gamma amplifier circuit GB1_a. [Figure 12] FIG. 2 is a circuit diagram showing the internal configuration of a differential amplifier unit G_OCA_a. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0017] The present invention will be described in detail below with reference to the drawings.

[0018] FIG. 1 is a block diagram showing a schematic configuration of a display device 100 equipped with a display driver including a level voltage generating circuit according to the present invention.

[0019] The display device 100 includes a display controller 101 , a gate driver 102 , a data driver 103 , and a display panel 200 .

[0020] The display panel 200 is made of, for example, a liquid crystal or organic EL display panel, and has gate lines GL1 to GLr (r is an integer of 2 or more) extending in the horizontal direction of the two-dimensional screen, and data lines DL1 to DLw (w is an integer of 2 or more) extending in the vertical direction of the two-dimensional screen. At each intersection of the gate lines GL1 to GLr and the data lines DL1 to DLw, a display cell (area surrounded by a dashed line) that displays red, green, or blue is formed.

[0021] The display controller 101 receives a video signal VD and supplies, to the gate driver 102, a gate timing signal indicating the timing at which to apply a gate selection signal to each of the gate lines GL1 to GLr, based on the video signal VD.

[0022] In addition, based on the video signal VD, the display controller 101 generates a video data signal DVS that includes various control signals including a clock signal, a load signal, etc., and a series of pixel data pieces that represent the brightness level of each pixel as a digital value, and supplies this to the data driver 103.

[0023] The gate driver 102 sequentially generates gate selection signals including at least one pulse for selecting a gate line in response to the gate timing signal supplied from the display controller 101, and supplies the gate selection signals to each of the gate lines GL1 to GLr of the display panel 200.

[0024] The data driver 103 receives each of the pixel data pieces included in the video data signal DVS for one horizontal scanning line (w pieces), converts each pixel data piece into a drive signal having a voltage value corresponding to the brightness level represented by the pixel data piece, and supplies the generated w drive signals as drive signals G1 to Gw to the data lines DL1 to DLw of the display panel 200, respectively.

[0025] FIG. 2 is a block diagram showing a schematic internal configuration of the data driver 103. As shown in FIG.

[0026] As shown in FIG. 2, the data driver 103 includes a control circuit 120, a data latch unit 121, a grayscale voltage generating circuit 122 as a level voltage generating circuit according to the present invention, a decoder unit 123, and an amplifier unit .

[0027] The control circuit 120 receives the video data signal DVS and extracts from the video data signal DVS various control signals including a horizontal synchronization signal, a vertical synchronization signal, a clock signal, a load signal, etc., and a series of pixel data fragments. The control circuit 120 supplies the extracted clock signal, load signal, and series of pixel data fragments to a data latch unit 121, and also supplies a control signal Sgma that performs gamma setting and timing control corresponding to the display device to a grayscale voltage generation circuit 122. The grayscale voltage generation circuit 122 may also receive gamma voltages VGMA0 and VGMA1 from the outside as reference gamma voltages.

[0028] The data latch unit 121 sequentially captures each pixel data piece in the sequence of pixel data pieces at the timing of the clock signal in response to the load signal. Every time the data latch unit 121 captures w pixel data pieces, it outputs the w pixel data pieces to the decoder unit 123 as pixel data P1 to Pw.

[0029] The grayscale voltage generation circuit 122 generates grayscale voltages VR0 to VR(n-1) (n is an integer of 2 or more), each having a voltage value according to a specified gamma characteristic, and supplies the generated grayscale voltages VR0 to VR(n-1) to the decoder unit 123. In generating the grayscale voltages VR0 to VR(n-1), the grayscale voltage generation circuit 122 cancels the offset of an operational amplifier (described later) included in itself for each frame period in accordance with a timing control signal included in the control signal Sgma.

[0030] The decoder unit 123 includes w decoders DEC that individually receive the pixel data P1 to Pw output from the data latch unit 121. Each of the decoders DEC receives the above-mentioned gradation voltages VR0 to VR(n-1) and selects, from the gradation voltages VR0 to VR(n-1), a gradation voltage having a voltage value corresponding to the luminance level indicated by the pixel data piece that it received. The decoder unit 123 receives the w gradation voltages selected by each decoder DEC and supplies gradation signals V1 to Vw having the respective voltage values ​​to the amplifier unit 124.

[0031] The amplifier section 124 amplifies the grayscale signals V1 to Vw individually and outputs the amplified signals to the data lines DL1 to DLw of the display panel 200 as the drive signals G1 to Gw.

[0032] The grayscale voltage generating circuit 122 will be described in detail below.

[0033] FIG. 3 is a circuit diagram showing an example of the internal configuration of the grayscale voltage generating circuit 122. As shown in FIG.

[0034] 3, the grayscale voltage generation circuit 122 includes amplifiers GA0 and GA1, a gamma selector GSL, a first resistor string LD1, a second resistor string LD2, and a gamma control circuit CNT. The grayscale voltage generation circuit 122 further includes gamma amplifier circuits GB1 to GBm (m is an integer equal to or greater than 2 and less than n) as gamma buffers, and amplifiers GB0 and GB(m+1).

[0035] The amplifiers GA0 and GA1 are input gamma amplifiers, each consisting of, for example, a voltage follower operational amplifier whose inverting input terminal and output terminal are connected. The amplifier GA0 receives a first DC voltage VGMA0 at its non-inverting input terminal and applies a voltage having the same voltage value as the voltage VGMA0 to a node nd1. The amplifier GA1 receives a second DC voltage VGMA1, which has a voltage value lower than the voltage VGMA0, at its non-inverting input terminal and applies a voltage having the same voltage value as the voltage VGMA1 to a node nd2.

[0036] The resistor string LD1 consists of first to xth (x is an integer greater than or equal to 2) resistors connected in series between nodes nd1 and nd2, and supplies the voltages at each of the (x+1) connection points (called taps) of the first to xth resistors to the gamma selector GSL as reference voltages Rf0 to Rfx.

[0037] The gamma control circuit CNT supplies a gamma characteristic designation signal de that designates a desired gamma characteristic to the gamma selector GSL. Furthermore, the gamma control circuit CNT generates binary (logical level 0 or 1) switch signals S1 and S2 that control the offset cancel operation in response to a timing control signal included in the control signal Sgma, and supplies these signals to the gamma amplifier circuits GB1 to GBm, respectively.

[0038] The gamma selector GSL receives the reference voltages Rf0 to Rfx, selects (m+2) reference voltages from the reference voltages Rf0 to Rfx, and outputs the selected (m+2) reference voltages as reference voltages VI0 to VI(m+1), respectively.

[0039] Each of the amplifiers GB0 and GB(m+1) consists of a voltage follower operational amplifier whose inverting input terminal and output terminal are connected. Amplifier GB0 receives a reference voltage VI0 at its non-inverting input terminal, amplifies it, and outputs it as a gamma voltage VG0 to a tap at one end of the second resistor string LD2. Amplifier GBm receives a reference voltage VI(m+1) at its non-inverting input terminal, amplifies it, and outputs it as a gamma voltage VG(m+1) to a tap at the other end of the second resistor string LD2.

[0040] Each of the gamma amplifier circuits GB1 to GBm receives switch signals S1 and S2 that control the offset cancellation operation, and also receives reference voltages VI1 to VIm individually as shown in Fig. 3. The gamma amplifier circuits GB1 to GBm individually amplify the reference voltages VI1 to VIm to obtain voltages as gamma voltages VG1 to VGm, which are output to each tap of the second resistor string LD2 except for one end and the other end.

[0041] Each of the gamma amplifier circuits GB1 to GBm is a so-called offset cancellation amplifier that has the function of removing an offset occurring in the operational amplifier included therein in response to the switch signals S1 and S2.

[0042] The second resistor string LD2 is composed of a series resistor group in which a plurality of resistors are connected in series. The resistor string LD2 outputs, as the above-mentioned grayscale voltages VR0 to VR(n-1), gamma voltages VG0 and VG(m+1) applied to one end and the other end of the series resistor group, respectively, and n voltages generated at n taps by gamma voltages VG1 to VGm applied to connection points (called taps) of each resistor.

[0043] Here, the configuration of each of the gamma amplifier circuits GB1 to GBm, which function as an independent offset cancellation amplifier, will be described.

[0044] Since the gamma amplifier circuits GB1 to GBm have the same configuration, the configuration of each of the gamma amplifier circuits GB1 to GBm will be described below, using the gamma amplifier circuit GB1 as a representative.

[0045] FIG. 4 is a circuit diagram showing an example of the internal configuration of the gamma amplifier circuit GB1.

[0046] As shown in FIG. 4, the gamma amplifier circuit GB1 has a differential amplifier section G_OCA with an offset cancellation circuit, and an output switch section G_Out.

[0047] The differential amplifier unit G_OCA includes a differential stage 10, an output stage 20, and a switch element 42 as a first feedback switch.

[0048] The differential stage 10 includes N-channel transistors 11 to 14, current sources Id and Is, switch elements 15 to 18, capacitors Ca and Cb, a Pch current mirror circuit CM1, an Nch current mirror circuit CM2, and floating current sources FG1 and FG2.

[0049] The transistor 11 receives the reference voltage VI1 supplied from the gamma selector GSL at its gate via the node nd1. The source of the transistor 11 is connected to the current source Id, and the drain of the transistor 11 is connected to a node nd11 on the output side of the Pch current mirror circuit CM1.

[0050] The transistor 12 receives the reference voltage VI1 at its gate via the switch element 17 and the node nd2, or receives the feedback voltage Vfb at its gate via the switch element 18 and the node nd2. The source of the transistor 12 is connected to the current source Id, and the drain of the transistor 12 is connected to a node nd12 on the input side of the Pch current mirror circuit CM1.

[0051] The switch element 17 receives the switch signal S1 and is in an OFF state while the switch signal S1 is at, for example, logic level 0, and is in an ON state while the switch signal S1 is at, for example, logic level 1. The switch element 18 receives the switch signal S2 and is in an OFF state while the switch signal S2 is at, for example, logic level 0, and is in an ON state while the switch signal S2 is at, for example, logic level 1.

[0052] The current source Id receives a power supply voltage VSI that is lower than the power supply voltage VDI, and draws a predetermined constant current from the sources of the transistors 11 and 12.

[0053] The differential pair (11, 12) of the transistors 11 and 12 described above is the differential pair of the operational amplifier that forms the core of the gamma amplifier circuit GB1.

[0054] In addition, in FIG. 4, the transistor 13 receives a predetermined reference voltage Vref at its gate via the switch element 15 and the node nd3.

[0055] The gate of the transistor 13 is connected to one end of the capacitor Ca. The power supply voltage VSI is applied to the other end of the capacitor Ca. The source of the transistor 13 is connected to the current source Is, and the drain of the transistor 13 is connected to a node nd11 on the output side of the Pch current mirror circuit CM1.

[0056] The transistor 14 receives the feedback voltage Vfb at its gate via the switch element 16 and a node nd4. The gate of the transistor 14 is connected to one end of a capacitor Cb. The power supply voltage VSI is applied to the other end of the capacitor Cb. The source of the transistor 14 is connected to a current source Is, and the drain of the transistor 14 is connected to a node nd12 on the input side of the Pch current mirror circuit CM1.

[0057] Both the switch elements 15 and 16 receive a switch signal S1, and are in an OFF state while the switch signal S1 is at logic level 0, for example, and in an ON state while the switch signal S1 is at logic level 1, for example.

[0058] The current source Is is connected to the power supply voltage VSI and causes a predetermined constant current to flow from the sources of the transistors 13 and 14 toward the power supply voltage VSI.

[0059] The above-mentioned transistor pair (13, 14), current source Is, capacitors Ca and Cb, and switch elements 15 to 18 constitute an offset cancellation circuit that cancels the offset occurring between the gates of the transistors 11 and 12 that form the differential pair of the operational amplifier. Furthermore, the reference voltage Vref may be the same as the reference voltage VI1.

[0060] The Pch current mirror circuit CM1 passes an input current to a node nd12 on the input side based on the power supply voltage VDI, and sends a current obtained by folding back the current flowing through the node nd12 to a node nd11 on the output side. At this time, the floating current source FG1 supplies the current received via the node nd12 to the input side of the Nch current mirror circuit CM2 via a node nd14.

[0061] The Nch current mirror circuit CM2 turns back the input current flowing from the node nd14 on its input side toward the power supply voltage VSI and flows it to the node nd13 on its output side. At this time, the floating current source FG2 extracts the current flowing to the node nd13 from the node nd11 on the output side of the Pch current mirror circuit CM1.

[0062] Here, the voltage generated at the node nd11 is supplied to the output stage 20 as a Pch drive signal VP, and the voltage generated at the node nd13 is supplied to the output stage 20 as an Nch drive signal VN.

[0063] The Pch current mirror circuit CM1, Nch current mirror circuit CM2, and floating current sources FG1 and FG2 function as a load circuit that outputs the voltages generated at nodes nd11 and nd13 as a Pch drive signal VP and an Nch drive signal VN when current is drawn from nodes nd11 and nd12 by the operational amplifier differential pair (11, 12) and the offset cancellation differential pair (13, 14).

[0064] The output stage 20 includes a P-channel transistor 21 and an N-channel transistor 22 whose drains are connected to each other.

[0065] A power supply voltage VDD is applied to the source of the transistor 21. The transistor 21 receives at its gate the voltage of a node nd11 on the output side of the Pch current mirror circuit CM1 as a Pch drive signal VP, and outputs a current based on the Pch drive signal VP to an intermediate node nd20 via its source.

[0066] The power supply voltage VS0 is applied to the source of the transistor 22. The transistor 22 receives at its gate the voltage of the node nd13 on the output side of the Nch current mirror circuit CM2 as an Nch drive signal VN, and draws a current based on this Nch drive signal VN from the intermediate node nd20 via its source.

[0067] The output stage 20 is a so-called output stage of an operational amplifier, which supplies the voltage generated at the intermediate node nd20 by the operation of the transistors 21 and 22 as an output voltage VOk to the switch element 42 and the output switch section G_Out.

[0068] The switch element 42 receives the switch signal S1 and is in an OFF state while the switch signal S1 is, for example, at logic level 0. On the other hand, when the switch signal S1 at logic level 1 is received, the switch element 42 is turned ON and supplies the output voltage VOk output from the output stage 20 to the switch elements 16 and 18 as the feedback voltage Vfb.

[0069] The output switch section G_Out includes a switch element 41 as a first output switch and a switch element 43 as a second feedback switch.

[0070] Both switch elements 41 and 43 receive switch signal S2 and are both in the OFF state while switch signal S2 is, for example, at logic level 0. On the other hand, when switch signal S2 of logic level 1 is received, both switch elements 41 and 43 are in the ON state. In this case, switch element 41 in the ON state supplies output voltage VOk output from output stage 20 as gamma voltage VG1 to a predetermined tap of resistor string LD2 via output node nd01. Switch element 43 in the ON state supplies the voltage of output node nd01 to switch elements 16 and 18 as feedback voltage Vfb.

[0071] The operation of each of the gamma amplifier circuits GB1 to GBm shown in FIG. 3 will be described below.

[0072] First, the gamma control circuit CNT receives a control signal Sgma from the control circuit of Fig. 2, and supplies switch signals S1 and S2 to each of the gamma amplifier circuits GB1 to GBm, which control the operation of the offset cancellation circuits (13 to 18, Ca, Cb, Is), in accordance with the timing control signal included in the control signal Sgma. At this time, the switch signals S1 and S2 are set to timings such that the control operation is performed within the vertical blanking period of the vertical synchronization signal extracted by the control circuit of Fig. 2.

[0073] FIG. 5 is a time chart showing the waveforms of the switch signals S1 and S2.

[0074] 5, during the vertical blanking period of each frame (from time t0 to time t1), the switch signal S1 switches from, for example, logic level 0, which indicates an OFF state, to logic level 1, which indicates an ON state, at time ts, and maintains that state until time th within the vertical blanking period (first step).Then, at time th, the switch signal S1 switches to logic level 0, which indicates an OFF state, and maintains that state until time ts within the next vertical blanking period (second step).

[0075] On the other hand, the switch signal S2 switches from, for example, logic level 1, which indicates an ON state, to logic level 0, which indicates an OFF state, at time ts during the vertical blanking period of each frame, and maintains that state until time th within the vertical blanking period (first step).Then, at time th, the switch signal S2 switches to logic level 1, which indicates an ON state, and maintains that state until time ts within the next vertical blanking period.

[0076] 5 is a diagram showing the logical values ​​of the switch signals S1 and S2 and the on / off control of the switch element controlled by the switch signal S1 or S2. Specifically, when the switch element is configured with an Nch transistor, the switch signal S1 or S2 in Fig. 5 is supplied directly to the gate of the Nch transistor. On the other hand, when the switch element is configured with a Pch transistor, the complementary signal of the switch signal S1 or S2 in Fig. 5 is supplied to the gate of the Pch transistor.

[0077] Next, the offset canceling operation performed in each of the gamma amplifier circuits GB1 to GBm in response to the switch signals S1 and S2 will be described, taking the gamma amplifier circuit GB1 shown in FIG. 4 as a representative example. [Operation in the first step] FIG. 6A is a schematic circuit diagram in which the on / off states of the switch elements 15 to 18 and 41 to 43 of the gamma amplifier circuit GB1 in the first step shown in FIG. 5 and the current paths are indicated by thick solid lines.

[0078] As shown in FIG. 6A, in the first step, the switch elements 15 to 17 and 42 are in the ON state, and the switch elements 18, 41 and 43 are in the OFF state.

[0079] At this time, with switch element 17 turned on and switch element 18 turned off, the gates of the differential pair of transistors 11 and 12 are shorted together, as shown by the thick solid line in Fig. 6A. Furthermore, with switch element 15 turned on, the reference voltage Vref is applied to the gate of transistor 13 and one end of capacitor Ca, and capacitor Ca is charged by the reference voltage Vref.

[0080] As a result, the voltage Va at one end of the capacitor Ca is Va=Vref and the voltage Va is held in the capacitor Ca.

[0081] 6A, when the switch elements 41 and 43 are turned off and the switch element 42 is turned on, the output voltage VOk output from the output stage 20 is applied as a feedback voltage Vfb to one end of the capacitor Cb as well as to the gate of the transistor 14. As a result, the capacitor Cb is charged by the output voltage VOk, and the voltage value of the voltage Vb at one end of the capacitor Cb becomes equal to the output voltage VOk.

[0082] In the circuit state shown in FIG. 6A, the gates of the transistors 11 and 12 that form a differential pair of the operational amplifier are short-circuited, so the difference in the differential pair is zero.

[0083] 6A, the reference voltage Vref applied to the gate of transistor 13 forming the offset circuit and the output voltage VOk applied to the gate of transistor 14 are made equal to each other. In this case, if an offset occurs in the output voltage VOk due to manufacturing variations in the pair transistors of the differential pair (11, 12) or the differential pair (13, 14), the output voltage VOk will be the reference voltage Vref plus the voltage of the offset. Therefore, the voltage Vb at one end of capacitor Cb is Vb=Vref+Voff Voff: Offset voltage and the voltage Vb (=Vref+Voff) is held in the capacitor Cb.

[0084] In this way, in the first step, the voltage Va having the reference voltage Vref is detected, as well as the voltage Vb obtained by adding the offset voltage occurring in the output voltage VOk to the reference voltage Vref, and these are respectively held in the capacitors Ca and Cb. [Operation in the second step] FIG. 6B is a schematic circuit diagram in which the on / off states of the switch elements 15 to 18 and 41 to 43 of the gamma amplifier circuit GB1 and the current paths are indicated by thick solid lines during the second step shown in FIG. 5, that is, during normal operation.

[0085] As shown in FIG. 6B, in the second step, the switch elements 15 to 17 and 42 are turned off, and the switch elements 18, 41 and 43 are turned on.

[0086] At this time, the switch elements 17 and 42 are turned off and the switch elements 18 and 43 are turned on, so that the gamma voltage VG1 applied to the tap of the resistor string LD2 is supplied as a feedback voltage Vfb to the gate of the transistor 12 of the differential pair via the switch elements 43 and 18, as shown by the thick solid line in FIG. 6B.

[0087] As a result, a pair of currents corresponding to the difference between the reference voltage VI1 and the gamma voltage VG1 flows through the node nd12 on the input side and the node nd11 on the output side of the Pch current mirror circuit CM1.

[0088] Furthermore, when switch elements 15 and 16 are turned off, the voltage Va (=Vref) held in capacitor Ca is applied to the gate of transistor 13, and the voltage Vb (=Vref+Voff) held in capacitor Cb is applied to the gate of transistor 14, as shown by the thick solid lines in FIG. 6B.

[0089] As a result, as described above, the current that the differential pair (11, 12) passes through the nodes nd12 and nd11 based on the difference between the reference voltage VI1 and the gamma voltage VG1 is combined with a pair of currents corresponding to the difference between the voltages Va and Vb, i.e., the offset voltage Voff.

[0090] As a result, a current corresponding to a voltage obtained by removing the offset (Voff) from the difference between the reference voltage VI1 and the gamma voltage VG1 is output via the intermediate node nd20 of the output stage 20 and the switch element 41. Therefore, a gamma voltage VG1 having a voltage value equal to the reference voltage VI1 with the offset voltage removed is generated, and this is output to the tap of the resistor string LD2.

[0091] As described above in detail, the grayscale voltage generation circuit 122 employs gamma amplifier circuits GB1 to GBm, each equipped with an offset cancellation circuit, as gamma buffers, which makes it possible to generate a group of grayscale voltages having desired voltage values ​​with high precision without increasing the size of each of the multiple transistors that make up the gamma buffer.

[0092] In each of the gamma amplifier circuits GB1 to GBm, in the first step shown in FIG. 5, the switch elements 41 and 43 are both turned off to cut off the connection with the tap of the resistor string LD2, and the output voltage VOk is fed back to the gate of the transistor 14 via the switch element 42, thereby obtaining the voltage Vb including the offset component (Voff).

[0093] This makes it possible to accurately acquire only the offset occurring in the differential stage 10 and the output stage 20 without being affected by the current flowing through the resistor string LD2. In other words, by providing the output switch unit G_Out shown in FIG. 4, it is possible to suppress a decrease in the accuracy of offset cancellation.

[0094] Furthermore, in each of the gamma amplifier circuits GB1 to GBm, in the second step, that is, during normal operation, the gamma voltage VG1 output to the tap of the resistor string LD2 via the switch element 41 is fed back to the gate of the transistor 12 via the switch element 43.

[0095] At this time, when the gamma amplifier circuit supplies current to the tap of the resistor string LD2, the voltage value of the output voltage VOk deviates from the gamma voltage VG1 output to the tap of the resistor string LD2 by the amount of the on-resistance of the switch element 41. However, the gamma amplifier circuit acts to make the gamma voltage VG1, which becomes the feedback voltage Vfb, coincide with the reference voltage VI1, and therefore it is possible to output a highly accurate gamma voltage VG1 to the tap of the resistor string LD2.

[0096] 4, the output stage 20 drives the resistor string LD2 via the switch element 41, and therefore performance degradation such as insufficient driving capability may occur unless a large-sized switch element 41 is used. Therefore, in order to ensure the desired driving capability without increasing the size of the switch element 41, a second output stage may be provided in the subsequent stage of the switch element 41 of each of the gamma amplifier circuits GB1 to GBm. [Example]

[0097] FIG. 7 is a circuit diagram showing the internal configuration of the gamma amplifier circuit GB1 selected from among the gamma amplifier circuits GB1 to GBm incorporating the above-described amplifiers.

[0098] In addition, in the configuration shown in Figure 7, an output switch unit G_Out_a is used instead of the output switch unit G_Out shown in Figure 4, and a differential amplifier unit G_OCA having the same configuration as that shown in Figure 4 is used.

[0099] The output switch section G_Out_a includes an output stage 30 as a second output stage, level shifters LS1 and LS2, and switch elements 41 and 43. Note that the output switch section G_Out_a is a new addition to the output stage 30 and level shifters LS1 and LS2, and the connection and operation of the switch elements 41 and 43 are the same as those included in the output switch section G_Out shown in FIG.

[0100] In FIG. 7, the level shifter LS1 includes a P-channel transistor 51 and a current source 52.

[0101] The current source 52 receives the power supply voltage VDD to generate a predetermined constant current and sends it to the source of the transistor 51 .

[0102] The transistor 51 has a power supply voltage VS0 applied to its drain and receives at its gate the Pch drive signal VP output from the differential stage 10 of the differential amplifier G_OCA. The transistor 51 has a power supply voltage VDD applied to its source, its gate connected to the source of the transistor 51, and its drain connected to the output node nd01. That is, the transistor 51 acts as a source follower and applies to the gate of the transistor 31 a voltage that is shifted higher than the Pch drive signal VP by approximately the threshold voltage (absolute value) of the transistor 51. Therefore, when the gamma voltage VG1 is approximately equal to the reference voltage VI1 and the Pch drive signal VP output from the differential stage 10 is stable, the transistor 31 is controlled to an off state. On the other hand, when the gamma voltage VG1 temporarily fluctuates significantly lower than the reference voltage VI1 due to the operation of the decoder unit 123 in FIG. 2, the gamma voltage VG1 is returned to the reference voltage VI1. At this time, the Pch drive signal VP fluctuates to the low voltage side, and the transistor 31 turns on when the potential difference between its gate voltage and the power supply voltage VDD exceeds the threshold voltage, outputting a current to the output node nd01 and contributing to the boosting action of the gamma voltage VG1.

[0103] The level shifter LS2 includes an N-channel transistor 53 and a current source .

[0104] The transistor 53 has a power supply voltage VDD applied to its drain and receives at its gate the Nch drive signal VN output from the differential stage 10 of the differential amplifier G_OCA. The transistor 32 has a power supply voltage VS0 applied to its source, its gate connected to the source of the transistor 53, and its drain connected to the output node nd01. That is, the transistor 53 acts as a source follower and applies to the gate of the transistor 32 a voltage that is shifted downward with respect to the Nch drive signal VN by approximately the threshold voltage of the transistor 53. Therefore, when the gamma voltage VG1 is approximately equal to the reference voltage VI1 and the Nch drive signal VN output from the differential stage 10 is stable, the transistor 32 is controlled to an off state. On the other hand, when the gamma voltage VG1 temporarily fluctuates significantly toward a voltage higher than the reference voltage VI1 due to the operation of the decoder unit 123 of FIG. 2, the gamma voltage VG1 is returned to the reference voltage VI1. At this time, the Nch drive signal VN changes to the high voltage side, and the transistor 32 turns on when the potential difference between its gate voltage and the power supply voltage VS0 exceeds the threshold voltage, and contributes to the step-down action of the gamma voltage VG1 by drawing current from the output node nd01.

[0105] 5, the switch element 41 of the output switch section G_Out_a is in the off state, so there is little change in the levels of the Pch drive signal VP and Nch drive signal VN output from the differential stage 10. Therefore, throughout the first step, the transistors 31 and 32 of the output switch section G_Out_a are in the off state, and the output stage 30 is inactive.

[0106] Meanwhile, in the second step shown in Figure 5, the switch element 41 is turned on and connected to the resistor string LD2. The operation of the decoder unit 123 in Figure 2 may cause the gamma voltage VG1 to temporarily fluctuate significantly from the reference voltage VI1. In this case, if the voltage fluctuation of the Pch drive signal VP or the Nch drive signal VN is large, the transistor 31 or 32 of the output stage 30 is turned on. This causes a current based on the Pch drive signal VP or the Nch drive signal VN to be sent to the output node nd01 not only from the output stage 20 but also from the output stage 30, enabling the voltage fluctuation of the gamma voltage VG1 to be quickly suppressed.

[0107] In this way, the output switch section G_Out_a shown in FIG. 7 makes it possible to obtain a desired driving capability without increasing the size of the switch element 41.

[0108] Incidentally, the output switch section G_Out_a shown in FIG. 7 is provided with level shifters LS1 and LS2 so that the output stage 30 is deactivated in the first step, while the output stage 30 is activated in the second step only when the difference between the reference voltage VI1 and the gamma voltage VG1 is greater than or equal to a predetermined value.

[0109] However, since the output stage 30 of the output switch unit G_Out_a in the second step is deactivated when the difference between the reference voltage VI1 and the gamma voltage VG1 is less than a predetermined value, it may take a long time for the gamma voltage VG1 to completely match the reference voltage VI1. Therefore, it may be possible to forcibly control the activation and deactivation of the second output stage mounted in the output switch unit, subject to the first and second steps shown in FIG. [Example]

[0110] FIG. 8 is a circuit diagram showing another internal configuration of the gamma amplifier circuit GB1 that has been designed in consideration of the above points.

[0111] In addition, in the configuration shown in Figure 8, an output switch unit G_Out_b is used instead of the output switch unit G_Out_a shown in Figure 7, and a differential amplifier unit G_OCA having the same configuration as that shown in Figure 7 is used.

[0112] 7, the output switch section G_Out_b omits the level shifters LS1 and LS2, employs an output stage 30a as a second output stage instead of the output stage 30, and is provided with new switch elements 44 and 45. The connection and operation of the switch elements 41 and 43 are the same as those included in the output switch section G_Out shown in FIG.

[0113] 8, like the output stage 30, the output stage 30a includes a P-channel transistor 31 and an N-channel transistor 32 whose drains are connected to each other via an output node nd01.

[0114] A power supply voltage VDD is applied to the source of transistor 31, and a power supply voltage VS0 is applied to the source of transistor 32. Furthermore, output stage 30a includes switch elements 33 and 34 that are turned on when switch signal S1 is at logic level 1 and turned off when switch signal S1 is at logic level 0. When in the on state, switch element 33 supplies the power supply voltage VDD to the gate of transistor 31, thereby setting transistor 31 to the off state. When in the on state, switch element 34 supplies the power supply voltage VS0 to the gate of transistor 32, thereby setting transistor 32 to the off state.

[0115] Switch elements 44 and 45 are turned on when switch signal S2 is at logic level 1, and turned off when switch signal S2 is at logic level 0. When switch element 44 is turned on, it supplies Pch drive signal VP output from differential stage 10 to the gate of transistor 31. When switch element 45 is turned on, it supplies Nch drive signal VN output from differential stage 10 to the gate of transistor 32.

[0116] 5, the switch elements 41, 44, and 45 of the output switch section G_Out_b are turned off, and the switch elements 33 and 34 of the output stage 30a are turned on. As a result, the transistors 31 and 32 of the output stage 30a are both turned off, and the output stage 30a is inactivated.

[0117] 5, switch elements 41, 44, and 45 are turned on, and switch elements 33 and 34 are turned off. At this time, Pch drive signal VP is supplied to the gate of transistor 31, and Nch drive signal VN is supplied to the gate of transistor 32. As a result, current based on Pch drive signal VP or Nch drive signal VN is sent to output node nd01 not only from output stage 20 but also from output stage 30a, making it possible to quickly suppress voltage fluctuations in gamma voltage VG1.

[0118] 8, the switch element 41 serving as the output switch element can be smaller in size than the other switch elements. In the second step, the output stage 30a generates the gamma voltage VG1 based on the Pch drive signal VP or the Nch drive signal VN, so the switch element 41 may not be provided. [Example]

[0119] FIG. 9 is a circuit diagram showing the internal configuration of a grayscale voltage generating circuit 122_a as another embodiment of the grayscale voltage generating circuit 122. In FIG.

[0120] The grayscale voltage generating circuit 122_a employs gamma amplifier circuits GB1_a to GBm_a instead of the gamma amplifier circuits GB1 to GBm, and employs a gamma control circuit CNT_a instead of the gamma control circuit CNT. Except for this, the other configurations (GA0, GA1, LD1, GSL, GB0, GB(m+1), LD2) are the same as those shown in FIG. 3.

[0121] The gamma control circuit CNT_a, like the gamma control circuit CNT, supplies a gamma characteristic designation signal de that designates a gamma characteristic to the gamma selector GSL. The gamma control circuit CNT_a also generates binary (logical level 0 or 1) switch signals S1 and S2 shown in Fig. 5 in response to a timing control signal included in the control signal Sgma, and supplies them to the gamma amplifier circuits GB1_a to GBm_a, respectively.

[0122] Furthermore, the gamma control circuit CNT_a generates a tap selection signal group TG associated with each of the gamma amplifier circuits GB1_a to GBm_a, and selects a tap of the resistor string LD2 to which the gamma voltage VG generated by each of the gamma amplifier circuits GB1_a to GBm_a is applied. That is, each of the gamma amplifier circuits GB1_a to GBm_a has a tap selection function that enables it to apply the gamma voltage VG generated by itself to any one of the multiple taps of the resistor string LD2 in accordance with the tap selection signal group TG.

[0123] 9, each of the gamma amplifier circuits GB1_a to GBm_a is connected to two different taps of the resistor string LD2 via a pair of wirings Lx (x is an integer from 1 to m)_1 and Lx_2. At this time, each of the gamma amplifier circuits GB1_a to GBm_a receives a pair of tap selection signals Tx_1 and Tx_2 corresponding to itself from the tap selection signal group TG. Then, each of the gamma amplifier circuits GB1_a to GBm_a selects one of the wirings Lx_1 and Lx_2 in accordance with the tap selection signals Tx_1 and Tx_2, and outputs the gamma voltage VGx generated by itself to the tap of the resistor string LD2 via this one wiring.

[0124] Here, since the gamma amplifier circuits GB1_a to GBm_a have the same internal configuration, the internal configuration of the gamma amplifier circuit GB1_a will be explained below.

[0125] FIG. 10 is a circuit diagram showing an example of the internal configuration of the gamma amplifier circuit GB1_a.

[0126] The gamma amplifier circuit GB1_a employs two output switch units G_Out_1 and G_Out_2 instead of the output switch unit G_Out shown in FIG. 4, and the other configurations, i.e., the differential amplifier unit G_OCA, are the same as those shown in FIG.

[0127] The output switch section G_Out_1 includes switch elements 41_1 and 43_1.

[0128] Both switch elements 41_1 and 43_1 receive a switch signal S2 and are both in an OFF state while the switch signal S2 is, for example, at logic level 0. On the other hand, when a switch signal S2 of logic level 1 is received, both switch elements 41_1 and 43_1 are in an ON state. At this time, the switch element 41_1 in the ON state outputs the output voltage VOk output from the output stage 20 of the differential amplifier unit G_OCA as a gamma voltage VG1 to the tap TP1 of the resistor string LD2 via the output node nd01 and the line L1_1. The switch element 43_1 in the ON state supplies the voltage of the output node nd01 to the differential amplifier unit G_OCA as a feedback voltage Vfb.

[0129] The output switch unit G_Out_1 receives a tap selection signal T1_1 corresponding to itself from the tap selection signal group TG output from the gamma control circuit CNT_a, and the output switch unit G_Out_2 receives a tap selection signal T1_2 corresponding to itself. At this time, when the gamma control circuit CNT_a causes the gamma amplifier circuit GB1_a to output the gamma voltage VG1 to the tap TP1 of the resistor string LD2, it supplies the tap selection signal T1_1 of logic level 1 indicating selection to the output switch unit G_Out_1, and supplies the tap selection signal T1_2 of logic level 0 indicating non-selection to the output switch unit G_Out_2.

[0130] On the other hand, when the gamma amplifier circuit GB1_a is to output the gamma voltage VG1 to the tap TP2 of the resistor string LD2, the gamma control circuit CNT_a supplies a tap selection signal T1_1 of logic level 0 indicating non-selection to the output switch unit G_Out_1, and supplies a tap selection signal T1_2 of logic level 1 indicating selection to the output switch unit G_Out_2.

[0131] When the output switch section G_Out_1 receives a tap selection signal T1_1 of logic level 1, it performs an on / off operation in accordance with the switch signal S2, but when it receives a tap selection signal T1_1 of logic level 0, it fixes both switch elements 41_1 and 43_1 to the off state regardless of the switch signal S2, becoming in a so-called inactive state.

[0132] When the output switch section G_Out_2 receives a tap selection signal T1_2 of logic level 1, it performs an on / off operation in accordance with the switch signal S2, but when it receives a tap selection signal T1_2 of logic level 0, it fixes both switch elements 41_2 and 43_2 to the off state regardless of the switch signal S2, becoming in a so-called inactive state.

[0133] As a result, the gamma amplifier circuit GB1_a outputs the gamma voltage VG1 corresponding to the reference voltage VI1 input to the differential amplifier section G_OCA to one of the taps TP1 and TP2 of the resistor string LD2 in accordance with the tap selection signals T1_1 and T1_2.

[0134] Therefore, according to the gradation voltage generation circuit 122_a, each gamma amplifier circuit (GB1_a to GBm_a) can switch the tap of the resistor string LD2 to which the gamma voltage VG is applied, making it possible to generate gradation voltages VR0 to VR(n-1) that conform to various gamma characteristics.

[0135] In order to improve the driving capability of each of the gamma amplifier circuits (GB1_a to GBm_a), a second output stage such as the output stage 30a shown in FIG. 8 may be provided in each of the multiple output switch sections included in each of the gamma amplifier circuits. [Example]

[0136] FIG. 11 is a circuit diagram showing the internal configuration of the gamma amplifier circuit GB1_a selected from the gamma amplifier circuits GB1_a to GBm_a each having the second output stage added thereto.

[0137] The gamma amplifier circuit GB1_a employs output switch units G_Out_1a and G_Out_2a instead of the output switch units G_Out_1 and G_Out_2 shown in FIG. 10, and the other configurations, i.e., the differential amplifier unit G_OCA, are the same as those shown in FIG. 10.

[0138] The output switch section G_Out_1a is obtained by adding new switch elements 44_1 and 45_1 and an output stage 30a_1 to the switch elements 41_1 and 43_1 that constitute the output switch section G_Out_1 shown in FIG.

[0139] The output stage 30a_1 includes a P-channel transistor 31_1 and an N-channel transistor 32_1 whose drains are connected to each other via an output node nd01 that is connected to a tap TP1 of the resistor string LD2 via a wiring L1_1.

[0140] The source of the transistor 31_1 is applied with the power supply voltage VDD, and the source of the transistor 32_1 is applied with the power supply voltage VS0.

[0141] Furthermore, the output stage 30a_1 includes switch elements 33_1 and 34_1 that are turned on when the switch signal S1 is at logic level 1 and turned off when the switch signal S1 is at logic level 0. When the switch element 33_1 is in the on state, it supplies a power supply voltage VDD to the gate of the transistor 31_1 to set the transistor 31_1 to the off state. When the switch element 34_1 is in the on state, it supplies a power supply voltage VS0 to the gate of the transistor 32_1 to set the transistor 32_1 to the off state.

[0142] The switch elements 41_1, 43_1, 44_1, and 45_1 are turned on when the switch signal S2 is at logic level 1, and turned off when the switch signal S2 is at logic level 0.

[0143] When the switch element 41_1 is in an ON state, it outputs the output voltage VOk output from the output stage 20 as a gamma voltage VG1 to the tap TP1 of the resistor string LD2 via the output node nd01 and the line L1_1.

[0144] When the switch element 43_1 is in an on state, it supplies the voltage of the output node nd01 to the differential amplifier part G_OCA as a feedback voltage Vfb.

[0145] When the switch element 44_1 is in the ON state, it supplies the Pch drive signal VP output from the differential stage 10 to the gate of the transistor 31_1. When the switch element 45_1 is in the ON state, it supplies the Nch drive signal VN output from the differential stage 10 to the gate of the transistor 32_1.

[0146] 5, the switch elements 41_1, 44_1, and 45_1 of the output switch section G_Out_1a are turned off, and the switch elements 33_1 and 34_1 of the output stage 30a_1 are turned on. As a result, the transistors 31_1 and 32_1 of the output stage 30a_1 are both turned off, and the output stage 30a_1 is inactivated.

[0147] 5, the switch elements 41_1, 44_1, and 45_1 are turned on, and the switch elements 33_1 and 34_1 are turned off. Therefore, at this time, the Pch drive signal VP is supplied to the gate of the transistor 31_1, and the Nch drive signal VN is supplied to the gate of the transistor 32_1. As a result, a current based on the Pch drive signal VP or the Nch drive signal VN is sent to the output node nd01 not only from the output stage 20 but also from the output stage 30a_1, thereby enabling voltage fluctuations in the gamma voltage VG1 to be quickly suppressed.

[0148] The output switch section G_Out_2a has the same configuration as the output switch section G_Out_1a, that is, it includes switch elements 43_2, 44_2, 41_2, and 45_2, and an output stage 30a_2 as a second output stage.

[0149] The output stage 30a_2 includes a P-channel transistor 31_2 and an N-channel transistor 32_2 whose drains are connected to each other via an output node nd02 that is connected to a tap TP2 of the resistor string LD2 via a wiring L1_2.

[0150] The source of the transistor 31_2 is applied with the power supply voltage VDD, and the source of the transistor 32_2 is applied with the power supply voltage VS0.

[0151] Furthermore, the output stage 30a_2 includes switch elements 33_2 and 34_2 that are turned on when the switch signal S1 is at logic level 1 and turned off when the switch signal S1 is at logic level 0. When the switch element 33_2 is in the on state, it supplies the power supply voltage VDD to the gate of the transistor 31_2 to set the transistor 31_2 to the off state. When the switch element 34_2 is in the on state, it supplies the power supply voltage VS0 to the gate of the transistor 32_2 to set the transistor 32_2 to the off state.

[0152] The switch elements 41_2, 43_2, 44_2, and 45_2 are turned on when the switch signal S2 is at logic level 1, and turned off when the switch signal S2 is at logic level 0.

[0153] When the switch element 41_2 is in an ON state, it outputs the output voltage VOk output from the output stage 20 as a gamma voltage VG1 to the tap TP2 of the resistor string LD2 via the output node nd02 and the line L1_2.

[0154] When the switch element 43_2 is in an on state, it supplies the voltage of the output node nd02 to the differential amplifier part G_OCA as a feedback voltage Vfb.

[0155] When the switch element 44_2 is in the ON state, it supplies the Pch drive signal VP output from the differential stage 10 to the gate of the transistor 31_2. When the switch element 45_2 is in the ON state, it supplies the Nch drive signal VN output from the differential stage 10 to the gate of the transistor 32_2.

[0156] 5, the switch elements 41_2, 44_2, and 45_2 of the output switch section G_Out_2a are turned off, and the switch elements 33_2 and 34_2 of the output stage 30a_2 are turned on. As a result, the transistors 31_2 and 32_2 of the output stage 30a_2 are both turned off, and the output stage 30a_2 is inactivated.

[0157] 5, the switch elements 41_2, 44_2, and 45_2 are turned on, and the switch elements 33_2 and 34_2 are turned off. Therefore, at this time, the Pch drive signal VP is supplied to the gate of the transistor 31_2, and the Nch drive signal VN is supplied to the gate of the transistor 32_2. As a result, a current based on the Pch drive signal VP or the Nch drive signal VN is sent to the output node nd02 not only from the output stage 20 but also from the output stage 30a_2, thereby enabling voltage fluctuations in the gamma voltage VG1 to be quickly suppressed.

[0158] Incidentally, the output switch section G_Out_1a receives the tap selection signal T1_1 in the same way as the output switch section G_Out_1, and the output switch section G_Out_2a receives the tap selection signal T1_2 in the same way as the output switch section G_Out_2. At this time, in accordance with the tap selection signals T1_1 and T1_2, one of the output switch sections G_Out_1a and G_Out_2a becomes active and the other becomes inactive in a complementary manner, in the same way as the output switch sections G_Out_1 and G_Out_2.

[0159] As a result, the gamma amplifier circuit GB1_a shown in FIG. 11 can also select the tap of the resistor string LD2 to which the gamma voltage VG1 generated by itself is to be applied from among the taps TP1 and TP2 using the tap selection signals T1_1 and T1_2.

[0160] 11, the switch elements 41_1 and 41_2 serving as the first and second output switch elements can be smaller in size than the other switch elements. Also, the switch elements 41_1 and 41_2 may not be provided. [Example]

[0161] FIG. 12 is a circuit diagram showing the internal configuration of a differential amplifier unit G_OCA_a as another embodiment of the differential amplifier unit G_OCA described above.

[0162] The differential amplifier unit G_OCA_a shown in FIG. 12 is configured by replacing the differential stage 10 included in the differential amplifier unit G_OCA shown in FIG. 4 with a differential stage 10a, and the other configurations are the same as the internal configuration of the differential amplifier unit G_OCA.

[0163] In the differential stage 10a, P-channel transistors 11 and 12 are used as the differential pair (11, 12) instead of the N-channel transistors shown in FIG. 4, and the other configurations are the same as those shown in FIG.

[0164] As shown in FIG. 12, when P-channel transistors are used as the transistors of the differential pair (11, 12), a current source Id that receives a power supply voltage VDI and generates a constant current is connected to the sources of the transistors 11 and 12, and the drains of the transistors are connected to a node nd14 on the input side and a node nd13 on the output side of the Nch current mirror circuit CM2, respectively, as shown in FIG.

[0165] As described above, in the configuration shown in Fig. 12, the differential pair (11, 12) forming the operational amplifier and the differential pair (13, 14) for offset cancellation are configured with different conductivity types. In this case, the configuration shown in Fig. 12 uses a load circuit in which the Pch current mirror circuit CM1 and the Nch current mirror circuit CM2 are current-coupled via two floating current sources FG1 and FG2, so offset cancellation can be performed correctly even if the conductivity types of the two differential pairs described above are different.

[0166] As shown in FIG. 12, the differential amplifier unit G_OCA_a, in which the differential pair (11, 12) forming the operational amplifier and the differential pair (13, 14) for offset cancellation are configured with different conductivity types, can be applied to all of the above-mentioned embodiments.

[0167] In addition, in the grayscale voltage generation circuit 122 or 122_a as a level voltage generation circuit, the reference voltages VI0 to VI(m+1) are generated by a reference voltage generation unit consisting of amplifiers GA0 and GA1, a resistor string LD1, and a gamma selector GSL, but the present invention is not limited to this configuration. In other words, the reference voltage generation unit may be any circuit that generates a plurality of reference voltages according to the desired gamma characteristics.

[0168] Furthermore, in the above embodiment, all of the gamma amplifier circuits GB1 to GBm are configured with offset cancellation amplifiers, but it is sufficient if at least one of these gamma amplifier circuits GB1 to GBm is an offset cancellation amplifier equipped with an offset cancellation circuit.

[0169] Furthermore, in the above-described embodiment, the offset cancellation circuit is configured with transistors 13 and 14, switch elements 15 to 18, capacitors Ca and Cb, and current source Is, but is not limited to this configuration. In other words, the configuration of the offset cancellation circuit itself is not limited as long as it detects the offset component occurring in the output voltage in the first step shown in Fig. 5 and then generates an output voltage from which the detected offset component has been removed in the second step.

[0170] In short, the level generation circuit (grayscale voltage generation circuit) according to the present invention may have the following resistor string, reference voltage generation unit, and 1st to mth (m is an integer of 2 or more) gamma amplifier circuits.

[0171] That is, the resistor string (LD2) includes a plurality of resistors connected in series with each other via each of a plurality of taps, and outputs n level voltages (VR0 to VR(n-1)) having different voltage levels from n (n is an integer equal to or greater than 2) taps out of the plurality of taps.

[0172] The reference voltage generating units (GA0, GA1, LD1, GSL) generate m reference voltages (VI1 to VIm) that conform to desired gamma characteristics.

[0173] The first to mth gamma amplifier circuits (GB1 to GBm, GB1_a to GBm_a) each individually receive m reference voltages, amplify the received reference voltages individually to generate m gamma voltages (VG1 to VGm), and output these m gamma voltages to m taps out of the multiple taps via the output node (nd01) included in each of them.

[0174] Here, at least one of the first to mth gamma amplifier circuits is an offset cancellation amplifier that generates an output voltage (VOk) at an intermediate node (nd20) included in itself by amplifying a reference voltage received by itself, and removes an offset occurring in this output voltage.

[0175] Such an offset cancellation amplifier sequentially performs the following steps: a first step of detecting the offset voltage occurring in the output voltage with the connection between its intermediate node and one of the m taps (TP1) cut off; and a second step of connecting the intermediate node (nd20) to the first tap (TP1) via the output node (nd01) and outputting the output voltage corrected for the offset voltage as a gamma voltage (VG) to the first tap (TP1).

[0176] According to this configuration, it is possible to generate gamma voltages having desired voltage values ​​with high precision without increasing the size of each of the transistors that make up the gamma amplifier circuit.

[0177] Furthermore, this offset cancellation amplifier detects the offset that occurs in the output voltage obtained by amplifying the reference voltage while the electrical connection to the resistor string is cut off, which makes it possible to detect the offset with high accuracy without being affected by the current flowing through the resistor string.

[0178] Therefore, according to the present invention, it is possible to suppress an increase in the circuit scale and to output a plurality of desired voltage levels from the resistor string with high precision. [Explanation of symbols]

[0179] 41-43 Switch element 103 Data Driver 122 Gradation voltage generation circuit 123 Decoder section CNT, CNTa control circuit GB1~GBm Gamma amplifier circuit G_OCA Differential amplifier G_Out Output switch section LD2 resistor string

Claims

1. a resistor string including a plurality of resistors connected in series to each other via a plurality of taps, and outputting n-level voltages having different voltage levels from n taps (n is an integer of 2 or more) of the plurality of taps; a reference voltage generating unit that generates m (m is an integer of 2 or more) reference voltages according to a desired gamma characteristic; first to m-th gamma amplifier circuits that individually receive the m reference voltages, individually amplify the received reference voltages to generate m gamma voltages, and output the m gamma voltages to m taps (m is an integer equal to or greater than 2) of the plurality of taps via output nodes included in each of the first to m-th gamma amplifier circuits; at least one of the first to mth Gamma amplifier circuits amplifies the reference voltage received by itself to generate an output voltage at an intermediate node included therein, and is an offset cancellation amplifier that removes an offset voltage occurring in the output voltage; The offset cancellation amplifier A level voltage generation circuit characterized by sequentially performing a first step of detecting the offset voltage occurring in the output voltage generated at the intermediate node of the circuit, and a second step of outputting the gamma voltage with the offset voltage corrected to the one tap.

2. The offset cancellation amplifier a differential stage having a first input terminal for receiving the reference voltage and a second input terminal for receiving a feedback voltage, including a differential pair for outputting a pair of currents corresponding to the difference between the reference voltage and the feedback voltage, and for outputting a drive signal having a voltage corresponding to the difference between the pair of currents; a first output stage that causes a current based on the drive signal to flow through the intermediate node, thereby causing the intermediate node to generate the output voltage; a first feedback switch element connected between the intermediate node and a second input terminal of the differential pair; a first output switch element connected between the intermediate node and the first tap; a second feedback switch element connected between the first tap and the second input terminal of the differential pair; in the first step, the first output switch element is turned off, the first feedback switch element is turned on, and the second feedback switch element is turned off, and the output voltage is fed back and supplied as the feedback voltage to the second input terminal of the differential pair via the first feedback switch element; 2. The level voltage generation circuit according to claim 1, wherein in the second step, the first output switch element is turned on, the first feedback switch element is turned off, and the second feedback switch element is turned on, so that the output voltage is output to the first tap as the gamma voltage via the first output switch element, and the gamma voltage output to the first tap is fed back and supplied to the second input terminal of the differential pair as the feedback voltage via the second feedback switch element.

3. 3. The level voltage generating circuit according to claim 2, further comprising a second output stage that receives the drive signal output from the differential stage via a level shifter and sends to the first tap a current based on the drive signal that has been level-shifted by the level shifter.

4. a control circuit for controlling the offset cancellation amplifier; The offset cancellation amplifier a first output switch section including the first output switch element and the second feedback switch element, a second output switch element connected between another tap different from the first tap and the intermediate node, and a third feedback switch element connected between the second input end of the differential stage and the other tap, the control circuit activates the first output switch unit and deactivates the second output switch unit when the gamma voltage is to be output to the one tap, and deactivates the first output switch unit and activates the second output switch unit when the gamma voltage is to be output to the other tap; 4. The level voltage generation circuit according to claim 3, wherein the second output switch element and the third feedback switch element included in the second output switch unit when activated are on / off controlled in the same manner as the on / off controls in the first step and the second step by the first output switch element and the second feedback switch element included in the first output switch unit when activated.

5. The offset cancellation amplifier a differential stage including a differential pair having a first input terminal for receiving the reference voltage and a second input terminal for receiving a feedback voltage, for outputting a pair of currents corresponding to a difference between the reference voltage and the feedback voltage, and for outputting a drive signal having a voltage corresponding to the difference between the pair of currents; a first output stage that causes a current based on the drive signal to flow through the intermediate node, thereby causing the intermediate node to generate the output voltage; a second output stage that delivers a current based on the drive signal to the first tap; a first feedback switch element connected between the second input terminal of the differential pair and the intermediate node; a second feedback switch element connected between the second input terminal of the differential pair and the first tap; in the first step, the first feedback switch element is turned on, the second feedback switch element is turned off, and the second output stage is inactivated, thereby feeding back and supplying the output voltage generated at the intermediate node as the feedback voltage to the second input terminal of the differential pair via the first feedback switch element; 2. The level voltage generation circuit according to claim 1, wherein in the second step, the first feedback switch element is turned off, the second feedback switch element is turned on, and the second output stage is activated, so that the output voltage generated by the second output stage is output to the first tap as the gamma voltage, and the gamma voltage output to the first tap is fed back and supplied to the second input terminal of the differential pair as the feedback voltage via the second feedback switch element.

6. the offset cancellation amplifier further includes a first output switch element connected between the intermediate node and the first tap; 6. The level voltage generating circuit according to claim 5, wherein the first output switch element is turned off in the first step, and the first output switch element is turned on in the second step.

7. a control circuit for controlling the offset cancellation amplifier; The offset cancellation amplifier a first output switch section including the second feedback switch element and a second output stage that sends a current based on the drive signal to the first tap, and a second output switch section including a third feedback switch element connected between another tap different from the first tap and the second input terminal of the differential stage, and a third output stage that sends a current based on the drive signal to the other tap; The control circuit When the gamma voltage is to be output to the first tap, the second output means and the third output stage are both inactivated in the first step, and the second output means is activated and the third output stage is inactivated in the second step; 6. The level voltage generating circuit according to claim 5, wherein, when the gamma voltage is to be output to the other tap, the second output means and the third output stage are both inactivated in the first step, and the third output means is activated and the second output stage is inactivated in the second step.

8. a control circuit for controlling the offset cancellation amplifier; The offset cancellation amplifier a differential stage having a first input terminal for receiving the reference voltage and a second input terminal for receiving a feedback voltage, including a differential pair for outputting a pair of currents corresponding to the difference between the reference voltage and the feedback voltage, and for outputting a drive signal having a voltage corresponding to the difference between the pair of currents; a first output stage that causes a current based on the drive signal to flow through the intermediate node, thereby causing the intermediate node to generate the output voltage; a first feedback switch element connected between the intermediate node and the second input terminal of the differential pair; a first output switch unit including a second output stage that outputs a current based on the drive signal to the first tap, and a second feedback switch element connected between the first tap and the second input terminal of the differential pair; a third output stage that outputs a current based on the drive signal to another tap different from the first tap, and a second output switch unit that includes a third feedback switch element connected between the other tap and the second input terminal of the differential pair, The control circuit When the gamma voltage is output to the first tap, in the first step, the first feedback switch element is turned on so that the output voltage generated by the first output stage is fed back and supplied to the second input terminal of the differential pair as the feedback voltage via the first feedback switch element, and the first output switch unit and the second output switch unit are deactivated; in the second step, the first feedback switch element is turned off, the first output switch unit is activated, and the second output switch unit is deactivated so that the output voltage generated by the second output stage is output to the first tap as the gamma voltage, and the second feedback switch element is turned on so that the gamma voltage output to the first tap is fed back and supplied to the second input terminal of the differential pair as the feedback voltage via the second feedback switch element; 2. The level voltage generation circuit according to claim 1, wherein, when the gamma voltage is to be output to the other tap, in the first step, the first feedback switch element is turned on to feed back and supply the output voltage generated by the first output stage to the second input terminal of the differential pair as the feedback voltage via the first feedback switch element, and the first output switch unit and the second output switch unit are deactivated; and in the second step, the first feedback switch element is turned off, the second output switch unit is activated, and the first output switch unit is deactivated to output the output voltage generated by the third output stage to the other tap as the gamma voltage, and the third feedback switch element is turned on to feed back and supply the gamma voltage output to the other tap to the second input terminal of the differential pair as the feedback voltage via the third feedback switch element.

9. a control circuit for controlling the offset cancellation amplifier; The offset cancellation amplifier a differential stage including a differential pair having a first input terminal for receiving the reference voltage and a second input terminal for receiving a feedback voltage, for outputting a pair of currents corresponding to a difference between the reference voltage and the feedback voltage, and for outputting a drive signal having a voltage corresponding to the difference between the pair of currents; a first output stage that causes a current based on the drive signal to flow through the intermediate node, thereby causing the intermediate node to generate the output voltage; The differential stage a first differential pair driven by a first tail current source; a second differential pair driven by a second tail current source; a current mirror circuit of a first conductivity type that receives a first power supply voltage and causes a current obtained by folding back an input current flowing through a first node to flow through a second node; a second conductivity type current mirror circuit that receives a second power supply voltage and causes a current obtained by folding back an input current flowing through a third node to flow through a fourth node; a first floating current source that combines the currents of the first and third nodes; a second floating current source that combines the currents of the second and fourth nodes; the first output stage: a first output transistor of a first conductivity type connected between a third power supply voltage and the intermediate node; a second output transistor of a second conductivity type connected between a fourth power supply voltage and the intermediate node; an output pair of the first differential pair is connected to either a first connection point pair consisting of the first node and the second node or a second connection point pair consisting of the third node and the fourth node; an output pair of the second differential pair is connected to one of the first pair of connection points or the second pair of connection points; a gate of each of the first output transistor and the second output transistor is connected to a node sandwiching the second floating current source on a current path that flows via the second node and the fourth node, a first input terminal of each of first and second capacitance elements is connected to an input pair of the second differential pair, and a predetermined power supply voltage is applied to a second input terminal of each of the first and second capacitance elements together with one terminal of the second tail current source; The control circuit In the first step, the reference voltage is input to each of the input pairs of the first differential pair, and a reference voltage is input to one of the input pairs of the second differential pair and a voltage of the intermediate node is input to the other of the input pairs of the second differential pair; 2. The level voltage generating circuit according to claim 1, wherein in the second step, the reference voltage is input to one of the input pair of the first differential pair and the voltage of the first tap is input to the other input pair of the first differential pair while blocking the input to the input pair of the second differential pair.

10. 10. The level voltage generating circuit according to claim 9, wherein the reference voltage is the same voltage as the reference voltage.

11. a control circuit for controlling the offset cancellation amplifier; The offset cancellation amplifier a first output switch section including the first output switch element and the second feedback switch element, a second output switch element connected between another tap different from the first tap and the intermediate node, and a third feedback switch element connected between the second input end of the differential stage and the other tap, the control circuit activates the first output switch unit and deactivates the second output switch unit when the gamma voltage is to be output to the one tap, and deactivates the first output switch unit and activates the second output switch unit when the gamma voltage is to be output to the other tap; 3. The level voltage generation circuit according to claim 2, wherein the second output switch element and the third feedback switch element included in the second output switch unit when activated are on / off controlled in the same manner as the on / off controls in the first step and the second step by the first output switch element and the second feedback switch element included in the first output switch unit when activated.

12. A display driver including the level voltage generating circuit according to any one of claims 1 to 11 as a grayscale voltage generating circuit, The display driver is characterized in that the first step is performed within a vertical blanking period of a frame period of a video signal.

Images