Display device

Abstract

To provide a display device capable of improving a display quality.SOLUTION: A display device according to an embodiment includes a plurality of pixels arranged along a first direction and a second direction intersecting the first direction, and each of the plurality of pixels includes: a first sub-pixel that emits light of a first color; a second sub-pixel that emits light of a second color different from the first color; and a third sub-pixel that emits light of a third color different from the first color and the second color. The plurality of pixels include: a first pixel in which the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged in a first array; and a second pixel in which the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged in a second array. The first array is an array in which the first sub-pixel and the second sub-pixel are arranged along the second direction, the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged along the first direction. The second array is an array line-symmetric to the first array with respect to an axis parallel to the first direction, and the first pixels and the second pixels are alternately arranged in the first direction.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Technology that can improve the display quality of these types of display devices is needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 [Patent Document 8] US Patent Application Publication No. 2018 / 0182827 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of improving display quality. [Means for solving the problem]

[0005] A display device according to one embodiment includes a plurality of pixels arranged along a first direction and a second direction intersecting the first direction, each of the plurality of pixels including a first subpixel that emits light of a first color, a second subpixel that emits light of a second color different from the first color, and a third subpixel that emits light of a third color different from the first color and the second color. The plurality of pixels includes a first pixel in which the first subpixel, the second subpixel, and the third subpixel are arranged in a first array, and a second pixel in which the first subpixel, the second subpixel, and the third subpixel are arranged in a second array. The first array is an array in which the first subpixel and the second subpixel are arranged along the second direction, and the first subpixel, the second subpixel, and the third subpixel are arranged in the first direction. The second array is an array that is line-symmetric to the first array with respect to an axis parallel to the first direction, and the first pixels and the second pixels are arranged alternately in the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of an arrangement of sub-pixels in a pixel. [Figure 3] FIG. 3 is a schematic plan view showing an example of the configuration of a pixel. [Figure 4] FIG. 4 is a schematic plan view of the rib layer of FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the display device taken along the line AA in FIG. [Figure 6] FIG. 6 is a schematic plan view showing an example of a layout of pixels in a display region. [Figure 7] FIG. 7 is a schematic plan view showing an enlarged view of the pixel shown in FIG. [Figure 8] FIG. 8 is a schematic plan view of a display device according to a comparative example. [Figure 9] FIG. 9 is a plan view for explaining the effect of the display device according to one embodiment. [Figure 10]FIG. 10 is a schematic plan view showing another example of the layout of pixels in the display region. [Figure 11] FIG. 11 is a schematic plan view showing yet another example of the layout of pixels in the display region. DETAILED DESCRIPTION OF THE INVENTION

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0008] In the drawings, mutually orthogonal X-, Y-, and Z-axes are shown as necessary to facilitate understanding. The direction along the X-axis is referred to as the X-direction (first direction), the direction along the Y-axis is referred to as the Y-direction (second direction), and the direction along the Z-axis is referred to as the Z-direction. Viewing various elements parallel to the Z-direction is referred to as a planar view.

[0009] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] 1 is a diagram showing an example of the configuration of a display device DSP according to one embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix along the X and Y directions. Each pixel PX includes a plurality of subpixels SP that emit light of different colors. In this embodiment, it is assumed that the pixel PX includes a subpixel SP1 (first subpixel) that emits red light (first color), a subpixel SP2 (second subpixel) that emits green light (second color), and a subpixel SP3 (third subpixel) that emits blue light (third color). However, the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0013] The color of light emitted by each of the subpixels SP1, SP2, and SP3 is not limited to the above example. For example, the subpixel SP1 may emit green light, the subpixel SP2 may emit red light, and the subpixel SP3 may emit blue light. Alternatively, the subpixel SP1 may emit red light, the subpixel SP2 may emit blue light, and the subpixel SP3 may emit green light.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the drive transistor 3 and the capacitor 4. The source electrode of the drive transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the drive transistor 3 is connected to the display element DE.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] 2A to 2D are schematic plan views showing examples of arrangements of subpixels SP1, SP2, and SP3 in a pixel PX. As shown in FIGS. 2A to 2D, the pixels PX arranged in the display area DA include pixels PX1, PX2, PX3, and PX4. The arrangements of subpixels SP1, SP2, and SP3 in the pixels PX1, PX2, PX3, and PX4 are different from each other.

[0019] Fig. 2(a) is a schematic plan view showing an example of the arrangement of subpixels SP1, SP2, and SP3 in pixel PX1. As shown in Fig. 2(a), in pixel PX1 (first pixel), subpixels SP1, SP2, and SP3 are arranged in an arrangement PT1 (first arrangement). In arrangement PT1, subpixels SP1 and SP2 are aligned along the Y direction, and subpixels SP1, SP2, and SP3 are aligned in the X direction.

[0020] Fig. 2(b) is a schematic plan view showing an example of the arrangement of subpixels SP1, SP2, and SP3 in pixel PX2. As shown in Fig. 2(b), in pixel PX2 (second pixel), subpixels SP1, SP2, and SP3 are arranged in an arrangement PT2 (second arrangement). The arrangement PT2 is an arrangement that is line-symmetrical to the arrangement PT1 shown in Fig. 2(a) with respect to an axis parallel to the X direction.

[0021] Fig. 2(c) is a schematic plan view showing an example of the arrangement of subpixels SP1, SP2, and SP3 in pixel PX3. As shown in Fig. 2(c), in pixel PX3 (third pixel), subpixels SP1, SP2, and SP3 are arranged in an arrangement PT3 (third arrangement). The arrangement PT3 is an arrangement that is line-symmetrical to the arrangement PT1 shown in Fig. 2(a) with respect to an axis parallel to the Y direction.

[0022] Fig. 2(d) is a schematic plan view showing an example of the arrangement of subpixels SP1, SP2, and SP3 in pixel PX4. As shown in Fig. 2(d), in pixel PX4 (fourth pixel), subpixels SP1, SP2, and SP3 are arranged in an arrangement PT4 (fourth arrangement). The arrangement PT4 is symmetrical to the arrangement PT3 shown in Fig. 2(c) with respect to an axis parallel to the X direction.

[0023] FIG. 3 is a schematic plan view showing an example of the configuration of pixel PX1. A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 (first to third pixel openings) that overlap with the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 3, pixel opening AP1 is smaller than pixel opening AP2, and pixel openings AP1 and AP2 are smaller than pixel opening AP3. That is, among the subpixels SP1, SP2, and SP3, subpixel SP1 has the smallest aperture ratio and subpixel SP3 has the largest aperture ratio. Note that the sizes of pixel openings AP1, AP2, and AP3 are not limited to this example. For example, pixel openings AP1 and AP2 may have the same size.

[0024] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel aperture AP3.

[0025] The lower electrode LE1, upper electrode UE1, and organic layer OR1 overlapping with the pixel aperture AP1 form the display element DE1 of the subpixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 overlapping with the pixel aperture AP2 form the display element DE2 of the subpixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 overlapping with the pixel aperture AP3 form the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0026] Partition walls 6 are arranged in the display area DA. The partition walls 6 are located above the rib layer 5 and entirely overlap the rib layer 5. In the example of FIG. 3, the partition walls 6 have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in the subpixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition walls 6 have a lattice shape in plan view and surround the display elements DE1, DE2, and DE3, respectively. The partition walls 6 also surround the pixel openings AP1, AP2, and AP3 in plan view. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0027] Figure 4 is a schematic plan view of the rib layer 5 in FIG. 3. As shown, the four sides of the pixel aperture AP1 surrounding the sub-pixel SP1 are defined as sides S1a, S1b, S1c, and S1d, the four sides of the pixel aperture AP2 surrounding the sub-pixel SP2 are defined as sides S2a, S2b, S2c, and S2d, and the four sides of the pixel aperture AP3 surrounding the sub-pixel SP3 are defined as sides S3a, S3b, S3c, and S3d. Sides S1a, S1b, S2a, S2b, S3a, and S3b are parallel to the X direction. Sides S1c, S1d, S2c, S2d, S3c, and S3d are parallel to the Y direction.

[0028] The pixel aperture AP1 has a width W1x along the X direction and a width W1y along the Y direction. The width W1x is equal to the distance along the X direction between side S1c and side S1d. The width W1y is equal to the distance along the Y direction between side S1a and side S1b. The pixel aperture AP2 has a width W2x along the X direction and a width W2y along the Y direction. The width W2x is equal to the distance along the X direction between side S2c and side S2d. The width W2y is equal to the distance along the Y direction between side S2a and side S2b. The pixel aperture AP3 has a width W3x along the X direction and a width W3y along the Y direction. The width W3x is equal to the distance along the X direction between side S3c and side S3d. The width W3y is equal to the distance along the Y direction between side S3a and side S3b.

[0029] In the example shown in FIG. 4, the width W1x is equal to the width W2x (W1x = W2x). Also, the width W1y is smaller than the width W2y (W1y < W2y). Further, the total width of the width W1y and the width W2y is smaller than the width W3y (W1y + W2y < W3y).

[0030] Pixel aperture AP1 has a center P1 (first center). In the example shown in FIG. 4, the distance between center P1 and side S1c in the X direction is equal to the distance between center P1 and side S1d in the X direction. That is, the distance between center P1 and side S1c in the X direction and the distance between center P1 and side S1d in the X direction correspond to half of the width W1x. Similarly, the distance between center P1 and side S1a in the Y direction is equal to the distance between center P1 and side S1b in the Y direction. That is, the distance between center P1 and side S1a in the Y direction and the distance between center P1 and side S1b in the Y direction correspond to half of the width W1y.

[0031] Pixel aperture AP2 has a center P2 (second center). In the example shown in FIG. 4, the distance between center P2 and side S2c in the X direction is equal to the distance between center P2 and side S2d in the X direction. That is, the distance between center P2 and side S2c in the X direction and the distance between center P2 and side S2d in the X direction correspond to half of the width W2x. Similarly, the distance between center P2 and side S2a in the Y direction is equal to the distance between center P2 and side S2b in the Y direction. That is, the distance between center P2 and side S2a in the Y direction and the distance between center P2 and side S2b in the Y direction correspond to half of the width W2y.

[0032] Pixel aperture AP3 has a center P3 (third center). In the example shown in FIG. 4, the distance between center P3 and side S3c in the X direction is equal to the distance between center P3 and side S3d in the X direction. That is, the distance between center P3 and side S3c in the X direction and the distance between center P3 and side S3d in the X direction correspond to half of the width W3x. Similarly, the distance between center P3 and side S3a in the Y direction is equal to the distance between center P3 and side S3b in the Y direction. That is, the distance between center P3 and side S3a in the Y direction and the distance between center P3 and side S3b in the Y direction correspond to half of the width W3y.

[0033] 5 is a schematic cross-sectional view of the display device DSP taken along line AA in FIG. 3. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0034] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 5, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 (the drain electrode of the drive transistor 3 shown in FIG. 1) through a contact hole provided in the organic insulating layer 12.

[0035] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0036] In the example of FIG. 5, the lower part 61 has a bottom layer 63 and a shaft layer 64. The bottom layer 63 is located between the shaft layer 64 and the rib layer 5 and is formed thinner than the shaft layer 64. In the example of FIG. 5, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0037] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0038] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0039] In the following description, the multilayer structure including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1 (first laminate film), the multilayer structure including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2 (second laminate film), and the multilayer structure including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3 (third laminate film).

[0040] A portion of the laminated film FL1 is located on the upper portion 62. This portion is separated from a portion of the laminated film FL1 that is located around the partition wall 6 (a portion that constitutes the display element DE1). Similarly, a portion of the laminated film FL2 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL2 that is located around the partition wall 6 (a portion that constitutes the display element DE2). Furthermore, a portion of the laminated film FL3 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL3 that is located around the partition wall 6 (a portion that constitutes the display element DE3).

[0041] The subpixels SP1, SP2, and SP3 are provided with sealing layers SE11, SE12, and SE13 (first to third sealing layers) that cover the stacked films FL1, FL2, and FL3, respectively. Specifically, the sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0042] 5, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE12 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE13 on the partition wall 6.

[0043] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0044] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0045] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0046] The lower electrodes LE1, LE2, and LE3 each include a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. The reflective layer can be made of a metal material with excellent light reflectivity, such as silver. Each conductive oxide layer can be made of a transparent conductive oxide, such as ITO (indium tin oxide), IZO (indium zinc oxide), or IGZO (indium gallium zinc oxide).

[0047] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0048] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0049] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0050] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0051] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. Examples of the metal material that can be used to form the lower layer include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the upper layer include ITO and IZO. The upper portion 62 may also have a single-layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0052] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0053] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the red wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength range.

[0054] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0055] Although the configuration of pixel PX1 has been described in detail in FIGS. 3 to 5, the same configuration as pixel PX1 can also be applied to pixels PX2, PX3, and PX4 shown in FIG.

[0056] Fig. 6 is a schematic plan view showing an example of the layout of pixels PX1 to PX4 in the display area DA. In the example shown in Fig. 6, pixels PX1 and PX2 are alternately arranged in the X direction, and pixels PX3 and PX4 are alternately arranged in the X direction. Furthermore, pixels PX1 and PX3 are alternately arranged in the Y direction, and pixels PX2 and PX4 are alternately arranged in the Y direction. In the display area DA, columns in which pixels PX1 and PX2 are alternately arranged in the X direction and columns in which pixels PX3 and PX4 are alternately arranged in the X direction are alternately arranged in the Y direction. From another perspective, in the display area DA, columns in which pixels PX1 and PX3 are alternately arranged in the Y direction and columns in which pixels PX2 and PX4 are alternately arranged in the Y direction are alternately arranged in the X direction.

[0057] Fig. 7 is a schematic plan view showing an enlargement of pixels PX1 to PX4 shown in Fig. 6. In one example, of two pixels PX adjacent to each other in the X direction, a center P1 of one pixel PX and a center P2 of the other pixel PX are arranged on a straight line parallel to the X direction. In addition, a center P3 of each of the two pixels PX adjacent to each other in the X direction is arranged on a straight line parallel to the X direction.

[0058] 7, pixels PX1 and PX2 are adjacent to each other in the X direction, and the center P1 of pixel PX1 and the center P2 of pixel PX2 are located on a straight line LX1 parallel to the X direction. Furthermore, the center P3 of each of pixels PX1 and PX2 is located on a straight line LX2 parallel to the X direction. Furthermore, the center P1 of pixel PX2 and the center P2 of pixel PX1 are located on a straight line LX3 parallel to the X direction.

[0059] 7, pixels PX3 and PX4 are adjacent to each other in the X direction, and the center P1 of pixel PX3 and the center P2 of pixel PX4 are located on a line LX4 parallel to the X direction. Furthermore, the center P3 of each of pixels PX3 and PX4 is located on a line LX5 parallel to the X direction. Furthermore, the center P1 of pixel PX4 and the center P2 of pixel PX3 are located on a line LX6 parallel to the X direction.

[0060] In one example, of two pixels PX adjacent to each other in the Y direction, the centers P1 and P2 of one pixel PX and the center P3 of the other pixel PX are arranged on a straight line parallel to the Y direction.

[0061] 7, pixels PX1 and PX3 are adjacent to each other in the Y direction, and centers P1 and P2 of pixel PX1 and center P3 of pixel PX3 are located on a straight line LY1 parallel to the Y direction. Centers P1 and P2 of pixel PX3 and center P3 of pixel PX1 are located on a straight line LY2 parallel to the Y direction.

[0062] 7, pixels PX2 and PX4 are adjacent to each other in the Y direction, and the centers P1 and P2 of pixel PX2 and the center P3 of pixel PX4 are located on a straight line LY3 ​​parallel to the Y direction. Also, the centers P1 and P2 of pixel PX4 and the center P3 of pixel PX2 are located on a straight line LY4 parallel to the Y direction.

[0063] An example of the effect achieved by this embodiment will now be described with reference to FIGS. FIG. 8 is a schematic plan view of a display device DSP according to a comparative example. In this comparative example, multiple pixels PX1 are arranged in a display area DA. The example shown in FIG. 8 shows multiple pixels PX1 that display white (four central pixels PX1) and multiple pixels PX1 that display black (pixels PX1 with dotted patterns) surrounding these pixels PX1. A first area AR1 is defined as a region between the subpixels SP1 and SP3 of the pixel PX1 that display white and the subpixels SP2 and SP3 of the pixel PX1 that display black. Similarly, a second area AR2 is defined as a region between the subpixels SP2 and SP3 of the pixel PX1 that display white and the subpixels SP1 and SP3 of the pixel PX1 that display black. A third area AR3 is defined as a region between the subpixels SP1 and SP2 of the pixel PX1 that display white and the subpixel SP3 of the pixel PX1 that display black. A fourth area AR4 is defined as a region between the subpixel SP3 of the pixel PX1 that display white and the subpixels SP1 and SP2 of the pixel PX1 that display black.

[0064] In the structure of this comparative example, the red subpixel SP1 and the blue subpixel SP3 overlap the first region AR1, the green subpixel SP2 and the blue subpixel SP3 overlap the second region AR2, the red subpixel SP1 and the green subpixel SP2 overlap the third region AR3, and the blue subpixel SP3 overlap the fourth region AR4. With this configuration, there is a risk that magenta, a mixture of red and blue, may be perceived in the first region AR1. Similarly, there is a risk that cyan, a mixture of green and blue, may be perceived in the second region AR2, yellow, a mixture of red and green, may be perceived in the third region AR3, and blue may be perceived in the fourth region AR4. If an unintended color is perceived at the boundary between a region where white is displayed and a region where black is displayed, the display quality of the display device DSP may be degraded.

[0065] 9 is a diagram for explaining the effect of the display device DSP according to this embodiment. In the example shown in FIG. 9, pixels PX1 to PX4 (the four central pixels PX1 to PX4) that display white and pixels PX1 to PX4 (pixels PX1 to PX4 with dotted patterns) that surround the pixels PX1 to PX4 and display black are shown. In the example shown in FIG. 9, the area between the pixels PX1 and PX2 that display white and the pixels PX3 and PX4 that display black is defined as a first area AR1. Similarly, the area between the pixels PX3 and PX4 that display white and the pixels PX1 and PX2 that display black is defined as a second area AR2, the area between the pixels PX1 and PX3 that display white and the pixels PX2 and PX4 that display black is defined as a third area AR3, and the area between the pixels PX2 and PX4 that display white and the pixels PX1 and PX3 that display black is defined as a fourth area AR4.

[0066] In this embodiment, the red subpixel SP1, the green subpixel SP2, and the blue subpixel SP3 overlap the first to fourth regions AR1 to AR4, respectively. With this configuration, a white color, which is a mixture of red, green, and blue, can be seen in the first to fourth regions AR1 to AR4. This makes the boundary between white and black clearer, improving the display quality of the display device DSP.

[0067] In the display device DSP according to this embodiment, of two pixels PX adjacent to each other in the X direction, the center P1 of one pixel PX and the center P2 of the other pixel PX are arranged on a straight line parallel to the X direction. Also, of two pixels PX adjacent to each other in the Y direction, the centers P1 and P2 of one pixel PX and the center P3 of the other pixel PX are arranged on a straight line parallel to the Y direction. This makes the boundary between white and black more distinct, improving the display quality of the display device DSP.

[0068] Fig. 10 is a schematic plan view showing another example of the layout of pixels PX1 and PX2 in the display area DA. In the example shown in Fig. 10, pixels PX1 and PX2 are arranged alternately in the X direction. In the display area DA, columns in which pixels PX1 and PX2 are arranged alternately in the X direction are repeatedly arranged in the Y direction. From another perspective, pixels PX1 are repeatedly arranged in the Y direction, and pixels PX2 are repeatedly arranged in the Y direction. Furthermore, in the display area DA, columns in which pixels PX1 are repeatedly arranged in the Y direction and columns in which pixels PX2 are repeatedly arranged in the Y direction are alternately arranged in the X direction.

[0069] In the pixel layout shown in FIG. 10, the same effects as those described above can be obtained in the first region AR1 and the second region AR2 shown in FIG.

[0070] Fig. 11 is a schematic plan view showing yet another example of the layout of pixels PX1 and PX3 in the display area DA. In the example shown in Fig. 11, pixels PX1 and PX3 are arranged alternately in the Y direction. In the display area DA, columns in which pixels PX1 and PX3 are arranged alternately in the Y direction are repeatedly arranged in the X direction. From another perspective, pixels PX1 are repeatedly arranged in the X direction, and pixels PX3 are repeatedly arranged in the X direction. Furthermore, in the display area DA, columns in which pixels PX1 are repeatedly arranged in the X direction and columns in which pixels PX3 are repeatedly arranged in the X direction are alternately arranged in the Y direction.

[0071] In the pixel layout shown in FIG. 11, the same effects as those described above can be obtained in the third region AR3 and the fourth region AR4 shown in FIG.

[0072] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0073] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0074] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0075] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axial layer, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, AP1, AP2, AP3...pixel aperture, P1, P2, P3...center, PT1, PT2, PT3, PT4...array.

Claims

1. a plurality of pixels arranged along a first direction and a second direction intersecting the first direction; Each of the plurality of pixels is a first subpixel that emits light of a first color; a second sub-pixel that emits light of a second color different from the first color; a third sub-pixel that emits light of a third color different from the first color and the second color; The plurality of pixels are a first pixel in which the first subpixel, the second subpixel, and the third subpixel are arranged in a first array; a second pixel in which the first subpixel, the second subpixel, and the third subpixel are arranged in a second array; the first arrangement is an arrangement in which the first subpixel and the second subpixel are aligned along the second direction, and the first subpixel, the second subpixel, and the third subpixel are aligned in the first direction, the second array is an array that is line-symmetric with the first array with respect to an axis that is parallel to the first direction, the first pixels and the second pixels are alternately arranged in the first direction; Display device.

2. The columns in which the first pixels and the second pixels are alternately arranged in the first direction are repeatedly arranged in the second direction. The display device according to claim 1 .

3. the first pixels are repeatedly arranged in the second direction, the second pixels are repeatedly arranged in the second direction, The display device according to claim 2 .

4. a rib layer having a first pixel opening overlapping the first subpixel, a second pixel opening overlapping the second subpixel, and a third pixel opening overlapping the third subpixel; the first pixel aperture has a first center; the second pixel aperture has a second center; the first center of one of the two pixels adjacent to each other in the first direction and the second center of the other pixel are arranged on a straight line parallel to the first direction; The display device according to claim 1 .

5. the third pixel opening has a third center; the third centers of two of the pixels adjacent to each other in the first direction are arranged on a straight line parallel to the first direction, The display device according to claim 4 .

6. a partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion; the partition wall is formed in a lattice shape surrounding the first pixel opening, the second pixel opening, and the third pixel opening in a plan view; The display device according to claim 5 .

7. The plurality of pixels are a third pixel in which the first subpixel, the second subpixel, and the third subpixel are arranged in a third array; a fourth pixel in which the first subpixel, the second subpixel, and the third subpixel are arranged in a fourth array, the third array is an array that is line-symmetric with the first array with respect to an axis that is parallel to the second direction, the fourth array is an array that is line-symmetric with the third array with respect to an axis that is parallel to the first direction, the third pixels and the fourth pixels are alternately arranged in the first direction, The display device according to claim 1 .

8. a column in which the first pixels and the second pixels are alternately arranged in the first direction, and a column in which the third pixels and the fourth pixels are alternately arranged in the first direction, are alternately arranged in the second direction; The display device according to claim 7 .

9. the first pixels and the third pixels are alternately arranged in the second direction, the second pixels and the fourth pixels are alternately arranged in the second direction, The display device according to claim 8 .

10. a rib layer having a first pixel opening overlapping the first subpixel, a second pixel opening overlapping the second subpixel, and a third pixel opening overlapping the third subpixel; the first pixel aperture has a first center; the second pixel aperture has a second center; the first center of one of the two pixels adjacent to each other in the first direction and the second center of the other pixel are arranged on a straight line parallel to the first direction; The display device according to claim 7 .

11. the third pixel opening has a third center; the third centers of two of the pixels adjacent to each other in the first direction are arranged on a straight line parallel to the first direction, The display device according to claim 10.

12. the first center and the second center of one of the two pixels adjacent to each other in the second direction and the third center of the other pixel are arranged on a straight line parallel to the second direction; The display device according to claim 11.

13. a width of the first pixel opening along the second direction is smaller than a width of the second pixel opening along the second direction; The display device according to claim 4 .

14. a width of the first pixel opening along the first direction is equal to a width of the second pixel opening along the first direction; The display device according to claim 4 .

15. a total width of the first pixel opening and the second pixel opening along the second direction is smaller than a width of the third pixel opening along the second direction; The display device according to claim 4 .

16. the first pixel aperture is smaller than the second pixel aperture; The display device according to claim 4 .

17. the first pixel opening and the second pixel opening are smaller than the third pixel opening; The display device according to claim 16.

18. The first color is red, the second color is green, and the third color is blue.

18. A display device according to any one of claims 1 to 17.

19. The first color is green, the second color is red, and the third color is blue.

18. A display device according to any one of claims 1 to 17.

20. The first color is red, the second color is blue, and the third color is green.

18. A display device according to any one of claims 1 to 17.

Images