Display device

Abstract

To provide a display device capable of suppressing degradation of display quality.SOLUTION: A display device according to an embodiment includes an organic insulating layer formed of an organic material, a first lower electrode arranged above the organic insulating layer, an inorganic insulating layer formed of an inorganic material and arranged between the organic insulating layer and the first lower electrode, and a rib layer having a first opening overlapping the first lower electrode, and the inorganic insulating layer overlaps the first opening in a planar view.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. In these types of display devices, there is a need for technology that can suppress degradation of display quality. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device that can suppress a decrease in display quality. [Means for solving the problem]

[0005] A display device according to one embodiment comprises an organic insulating layer formed of an organic material, a first lower electrode arranged above the organic insulating layer, an inorganic insulating layer formed of an inorganic material and arranged between the organic insulating layer and the first lower electrode, and a rib layer having a first opening that overlaps with the first lower electrode, wherein the inorganic insulating layer overlaps with the first opening in a planar view. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 3] FIG. 3 is a schematic plan view showing an enlargement of the subpixels SP1, SP2, and SP3 shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the display device DSP taken along the line AA' in FIG. [Figure 5] FIG. 5 is a schematic plan view showing an enlarged view of the vicinity of the contact holes CH1 and CH2 shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device DSP taken along the line BB' in FIG. [Figure 7] FIG. 7 is a schematic plan view showing an enlarged view of the vicinity of the contact hole CH3 shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the display device DSP taken along the line CC' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0008] In the drawings, mutually perpendicular X-axis, Y-axis, and Z-axis are shown as necessary to facilitate understanding. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis is referred to as the Y-direction, and the direction along the Z-axis is referred to as the Z-direction. Viewing various elements parallel to the Z-direction is referred to as a planar view.

[0009] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] 1 is a diagram showing an example of the configuration of a display device DSP according to one embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. However, the pixel PX may also include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0013] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0014] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the drive transistor 3 and the capacitor 4. The source electrode of the drive transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the drive transistor 3 is connected to the display element DE.

[0016] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, a column in which subpixels SP1 and SP2 are alternately arranged in the Y direction and a column in which multiple subpixels SP3 are repeatedly arranged in the Y direction are formed. These columns are alternately arranged in the X direction.

[0018] The layout and sizes of the subpixels SP1, SP2, and SP3 are not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 may be aligned in the X direction. Furthermore, at least two of the subpixels SP1, SP2, and SP3 may have the same size.

[0019] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 (first openings) in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel opening AP1 is smaller than the pixel opening AP2, and the pixel opening AP2 is smaller than the pixel opening AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the smallest aperture ratio and the subpixel SP3 has the largest aperture ratio.

[0020] Partition walls 6 are arranged in the display area DA. The partition walls 6 are located above the rib layer 5 and entirely overlap the rib layer 5. In the example of FIG. 2, the partition walls 6 have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in the subpixels SP1, SP2, and SP3. From another perspective, the partition walls 6 have a lattice shape in plan view and surround each of the pixel openings AP1, AP2, and AP3.

[0021] Subpixel SP1 has a display element DE1 including a lower electrode LE1 that overlaps pixel aperture AP1. Subpixel SP2 has a display element DE2 including a lower electrode LE2 that overlaps pixel aperture AP2. Subpixel SP3 has a display element DE3 including a lower electrode LE3 that overlaps pixel aperture AP3. The lower electrodes LE1, LE2, and LE3 are spaced apart from one another.

[0022] The pixel circuits 1 of the subpixels SP1, SP2, and SP3 (see FIG. 1) are disposed below the lower electrodes LE1, LE2, and LE3, respectively. The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 through a contact hole CH1 (first contact hole). The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2 (second contact hole). The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0023] An inorganic insulating layer 7 is disposed in the display region DA. The inorganic insulating layer 7 is located below the rib layer 5 and the partition walls 6. The inorganic insulating layer 7 overlaps with the pixel openings AP1, AP2, and AP3 in plan view.

[0024] The inorganic insulating layer 7 has openings 71 and 72 (second openings). The openings 71 and 72 overlap with the rib layer 5 and the partition wall 6 in a plan view. The opening 71 is located between the pixel openings AP1 and AP2 in the Y direction. The opening 72 is disposed between two pixel openings AP3 adjacent to each other in the Y direction. The contact holes CH1 and CH2 overlap with the opening 71 in a plan view. The contact hole CH3 overlaps with the opening 72 in a plan view.

[0025] Fig. 3 is a schematic plan view showing an enlargement of the subpixels SP1, SP2, and SP3 shown in Fig. 2. The display element DE1 of the subpixel SP1 further includes an upper electrode UE1 and an organic layer OR1 that overlap with the pixel aperture AP1. The display element DE2 of the subpixel SP2 further includes an upper electrode UE2 and an organic layer OR2 that overlap with the pixel aperture AP2. The display element DE3 of the subpixel SP3 further includes an upper electrode UE3 and an organic layer OR3 that overlap with the pixel aperture AP3. The upper electrodes UE1, UE2, and UE3 and the organic layers OR1, OR2, and OR3 overlap with the inorganic insulating layer 7 in a plan view.

[0026] In the example of FIG. 3, the lower electrode LE1 has a convex portion PR1 (first convex portion) formed in a convex shape toward the lower electrode LE2, and the lower electrode LE2 has a convex portion PR2 (second convex portion) formed in a convex shape toward the lower electrode LE1. The convex portions PR1 and PR2 overlap with the opening 71 in a planar view. The contact holes CH1 and CH2 overlap with the convex portions PR1 and PR2, respectively, in a planar view. Note that the lower electrodes LE1 and LE2 do not necessarily have the convex portions PR1 and PR2, respectively. Furthermore, the lower electrode LE3 may have a convex portion that overlaps with the contact hole CH3 in a planar view.

[0027] 3, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed-dotted lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the figure do not necessarily reflect the exact shapes.

[0028] 4 is a schematic cross-sectional view of the display device DSP taken along line A-A' in FIG. 3. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is disposed below and covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0029] The lower electrodes LE1, LE2, and LE3 are disposed above the organic insulating layer 12. The inorganic insulating layer 7 is disposed between the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The lower electrodes LE1 and LE2 contact the organic insulating layer 12 at the opening 71. The inorganic insulating layer 7 is formed to be thicker than the lower electrodes LE1, LE2, and LE3.

[0030] The rib layer 5 is disposed on the organic insulating layer 12, the inorganic insulating layer 7, and the lower electrodes LE1, LE2, and LE3. The rib layer 5 contacts the organic insulating layer 12 between the lower electrodes LE1 and LE2, and contacts the inorganic insulating layer 7 between the lower electrodes LE2 and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered with the rib layer 5.

[0031] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0032] In the example of FIG. 4, the lower part 61 has a conductive bottom layer 63 arranged on the rib layer 5 and a shaft layer 64 arranged on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Also, in the example of FIG. 4, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64. The opening 71 overlaps with the bottom layer 63 in a plan view.

[0033] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0034] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0035] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0036] A portion of the laminated film FL1 is located on the upper portion 62. This portion is separated from a portion of the laminated film FL1 that is located around the partition wall 6 (a portion that constitutes the display element DE1). Similarly, a portion of the laminated film FL2 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL2 that is located around the partition wall 6 (a portion that constitutes the display element DE2). Furthermore, a portion of the laminated film FL3 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL3 that is located around the partition wall 6 (a portion that constitutes the display element DE3).

[0037] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0038] 4, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE12 on the partition wall 6. In addition, the stacked film FL2 and the sealing layer SE12 on the partition wall 6 between the subpixels SP2 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE13 on the partition wall 6.

[0039] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0040] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0041] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5, the inorganic insulating layer 7, and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the inorganic insulating layer 7 is formed of the same material as the rib layer 5. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0042] As will be described in detail later, the lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), or IGZO (indium gallium zinc oxide).

[0043] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0044] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0045] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0046] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0047] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. Examples of the metal material that can be used to form the lower layer include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the upper layer include ITO and IZO. The upper portion 62 may also have a single-layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0048] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0049] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the red wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the blue wavelength range.

[0050] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0051] 5 is a schematic plan view showing an enlarged view of the vicinity of the contact holes CH1 and CH2 shown in FIG. 3. As shown in FIG. 5, a first region AR1 is formed in the display area DA, which corresponds to a region located between the lower electrodes LE1 and LE2 and overlapping with the opening 71. That is, the first region AR1 does not overlap with the lower electrodes LE1 and LE2 and the inorganic insulating layer 7 in a planar view. The partition wall 6 covers the first region AR1 in a planar view. In the example of FIG. 5, the first region AR1 contacts the protrusions PR1 and PR2 in a planar view. In addition, in the example of FIG. 5, the first region AR1 is indicated by diagonal hatching.

[0052] The lower electrode LE1 has a first side S11. The lower electrode LE2 has a second side S12. The first side S11 and the second side S12 extend in the X direction. The first side S11 is located between the pixel opening AP1 and the contact hole CH2 in the Y direction. In the example shown in FIG. 5, the first side S11 is located between the pixel opening AP1 and the contact hole CH1 in the Y direction. The second side S12 is located between the pixel opening AP2 and the contact hole CH1 in the Y direction. In the example shown in FIG. 5, the second side S12 is located between the pixel opening AP2 and the contact hole CH2 in the Y direction.

[0053] The protrusion PR1 protrudes from the first side S11 toward the lower electrode LE2 and overlaps with the contact hole CH1. The protrusion PR2 protrudes from the second side S12 toward the lower electrode LE1 and overlaps with the contact hole CH2. In the example of FIG. 5, the protrusions PR1 and PR2 have a trapezoidal shape.

[0054] The opening 71 has a first edge E11 and a second edge E12. The first edge E11 extends in the X direction. The second edge E12 faces the first edge E11 in the Y direction and extends in the X direction.

[0055] The first edge E11 is located between the contact hole CH1 and the pixel opening AP1 in the Y direction and overlaps with the partition wall 6 in a plan view. In the example shown in FIG. 5, the first edge E11 is located between the first side S11 and the pixel opening AP1 in the Y direction. The second edge E12 is located between the contact hole CH2 and the pixel opening AP2 in the Y direction and overlaps with the partition wall 6 in a plan view. In the example shown in FIG. 5, the second edge E12 is located between the second side S12 and the pixel opening AP2 in the Y direction. The first edge E11 may be located between the first side S11 and the contact hole CH1 in the Y direction. The second edge E12 may be located between the second side S12 and the contact hole CH2 in the Y direction.

[0056] Fig. 6 is a schematic cross-sectional view of the display device DSP taken along line BB' in Fig. 5. In Fig. 6 and Fig. 8 described later, the substrate 10, resin layers RS1 and RS2, and sealing layer SE2 shown in Fig. 4 are omitted. The rib layer 5 contacts the organic insulating layer 12 in the first region AR1. The bottom layer 63 covers the first region AR1 in plan view.

[0057] The contact hole CH1 is provided in the organic insulating layer 12 and penetrates the organic insulating layer 12. The lower electrode LE1 is in contact with the conductive layer CL included in the circuit layer 11 through the contact hole CH1. The conductive layer CL corresponds to, for example, the source electrode or drain electrode of the driving transistor 3 shown in FIG.

[0058] As shown enlarged in the lower part of Figure 6, each of the lower electrodes LE1 and LE2 includes a metal layer ML, a first layer L1 covering the upper surface of the metal layer ML, and a second layer L2 covering the lower surface of the metal layer ML. The metal layer ML is a reflective layer made of, for example, silver. The first layer L1 and the second layer L2 are conductive oxide layers made of, for example, a transparent conductive oxide such as ITO.

[0059] In one example, the thickness of the second layer L2 is smaller than the thickness of each of the first layer L1 and the metal layer ML. The thickness of the first layer L1 is smaller than or equal to the thickness of the metal layer ML. The relationship between the thicknesses of the metal layer ML, the first layer L1, and the second layer L2 is not limited to the above example. For example, the thickness of the second layer L2 may be larger than the thickness of each of the first layer L1 and the metal layer ML.

[0060] 5 is provided in the organic insulating layer 12 and penetrates the organic insulating layer 12, similar to the contact hole CH1, although not shown in the figure. The lower electrode LE2 is in contact with the conductive layer CL included in the circuit layer 11 through the contact hole CH2.

[0061] 7 is a schematic plan view showing an enlarged view of the vicinity of the contact hole CH3 shown in FIG. 3. As shown in FIG. 7, a second region AR2 is formed in the display area DA. The second region AR2 is located between two lower electrodes LE3 adjacent in the Y direction and corresponds to a region overlapping with the opening 72. In other words, the second region AR2 does not overlap with the lower electrode LE3 or the inorganic insulating layer 7. The partition wall 6 covers the second region AR2 in plan view. In the example of FIG. 7, the second region AR2 is indicated by diagonal hatching.

[0062] The lower electrode LE3 has a third side S13 and a fourth side S14. The third side S13 and the fourth side S14 extend in the X direction. The third side S13 corresponds to the side of the lower electrode LE3 on which the contact hole CH3 is located. The fourth side S14 corresponds to the side located on the opposite side of the pixel aperture AP3 from the third side S13 in the Y direction.

[0063] The opening 72 has a third edge E13 and a fourth edge E14. The third edge E13 extends in the X direction. The fourth edge E14 faces the third edge E13 in the Y direction and extends in the X direction.

[0064] The third edge E13 is located between the contact hole CH3 and the pixel opening AP3 in the Y direction and overlaps with the partition wall 6 in plan view. In the example shown in FIG. 7, the third edge E13 is located between the third side S13 and the pixel opening AP3 in the Y direction. The fourth edge E14 overlaps with the partition wall 6 in plan view. In the example shown in FIG. 7, the fourth edge E14 is located between the third side S13 and the fourth side S14 in the Y direction. The third edge E13 may be located between the third side S13 and the fourth side S14 in the Y direction. The fourth edge E14 may also be located between the fourth side S14 and the pixel opening AP3 in the Y direction.

[0065] 8 is a schematic cross-sectional view of the display device DSP taken along line CC' in FIG. 7. The lower electrode LE3 contacts the organic insulating layer 12 in an opening 72. The opening 72 overlaps with the bottom layer 63 of the partition wall 6 in a plan view. The rib layer 5 contacts the organic insulating layer 12 in a second region AR2. The bottom layer 63 covers the second region AR2 in a plan view.

[0066] The contact hole CH3 is provided in the organic insulating layer 12 and penetrates the organic insulating layer 12. The lower electrode LE3 is in contact with the conductive layer CL included in the circuit layer 11 through the contact hole CH3.

[0067] Like the lower electrodes LE1 and LE2, the lower electrode LE3 has a metal layer ML, a first layer L1 covering the upper surface of the metal layer ML, and a second layer L2 covering the lower surface of the metal layer ML.

[0068] In this embodiment, the inorganic insulating layer 7 is disposed between the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. If the display device DSP does not include the inorganic insulating layer 7, for example, if the portion of the lower electrode LE1 overlapping with the pixel opening AP1 has a defect such as a pinhole, moisture contained in the organic insulating layer 12 may penetrate into the organic layer OR1 through the defect. Since the organic layer OR1 generally has low resistance to moisture, the penetration of moisture into the organic layer OR1 may cause display defects.

[0069] In contrast to this, in the present embodiment, even if the portion of the lower electrode LE1 that overlaps with the pixel aperture AP1 has a defect such as a pinhole, the inorganic insulating layer 7 prevents moisture from penetrating into the defect. This makes it possible to prevent display defects and suppress deterioration in the display quality of the display device DSP.

[0070] In this embodiment, the openings 71 and 72 in the inorganic insulating layer 7 overlap with the rib layer 5 made of an inorganic material. Therefore, the rib layer 5 prevents moisture from penetrating into the organic layers OR1, OR2, and OR3 from the openings 71 and 72. This prevents display defects and makes it possible to prevent a decrease in the display quality of the display device DSP.

[0071] As an example of a method for manufacturing the display device DSP, after patterning the lower electrodes LE1, LE2, and LE3, a heat treatment is performed to crystallize the ITO contained in the second layer L2 of the lower electrodes LE1, LE2, and LE3. The heat treatment also raises the temperature of the organic insulating layer 12, causing the moisture contained in the organic insulating layer 12 to evaporate.

[0072] In this embodiment, a first region AR1 and a second region AR2 are provided that do not overlap with the lower electrodes LE1, LE2, and LE3 and the inorganic insulating layer 7. The moisture in the organic insulating layer 12 that evaporates during the heat treatment is released into the atmosphere through the first region AR1 and the second region AR2. This reduces the amount of moisture contained in the organic insulating layer 12, making it possible to further suppress display defects caused by the moisture.

[0073] In this embodiment, the rib layer 5 is in contact with the organic insulating layer 12 in the first region AR1 and the second region AR2. Therefore, the rib layer 5 prevents moisture from penetrating from the first region AR1 and the second region AR2 into the organic layers OR1, OR2, and OR3. This prevents display defects and makes it possible to prevent a decrease in the display quality of the display device DSP.

[0074] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0075] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0076] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0077] DA...display area, SA...peripheral area, PX...pixel, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 7...inorganic insulating layer, 71, 72...opening, 12...organic insulating layer, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, CH1, CH2, CH3...contact hole, PR1, PR2...protrusion.

Claims

1. an organic insulating layer formed of an organic material; a first lower electrode disposed above the organic insulating layer; an inorganic insulating layer formed of an inorganic material and disposed between the organic insulating layer and the first lower electrode; a rib layer having a first opening overlapping the first lower electrode; Equipped with the inorganic insulating layer overlaps with the first opening in a plan view; Display device.

2. the inorganic insulating layer has a second opening that overlaps with the rib layer in a plan view; The display device according to claim 1 .

3. a partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion; the second opening overlaps with the partition wall in a plan view; The display device according to claim 2 .

4. The lower part is a conductive bottom layer disposed on the rib layer; a shaft layer disposed on the bottom layer; and the second opening overlaps with the bottom layer in a plan view; The display device according to claim 3 .

5. further comprising a pixel circuit disposed below the organic insulating layer; the first lower electrode is connected to the pixel circuit through a first contact hole provided in the organic insulating layer; the first contact hole overlaps with the second opening in a plan view; The display device according to claim 2 .

6. a second lower electrode spaced apart from the first lower electrode; the inorganic insulating layer is further disposed between the organic insulating layer and the second lower electrode; the rib layer is in contact with the organic insulating layer between the first lower electrode and the second lower electrode. The display device according to claim 2 .

7. a region located between the first lower electrode and the second lower electrode and overlapping with the second opening; the rib layer is in contact with the organic insulating layer in the region; The display device according to claim 6.

8. a partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion; The partition wall covers the region in a plan view. The display device according to claim 7 .

9. The lower part is a conductive bottom layer disposed on the rib layer; a shaft layer disposed on the bottom layer; and the bottom layer covers the region in a plan view; The display device according to claim 8 .

10. the first lower electrode has a first convex portion formed in a convex shape toward the second lower electrode, the first protrusion overlaps with the second opening in a plan view; The display device according to claim 6.

11. further comprising a pixel circuit disposed below the organic insulating layer; the first lower electrode is connected to the pixel circuit through a first contact hole provided in the organic insulating layer; the first contact hole overlaps with the first convex portion and the second opening in a plan view; The display device according to claim 10.

12. the second lower electrode has a second convex portion formed in a convex shape toward the first lower electrode, the second protrusion overlaps with the second opening in a plan view; The display device according to claim 11.

13. the second lower electrode is connected to the pixel circuit through a second contact hole provided in the organic insulating layer; the second contact hole overlaps with the second convex portion and the second opening in a plan view; The display device according to claim 12.

14. a region located between the first lower electrode and the second lower electrode and overlapping with the second opening; the first convex portion and the second convex portion are in contact with the region; The display device according to claim 13.

15. an organic layer covering the first lower electrode through the first opening and having a light-emitting layer; an upper electrode covering the organic layer; Furthermore, the organic layer and the upper electrode overlap the inorganic insulating layer in a plan view; 15. A display device according to any one of claims 1 to 14.

16. the inorganic insulating layer is formed to be thicker than the first lower electrode; 15. A display device according to any one of claims 1 to 14.

17. the first lower electrode has a layer formed of ITO; 15. A display device according to any one of claims 1 to 14.

18. the inorganic insulating layer is formed of the same material as the rib layer; 15. A display device according to any one of claims 1 to 14.

19. the rib layer is formed of silicon nitride or silicon oxynitride; 15. A display device according to any one of claims 1 to 14.

20. the inorganic insulating layer is formed of silicon nitride or silicon oxynitride; 15. A display device according to any one of claims 1 to 14.

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