Display device

Abstract

To provide a display device capable of suppressing flare.SOLUTION: Embodiments of the present disclosure relate to a display device, specifically, a display device capable of suppressing flare when a camera is in use by including an anode extension line having a curved shape.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to a display device. [Background technology]

[0002] With the development of technology, display devices can provide functions such as photographing and various sensing functions in addition to image display functions. To this end, the display device can be equipped with optical electronic devices (also called light receiving devices or sensors) such as cameras and / or sensing sensors.

[0003] Since optical electronic devices must receive light from the front of the display device, they must be installed in a location that is favorable for receiving light. Therefore, in the past, cameras (camera lenses) and detection sensors had to be installed in an exposed manner on the front of the display device. This resulted in a wide bezel for the display panel or a cutout or physical hole in the display area of ​​the display panel where the camera or detection sensor was installed.

[0004] Therefore, if a display device is equipped with optical electronic devices such as cameras and sensors that receive light from the front and perform certain functions, the bezel on the front of the display device may become larger or restrictions may be placed on the front design of the display device. Summary of the Invention [Problem to be solved by the invention]

[0005] In the field of display technology, technologies for providing optical electronic devices such as cameras and sensors without reducing the display area of ​​a display panel have been researched. Display devices can be provided that include an optical electronic device below the display area of ​​a display panel, thereby enabling the optical electronic device to receive light normally without being exposed on the front surface of the display device. However, when using an optical electronic device in such a display device, there is a problem that the wiring structure of the display device makes it difficult to receive light smoothly. In particular, when a camera is used below the display area, there is a problem that flare occurs due to the wiring structure of the display device. Therefore, the inventors of the present specification have invented a display device that includes a camera without reducing the display area, yet can suppress the occurrence of flare even when the camera is used.

[0006] Generally, the present disclosure provides a display device suitable for use with a camera. The display device is designed to efficiently transmit light through an optical region of the display device. In particular, the display device can have the ability to suppress flare by including a curved anode extension line. [Means for solving the problem]

[0007] An embodiment of the present disclosure can provide a display device including a display area, a cathode electrode, a first light-emitting element, a first subpixel circuit portion, and an anode extension line.

[0008] The display area may include a first optical area and a first optical bezel area. The first optical bezel area may be located on the outer periphery of the first optical area. The display area may include the first optical area and the first optical bezel area. The first optical bezel area may be located outside the first optical area, for example, surrounding the first optical area. The first optical area may be configured to effectively transmit light. The first optical area may have a higher light transmittance than the first optical bezel area. The first optical bezel area may be configured to block light. The display area may further include a general area. The general area may surround the first optical bezel area. Each of the general area, the first optical area, and the first optical bezel area may be configured to disperse light, for example, to display an image. That is, the first optical area, the first optical bezel area, and the general area may form a display area of ​​the device. The general area may be configured to block light. The non-display area may be located outside the display area (e.g., at the peripheral edge), and may be configured to not diverge light.

[0009] The cathode electrode may include a plurality of cathode holes within the first optical region. The cathode holes may include extended open holes for transmitting light through the cathode. The cathode may extend into the first optical bezel region and the general region, and the first optical bezel region and the general region may be free of cathode holes.

[0010] The first light-emitting element is located in the first optical region and can include a first anode electrode. The first light-emitting element can be an element (e.g., a pixel or subpixel) configured to emit light. The first light-emitting element can define a corresponding light-emitting region in the display device.

[0011] The first subpixel circuitry can be disposed in the first optical bezel region, and can be circuitry configured to drive the first subpixel.

[0012] The anode extension line can electrically connect the first subpixel circuit portion and the first anode electrode, and can be arranged so as not to overlap with the cathode hole.

[0013] The shape of the anode extension line may be curved.

[0014] The anode extension lines can extend in a first direction across the first optical region, and each anode extension line can terminate at a connection point with the anode electrode.

[0015] The number of anode extension lines per unit area can decrease from the edge of the first optical region toward the center of the first optical region.

[0016] The plurality of anode extension lines may be divided into a plurality of groups, and the thickness of each of the plurality of groups may decrease from an edge of the first optical region toward the center of the first optical region.

[0017] The invention is defined in the appended claims. [Effects of the Invention]

[0018] According to the present disclosure, a display device can be provided that includes a curved anode extension line, thereby suppressing the occurrence of flare when a camera is used below the display device.

[0019] According to the present disclosure, a display device with optimized processes can be provided by forming the anode extension line without introducing an additional process. [Brief explanation of the drawings]

[0020] [Figure 1a] 1 illustrates a display device according to an embodiment of the present disclosure. [Figure 1b] 1 illustrates a display device according to an embodiment of the present disclosure. [Figure 1c]1 illustrates a display device according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a configuration diagram of a display device system according to an embodiment of the present disclosure. [Figure 3] 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure. [Figure 4] 1A and 1B schematically illustrate a general area, a first optical bezel area, and a first optical area in a display panel according to an embodiment of the present disclosure. [Figure 5] 1 shows a display panel according to an embodiment of the present disclosure, with light-emitting elements arranged in the general region, the first optical bezel region, and the first optical region, and subpixel circuitry for driving the light-emitting elements. [Figure 6] 1 shows a display panel according to an embodiment of the present disclosure, with light-emitting elements arranged in the general region, the first optical bezel region, and the first optical region, and subpixel circuitry for driving the light-emitting elements. [Figure 7] 1 is a plan view of a general area, an optical bezel area, and an optical area in a display panel according to an embodiment of the present disclosure. [Figure 8] 1 is a cross-sectional view of a display panel according to an embodiment of the present disclosure, taken along a first optical bezel region and a first optical region of the display panel. [Figure 9] 1 is a cross-sectional view of a display panel according to an embodiment of the present disclosure, taken along a first optical bezel region and a first optical region of the display panel. [Figure 10] FIG. 10 is a plan view of a first optical region of a display device according to a comparative example of the present disclosure. [Figure 11] FIG. 2 is a plan view of a first optical region of a display device according to an embodiment of the present disclosure. [Figure 12] 12 is an enlarged plan view of a partial area of ​​the plan view shown in FIG. 11. FIG. [Figure 13] 12 is an enlarged plan view of a partial area of ​​the plan view shown in FIG. 11. FIG. [Figure 14] FIG. 2 is a schematic diagram illustrating a cross section of an anode extension line according to an embodiment of the present disclosure. [Figure 15]FIG. 2 is a schematic diagram illustrating a cross section of an anode extension line according to an embodiment of the present disclosure. [Figure 16] 1 is a cross-sectional view of a display device according to an embodiment of the present disclosure. [Figure 17] 1 is a cross-sectional view of a display device according to an embodiment of the present disclosure. [Figure 18] 1 is a cross-sectional view of a display device according to an embodiment of the present disclosure. [Figure 19] 10A and 10B are diagrams illustrating the flare suppression effect of the shape of the anode extension line according to the embodiment of the present disclosure. [Figure 20] 10A and 10B are diagrams illustrating the flare suppression effect of the shape of the anode extension line according to the embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0021] Some embodiments of the present disclosure will be described in detail below with reference to exemplary drawings. When adding reference numerals to components in each drawing, identical components may be assigned the same numerals as much as possible, even if they appear in different drawings. Note that, in describing the present disclosure, if a specific description of related publicly known configurations or functions is deemed to obscure the gist of the present disclosure, such detailed description will be omitted. When terms such as "comprise," "have," and "consist" are used in this specification, other parts may be added unless "only" is used. When a component is expressed as singular, it may also include plurals unless otherwise explicitly stated.

[0022] Furthermore, when describing components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. are used. These terms are merely used as arbitrary labels to distinguish the components from other components, and do not limit the essence, order, sequence, number, etc. of the components.

[0023] When two or more components are described as being "coupled," "coupled," or "connected" in a description of the positional relationship of components, it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that the two or more components may also be "coupled," "coupled," or "connected" to other components through further "intervening" connections. Here, the other components may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0024] In describing the temporal relationship between components, methods of operation, methods of production, etc., when a temporal or sequential relationship is described using, for example, "after," "following," "next," or "before," this may also include cases where the relationship is not consecutive, unless "immediately" or "directly" is used.

[0025] On the other hand, when a numerical value or its corresponding information (e.g., level, etc.) relating to a component is mentioned, the numerical value or its corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external impact, noise, etc.) even if there is no other explicit statement.

[0026] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0027] 1a, 1b and 1c show a display device 100 according to an embodiment of the present disclosure.

[0028] 1a, 1b, and 1c, a display device 100 according to an embodiment of the present disclosure may include a display panel 110 for displaying images, and one or more optical-electronic devices 11, 12.

[0029] The display panel 110 can include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed.

[0030] In the display area DA, a plurality of sub-pixels may be arranged, and various signal lines for driving the sub-pixels may be arranged.

[0031] The non-display area NDA may be an area outside the display area DA. Various signal lines may be arranged in the non-display area NDA, and various driving circuits may be connected to the non-display area NDA. The non-display area NDA may be bent so that it cannot be seen from the front, or may be covered by a case (not shown). The non-display area NDA is also called a bezel or bezel area.

[0032] 1a, 1b and 1c, in a display device 100 according to an embodiment of the present disclosure, one or more optical-electronic devices 11, 12 are electronic components that are provided and installed separately from the display panel 110 and are located below the display panel 110 (opposite the viewing surface).

[0033] Light may enter the front (viewing surface) of the display panel 110 and be transmitted through the display panel 110 to one or more opto-electronic devices 11, 12 located underneath (opposite the viewing surface) the display panel 110. For example, the light transmitted through the display panel 110 may include visible light, infrared light, or ultraviolet light.

[0034] The one or more optical electronic devices 11, 12 may be devices that receive light transmitted through the display panel 110 and perform a predetermined function in response to the received light. For example, the one or more optical electronic devices 11, 12 may include one or more of an imaging device such as a camera (image sensor), a proximity sensor, an illuminance sensor, and the like. Here, for example, the detection sensor may be an infrared sensor.

[0035] 1a, 1b, and 1c, in a display panel 110 according to an embodiment of the present disclosure, a display area DA may include a general area NA and one or more optical areas OA1, OA2, which may overlap one or more optical-electronic devices 11, 12.

[0036] 1a, the display area DA may include a general area NA and a first optical area OA1, where at least a part of the first optical area OA1 may overlap with the first optical-electronic device 11.

[0037] 1b, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of FIG. 1b, the general area NA may be present between the first optical area OA1 and the second optical area OA2. Here, at least a portion of the first optical area OA1 may overlap the first opto-electronic device 11, and at least a portion of the second optical area OA2 may overlap the second opto-electronic device 12.

[0038] 1c, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of FIG. 1c, the general area NA does not exist between the first optical area OA1 and the second optical area OA2. That is, the first optical area OA1 and the second optical area OA2 are adjacent to each other. Here, at least a portion of the first optical area OA1 may overlap the first opto-electronic device 11, and at least a portion of the second optical area OA2 may overlap the second opto-electronic device 12.

[0039] One or more optical regions OA1, OA2 must have both an image display structure and a light-transmitting structure. That is, since one or more optical regions OA1, OA2 are part of the display area DA, one or more optical regions OA1, OA2 must have light-emitting regions of subpixels for image display arranged therein. Furthermore, one or more optical regions OA1, OA2 must have a light-transmitting structure formed therein to transmit light to one or more optical-electronic devices 11, 12.

[0040] The one or more optical electronic devices 11, 12 are devices that need to receive light and are located behind (below, opposite the viewing surface) the display panel 110, and receive light that has passed through the display panel 110. The one or more optical electronic devices 11, 12 are not exposed on the front (viewing surface) of the display panel 110. Therefore, when a user looks at the front of the display device 110, the optical electronic devices 11, 12 are not visible to the user.

[0041] For example, the first optical-electronic device 11 may be a camera, and the second optical-electronic device 12 may be a detection sensor such as a proximity sensor or an illuminance sensor. For example, the detection sensor may be an infrared sensor that detects infrared rays. Conversely, the first optical-electronic device 11 may be a detection sensor, and the second optical-electronic device 12 may be a camera.

[0042] For convenience of explanation, the following description will be given taking the first optical-electronic device 11 as a camera and the second optical-electronic device 12 as an infrared-based sensing sensor as an example, where the camera can be a camera lens or an image sensor.

[0043] When the first optical electronic device 11 is a camera, this camera is located behind (below) the display panel 110, but may be a front camera that captures an image in the front direction of the display panel 110. Therefore, while looking at the viewing surface of the display panel 110, the user can take an image via a camera that is not visible on the viewing surface.

[0044] The general area NA and one or more optical areas OA1 and OA2 included in the display area DA are areas where images can be displayed, but the general area NA is an area where a light-transmitting structure does not need to be formed, and the one or more optical areas OA1 and OA2 are areas where a light-transmitting structure should be formed.

[0045] Therefore, one or more optical regions OA1, OA2 should have a transmittance above a certain level, and the general region NA may have no light transmittance or a low transmittance below a certain level.

[0046] For example, one or more optical areas OA1, OA2 and the general area NA may differ from each other in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure.

[0047] For example, the number of subpixels per unit area in one or more optical areas OA1 and OA2 may be smaller than the number of subpixels per unit area in the general area NA. That is, the resolution of one or more optical areas OA1 and OA2 may be lower than the resolution of the general area NA. Here, the number of subpixels per unit area may be synonymous with resolution, pixel density, or pixel integration. For example, the unit of the number of subpixels per unit area may be PPI (Pixels Per Inch), which means the number of pixels within 1 inch.

[0048] For example, the number of subpixels per unit area in the first optical area OA1 may be less than the number of subpixels per unit area in the general area NA, and the number of subpixels per unit area in the second optical area OA2 may be equal to or greater than the number of subpixels per unit area in the first optical area OA1 but less than the number of subpixels per unit area in the general area NA.

[0049] Meanwhile, as one method for increasing the transmittance of at least one of the first optical area OA1 and the second optical area OA2, the pixel density differential design method can be applied, as described above. According to the pixel density differential design method, the display panel 110 can be designed so that the number of subpixels per unit area in at least one of the first optical area OA1 and the second optical area OA2 is smaller than the number of subpixels per unit area in the general area NA.

[0050] However, in some cases, a pixel size differential design method can be applied as another method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2. According to the pixel size differential design method, the display panel 110 can be designed so that the number of subpixels per unit area in at least one of the first optical region OA1 and the second optical region OA2 is the same as or similar to the number of subpixels per unit area in the general region NA, but the size of each subpixel SP (i.e., the size of the light-emitting region) arranged in at least one of the first optical region OA1 and the second optical region OA2 is smaller than the size of each subpixel SP (i.e., the size of the light-emitting region) arranged in the general region NA.

[0051] For ease of explanation, the following description will be made on the assumption that the pixel density differential design method is applied among two methods (pixel density differential design method and pixel size differential design method) for increasing the transmittance of at least one of the first optical area OA1 and the second optical area OA2. Therefore, hereinafter, a small number of subpixels per unit area may be expressed as a small subpixel size, and a large number of subpixels per unit area may be expressed as a large subpixel size.

[0052] The first optical area OA1 can have various shapes such as a circle, an ellipse, a square, a hexagon, or an octagon. The second optical area OA2 can have various shapes such as a circle, an ellipse, a square, a hexagon, or an octagon. The first optical area OA1 and the second optical area OA2 can have the same shape or different shapes.

[0053] 1c, when the first optical area OA1 and the second optical area OA2 are adjacent to each other, the entire optical area including the first optical area OA1 and the second optical area OA2 may have various shapes, such as a circle, an ellipse, a rectangle, a hexagon, an octagon, etc. For convenience of explanation, the following description will be given assuming that the first optical area OA1 and the second optical area OA2 are each a circle.

[0054] In the display device 100 according to the embodiment of the present disclosure, if the first optical electronic device 11 that is not exposed to the outside and is hidden at the bottom of the display device 100 is a camera, the display device 100 according to the embodiment of the present disclosure can be said to be a display to which UDC (Under Display Camera) technology is applied.

[0055] Accordingly, in the case of the display device 100 according to the embodiment of the present disclosure, a reduction in the area of ​​the display area DA does not occur because a notch or a camera hole for camera exposure does not need to be formed in the display panel 110. As a result, since a notch or a camera hole for camera exposure does not need to be formed in the display panel 110, the size of the bezel area can be reduced, design restrictions are eliminated, and design freedom can be increased.

[0056] In the display device 100 according to an embodiment of the present disclosure, although one or more optical-electronic devices 11, 12 are hidden and positioned behind the display panel 110, the one or more optical-electronic devices 11, 12 must be able to receive light normally and perform their predetermined functions normally.

[0057] Furthermore, in the display device 100 according to an embodiment of the present disclosure, although one or more optical-electronic devices 11, 12 are arranged hidden behind the display panel 110 and overlap with the display area DA, normal image display must be possible in one or more optical areas OA1, OA2 in the display area DA that overlap with the one or more optical-electronic devices 11, 12.

[0058] The first optical area OA1 mentioned above is designed as a transmissive area, and therefore the image display characteristics in the first optical area OA1 may be different from the image display characteristics in the general area NA.

[0059] Furthermore, when the first optical area OA1 is designed to improve the image display characteristics, the transmittance of the first optical area OA1 may be reduced.

[0060] Therefore, an embodiment of the present disclosure presents a structure of the first optical area OA1 that can improve the transmittance in the first optical area OA1 without causing any variation in image quality between the first optical area OA1 and the general area NA.

[0061] Furthermore, the embodiment of the present disclosure presents a structure of the second optical area OA2 that can improve the image quality in the second optical area OA2 and improve the transmittance in the second optical area OA2, not only for the first optical area OA1 but also for the second optical area OA2.

[0062] In the display device 100 according to the embodiment of the present disclosure, the first optical area OA1 and the second optical area OA2 are similar in that they are light-transmittable areas, but may have different application examples. Therefore, in the display device 100 according to the embodiment of the present disclosure, the structure of the first optical area OA1 and the structure of the second optical area OA2 may be designed to be different from each other.

[0063] FIG. 2 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0064] Referring to FIG. 2, the display device 100 is a component for displaying an image and may include a display panel 110 and a display driver circuit.

[0065] The display driving circuit is a circuit for driving the display panel 110, and may include a data driving circuit 220, a gate driving circuit 230, a display controller 240, and the like.

[0066] The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. The non-display area NDA may be an outer periphery of the display area DA and may also be referred to as a bezel area. All or part of the non-display area NDA may be an area visible from the front surface of the display device 100, or may be a curved area that is not visible from the front surface of the display device 100.

[0067] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. Furthermore, the display panel 110 may further include various types of signal lines to drive the plurality of sub-pixels SP.

[0068] The display device 100 according to the embodiment of the present disclosure may be a liquid crystal display device or a self-emissive display device in which the display panel 110 emits light by itself. When the display device 100 according to the embodiment of the present disclosure is a self-emissive display device, each of the plurality of subpixels SP may include a light-emitting element. For example, the display device 100 according to the embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting elements are organic light-emitting diodes (OLEDs). As another example, the display device 100 according to the embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting elements are inorganic-based light-emitting diodes. As yet another example, the display device 100 according to the embodiment of the present disclosure may be a quantum dot display device in which the light-emitting elements are quantum dots, which are semiconductor crystals that emit light themselves.

[0069] The structure of each of the subpixels SP may vary depending on the type of display device 100. For example, if the display device 100 is a self-emitting display device that emits light from the subpixels SP, each subpixel SP may include a light-emitting element that emits light from itself, one or more transistors, and one or more capacitors.

[0070] For example, some types of signal lines may include a plurality of data lines DL that transmit data signals (also called data voltages or video signals) and a plurality of gate lines GL that transmit gate signals (also called scan signals).

[0071] The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend in a first direction. Each of the plurality of gate lines GL may be arranged to extend in a second direction that may be perpendicular to the first direction. Here, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be the row direction, and the second direction may be the column direction.

[0072] The data driving circuit 220 is a circuit for driving a plurality of data lines DL and can output data signals to the plurality of data lines DL. The gate driving circuit 230 is a circuit for driving a plurality of gate lines GL and can output gate signals to the plurality of gate lines GL.

[0073] The display controller 240 is a device for controlling the data driving circuit 220 and the gate driving circuit 230, and can control the driving timing for the plurality of data lines DL and the driving timing for the plurality of gate lines GL.

[0074] The display controller 240 can provide data drive control signals DCS to the data drive circuit 220 to control the data drive circuit 220, and can provide gate drive control signals GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0075] The display controller 240 can receive input video data from the host system 250 and provide video data (Data) to the data driving circuit 220 based on the input video data.

[0076] The data driving circuit 220 can receive digital image data Data from the display controller 240, convert the received image data Data into analog data signals, and output the analog data signals to a plurality of data lines DL.

[0077] The gate driving circuit 230 is supplied with a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage, along with various gate driving control signals GCS, and can generate gate signals and supply the generated gate signals to multiple gate lines GL.

[0078] For example, the data driving circuit 220 may be connected to the display panel 110 using a tape automated bonding (TAB) method, connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or configured using a chip on film (COF) method and connected to the display panel 110.

[0079] The gate driving circuit 230 may be connected to the display panel 110 using a tape automated bonding (TAB) method, a bonding pad of the display panel 110 using a chip-on-glass (COG) or chip-on-panel (COP) method, or a chip-on-film (COF) method. Alternatively, the gate driving circuit 230 may be formed in the non-display area (NDA) of the display panel 110 using a gate-in-panel (GIP) type. The gate driving circuit 230 may be disposed on a substrate or connected to the substrate. That is, in the case of a GIP type, the gate driving circuit 230 may be disposed in the non-display area (NDA) of the substrate. In the case of a chip-on-glass (COG) type, chip-on-film (COF) type, etc., the gate driving circuit 230 may be connected to the substrate.

[0080] Meanwhile, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed so as not to overlap with the sub-pixels SP, or may be disposed so as to overlap partially or entirely with the sub-pixels SP.

[0081] The data driving circuit 220 may be connected to one side (e.g., the upper or lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 220 may be connected to both sides (e.g., the upper and lower sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0082] The gate driving circuit 230 may be connected to one side (e.g., the left or right side) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 230 may be connected to both sides (e.g., the left and right sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0083] The display controller 240 may be configured as a separate component from the data driver circuitry 220, or may be integrated with the data driver circuitry 220 and configured as an integrated circuit.

[0084] The display controller 240 may be a timing controller used in conventional display technology, or may be a control device that can perform other control functions including a timing controller, or may be a control device different from a timing controller, or may be a circuit within a control device. The display controller 240 can be realized as various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0085] The display controller 240 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 220 and the gate driving circuit 230 via the printed circuit board, the flexible printed circuit, or the like.

[0086] The display controller 240 can transmit and receive signals to and from the data driving circuit 220 according to one or more predetermined interfaces. For example, the interfaces may include a Low Voltage Differential Signaling (LVDS) interface, an Embedded Clock Point-Point Interface (EPI), a Serial Peripheral Interface (SPI), etc.

[0087] The display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen and detect the touch position, in order to provide not only an image display function but also a touch sensing function.

[0088] The touch sensing circuit may include a touch driving circuit 260 that drives and senses the touch sensor, generates and outputs touch sensing data, and a touch controller 270 that can sense the occurrence of a touch and detect the touch position using the touch sensing data.

[0089] The touch sensor may include a plurality of touch electrodes, and may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch drive circuit 260.

[0090] The touch sensor may be present outside the display panel 110 in the form of a touch panel, or may be present inside the display panel 110. When the touch sensor is present outside the display panel 110 in the form of a touch panel, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 110 can be fabricated separately and combined during an assembly process. The external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0091] If the touch sensor is present inside the display panel 110, the touch sensor may be formed on the substrate SUB along with signal lines, electrodes, etc. related to display driving during the manufacturing process of the display panel 110.

[0092] The touch driving circuit 260 may supply a touch driving signal to at least one of the plurality of touch electrodes, sense the at least one of the plurality of touch electrodes, and generate touch sensing data.

[0093] The touch sensing circuit can perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method.

[0094] When the touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self-capacitance sensing method, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all or some of the plurality of touch electrodes and sense all or some of the plurality of touch electrodes.

[0095] When the touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to the mutual capacitance sensing method, the touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0096] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be realized by separate devices or may be realized by a single device, and the touch driving circuit 260 and the data driving circuit 220 may be realized by separate devices or may be realized by a single device.

[0097] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or the touch sensing circuit.

[0098] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smartphone or a tablet, or may be a monitor or television (TV) of various sizes, but is not limited to these, and may be a display of various types and sizes capable of displaying information or images.

[0099] As described above, the display area DA of the display panel 110 may include a general area NA and one or more optical areas OA1 and OA2. The general area NA and one or more optical areas OA1 and OA2 are areas where an image can be displayed. However, the general area NA is an area where a light-transmitting structure does not need to be formed, while the one or more optical areas OA1 and OA2 are areas where a light-transmitting structure should be formed.

[0100] As mentioned above, the display area DA in the display panel 110 may include one or more optical areas OA1, OA2 along with a general area NA, but for ease of explanation, we will assume that the display area DA includes both a first optical area OA1 and a second optical area OA2 (Figures 1b and 1c).

[0101] FIG. 3 is a schematic diagram of a display panel 110 according to an embodiment of the present disclosure.

[0102] 3, a plurality of sub-pixels SP may be arranged in the display area DA of the display panel 110. The sub-pixels SP may be arranged in a general area NA, a first optical area OA1, and a second optical area OA2 included in the display area DA.

[0103] Referring to FIG. 3, each of the plurality of sub-pixels SP may include a light-emitting element ED and a sub-pixel circuit portion SPC configured to drive the light-emitting element ED.

[0104] Referring to FIG. 3, the sub-pixel circuit unit SPC may include a driving transistor DT for driving the light emitting element ED, a scan transistor ST for transmitting a data voltage Vdata to a first node N1 of the driving transistor DT, and a storage capacitor Cst for maintaining a constant voltage during one frame.

[0105] The driving transistor DT may include a first node N1 to which a data voltage can be applied, a second node N2 electrically connected to the light emitting element ED, and a third node N3 to which a driving voltage ELVDD is applied from a driving voltage line DVL. In the driving transistor DT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. For convenience of explanation, the following description will be given taking as an example a case in which the first node N1 is a gate node, the second node N2 is a source node, and the third node N3 is a drain node in the driving transistor DT.

[0106] The light-emitting element ED may include an anode electrode AE, an emitting layer EL, and a cathode electrode CE. The anode electrode AE ​​is a pixel electrode disposed in each subpixel SP and may be electrically connected to the second node N2 of the driving transistor DT of each subpixel SP. The cathode electrode CE is a common electrode disposed in common to the plurality of subpixels SP and may be applied with a base voltage ELVSS.

[0107] For example, the anode electrode AE ​​may be a pixel electrode and the cathode electrode CE may be a common electrode. Conversely, the anode electrode AE ​​may be a common electrode and the cathode electrode CE may be a pixel electrode. In the following, for convenience of explanation, it is assumed that the anode electrode AE ​​is a pixel electrode and the cathode electrode CE is a common electrode.

[0108] The light emitting element ED can have a predetermined light emitting area EA, and the light emitting area EA of the light emitting element ED can be defined as an area where the anode electrode AE, the light emitting layer EL, and the cathode electrode CE overlap.

[0109] For example, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, a quantum dot light-emitting element, etc. When the light-emitting element ED is an organic light-emitting diode, the light-emitting layer EL in the light-emitting element ED may include an organic light-emitting layer EL containing an organic material.

[0110] The scan transistor ST is controlled to be turned on or off by a scan signal SCAN, which is a gate signal applied via the gate line GL, and can be electrically connected between the first node N1 of the drive transistor DT and the data line DL.

[0111] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT.

[0112] As shown in FIG. 3, the subpixel circuit unit SPC may have a 2T (Transistor) 1C (Capacitor) structure including two transistors DT and ST and one capacitor Cst, and in some cases may further include one or more transistors or one or more capacitors.

[0113] The storage capacitor Cst may be an external capacitor intentionally designed outside the drive transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) that may be present between the first node N1 and the second node N2 of the drive transistor DT. Each of the drive transistor DT and the scan transistor ST may be an n-type transistor or a p-type transistor.

[0114] Since the circuit elements in each subpixel SP (particularly, the light-emitting element ED formed of an organic light-emitting diode OLED containing organic matter) are vulnerable to external moisture and oxygen, an encapsulation layer ENCAP for preventing external moisture and oxygen from penetrating into the circuit elements (particularly, the light-emitting element ED) can be disposed on the display panel 110. The encapsulation layer ENCAP can be disposed so as to cover the light-emitting element ED.

[0115] FIG. 4 schematically illustrates a general area NA, a first optical bezel area OBA1, and a first optical area OA1 in a display panel 110 according to an embodiment of the present disclosure.

[0116] Referring to FIG. 4, a display panel 110 according to an embodiment of the present disclosure may include a display area DA where an image is displayed and a non-display area NDA where no image is displayed.

[0117] Referring to FIG. 4, the display area DA may include a first optical area OA1, a first optical bezel area OBA1, and a general area NA.

[0118] Referring to FIG. 4 , the first optical region OA1 overlaps with the first opto-electronic device 11 and may be a transmissive region through which light necessary for the operation of the first opto-electronic device 11 can pass. Here, the light passing through the first optical region OA1 may include light of a single wavelength band or light of various wavelength bands. For example, the light passing through the first optical region OA1 may include one or more of visible light, infrared light, ultraviolet light, and the like. For example, if the first opto-electronic device 11 is a camera, the light passing through the first optical region OA1 and used by the first opto-electronic device 11 may include visible light. As another example, if the first opto-electronic device 11 is an infrared-based sensor, the light passing through the first optical region OA1 and used by the first opto-electronic device 11 may include infrared light (also referred to as infrared light).

[0119] 4, the first optical bezel area OBA1 may be an area located outside the first optical area OA1. The general area NA may be an area located outside the first optical bezel area OBA1. The first optical bezel area OBA1 may be disposed between the first optical area OA1 and the general area NA.

[0120] For example, the first optical bezel area OBA1 may be arranged only on the outer periphery of a portion of the boundary of the first optical area OA1, or may be arranged on the outer periphery of the entire boundary of the first optical area OA1.

[0121] When the first optical bezel area OBA1 is arranged on the periphery of the entire boundary of the first optical area OA1, the first optical bezel area OBA1 can have a ring shape surrounding the first optical area OA1.

[0122] For example, the first optical area OA1 can have various shapes such as a circle, an ellipse, a polygon, or an irregular shape, etc. The first optical bezel area OBA1 can have various ring shapes (e.g., a ring shape, an ellipse ring shape, a polygonal ring shape, an irregular ring shape, etc.) surrounding the first optical area OA1 having various shapes.

[0123] 4, the display area DA may include a plurality of light-emitting areas EA. Since the first optical area OA1, the first optical bezel area OBA1, and the general area NA are areas included in the display area DA, each of the first optical area OA1, the first optical bezel area OBA1, and the general area NA may include a plurality of light-emitting areas EA.

[0124] For example, the plurality of light emitting regions EA may include a first color light emitting region that emits light of a first color, a second color light emitting region that emits light of a second color, and a third color light emitting region that emits light of a third color.

[0125] At least one of the first color light-emitting region, the second color light-emitting region, and the third color light-emitting region can have a different area than the rest.

[0126] The first color, the second color, and the third color may be a variety of different colors, for example, the first color, the second color, and the third color may include red, green, and blue.

[0127] For the sake of convenience, the following description will be given taking an example in which the first color is red, the second color is green, and the third color is blue, but is not limited thereto.

[0128] When the first color is red, the second color is green, and the third color is blue, the area of ​​the blue light-emitting region EA_B may be the largest among the areas of the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B.

[0129] The light-emitting element ED disposed in the red light-emitting region EA_R may include a light-emitting layer EL that emits red light. The light-emitting element ED disposed in the green light-emitting region EA_G may include a light-emitting layer EL that emits green light. The light-emitting element ED disposed in the blue light-emitting region EA_B may include a light-emitting layer EL that emits blue light.

[0130] Of the light-emitting layer EL that emits red light, the light-emitting layer EL that emits green light, and the light-emitting layer EL that emits blue light, the organic material contained in the light-emitting layer EL that emits blue light may be the most susceptible to deterioration in terms of material.

[0131] Since the area of ​​the blue light-emitting region EA_B is designed to be the largest, the current density supplied to the light-emitting element ED arranged in the blue light-emitting region EA_B may be the smallest. Therefore, the degree of deterioration of the light-emitting element ED arranged in the blue light-emitting region EA_B may be similar to the degree of deterioration of the light-emitting element ED arranged in the red light-emitting region EA_R and the degree of deterioration of the light-emitting element ED arranged in the green light-emitting region EA_G.

[0132] Therefore, the variation in deterioration among the light-emitting elements ED arranged in the red light-emitting region EA_R, the light-emitting elements ED arranged in the green light-emitting region EA_G, and the light-emitting elements ED arranged in the blue light-emitting region EA_B is eliminated or reduced, thereby improving image quality. Furthermore, the elimination or reduction of the variation in deterioration among the light-emitting elements ED arranged in the red light-emitting region EA_R, the light-emitting elements ED arranged in the green light-emitting region EA_G, and the light-emitting elements ED arranged in the blue light-emitting region EA_B can have the effect of reducing the variation in lifespan among the light-emitting elements ED arranged in the red light-emitting region EA_R, the light-emitting elements ED arranged in the green light-emitting region EA_G, and the light-emitting elements ED arranged in the blue light-emitting region EA_B.

[0133] 4, the first optical area OA1 is a transmissive area and should have high transmittance. To this end, the cathode electrode CE may include a plurality of cathode holes CH in the first optical area OA1. That is, in the first optical area OA1, the cathode electrode CE may include a plurality of cathode holes CH.

[0134] 4, the cathode electrode CE does not include a cathode hole CH in the general area NA. That is, in the general area NA, the cathode electrode CE does not include a cathode hole CH.

[0135] Furthermore, the cathode electrode CE does not include a cathode hole CH in the first optical bezel area OBA1. That is, in the first optical bezel area OBA1, the cathode electrode CE does not include a cathode hole CH.

[0136] In the first optical area OA1, the plurality of cathode holes CH formed in the cathode electrode CE can also be referred to as a plurality of first transmission areas TA1 or a plurality of openings. Here, in Fig. 4, one cathode hole CH has a circular shape, but it may have various shapes other than a circle, such as an ellipse, a polygon, or an irregular shape.

[0137] Referring to FIG. 4, the second optical area OA2 can be positioned adjacent to the first optical area OA1, and the placement of the light-emitting area EA in the second optical area OA2 will be described in more detail with reference to FIG.

[0138] FIG. 5 shows light-emitting elements ED1, ED2, ED3, and ED4 arranged in a general area NA, a first optical bezel area OBA1, and a first optical area OA1 in a display panel 110 according to an embodiment of the present disclosure, and subpixel circuit units SPC1, SPC2, SPC3, and SPC4 for driving the light-emitting elements ED1, ED2, ED3, and ED4.

[0139] However, each of the sub-pixel circuit units SPC1, SPC2, SPC3, and SPC4 may include transistors DT and ST and a storage capacitor Cst, etc., as shown in Fig. 3. However, for convenience of explanation, the sub-pixel circuits SPC1, SPC2, SPC3, and SPC4 are abbreviated as driving transistors DT1, DT2, DT3, and DT4, respectively.

[0140] Referring to FIG. 5, the general area NA, the first optical area OA1, and the first optical bezel area OBA1 may have not only positional differences but also structural differences.

[0141] A structural difference is that subpixel circuits SPC1, SPC2, SPC3, and SPC4 may be arranged in the first optical bezel area OBA1 and the general area NA, but no subpixel circuits are arranged in the first optical area OA1. That is, transistors DT1, DT2, DT3, and DT4 may be arranged in the first optical bezel area OBA1 and the general area NA, but no transistors are arranged in the first optical area OA1.

[0142] The transistors and storage capacitors included in the sub-pixel circuit units SPC1, SPC2, SPC3, and SPC4 are configured to reduce transmittance, and thus, since the sub-pixel circuit units SPC1, SPC2, SPC3, and SPC4 are not disposed in the first optical area OA1, the transmittance of the first optical area OA1 can be further increased.

[0143] The subpixel circuit portions SPC1, SPC2, SPC3, and SPC4 are arranged only in the general area NA and the first optical bezel area OBA1, but the light-emitting elements ED1, ED2, ED3, and ED4 can be arranged in all of the general area NA, the first optical bezel area OBA1, and the first optical area OA1.

[0144] Referring to Figure 5, a first light-emitting element ED1 is arranged in the first optical area OA1, but a first pixel circuit unit SPC1 for driving the first light-emitting element ED1 is not arranged in the first optical area OA1.

[0145] Referring to Figure 5, the first subpixel circuit unit SPC1 for driving the first light-emitting element ED1 arranged in the first optical area OA1 may not be arranged in the first optical area OA1, but may be arranged in the first optical bezel area OBA1.

[0146] The general area NA, the first optical area OA1, and the first optical bezel area OBA1 will be described in more detail below.

[0147] 5, the plurality of light-emitting regions EA included in the display panel 110 according to the embodiment of the present disclosure may include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. Here, the first light-emitting region EA1 may be included in the first optical region OA1, the second light-emitting region EA2 may be included in the first optical bezel region OBA1, and the third light-emitting region EA3 may be included in the general region NA. Hereinafter, it is assumed that the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are light-emitting regions of the same color.

[0148] Referring to FIG. 5, a display panel 110 according to an embodiment of the present disclosure may include a first light-emitting element ED1 disposed in a first optical area OA1 and having a first light-emitting area EA1, a second light-emitting element ED2 disposed in a first optical bezel area OBA1 and having a second light-emitting area EA2, and a third light-emitting element ED3 disposed in a general area NA and having a third light-emitting area EA3.

[0149] Referring to FIG. 5, the display panel 110 according to an embodiment of the present disclosure may further include a first subpixel circuit unit SPC1 configured to drive the first light-emitting element ED1, a second subpixel circuit unit SPC2 configured to drive the second light-emitting element ED2, and a third subpixel circuit unit SPC3 configured to drive the third light-emitting element ED3.

[0150] 5, the first subpixel circuit portion SPC1 may include a first drive transistor DT1, the second subpixel circuit portion SPC2 may include a second drive transistor DT2, and the third subpixel circuit portion SPC3 may include a third drive transistor DT3.

[0151] Referring to FIG. 5, in a display panel 110 according to an embodiment of the present disclosure, the second subpixel circuit unit SPC2 may be disposed in the first optical bezel area OBA1 in which the corresponding second light-emitting element ED2 is disposed, and the third subpixel circuit unit SPC3 may be disposed in the general area NA in which the corresponding third light-emitting element ED3 is disposed.

[0152] 5, in the display panel 110 according to the embodiment of the present disclosure, the first subpixel circuit unit SPC1 may be disposed in a first optical bezel area OBA1 located outside the first optical area OA1, rather than in the first optical area OA1 where the corresponding first light emitting element ED1 is disposed, thereby increasing the transmittance of the first optical area OA1.

[0153] Referring to FIG. 5, the display panel 110 according to an embodiment of the present disclosure may further include an anode extension line AEL electrically connecting the first subpixel circuit unit SPC1 arranged in the first optical bezel area OBA1 and the first light-emitting element ED1 arranged in the first optical area OA1.

[0154] The anode extension line AEL can electrically extend the anode electrode AE ​​of the first light emitting element ED1 to the second node N2 of the first driving transistor DT1 in the first subpixel circuit unit SPC1.

[0155] As described above, in the display panel 110 according to the embodiment of the present disclosure, the first subpixel circuit unit SPC1 for driving the first light-emitting element ED1 arranged in the first optical area OA1 may be arranged in the first optical bezel area OBA1 instead of in the first optical area OA1. Such a structure is also called an anode extension structure.

[0156] When the display panel 110 according to the embodiment of the present disclosure has an anode extension structure, all or part of the anode extension line AEL may be disposed in the first optical area OA1, and the anode extension line AEL may include a transparent wiring, thereby preventing a decrease in the transmittance of the first optical area OA1 even if the anode extension line AEL connecting the first subpixel circuit unit SPC1 and the first light-emitting element ED1 is disposed in the first optical area OA1.

[0157] Referring to FIG. 5, the plurality of light-emitting areas EA may further include a fourth light-emitting area EA4 that emits light of the same color as the first light-emitting area EA1 and is included in the first optical area OA1.

[0158] Referring to FIG. 5, the fourth light-emitting area EA4 may be disposed adjacent to the first light-emitting area EA1 in the row or column direction.

[0159] Referring to FIG. 5, the display panel 110 according to an embodiment of the present disclosure may further include a fourth light-emitting element ED4 arranged in the first optical area OA1 and having a fourth light-emitting area EA4, and a fourth subpixel circuit unit SPC4 configured to drive the fourth light-emitting element ED4.

[0160] 5, the fourth sub-pixel circuit unit SPC4 may include a fourth driving transistor DT4. For convenience of explanation, the scan transistor ST and the storage capacitor Cst included in the fourth sub-pixel circuit unit SPC4 are omitted from FIG.

[0161] Referring to FIG. 5, the fourth subpixel circuit unit SPC4 is a circuit for driving the fourth light-emitting element ED4 arranged in the first optical area OA1, but may also be arranged in the first optical bezel area OBA1.

[0162] Referring to FIG. 5, the display panel 110 according to the embodiment of the present disclosure may further include an anode extension line AEL electrically connecting the fourth pixel circuit SPC4 and the fourth light-emitting element ED4.

[0163] All or part of such anode extension line AEL may be disposed in the first optical area OA1, and the anode extension line AEL may include a transparent wiring.

[0164] As described above, the first subpixel circuit unit SPC1 arranged in the first optical bezel area OBA1 can drive one light-emitting element ED1 arranged in the first optical area OA1. This circuit unit connection method is called a one-to-one (1:1) circuit unit connection method.

[0165] This allows the number of subpixel circuit units SPC arranged in the first optical bezel area OBA1 to be significantly increased, which complicates the structure of the first optical bezel area OBA1 and reduces the aperture ratio (or light-emitting area) of the first optical bezel area OBA1.

[0166] Despite having an anode extension structure, in order to increase the aperture ratio (or light-emitting area) of the first optical bezel area OBA1, the display device 100 according to an embodiment of the present disclosure can have a 1:N (N is 2 or more) circuit unit connection scheme.

[0167] According to the 1:N circuit unit connection method, the first subpixel circuit unit SPC1 arranged in the first optical bezel area OBA1 can simultaneously drive two or more light-emitting elements ED arranged in the first optical area OA1.

[0168] For ease of explanation, Figure 6 takes as an example a case where a 1:2 circuit unit connection method is applied, i.e., a case where a first subpixel circuit unit SPC1 arranged in the first optical bezel area OBA1 simultaneously drives two or more light-emitting elements ED1 and ED4 arranged in the first optical area OA1.

[0169] FIG. 6 shows light-emitting elements ED1, ED2, ED3, and ED4 arranged in a general area NA, a first optical bezel area OBA1, and a first optical area OA1 in a display panel 110 according to an embodiment of the present disclosure, and subpixel circuit sections SPC1, SPC2, and SPC3 for driving the light-emitting elements ED1, ED2, ED3, and ED4.

[0170] 6, the fourth light-emitting element ED4 disposed in the first optical area OA1 may be driven by the first sub-pixel circuit unit SPC1 for driving the first light-emitting element ED1 disposed in the first optical area OA1. That is, the first sub-pixel circuit unit SPC1 disposed in the first optical bezel area OBA1 may be configured to drive both the first light-emitting element ED1 and the fourth light-emitting element ED4 disposed in the first optical area OA1.

[0171] As a result, even though the display panel 110 has an anode extension structure, the number of subpixel circuit units SPC arranged in the first optical bezel area OBA1 is reduced, thereby increasing the opening and light-emitting area of ​​the first optical bezel area OBA1.

[0172] In FIG. 6, the first light-emitting element ED1 and the fourth light-emitting element ED4, which are both driven by the first subpixel circuit unit SPC1 arranged in the first optical bezel area OBA1, are light-emitting elements that emit light of the same color and may be adjacent light-emitting elements in the row or column direction.

[0173] Referring to FIG. 6, the anode extension line AEL can connect the first subpixel circuit unit SPC1 arranged in the first optical bezel area OBA1 to the first light-emitting element ED1 and the fourth light-emitting element ED4 arranged in the first optical area OA1.

[0174] FIG. 7 is a plan view of a general area NA, an optical bezel area OBA, and an optical area OA in a display panel 110 according to an embodiment of the present disclosure.

[0175] Referring to FIG. 7, in a display panel 110 according to an embodiment of the present disclosure, the multiple light-emitting areas EA arranged in each of the general area NA, the optical bezel area OBA, and the optical area OA may include a red light-emitting area EA_R, a green light-emitting area EA_G, and a blue light-emitting area EA_B.

[0176] Referring to FIG. 7, in a display panel 110 according to an embodiment of the present disclosure, a cathode electrode CE may be disposed in common in the general area NA, the optical bezel area OBA, and the optical area OA.

[0177] The cathode electrode CE may include a plurality of cathode holes CH, and the plurality of cathode holes CH of the cathode electrode CE may be arranged in the optical area OA.

[0178] The general area NA and the optical bezel area OBA may be areas that do not transmit light, and the optical area OA may be an area that transmits light, so that the transmittance in the optical area OA may be higher than the transmittance in the optical bezel area OBA and the general area NA.

[0179] The entire optical area OA is a light-transmitting area, and the plurality of cathode holes CH in the optical area OA may be a transmission area TA through which light can be more efficiently transmitted. That is, the remaining area of ​​the optical area OA excluding the plurality of cathode holes CH is a light-transmitting area, and the transmittance of the plurality of cathode holes CH in the optical area OA may be higher than the transmittance of the remaining area of ​​the optical area OA excluding the plurality of cathode holes CH.

[0180] Alternatively, the plurality of cathode holes CH in the optical area OA may be light-transmitting areas TA, and the remaining areas of the optical area OA excluding the plurality of cathode holes CH may be areas that do not transmit light.

[0181] Referring to FIG. 7, the arrangement of the luminous areas EA in the optical area OA, the arrangement of the luminous areas EA in the optical bezel area OBA, and the arrangement of the luminous areas EA in the general area NA may be the same as each other.

[0182] Referring to Figure 7, the multiple light-emitting areas EA may include a first light-emitting area EA1 included in the optical area OA, a second light-emitting area EA2 that emits light of the same color as the first light-emitting area EA1 and is included in the optical bezel area OBA, and a third light-emitting area EA3 that emits light of the same color as the first light-emitting area EA1 and is included in the general area NA.

[0183] Referring to FIG. 7, the plurality of light-emitting areas EA may further include a fourth light-emitting area EA4 that emits light of the same color as the first light-emitting area EA1 and is included in the optical area OA.

[0184] Referring to FIG. 7, a display panel 110 according to an embodiment of the present disclosure may include a first anode electrode AE1 disposed in the optical area OA, a second anode electrode AE2 disposed in the optical bezel area OBA, a third anode electrode AE3 disposed in the general area NA, and a fourth anode electrode AE4 disposed in the optical area OA1.

[0185] The display panel 110 according to the embodiment of the present disclosure may further include a cathode electrode CE disposed in common in the general area NA, the optical bezel area OBA, and the optical area OA.

[0186] The display panel 110 according to an embodiment of the present disclosure may include a first luminescent layer EL1 arranged in the optical area OA, a second luminescent layer EL2 arranged in the optical bezel area OBA, a third luminescent layer EL3 arranged in the general area NA, and a fourth luminescent layer EL4 arranged in the optical area OA, etc.

[0187] The first to fourth light-emitting layers EL4 may be light-emitting layers that emit light of the same color. In this case, the first to fourth light-emitting layers EL4 may be disposed separately or integrated into one layer.

[0188] Referring to FIG. 7, a first light-emitting element ED1 can be formed by a first anode electrode AE1, a first light-emitting layer EL1, and a cathode electrode CE; a second light-emitting element ED2 can be formed by a second anode electrode AE2, a second light-emitting layer EL2, and a cathode electrode CE; a third light-emitting element ED3 can be formed by a third anode electrode AE3, a third light-emitting layer EL3, and a cathode electrode CE; and a fourth light-emitting element ED4 can be formed by a fourth anode electrode AE4, a fourth light-emitting layer EL4, and a cathode electrode CE.

[0189] The cross-sectional structure taken along line XY in FIG. 7 will be described in more detail below with reference to FIGS. 8 and 9. FIG.

[0190] The portion indicated by the XY lines in FIG. 7 includes a part of the optical bezel area OBA and a part of the optical area OA, with the boundary between the optical bezel area OBA and the optical area OA as the reference.

[0191] 7 may include the first light-emitting area EA1 and the fourth light-emitting area EA4 included in the optical area OA, and the second light-emitting area EA2 included in the optical bezel area OBA. The first light-emitting area EA1, the fourth light-emitting area EA4, and the second light-emitting area EA2 are examples of light-emitting areas EA that emit light of the same color.

[0192] 8 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure, taken along an optical bezel area OBA and an optical area OA of the display panel 110. However, like FIG. 5, FIG. 8 is a cross-sectional view of a case where a 1:1 circuit unit connection method is applied.

[0193] Referring to FIG. 8, the display panel 110 may include, in a vertical structure, a transistor forming part, a light emitting element forming part, and an encapsulation part.

[0194] The transistor forming part may include a substrate SUB, a first buffer layer BUF1 on the substrate SUB, and various transistors DT1, DT2, storage capacitors Cst, and various electrodes or signal wirings formed on the first buffer layer BUF1.

[0194] The substrate SUB may include a first substrate SUB1 and a second substrate SUB2, and an intermediate film INTL between the first substrate SUB1 and the second substrate SUB2. Here, for example, the intermediate film INTL is an inorganic film that can block moisture penetration.

[0195] A bottom shield metal BSM may be disposed on the substrate SUB, and may be located below the first active layer ACT1 of the first drive transistor DT1.

[0196] The first buffer layer BUF1 may be a single layer or a multi-layer. When the first buffer layer BUF1 is a multi-layer, the first buffer layer BUF1 may include a multi-buffer layer MBUF and an active buffer layer ABUF.

[0197] Various transistors DT1, DT2, storage capacitors Cst, and various electrodes or signal wirings can be formed on the first buffer layer BUF1.

[0198] For example, the transistors DT1 and DT2 formed on the first buffer layer BUF1 can be made of the same material and located in the same layer. Alternatively, as shown in FIG. 8, the first drive transistor DT1 and the second drive transistor DT2 of the transistors DT1 and DT2 can be made of different materials and located in different layers.

[0199] Referring to FIG. 8, the first drive transistor DT1 may be a drive transistor DT for driving a first light-emitting element ED1 included in the optical area OA, and the second drive transistor DT2 may be a drive transistor DT for driving a second light-emitting element ED2 included in the optical bezel area OBA.

[0200] In other words, the first drive transistor DT1 may be a drive transistor included in the first subpixel circuit unit SPC1 for driving the first light-emitting element ED1 included in the optical area OA, and the second drive transistor DT2 may be a drive transistor included in the second subpixel circuit unit SPC2 for driving the second light-emitting element ED2 included in the optical bezel area OBA.

[0201] The formation of the first drive transistor DT1 and the second drive transistor DT2 will be described as follows.

[0202] The first drive transistor DT1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.

[0203] The second drive transistor DT2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.

[0204] The second active layer ACT2 of the second drive transistor DT2 may be located higher than the first active layer ACT1 of the first drive transistor DT1.

[0205] A first buffer layer BUF1 may be arranged below the first active layer ACT1 of the first drive transistor DT1, and a second buffer layer BUF2 may be arranged below the second active layer ACT2 of the second drive transistor DT2.

[0206] That is, the first active layer ACT1 of the first drive transistor DT1 can be located on the first buffer layer BUF1, and the second active layer ACT2 of the second drive transistor DT2 can be located on the second buffer layer BUF2, where the second buffer layer BUF2 can be located higher than the first buffer layer BUF1.

[0207] The first active layer ACT1 of the first drive transistor DT1 may be disposed on the first buffer layer BUF1, and a first gate insulating film GI1 may be disposed on the first active layer ACT1 of the first drive transistor DT1. The first gate electrode G1 of the first drive transistor DT1 may be disposed on the first gate insulating film GI1, and a first interlayer insulating film ILD1 may be disposed on the first gate electrode G1 of the first drive transistor DT1.

[0208] Here, the first active layer ACT1 of the first drive transistor DT1 may include a first channel region overlapping with the first gate electrode G1, a first source connection region located on one side of the first channel region, and a first drain connection region located on the other side of the channel region.

[0209] A second buffer layer BUF2 can be disposed on the first interlayer insulating film ILD1.

[0210] A second active layer ACT2 of the second drive transistor DT2 may be disposed on the second buffer layer BUF2, a second gate insulating film GI2 may be disposed on the second active layer ACT2, a second gate electrode G2 of the second drive transistor DT2 may be disposed on the second gate insulating film GI2, and a second interlayer insulating film ILD2 may be disposed on the second gate electrode G2.

[0211] Here, the second active layer ACT2 of the second drive transistor DT2 may include a second channel region overlapping with the second gate electrode G2, a second source connection region located on one side of the second channel region, and a second drain connection region located on the other side of the channel region.

[0212] The first source electrode S1 and the first drain electrode D1 of the first drive transistor DT1 may be disposed on the second interlayer insulating film ILD2, and the second source electrode S2 and the second drain electrode D2 of the second drive transistor DT2 may be disposed on the second interlayer insulating film ILD2.

[0213] The first source electrode S1 and the first drain electrode D1 of the first drive transistor DT1 can be connected to the first source connection region and the first drain connection region of the first active layer ACT1, respectively, via through holes in the second interlayer insulating film ILD2, the second gate insulating film GI2, the second buffer layer BUF2, the first interlayer insulating film ILD1, and the first gate insulating film GI1.

[0214] The second source electrode S2 and the second drain electrode D2 of the second drive transistor DT2 can be connected to the second source connection region and the second drain connection region of the second active layer ACT2, respectively, via through holes in the second interlayer insulating film ILD2 and the second gate insulating film GI2.

[0215] 8 shows only the first drive transistor DT1 and storage capacitor Cst included in the second subpixel circuit unit SPC2, and other transistors are omitted. Also, in FIG. 8, only the first drive transistor DT1 included in the first subpixel circuit unit SPC1 is shown, and other transistors and storage capacitors are omitted.

[0216] Referring to FIG. 8, the storage capacitor Cst included in the second subpixel circuit unit SPC2 may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.

[0217] The first capacitor electrode PLT1 can be electrically connected to the second gate electrode G2 of the second drive transistor DT2, and the second capacitor electrode PLT2 can be electrically connected to the second source electrode S2 of the second drive transistor DT2.

[0218] 8, a lower metal BML may be disposed below the second active layer ACT2 of the second drive transistor DT2. The lower metal BML may overlap all or part of the second active layer ACT2.

[0219] For example, the lower metal BML may be electrically connected to the second gate electrode G2. As another example, the lower metal BML may function as a light shield that blocks light entering from below. In this case, the lower metal BML may be electrically connected to the second source electrode S2.

[0220] The first drive transistor DT1 is a transistor for driving the first light-emitting element ED1 arranged in the optical area OA, but may also be arranged in the optical bezel area OBA.

[0221] The second drive transistor DT2 is a transistor for driving the second light-emitting element ED2 arranged in the optical bezel area OBA, and may be arranged in the optical bezel area OBA.

[0222] 8, a first planarization layer PLN1 may be disposed on the first drive transistor DT1 and the second drive transistor DT2. That is, the first planarization layer PLN1 may be disposed on the first source electrode S1 and the first drain electrode D2 of the first drive transistor DT1 and the second source electrode S2 and the second drain electrode D2 of the second drive transistor DT2.

[0223] Referring to FIG. 8, a first relay electrode RE1 and a second relay electrode RE2 may be disposed on the first planarization layer PLN1.

[0224] Here, the first relay electrode RE1 may be an electrode that relays the electrical connection between the first source electrode S1 of the first drive transistor DT1 and the first anode electrode AE1 of the first light-emitting element ED1, and the second relay electrode RE2 may be an electrode that relays the electrical connection between the second source electrode S2 of the second drive transistor DT2 and the second anode electrode AE2 of the second light-emitting element ED2.

[0225] The first relay electrode RE1 can be electrically connected to the first source electrode S1 of the first drive transistor DT1 through a hole in the first planarization layer PLN1, and the second relay electrode RE2 can be electrically connected to the second source electrode S2 of the second drive transistor DT2 through another hole in the first planarization layer PLN1.

[0226] Referring to FIG. 8, the first relay electrode RE1 and the second relay electrode RE2 may be disposed in the first optical bezel area OBA1.

[0227] Meanwhile, referring to FIG. 8, the anode extension line AEL may be connected to the first relay electrode RE1 and extended from the optical bezel area OBA to the optical area OA.

[0228] Referring to FIG. 8, the anode extension line AEL is a metal layer formed on the first relay electrode RE1 and may be made of a transparent material.

[0229] Referring to FIG. 8, the second planarization layer PLN2 may be disposed to cover the first relay electrode RE1, the second relay electrode RE2, and the anode extension line AEL.

[0230] Referring to FIG. 8, a light emitting element forming part may be located on the second planarization layer PNL2.

[0231] Referring to FIG. 8, the light emitting element formation portion may include a first light emitting element ED1, a second light emitting element ED2, and a fourth light emitting element ED4 formed on the second planarization layer PNL2.

[0232] Referring to FIG. 8, the first light-emitting element ED1 and the fourth light-emitting element ED4 may be disposed in the optical area OA, and the second light-emitting element ED2 may be disposed in the optical bezel area OBA.

[0233] 8, the first light-emitting element ED1, the second light-emitting element ED2, and the fourth light-emitting element ED4 are light-emitting elements that emit light of the same color. In the following, it is assumed that the light-emitting layers EL of the first light-emitting element ED1, the second light-emitting element ED2, and the fourth light-emitting element ED4 are formed in common, although they may be formed separately.

[0234] 8, the first light-emitting element ED1 may be configured in a region where a first anode electrode AE1, an emitting layer EL, and a cathode electrode CE overlap. The second light-emitting element ED2 may be configured in a region where a second anode electrode AE2, an emitting layer EL, and a cathode electrode CE overlap. The fourth light-emitting element ED4 may be configured in a region where a fourth anode electrode AE4, an emitting layer EL, and a cathode electrode CE overlap.

[0235] Referring to FIG. 8, the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4 may be disposed on the second planarization layer PLN2.

[0236] The second anode electrode AE2 can be connected to the second relay electrode RE2 through a hole in the second planarization layer PLN2.

[0237] The first anode electrode AE1 may be connected to an anode extension line AEL extending from the optical bezel area OBA to the optical area OA through another hole in the second planarization layer PLN2.

[0238] The fourth anode electrode AE4 can be connected to another anode extension line AEL extending from the optical bezel area OBA to the optical area OA1 through another hole in the second planarization layer PLN2.

[0239] Referring to FIG. 8, the bank BK can be disposed on the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4.

[0240] The bank BK may include a plurality of bank holes, through which a portion of each of the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4 may be exposed. That is, the plurality of bank holes formed in the bank BK may overlap a portion of each of the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4.

[0241] 8, the light-emitting layer EL can be disposed on the bank BK. The light-emitting layer EL can be in contact with a part of the first anode electrode AE1, a part of the second anode electrode AE2, and a part of the fourth anode electrode AE4 through the multiple bank holes.

[0242] Referring to FIG. 8, at least one space SPC may exist between the light-emitting layer EL and the bank BK.

[0243] 8, a cathode electrode CE may be disposed on the light-emitting layer EL. The cathode electrode CE may include a plurality of cathode holes CH. The plurality of cathode holes CH formed in the cathode electrode CE may be disposed in the optical area OA.

[0244] One cathode hole CH illustrated in FIG. 8 is a cathode hole located between the first light-emitting region EA1 and the fourth light-emitting region EA4.

[0245] 8, an encapsulation part may be disposed on the cathode electrode CE. The encapsulation part may include an encapsulation layer ENCAP formed on the cathode electrode CE.

[0246] 8, the encapsulating layer ENCAP may be a layer that prevents moisture or oxygen from penetrating into the light emitting elements ED1, ED2, and ED4 disposed thereunder. In particular, the encapsulating layer ENCAP may prevent moisture or oxygen from penetrating into the light emitting layer EL, which may include an organic layer. Here, the encapsulating layer ENCAP may be formed of a single layer or multiple layers.

[0247] 8, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2. The first encapsulation layer PAS1 and the third encapsulation layer PAS2 may be inorganic films, and the second encapsulation layer PCL may be an organic film.

[0248] By forming the second sealing layer PCL from an organic film, the second sealing layer PCL can also function as a planarizing layer.

[0249] Meanwhile, the display panel 110 according to the embodiment of the present disclosure may have a built-in touch sensor. In this case, the display panel 110 according to the embodiment of the present disclosure may include a touch sensor portion formed on the encapsulation layer ENCAP.

[0250] Referring to FIG. 8, the touch sensor unit may include a touch sensor metal TSM and a bridge metal BRG, and may further include insulating film configurations such as a sensor buffer layer S-BUF, a sensor interlayer insulating film S-ILD, and a sensor protection layer S-PAC.

[0251] The sensor buffer layer S-BUF may be disposed on the encapsulation layer ENCAP. The bridge metal BRG may be disposed on the sensor buffer layer S-BUF, and the sensor interlayer insulating film S-ILD may be disposed on the bridge metal BRG.

[0252] The touch sensor metal TSM may be disposed on the sensor interlayer insulating film S-ILD. A part of the touch sensor metal TSM may be connected to the bridge metal BRG through a hole in the sensor interlayer insulating film S-ILD.

[0253] 8, the touch sensor metal TSM and the bridge metal BRG may be disposed in the optical bezel area OBA. The touch sensor metal TSM and the bridge metal BRG may be disposed so as not to overlap with the second light-emitting area EA2 of the optical bezel area OBA.

[0254] A plurality of touch sensor metals TSM can constitute one touch electrode (or one touch electrode line), and can be arranged in the form of a mesh and electrically connected to each other. A part of the touch sensor metals TSM and another part of the touch sensor metals TSM can be electrically connected via a bridge metal BRG to constitute one touch electrode (or one touch electrode line).

[0255] The sensor protection layer S-PAC can be disposed while covering the touch sensor metal TSM and the bridge metal BRG.

[0256] On the other hand, if the display panel 110 is a type having a built-in touch sensor, in the display area DA, at least a part of the touch sensor metal TSM located on the encapsulation layer ENCAP extends, is arranged along the outer inclined surface of the encapsulation layer ENCAP, and can be electrically connected to a pad located outside the outer inclined surface of the encapsulation layer ENCAP. Here, the pad may be arranged in the non-display area NDA, or may be a metal pattern to which the touch drive circuit 260 is electrically connected.

[0257] The display panel 110 according to an embodiment of the present disclosure may further include a bank BK located on the first anode electrode AE1 but having a bank hole exposing a portion of the first anode electrode AE1, and an emitting layer EL located on the bank BK but in contact with the portion of the first anode electrode AE1 exposed through the bank hole.

[0258] The bank holes formed in the bank BK may not overlap with multiple cathode holes CH. That is, the bank BK is not depressed or penetrated at the points where the cathode holes CH are present. Therefore, the second planarization layer PLN2 and the first planarization layer PLN1 located below the bank BK are also not depressed or penetrated at the points where the cathode holes CH are present.

[0259] The upper surface of the bank BK located under the plurality of cathode holes CH may be undamaged and flat, which may mean that the process of forming the plurality of cathode holes CH in the cathode electrode CE does not damage the insulating layer, metal patterns (electrodes, wiring, etc.), or light-emitting layer EL located under the cathode electrode CE.

[0260] The process of forming a plurality of cathode holes CH in the cathode electrode CE can be briefly described as follows. A specific mask pattern (deposition prevention pattern, not shown) is deposited in advance at the position where the plurality of cathode holes CH will be formed, and then a cathode electrode material is deposited thereon. This allows the cathode electrode material to be deposited only in the area where the specific mask pattern is not present, forming a cathode electrode CE with a plurality of cathode holes CH. For example, the specific mask pattern may include an organic material. The cathode electrode material may include a magnesium-silver (Mg-Ag) alloy.

[0261] On the other hand, after the cathode electrode CE having a plurality of cathode holes CH is formed, the display panel 110 may be in a state in which the specific mask pattern is completely removed, or in which all or part of the specific mask pattern remains.

[0262] A display panel 110 according to an embodiment of the present disclosure may include a first drive transistor DT1 arranged in the optical bezel area OBA for driving a first light-emitting element ED1 arranged in the optical area OA, and a second drive transistor DT2 arranged in the optical bezel area OBA for driving a second light-emitting element ED2 arranged in the optical bezel area OBA.

[0263] The display panel 110 according to an embodiment of the present disclosure may further include a first planarization layer PLN1 disposed on the first drive transistor DT1 and the second drive transistor DT2, a first relay electrode RE1 disposed on the first planarization layer PLN1 and electrically connected to the first source electrode S1 of the first drive transistor DT1 through a hole in the first planarization layer PLN1, a second relay electrode RE2 disposed on the first planarization layer PLN1 and electrically connected to the second source electrode S2 of the second drive transistor DT2 through another hole in the first planarization layer PLN1, and a second planarization layer PLN2 disposed on the first relay electrode RE1 and the second relay electrode RE2.

[0264] The display panel 110 according to the embodiment of the present disclosure may further include an anode extension line AEL connecting the first relay electrode RE1 and the first anode electrode AE1 and located on the first planarization layer PLN1.

[0265] The second anode electrode AE2 can be electrically connected to the second relay electrode RE2 through a hole in the second planarization layer PLN2, and the first anode electrode AE1 can be electrically connected to the anode extension line AEL through another hole in the second planarization layer PLN2.

[0266] All or a part of the anode extension line AEL is disposed in the optical area OA, and the anode extension line AEL may include a transparent material. The first pixel circuit SPC1 may include a first drive transistor DT1 for driving the first light-emitting element ED1, and the second pixel circuit SPC2 may include a second drive transistor DT2 for driving the second light-emitting element ED2.

[0267] The first active layer ACT1 of the first drive transistor DT1 and the second active layer ACT2 of the second drive transistor DT2 may be different layers.

[0268] The display panel 110 according to an embodiment of the present disclosure may further include a substrate SUB, a first buffer layer BUF1 disposed between the substrate SUB and the first drive transistor DT1, and a second buffer layer BUF2 disposed between the first drive transistor DT1 and the second drive transistor DT2.

[0269] The first active layer ACT1 of the first drive transistor DT1 and the second active layer ACT2 of the second drive transistor DT2 may comprise different semiconductor materials.

[0270] For example, the second active layer ACT2 of the second drive transistor DT2 may include an oxide semiconductor material such as IGZO (indium gallium zinc oxide), IGZTO (indium gallium zinc tin oxide), ZnO (zinc oxide), CdO (cadmium oxide), InO (indium oxide), ZTO (zinc tin oxide), or ZITO (zinc indium tin oxide).

[0271] For example, the first active layer ACT1 of the first drive transistor DT1 may comprise a different semiconductor material than the second active layer ACT2 of the second drive transistor DT2.

[0272] For example, the first active layer ACT1 of the first drive transistor DT1 may include a silicon-based semiconductor material, such as low-temperature polycrystalline silicon (LTPS).

[0273] The display panel 110 according to the embodiment of the present disclosure may further include an encapsulation layer ENCAP on the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3, and a touch sensor metal TSM on the encapsulation layer ENCAP.

[0274] The touch sensor metal TSM may be arranged in the general area NA and the optical bezel area OBA. In the optical area OA, the touch sensor metal TSM may not be arranged or may be arranged at a lower density than in the general area NA and the optical bezel area OBA.

[0275] 8, the optical area OA can overlap the optical-electronic device. The optical bezel area OBA may not overlap the optical-electronic device. In some cases, a portion of the optical bezel area OBA may overlap the optical-electronic device.

[0276] The optical-electronic device overlapping the optical area OA may be the first optical-electronic device 11 and / or the second optical-electronic device 12. For example, the optical-electronic device may include a camera, an infrared sensor, an ultraviolet sensor, etc. For example, the optical-electronic device may be a device that receives visible light and performs a predetermined operation, or may be a device that receives light different from visible light (e.g., infrared light, ultraviolet light) and performs a predetermined operation.

[0277] 8, the cross-sectional structure of the general area NA may be the same as the cross-sectional structure of the optical bezel area OBA, except that the first subpixel circuit unit SPC1 arranged in the optical bezel area OBA to drive the first light-emitting element ED1 arranged in the optical area OA is not arranged in the general area NA.

[0278] 9 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure, and is a cross-sectional view of an optical bezel area OBA and an optical area OA of the display panel 110. However, like FIG. 6, FIG. 9 is a cross-sectional view when a 1:2 circuit unit connection method is applied.

[0279] The cross-sectional view of Fig. 9 is basically the same as the cross-sectional view of Fig. 8. However, the cross-sectional view of Fig. 8 is different from the cross-sectional view of Fig. 8 in that the 1:1 circuit unit connection method as in Fig. 5 is applied, while the cross-sectional view of Fig. 9 is different from the 1:2 circuit unit connection method as in Fig. 6. Therefore, in the following description of the cross-sectional structure of Fig. 9, the differences from the cross-sectional structure of Fig. 8 will be mainly explained.

[0280] Referring to FIG. 9, the first light-emitting element ED1 and the fourth light-emitting element ED4 arranged in the optical area OA can be simultaneously driven by the first driving transistor DT1 arranged in the optical bezel area OBA.

[0281] 9, the anode extension line AEL may be further electrically connected to the first anode electrode AE1 and another fourth anode electrode AE4, i.e., the anode extension line AEL may be electrically connected to both the first anode electrode AE1 of the first light-emitting element ED1 and the fourth anode electrode AE4 of the fourth light-emitting element ED4.

[0282] Referring to FIG. 9, the anode extension line AEL may overlap with the cathode hole CH located between the first light emitting element ED1 and the fourth light emitting element ED4 among the plurality of cathode holes CH.

[0283] Referring to FIG. 9, the first light-emitting area EA1 formed by the first light-emitting element ED1 and the fourth light-emitting area EA4 formed by the fourth light-emitting element ED4 may be light-emitting areas that emit light of the same color.

[0284] FIG. 10 is a plan view of a first optical area OA1 of a display device according to a comparative example of the present disclosure.

[0285] Referring to FIG. 10, the display device may include a plurality of cathode holes CH in the first optical area OA1.

[0286] The display device may include a plurality of signal lines SL extending in the second direction D2. The signal lines SL may be arranged in the first direction D1.

[0287] By locating a plurality of signal lines SL arranged in a first direction D1 and extending in a second direction D2 in the first optical area OA1, the plurality of signal lines SL are arranged on an optical-electronic device, such as a camera, located below the first optical area OA1. If the optical-electronic device is a camera, the camera receives light passing between the plurality of signal lines SL to capture an image, allowing the camera to capture flare in a specific direction. For example, if a plurality of signal lines SL extending in the second direction D2 are arranged in the first direction D1, flare may occur in the first direction D1.

[0288] In order to solve this problem, the inventors of the present disclosure have invented a display device having a curved anode extension line.

[0289] FIG. 11 is a plan view of a portion of a display area of ​​a display device according to an embodiment of the present disclosure.

[0290] Referring to Figures 4, 5, 6, 8, 9 and 11, a display device according to an embodiment of the present disclosure may include a display area DA, a cathode electrode CE, a first light-emitting element ED1, a first sub-pixel circuit unit SPC1 and an anode extension line AEL.

[0291] More specifically, referring to FIG. 4, the display area DA may include a first optical area OA1 and a first optical bezel area OBA1 located on the periphery of the first optical area OA1. More specifically, referring to FIGS. 8 and 9, the cathode electrode CE may include a plurality of cathode holes CH within the first optical area OA1. The first light-emitting element ED1 may be located in the first optical area OA1 and may include a first anode electrode AE1. More specifically, referring to FIGS. 5 and 6, the first subpixel circuit unit SPC1 may be located in the first optical bezel area OBA1. Referring to FIGS. 5, 6, 8, and 9, the anode extension line AEL may electrically connect the first subpixel circuit unit SPC1 and the first anode electrode AE1. Referring to FIG. 11, the anode extension line AEL may have a curved shape.

[0292] 11, when the anode extension lines AEL extend in the second direction D2 and have a curved shape, even if the multiple anode extension lines AEL are arranged in the first direction D1, flare can be suppressed when using an optical-electronic device overlapping with a first optical region OA1. As shown in FIG. 11, the number of anode extension lines per unit area decreases from the edge of the first optical region toward the center of the first optical region. Furthermore, the multiple anode extension lines are divided into multiple groups, and the thickness of each of the multiple groups decreases from the edge of the first optical region toward the center of the first optical region.

[0293] The display device may include a plurality of anode extension lines AEL. The anode extension lines AEL refer to wiring for electrically connecting the subpixel circuit units located in the first optical bezel area OBA1 to the anode electrodes of the light-emitting elements located in the first optical area OA1, and therefore the display device may include a plurality of anode extension lines AEL.

[0294] The number of anode extension lines AEL may decrease toward the center of the first optical area OA1. For example, in row A1 of the first optical area OA1, multiple anode extension lines AEL may overlap one pixel PXL, while in row A8, which is closer to the center of the first optical area OA1, fewer anode extension lines AEL may overlap one pixel PXL. This is because the number of light-emitting elements and sub-pixel circuit units to which the anode extension lines AEL must be electrically connected decreases from row A1 to row A8.

[0295] The anode extension line AEL may be arranged so as not to overlap with the cathode hole. Referring to FIG. 11, a plurality of pixels PXL may be arranged in the first optical region OA1 and the first optical bezel region OBA1. Each pixel PXL may include, for example, a red light-emitting region EA_R, a green light-emitting region EA_G, and a blue light-emitting region EA_B. As previously described with reference to FIGS. 4 and 7, a cathode hole CH may be arranged in the first optical region OA1 to ensure transmittance. However, the cathode hole is not shown in FIG. 11.

[0296] Figures 12 and 13 are enlarged views of the first optical area OA1 in Figure 11. More specifically, Figure 12 is an enlarged view of a portion of row A6 of the first optical area OA1 in Figure 11, and Figure 13 is an enlarged view of a portion of row A8 of the first optical area OA1 in Figure 11.

[0297] 12 and 13, the anode extension line AEL can be arranged so as not to overlap with the cathode hole CH. By arranging the anode extension line AEL so as not to overlap with the cathode hole CH, the display device can ensure higher transmittance in the first optical area OA1. Furthermore, because the anode extension line AEL does not overlap with the cathode hole CH and can be positioned so as to overlap with other opaque wiring, a decrease in transmittance in the first optical area OA1 due to the anode extension line AEL can be prevented.

[0298] 12 and 13, it can be seen that the number of anode extension lines AEL is greater in the portion shown in Fig. 12 than in the portion shown in Fig. 13. Fig. 12 is an enlarged view of a portion of row A6 in the first optical region OA1 when referring to Fig. 11, and Fig. 13 is an enlarged view of a portion of row A8 in the first optical region OA1 when referring to Fig. 11. In consideration of this difference, in Fig. 12, as the anode extension lines AEL extend in the second direction D2, more pixels PXL need to be connected, and therefore more anode extension lines AEL may be arranged in the portion shown in Fig. 12.

[0299] 12 and 13, the anode extension line AEL may have a curved shape that bypasses the cathode hole CH. When the anode extension line AEL bypasses the cathode hole CH, the anode extension line AEL does not overlap with the cathode hole CH, allowing the first optical area OA1 to have high transmittance, as described above. Furthermore, when the anode extension line AEL has a curved shape, flare can be suppressed by using a camera positioned overlapping the first optical area OA1, as described above.

[0300] The cathode hole CH may have a circular shape. In this example, the anode extension line AEL may have an S-shape that bypasses the cathode hole CH. When the cathode hole CH is circular and the anode extension line AEL is S-shaped that bypasses the cathode hole CH, the anode extension line AEL does not overlap the cathode hole CH and overlaps other opaque wiring that does not overlap the cathode hole CH, thereby maximizing the transmittance of the first optical region OA1. Furthermore, since space for positioning the anode extension line AEL can be effectively secured, more anode extension lines AEL can be arranged, allowing the first optical region OA1 to have a higher number of pixels per unit area.

[0301] 12 and 13, contact holes that connect the anode electrodes that drive the light-emitting regions EA_R, EA_G, and EA_B to the anode extension lines AEL are not shown.

[0302] The display device may include a first light-emitting region EA1, a second light-emitting region EA2, and an anode connection line ACL. The first light-emitting region EA1 and the second light-emitting region EA2 may be located in a first optical region. The anode connection line ACL may connect the first light-emitting region EA1 and the second light-emitting region EA2. By including such an anode connection line ACL, some of the light-emitting regions EA1 and EA2 located in the first optical region can be simultaneously driven via a single anode connection line ACL. This allows the light-emitting regions EA_R, EA_G, and EA_B located in the first optical region to be driven using fewer anode extension lines AEL. This allows for fewer subpixel circuit units to be arranged than in the first optical bezel region, thereby reducing the thickness of the first optical bezel region. In this example, the first light-emitting region EA1 and the second light-emitting region EA2 can emit light of the same color. Emitting light of the same color may mean being identical, taking into account common errors that may occur between sub-pixels in display technology.

[0303] The anode connection line ACL can be arranged so as not to overlap with the cathode hole CH. The anode connection line ACL may also be curved so as to bypass the cathode hole CH. When the anode connection line ACL is positioned so as not to overlap with the cathode hole CH and bypasses the cathode hole CH, the transmittance of the first optical region can be maximized, allowing the optical electronic device to effectively receive light. Furthermore, when the anode connection line ACL has a curved shape, flare caused by the anode connection line ACL can be suppressed when using an optical electronic device such as a camera.

[0304] Figures 14 and 15 are diagrams schematically illustrating cross sections of anode extension lines according to embodiments of the present disclosure. More specifically, Figure 14 schematically illustrates cross sections of a first anode extension line AEL1, a second anode extension line AEL2, and a third anode extension line AEL3 included in the anode extension line AEL shown in Figure 12, and Figure 15 schematically illustrates a cross section of a first anode extension line AEL1 included in the anode extension line AEL shown in Figure 13.

[0305] Referring to Figures 14 and 15, the first anode extension line AEL1 may include a first metal layer M1, a second metal layer M2 located on the first metal layer M1, and a third metal layer M3 located on the second metal layer M2.

[0306] The first metal layer M1 and the second metal layer M2 can be arranged so as not to overlap each other. Positioning the first metal layer M1 and the second metal layer M2 so as not to overlap each other can prevent unnecessary capacitance from being generated in the display device. For example, the first metal layer M1 and the second metal layer M2 may be arranged on different layers, but may be the two most adjacent metal layers with one or more insulating films between them. When such adjacent metal layers, the first metal layer M1 and the second metal layer M2, overlap each other, the distance between the two layers is very short, which can cause capacitance that degrades the display quality of the display device. However, in the embodiment of the present disclosure, positioning the first metal layer M1 and the second metal layer M2 so as not to overlap each other can prevent degradation of display quality due to capacitance between the first metal layer M1 and the second metal layer M2.

[0307] The first metal layer M1 and the second metal layer M2 can be positioned so as not to overlap each other to form the first slit SLT1. In this example, the third metal layer M3 can be arranged so as to overlap the first slit SLT1. By positioning the third metal layer M3 so as to overlap the first slit SLT1, it is possible to effectively prevent haze defects from occurring due to the first slit SLT1.

[0308] The display device may further include a fourth metal layer M4. The fourth metal layer M4 may be a layer that does not constitute the anode extension lines AEL1, AEL2, and AEL3.

[0309] The first anode extension line AEL1 and the second anode extension line AEL2 may form a second slit SLT2. The second slit SLT2 may refer to a slit formed by the first metal layer M1 and the second metal layer M2 that constitute two adjacent anode extension lines AEL1 and AEL2. For example, the second slit SLT2 may refer to a slit formed by the second metal layer M2 that constitutes the first anode extension line AEL1 and the first metal layer M1 that constitutes the second anode extension line AEL2. The second slit SLT2 differs from the first slit SLT1 in that, while the first slit SLT1 is a slit formed by the metal layers M1 and M2 that constitute one anode extension line AEL1, the second slit SLT2 is a slit formed by the metal layers M1 and M2 that constitute two adjacent anode extension lines AEL1 and AEL2.

[0310] The fourth metal layer M4 can be positioned so as to overlap the second slits SLT2. By positioning the fourth metal layer M4 so as to overlap the second slits SLT2, it is possible to effectively prevent haze defects from occurring due to the second slits SLT2.

[0311] Furthermore, the fourth metal layer M4 can be positioned so as to overlap the first slit SLT1 as well. When not only the third metal layer M3 but also the fourth metal layer M4 are positioned so as to overlap the first slit SLT1, haze that may be caused by the first slit SLT1 can be more effectively prevented. In another embodiment, the fourth metal layer M4 covers all of the first to third metal layers M1, M2, and M3, and can prevent a parasitic capacitor from being generated between the first to third metal layers M1, M2, and M3 and the anode electrode AE.

[0312] Fig. 16 is a cross-sectional view of a display device according to an embodiment of the present disclosure. In the following description with reference to Fig. 16, matters not specifically mentioned may be the same as those previously described with reference to Figs. 8 and 9.

[0313] Referring to Figure 16, the line width w1 of the first metal layer M1 that constitutes the anode extension line AEL in the first optical area OA1 and the line width w2 of the second metal layer M2 that constitutes the anode extension line AEL in the first optical area OA1 may be the same as each other.

[0314] For example, the line widths w1 and w2 may be minimum line widths determined taking into account process tolerances. When both the line widths w1 and w2 have minimum line widths, more anode extension lines AEL can be formed. Therefore, a larger number of light-emitting elements can be driven in the first optical area OA1, allowing the display device to have excellent display quality in the first optical area OA1. In this example, the line width w1 of the first metal layer M1 and the line width w2 of the second metal layer M2 may be the same because they are both minimum line widths that can be formed taking into account process tolerances.

[0315] The anode extension lines may include a second anode extension line AEL2. The second anode extension line AEL2 may be located adjacent to the first anode extension line AEL1. A distance d1 between the first metal layer M1 of the first anode extension line AEL1 and the first metal layer M1 of the second anode extension line AEL2 may be the same as a distance d2 between the second metal layer M2 of the first anode extension line AEL1 and the second metal layer M2 of the second anode extension line AEL2.

[0316] For example, the distances d1 and d2 may be minimum distances determined in consideration of process tolerances. When both the distances d1 and d2 are minimum distances, more anode extension lines AEL can be formed. Therefore, a larger number of light-emitting elements can be driven in the first optical area OA1, resulting in superior display quality in the first optical area OA1. In this example, the distance d1 between the first metal layer M1 of the first anode extension line AEL1 and the first metal layer M1 of the second anode extension line AEL2, and the distance d2 between the second metal layer M2 of the first anode extension line AEL1 and the second metal layer M2 of the second anode extension line AEL2, are both minimum distances that can be formed in consideration of process tolerances, and therefore the distances d1 and d2 may be the same.

[0317] The first source-drain electrode SD1 may be the first source electrode or the first drain electrode previously described with reference to Figures 8 and 9. The second source-drain electrode SD2 may be the first relay electrode or the second relay electrode previously described with reference to Figures 8 and 9.

[0318] The first metal layer M1 may be located in the same layer as the first gate electrode G1 and the first capacitor electrode PLT1. The second metal layer M2 may be located in the same layer as the second capacitor electrode PLT2. The third metal layer M3 may be located in the same layer as the second gate electrode G2. The fourth metal layer M4 may be located in the same layer as the first source-drain electrode SD1.

[0319] Fig. 17 is a cross-sectional view of a display device according to an embodiment of the present disclosure. In the following description with reference to Fig. 17, matters not specifically mentioned may be the same as those previously described with reference to Figs. 8 and 9.

[0320] 17, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may be opaque. That is, in the first optical area OA1, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 constituting the anode extension lines AEL1 and AEL2 may be opaque. For example, the opaque first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may be made of the same material as the opaque metal layer constituting the thin film transistor array substrate.

[0321] If the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4 are opaque, the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4 can have higher conductivity, thereby improving the efficiency of the display device.

[0322] Furthermore, when the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are opaque, the third metal layer M3 and the fourth metal layer M4 can effectively block light passing through or diffracted by the slits SLT1 and SLT2 formed by adjacent metal layers, so that optical electronic devices such as cameras positioned overlapping with the first optical area OA1 can receive light more smoothly.

[0323] Fig. 18 is a cross-sectional view of a display device according to an embodiment of the present disclosure. In the following description with reference to Fig. 18, matters not specifically mentioned may be the same as those previously described with reference to Figs. 8 and 9.

[0324] 18, the first metal layer M1′, the second metal layer M2′, and the third metal layer M3′ may be transparent. That is, in the first optical area OA1, the first metal layer M1′, the second metal layer M2′, and the third metal layer M3′ constituting the anode extension lines AEL1 and AEL2 may be transparent. For example, the transparent first metal layer M1′, the second metal layer M2′, and the third metal layer M3′ may be made of the same material as the transparent conductive metal layer located on top of the thin film transistor array.

[0325] When the first metal layer M1', the second metal layer M2', and the third metal layer M3' are transparent, the first optical area OA1 can have a higher transmittance, so that the optical electronic device located overlapping with the first optical area OA1 can receive light more smoothly.

[0326] FIG. 19 illustrates the flare suppression effect depending on the shape of the anode extension line AEL according to an embodiment of the present disclosure.

[0327] 19, display devices according to embodiments of the present disclosure may include anode extension lines AEL of various shapes. More specifically, Example 1 is an example in which the metal layer forming the anode extension lines AEL forms slits, Example 2 is an example in which the slits formed by a metal layer overlap with a different metal layer as previously described with reference to FIGS. 14 to 18, and Example 3 is an example in which the phases of some anode extension line patterns in Example 2 are inverted. REF.1 is a comparative example in which only a camera hole is arranged in the first optical area OA1.

[0328] Looking at the flare in Examples 1 to 3, it can be seen that, compared to REF. 1, some degree of flare occurred, but none of the flare occurred in a specific direction. In other words, even if the anode extension line AEL extending in any direction is located, the flare shape is symmetrical, which effectively prevents flare from being maximized in any direction.

[0329] Specifically, both Examples 1 and 2 are excellent in flare suppression effect, and Example 3, in which the pattern phase is inverted, is not significantly different from Examples 1 and 2 in terms of flare suppression ability.

[0330] FIG. 20 is a diagram illustrating the flare suppression effect depending on the shape of the anode connection line ACL according to the comparative example and the example of the present disclosure.

[0331] Referring to Figure 20, REF.1 is a comparative example in which only a camera hole is located in the first optical area OA1, REF.2 is an example in which multiple cathode hole patterns are arranged, and the example is an example in which an anode electrode and an anode connection line ACL are located.

[0332] In REF.2, flare that is not observed in REF.1 is observed due to the cathode hole pattern. In the example, flare is suppressed more than in REF.2. Therefore, it can be seen that flare is suppressed in a display device including a curved anode connection line ACL according to an embodiment of the present disclosure.

[0333] The above-described embodiment of the present disclosure can be briefly described as follows.

[0334] The display device 100 according to the embodiment of the present disclosure may include a display area DA, a cathode electrode CE, a first light emitting element ED1, a first subpixel circuit unit SPC1, a first anode electrode AE1, and an anode extension line AEL.

[0335] The display area DA may include a first optical area OA1 and a first optical bezel area OBA1 located on the periphery of the first optical area OA1. The cathode electrode CE may include a plurality of cathode holes CH within the first optical area OA1. The first light-emitting element ED1 may be located in the first optical area OA1 and may include a first anode electrode AE1. The first subpixel circuit unit SPC1 may be located in the first optical bezel area OBA1. The anode extension line AEL may electrically connect the first subpixel circuit unit SPC1 and the first anode electrode AE1 and may be positioned so as not to overlap the cathode hole CH. The anode extension line AEL may have a curved shape.

[0336] The anode extension line AEL may have a curved shape that bypasses the cathode hole CH.

[0337] The cathode hole CH may have a circular shape, and the anode extension line AEL may have an S-shape that bypasses the cathode hole CH.

[0338] The display device 100 may include a first light-emitting region EA1 located in the first optical region OA1, a second light-emitting region EA2 located in the first optical region OA1, and an anode connection line ACL connecting the first light-emitting region EA1 and the second light-emitting region EA2. The first light-emitting region EA1 and the second light-emitting region EA2 may emit light of the same color. The anode connection line ACL may be positioned so as not to overlap with the cathode hole CH, and the anode connection line ACL may have a curved shape that bypasses the cathode hole CH.

[0339] The anode extension line AEL may include a first anode extension line AEL1. The first anode extension line AEL1 may include a first metal layer M1, a second metal layer M2 positioned on the first metal layer M1, and a third metal layer M3 positioned on the second metal layer M2. The first metal layer M1 and the second metal layer M2 may be positioned so as not to overlap each other to form a first slit SLT1. The third metal layer M3 may be positioned so as to overlap the first slit SLT1. The display device 100 may further include a fourth metal layer M3. The first metal layer M1 and the second metal layer M2 may be positioned so as not to overlap each other to form a second slit SLT2, and the fourth metal layer M4 may be positioned so as to overlap the second slit SLT2. The line width w1 of the first metal layer M1 and the line width w2 of the second metal layer M2 may be the same.

[0340] The anode extension line AEL may include a second anode extension line AEL2. The second anode extension line AEL2 may include a first metal layer M1, a second metal layer M2, and a third metal layer M3. The second anode extension line AEL2 may be located adjacent to the first anode extension line AEL1.

[0341] The distance d1 between the first metal layer M1 of the first anode extension line AEL1 and the first metal layer M1 of the second anode extension line AEL2 may be the same as the distance d2 between the second metal layer M2 of the first anode extension line AEL1 and the second metal layer M2 of the second anode extension line AEL2.

[0342] The first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may be opaque.

[0343] The first metal layer M1, the second metal layer M2, and the third metal layer M3 may be transparent.

[0344] The above description merely exemplifies the technical idea of ​​the present disclosure, and various modifications and variations are possible by a person having ordinary skill in the art to which the present disclosure pertains, without departing from the essential characteristics of the present disclosure. Furthermore, the embodiments shown in the present disclosure are for the purpose of explanation, and do not limit the technical idea of ​​the present disclosure, and therefore the scope of the technical idea of ​​the present disclosure is not limited by these embodiments. [Explanation of symbols]

[0345] 100 display device 110 Display panel

Claims

1. a display area including a first optical area and a first optical bezel area located on the outer periphery of the first optical area; a cathode electrode including a plurality of cathode holes in the first optical region; a first light-emitting element located in the first optical region and including a first anode electrode; a first subpixel circuit portion located in the first optical bezel region; an anode extension line electrically connecting the first subpixel circuit unit and the first anode electrode and positioned so as not to overlap the cathode hole; The anode extension line has a curved shape; A display device wherein the number of the anode extension lines decreases towards the center of the first optical region.

2. 2. The display device of claim 1, wherein the number of anode extension lines overlapping one pixel in the first optical region farther from the center is greater than the number of anode extension lines overlapping one pixel in the first optical region closer to the center.

3. The display device according to claim 1 , wherein the anode extension line overlaps with other opaque wiring.

4. The display device of claim 1 , wherein the first optical region includes a first light-emitting region and a second light-emitting region.

5. 5. The display device according to claim 4, wherein the first optical region includes an anode connection line that connects the first light-emitting region and the second light-emitting region and does not overlap the cathode hole.

6. The display device according to claim 5 , wherein the first light-emitting region and the second light-emitting region are simultaneously driven via the anode connecting line.

7. The display device of claim 6 , wherein the first light-emitting region and the second light-emitting region emit light of the same color.

8. The display device of claim 6 , wherein the first light-emitting region and the second light-emitting region emit light of different colors.

9. a display area including a first optical area including a first light-emitting area and a second light-emitting area, and a first optical bezel area located on the outer periphery of the first optical area; a cathode electrode including a plurality of cathode holes in the first optical region; an anode connection line that connects the first light-emitting region and the second light-emitting region and does not overlap the cathode hole; A display device comprising:

10. a first light-emitting element located in the first optical region and including a first anode electrode; a first subpixel circuit portion located in the first optical bezel region; The display device according to claim 9 , further comprising:

11. an anode extension line electrically connecting the first subpixel circuit unit and the first anode electrode and positioned so as not to overlap the cathode hole; The display device according to claim 10 , wherein the anode extension line has a curved shape.

12. The display device of claim 11 , wherein the anode extension line overlaps with other opaque wiring.

13. The display device according to claim 9 , wherein the first light-emitting region and the second light-emitting region are simultaneously driven via the anode connecting line.

14. 14. The display device of claim 13, wherein the first light-emitting region and the second light-emitting region emit light of the same color.

15. 14. The display device of claim 13, wherein the first light-emitting region and the second light-emitting region emit light of different colors.

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