Dimmer and display device

Abstract

To provide a dimmer and a display device with which dimming can be performed in halftone, and dimming performance can be improved.SOLUTION: A dimmer according to the present disclosure comprises: a dimming panel including a plurality of row electrodes extending in a first direction, a plurality of column electrodes extending in a second direction intersecting the first direction, and a dimming layer having a plurality of dimming regions demarcated in a matrix form by the plurality of row electrodes and the plurality of column electrodes; and a dimming control device for exercising control on which one of a plurality of pattern voltages of a predetermined voltage waveform should be applied to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the grayscale of each of the plurality of dimming regions. In each of a plurality of frame periods mutually differing in respective periods constituting a repeat period indicating a period in which units dimming control is repeated, the dimming control device selects the pattern voltage to be applied to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the grayscale of each of the plurality of dimming regions.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a light control device and a display device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there has been known a light control device that can transmit or attenuate external light from the back surface. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-26222 [Patent Document 2] Japanese Patent Publication No. 2021-184062 Summary of the Invention [Problem to be solved by the invention]

[0004] In such a light control device, several means have been proposed for performing dimming in intermediate tones using a frame rate control (FRC) method in a passive matrix. However, there has been no proposal for a means for performing dimming in intermediate tones using a driving method that has a matrix-shaped dimming region and can set the driving voltage to zero. Therefore, the present disclosure provides a light control device and a display device that can perform light control in intermediate tones and improve light control performance. [Means for solving the problem]

[0005] The dimming device of the present disclosure comprises a dimming panel including a plurality of row electrodes extending in a first direction, a plurality of column electrodes extending in a second direction intersecting the first direction, and a dimming layer having a plurality of dimming areas partitioned in a matrix by the plurality of row electrodes and the plurality of column electrodes, and a dimming control device that controls the application of one of a plurality of pattern voltages of predetermined voltage waveforms to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the gradation of each of the plurality of dimming areas, wherein the dimming control device selects the pattern voltage to be applied to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the gradation of each of the plurality of dimming areas in each of a plurality of frame periods having different periods that constitute a repeating period that indicates a period that is a repeating unit for controlling dimming. [Effects of the Invention]

[0006] The light control device and display device according to the present disclosure can perform light control in intermediate tones and can improve light control performance. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic block diagram of a light control system including a light control device according to a first embodiment. [Figure 2] FIG. 2 is a perspective view showing a configuration of a part of the light control panel. [Figure 3] FIG. 3 is a plan view of the column electrodes and row electrodes. [Figure 4] FIG. 4 is a plan view showing a plurality of light control areas partitioned by the light control panel 2. As shown in FIG. [Figure 5] FIG. 5 is a diagram illustrating the correspondence between the gray level and the relative ON period. [Figure 6] FIG. 6 is a diagram illustrating the relationship between the dimming pattern and the on / off state of the dimming area in each frame. [Figure 7] FIG. 7 is an explanatory diagram of the pattern voltage. [Figure 8] FIG. 8 is a timing chart (part 1) corresponding to an operation example of the first embodiment. [Figure 9]FIG. 9 is a timing chart (part 2) corresponding to the operation example of the first embodiment. [Figure 10] FIG. 10 is a timing chart corresponding to an example of operation of the second row, second column to fourth column of the first embodiment. [Figure 11] FIG. 11 is an operation timing chart (part 1) of the second embodiment. [Figure 12] FIG. 12 is a second operation timing chart of the second embodiment. [Figure 13] FIG. 13 is a schematic configuration block diagram of a light control system including a light control device according to the third embodiment. [Figure 14] FIG. 14 is a diagram illustrating the operation of the third embodiment. [Figure 15] FIG. 15 is a schematic configuration block diagram of a display device to which the light control devices according to the first to third embodiments are applied. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, a light control device according to an embodiment will be described with reference to the drawings. [1] First embodiment FIG. 1 is a schematic block diagram of a light control system including a light control device according to a first embodiment. The light control system 1 includes an analysis device 10 and a light control device 20. The analysis device 10 receives a request command CMD related to dimming from a higher-level controller such as a personal computer. The request command CMD may be, for example, instruction data for the gradation level distribution of the dimming panel in response to external light, or image data corresponding to an image to be displayed when the dimming panel is used as a display device. The analysis device 10 analyzes the received request command CMD, generates a dimming signal SDM in accordance with the analysis result, and supplies the dimming signal SDM to the dimming device 20.

[0009] As shown in FIG. 1, the light control device 20 includes a light control panel 21, a row electrode drive circuit 22, a column electrode drive circuit 23, an arithmetic circuit 24, a reference voltage generation circuit 25, and a timing generation circuit 26.

[0010] FIG. 2 is a perspective view showing a configuration of a part of the light control panel. As shown in FIG. 2, the light control panel 21 includes a light control layer 31, a plurality of column electrodes EY1 to EY5, and a plurality of row electrodes EX1 to EX3.

[0011] The light control layer 31 extends in a substantially plate-like shape in the X and Y directions. The light control layer 31 includes, for example, a plate-shaped member 31a and a light control liquid crystal 31b sealed in the plate-shaped member 31a. 2, the +Z side of the light-switching layer 31 is the front side, and the −Z side is the back side. The +Z side surface of the box-shaped member 31a forms the front side of the light-switching layer 31, and the −Z side surface of the member 31a forms the back side of the light-switching layer 31.

[0012] The column electrodes EY1 to EY5 are disposed on the front surface side (+Z side) of the light control layer 31. The column electrodes EY1 to EY5 are provided, for example, on a substrate 32 disposed on the front surface of the light control layer 31. The substrate 32 may be adhered to the front surface of the light control layer 31 with an adhesive or the like. The substrate 32 is formed in the shape of a plate extending in the X and Y directions.

[0013] The column electrodes EY1 to EY5 are made of a transparent conductive material such as ITO, etc. The substrate 32 is made of a transparent insulating resin, etc.

[0014] FIG. 3 is a plan view of the column electrodes and row electrodes. 3(a), on the substrate 22, the column electrodes EY1 to EY5 are insulated from one another by the insulating portions 32a and 32b and are arranged in the X direction. As a result, the column electrodes EY1 to EY5 are arranged in the X direction along the front surface of the light-controlling layer 31. On the substrate 22, the column electrodes EY1 to EY5 extend in the Y direction. The insulating portions 32a extend in the Y direction between the column electrodes EY1 to EY5. The insulating portions 32b extend in the X direction and connect the +Y side ends of the insulating portions 32a.

[0015] The row electrodes EX1 to EX3 shown in FIG. 2 are arranged on the -Z side of the light control layer 31. The row electrodes EX1 to EX3 may be arranged on a substrate 33 arranged on the back surface of the light control layer 31. The row electrodes EX1 to EX3 face the column electrodes EY1 to EY5 with the light control layer 31 in between. The substrate 33 may be attached to the back surface of the light control layer 31 via an adhesive or the like. The substrate 33 extends in a plate shape in the X and Y directions. Each row electrode EX may be made of a transparent conductive material such as ITO. The substrate 33 is made of, for example, a transparent insulating resin or the like.

[0016] 3(b), on the substrate 33, the row electrodes EX1 to EX3 are insulated from one another by insulating portions 33a and 33b and are arranged in the Y direction. As a result, the row electrodes EX1 to EX3 are arranged in the Y direction along the front surface of the light-controlling layer 31. On the substrate 33, the row electrodes EX1 to EX3 extend in the X direction. The insulating portions 33a extend in the X direction between the row electrodes EX1 to EX3. The insulating portions 33b extend in the Y direction and connect the +X side ends of the insulating portions 33a.

[0017] FIG. 4 is a plan view showing a plurality of light control areas partitioned by the light control panel 2. As shown in FIG. In the light-modulating layer 31 shown in FIG. 2, a plurality of light-modulating regions R(1,1) to R(5,3) as shown in FIG. 4 are defined at a plurality of intersections between the plurality of column electrodes EY1 to EY5 and the plurality of row electrodes EX1 to EX3. The following describes an example of the correspondence between the column electrodes EY1 to EY5 and row electrodes EX1 to EX3 and the dimming regions R(1,1) to R(5,3).

[0018] The dimming region R(1,1) is formed at a position where the row electrode EX1 and the column electrode EY1 intersect when viewed from the Z direction in the dimming layer 31. In the dimming region R(1,1), one pattern voltage VX1 of a plurality of pattern voltages with a predetermined voltage waveform is applied from the row electrode EX1 on the -Z side, and one pattern voltage VY1 of a plurality of pattern voltages with a predetermined voltage waveform is applied from the column electrode EY1 on the +Z side.

[0019] The dimming region R(1,2) is formed at a position where the row electrode EX1 and the column electrode EY2 intersect when viewed from the Z direction in the dimming layer 31. In the dimming region R(1,2), one pattern voltage VX1 from a plurality of pattern voltages with a predetermined voltage waveform is applied from the row electrode EX1 on the -Z side, and one pattern voltage VY2 from a plurality of pattern voltages with a predetermined voltage waveform is applied from the column electrode EY2 on the +Z side.

[0020] The dimming region R(1,3) is formed at a position where the row electrode EX1 and the column electrode EY3 intersect when viewed from the Z direction in the dimming layer 31. In the dimming region R(1,3), one pattern voltage VX1 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the row electrode EX1 on the -Z side, and one pattern voltage VY3 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the column electrode EY3 on the +Z side.

[0021] The dimming region R(1,4) is formed at a position where the row electrode EX1 and the column electrode EY4 intersect when viewed from the Z direction in the dimming layer 31. In the dimming region R(1,4), one pattern voltage VX1 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the row electrode EX1 on the -Z side, and one pattern voltage VY4 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the column electrode EY4 on the +Z side.

[0022] The dimming region R(1,5) is formed at a position where the row electrode EX1 and the column electrode EY5 intersect when viewed from the Z direction in the dimming layer 31. In the dimming region R(1,5), one pattern voltage VX1 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the row electrode EX1 on the -Z side, and one pattern voltage VY5 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the column electrode EY5 on the +Z side.

[0023] The dimming region R(2,1) is formed at a position where the row electrode EX2 and the column electrode EY1 intersect when viewed from the Z direction in the dimming layer 31. In the dimming region R(2,1), one pattern voltage VX2 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the row electrode EX2 on the -Z side, and one pattern voltage VY1 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the column electrode EY1 on the +Z side.

[0024] The dimming region R(3,1) is formed at a position where the row electrode EX3 and the column electrode EY1 intersect when viewed from the Z direction in the dimming layer 31. In the dimming region R(3,1), one pattern voltage VX3 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the row electrode EX3 on the -Z side, and one pattern voltage VY1 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the column electrode EY1 on the +Z side.

[0025] The dimming region R(3,5) is formed at a position where the row electrode EX3 and the column electrode EY5 intersect when viewed from the Z direction in the dimming layer 31. In the dimming region R(3,5), one pattern voltage VX3 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the row electrode EX3 on the -Z side, and one pattern voltage VY5 out of a plurality of pattern voltages with a predetermined voltage waveform is applied from the column electrode EY5 on the +Z side. The same applies to the other light control regions R(2,2) to R(2,5) and R(3,2) to R(3,4).

[0026] The row electrode drive circuit 22 is electrically connected to the plurality of row electrodes EX1 to EX3. The row electrode drive circuit 3 drives each of the plurality of row electrodes EX1 to EX3 in synchronization with a clock signal, using a reference voltage, with a voltage waveform according to a row control signal. The row electrode drive circuit 22 is capable of individually driving the plurality of row electrodes EX1 to EX3. The row electrode drive circuit 22 selects one of the plurality (three in this embodiment) of pattern voltages (pattern voltages Va, Vb, and Vc in this embodiment) according to the row control signal. Then, the row electrode drive circuit 22 supplies the selected pattern voltage to the row electrodes EX1 to EX3 in synchronization with the clock signal.

[0027] The column electrode drive circuit 23, like the row electrode drive circuit 22, is electrically connected to the plurality of column electrodes EY1 to EY5. The column electrode drive circuit 23 drives each of the plurality of column electrodes EY1 to EY4 using a reference voltage in synchronization with a clock signal with a voltage waveform corresponding to a column control signal. The column electrode drive circuit 4 can drive the plurality of column electrodes EY1 to EY4 individually. The column electrode drive circuit 4 selects either a first reference voltage or a second reference voltage in response to the column control signal. The column electrode drive circuit 4 can supply the selected reference voltage to the column electrodes EY1 to EY4 in synchronization with the clock signal.

[0028] The arithmetic circuit 24 is electrically connected between the analysis device 10 and the row electrode drive circuit 22 and column electrode drive circuit 23. The arithmetic circuit 24 receives a dimming signal SDM from the analysis device 10. A plurality of pattern voltages are set in advance in the dimming device 20. The plurality of pattern voltages may be set in advance in the arithmetic circuit 24, the row electrode drive circuit 22, and the column electrode drive circuit 23, respectively. The dimming signal SDM includes an instruction to specify pattern voltages to be supplied to a plurality of column electrodes EY1 to EY5, and an instruction to specify pattern voltages to be supplied to a plurality of row electrodes EX1 to EX3, from the plurality of pattern voltages.

[0029] The arithmetic circuit 24 generates a column control signal corresponding to the dimming signal SDM in synchronization with the clock signal, supplies the signal to the column electrode drive circuit 23, and generates a row control signal corresponding to the dimming signal SDM, supplies the signal to the row electrode drive circuit 22. The column control signal includes an instruction for a pattern voltage to be supplied to each column electrode EY. The row control signal includes an instruction for a pattern voltage to be supplied to each row electrode EX.

[0030] The reference voltage generation circuit 25 is electrically connected to the row electrode drive circuit 22 and the column electrode drive circuit 23. The reference voltage generation circuit 25 generates a reference voltage and supplies the reference voltage to the row electrode drive circuit 22 and the column electrode drive circuit 23.

[0031] The reference voltage generation circuit 25 may generate a first reference voltage (="H" level) and a second reference voltage (="L" level). The reference voltage generation circuit 25 may generate the reference voltages using a bandgap voltage (for example, the forward voltage of a diode) corresponding to the bandgap energy of a semiconductor. The reference voltage generation circuit 6 may supply the first reference voltage and the second reference voltage to the row electrode drive circuit 3 and the column electrode drive circuit 4, respectively.

[0032] The timing generation circuit 26 is electrically connected to each of the row electrode drive circuit 22, the column electrode drive circuit 23, and the arithmetic circuit 24. The timing generation circuit 26 generates a clock signal, and supplies the clock signal to each of the row electrode drive circuit 22, the column electrode drive circuit 23, and the arithmetic circuit 24. The timing generation circuit 26 can also be configured to generate a clock signal using a reference clock signal from an oscillator.

[0033] In the following description, the dimming device 20 is assumed to be capable of displaying five gradations, and in one dimming region, the state in which the most external light is transmitted is assumed to be gradation level = 1, and the state in which the most external light is attenuated (or blocked) is assumed to be gradation level = 0.

[0034] Furthermore, the dimming device 20 defines a state in which approximately 75% of external light is transmitted relative to the amount of light transmitted at gradation level = 1 as gradation level = 3 / 4, a state in which approximately 50% of external light is transmitted relative to the amount of light transmitted at gradation level = 1 as gradation level = 2 / 4, and a state in which approximately 25% of external light is transmitted relative to the amount of light transmitted at gradation level = 1 as gradation level = 1 / 4. Then, the light control device 20 determines which of the gradation levels 0 to 1 should be applied to each of the light control regions in accordance with the light control signal, and performs control.

[0035] Next, the operating principle of the embodiment will be described. In this embodiment, frame rate control (FRC) is adopted, and in each dimming region, in order to express intermediate gradation levels, a repeating period indicating a period that is a repeating unit for controlling dimming is used, which is a plurality of frames (in this embodiment, four frames, frame 0 to frame 3) with different durations.

[0036] FIG. 5 is a diagram illustrating the correspondence between the gray level and the relative ON period. Here, the relative on period refers to the proportion of the period during which each dimming area is in the on state in one repeating period, when the external light transmitting state of each dimming area (corresponding to gradation level = 1) is represented as the on state and the external light blocking state (corresponding to gradation level = 0) is represented as the off state.

[0037] More specifically, as shown in Fig. 5, when the length of one repeating period is 1, in the dimming region where the gradation level is 0, the length of the period in the on state is 0. In other words, this indicates that there is no time at all in the on state during one repeating period.

[0038] Furthermore, when the gradation level is 1 / 4, the length of the ON period is 0.1, which means that the proportion of ON states during one repeat period is 10% (=0.1 / 1×100).

[0039] Furthermore, when the gradation level is 2 / 4, the length of the ON period is 0.2, which means that the proportion of ON states during one repeat period is 20% (=0.2 / 1×100).

[0040] Furthermore, when the gradation level is 3 / 4, the length of the ON period is 0.4, which means that the proportion of ON states during one repeat period is 40% (=0.4 / 1×100).

[0041] Furthermore, when the gradation level is 1, the length of the period in the on state is 1. In other words, it indicates that the state is on throughout one repetition period, and the proportion of this state is 100% (=1 / 1×100). In other words, gray scales can be expressed by changing the length of the ON state of the dimming region in one repeating period.

[0042] FIG. 6 is a diagram illustrating the relationship between the dimming pattern and the on / off state of the dimming area in the frame. The dimming pattern PTN is configured to correspond to 3×5 dimming regions as shown in FIG.

[0043] Specifically, as shown in FIG. 6(a), in the dimming pattern PTN, the areas corresponding to the dimming areas R(1,1) to R(1,5), R(2,5) and R(3,5) shown in FIG. 4 are set to a gradation level of 1. In addition, in the dimming pattern PTN, the areas corresponding to the dimming area R(2,4) and the dimming area R(3,4) shown in FIG. 4 are set to a gradation level of 3 / 4.

[0044] In addition, in the dimming pattern PTN, the areas corresponding to the dimming area R(2,3) and the dimming area R(3,3) shown in FIG. 4 are set to a gradation level of 2 / 4. In addition, in the dimming pattern PTN, the areas corresponding to the dimming area R(2,2) and the dimming area R(3,2) shown in FIG. 4 are set to a gradation level of 1 / 4.

[0045] In addition, in the dimming pattern PTN, the areas corresponding to the dimming area R(2,1) and the dimming area R(3,1) shown in FIG.

[0046] In the case of the dimming pattern PTN shown in FIG. 6(a), during the frame period of frame FM0, the gradation area where the gradation level is 1 is in the ON state, and the area where the gradation level is less than 1 is in the OFF state.

[0047] More specifically, as shown in FIG. 6(b), the areas corresponding to the dimming region R(1,1) to dimming region R(1,5), dimming region R(2,5) and dimming region R(3,5) shown in FIG. 4 are in the ON state, and the areas corresponding to the dimming region R(2,1) to dimming region R(2,4) and dimming region R(3,1) to dimming region R(3,4) are in the OFF state. The period ratio of the frame period of frame FM0 is set to 0.6.

[0048] In the case of the dimming pattern PTN shown in FIG. 6(a), during the frame period of frame FM1, the gradation area where the gradation level is 3 / 4 or higher is in the ON state, and the area where the gradation level is less than 3 / 4 is in the OFF state.

[0049] More specifically, as shown in FIG. 6(c), the areas corresponding to the dimming region R(1,1) to dimming region R(1,5), the dimming region R(2,4) to dimming region (2,5), and the dimming region R(3,4) to dimming region R(3,5) shown in FIG. 4 are in the ON state, and the areas corresponding to the dimming region R(2,1) to dimming region R(2,3) and the dimming region R(3,1) to dimming region R(3,3) are in the OFF state. The period ratio of the frame period of the frame FM1 is set to 0.2.

[0050] In the case of the dimming pattern PTN shown in FIG. 6(a), during the frame period of frame FM2, the gradation area with a gradation level of 2 / 4 or more is in the ON state, and the dimming area with a gradation level of less than 2 / 4 is in the OFF state.

[0051] More specifically, as shown in FIG. 6(d), the areas corresponding to the dimming region R(1,1) to dimming region R(1,5), the dimming region R(2,3) to dimming region (2,5), and the dimming region R(3,3) to dimming region R(3,5) shown in FIG. 4 are set to the ON state, and the areas corresponding to the dimming region R(2,1) to dimming region R(2,2) and the dimming region R(3,1) to dimming region R(3,2) are set to the OFF state. The period ratio of the frame period of frame FM2 is set to 0.1.

[0052] In the case of the dimming pattern PTN shown in FIG. 6(a), during the frame period of frame FM3, the gradation areas with a gradation level of 1 / 4 or more are set to the ON state, and the dimming areas with a gradation level of less than 1 / 4, i.e., in this embodiment, gradation level = 0, are set to the OFF state.

[0053] More specifically, as shown in FIG. 6(e), the areas corresponding to the dimming region R(1,1) to dimming region R(1,5), dimming region R(2,2) to dimming region (2,5), and dimming region R(3,2) to dimming region R(3,5) shown in FIG. 4 are set to the ON state, and the areas corresponding to the dimming region R(2,1) and dimming region R(3,1) are set to the OFF state. The period ratio of the frame period of frame FM3 is set to 0.1.

[0054] As a result, the relative on-periods in the areas corresponding to the dimming region R(1,1) to dimming region R(1,5), dimming region R(2,5) and dimming region R(3,5) shown in Figure 4 total 1, which corresponds to a gradation level of 1.

[0055] In addition, in the dimming pattern PTN, the relative on-periods in the areas corresponding to the dimming area R(2,4) and the dimming area R(3,4) shown in FIG. 4 are 0.4 in total, which corresponds to a gradation level of 3 / 4.

[0056] In addition, in the dimming pattern PTN, the relative on-periods in the areas corresponding to the dimming area R(2,3) and the dimming area R(3,3) shown in FIG. 4 are 0.2 in total, which corresponds to a gradation level of 2 / 4.

[0057] In addition, in the dimming pattern PTN, the relative on periods in the areas corresponding to the dimming area R(2,2) and dimming area R(3,2) shown in FIG. 4 are 0.1 in total, which corresponds to a gradation level of 1 / 4.

[0058] In the dimming pattern PTN, the relative on periods in the areas corresponding to the dimming area R(2,1) and the dimming area R(3,1) shown in FIG.

[0059] As explained above, in each dimming region, during a certain repeating period (= a period corresponding to successive frames FM0 to FM), grayscale display is performed by controlling the on state (light-transmitting state) and off state (light-blocking state) in frames FM0 to FM3 so that the relative on period corresponds to the gradation level corresponding to the dimming pattern PTN.

[0060] Next, the selection and application of pattern voltages for realizing the dimming pattern PTN will be described. First, the pattern voltage of the embodiment will be described. FIG. 7 is an explanatory diagram of the pattern voltage.

[0061] In this embodiment, there are three types of pattern voltages: pattern voltage Va, pattern voltage Vb, and pattern voltage Vc.

[0062] Each of the pattern voltages Va to Vc has a divided period obtained by equally dividing each frame period of frames FM0 to FM3 into three, and maintains a signal level ("H" level or "L" level) at least during each divided period. In this case, the frame periods of frames FM0 to FM3 have different lengths, and in this embodiment, the ratios of the frame periods are as follows: FM0:FM1:FM2:FM3=0.6:0.2:0.1:0.1

[0063] Here, each of the pattern voltages Va to Vc is a binary level signal, and is a combination of either a high level "1" or a low level "0."

[0064] In the example of Figure 7, in the first frame period PFM1, the pattern voltage Va has signal levels of "1", "1", "1" from the period before the three periods obtained by dividing the first frame period PFM1 into thirds (= the three sub-frame periods of the frame period PFM1; similarly below), and has signal levels of "0", "0", "0" from the period before the three periods obtained by dividing the second frame period PFM2 following the first frame period PFM1 into thirds (= the three sub-frame periods of the frame period PFM2; similarly below).

[0065] In addition, the signal levels of the pattern voltage Vb are "0", "0", and "1" from the period before the three periods obtained by dividing the first frame period PFM1 into thirds, and the signal levels are "1", "1", and "0" from the period before the three periods obtained by dividing the second frame period PFM2 following the first frame period PFM1 into thirds.

[0066] In addition, the signal levels of the pattern voltage Vc are "1", "0", "0" from the period before the three periods obtained by dividing the first frame period into thirds, and the signal levels are "0", "1", "1" from the period before the three periods obtained by dividing the second frame period following the first frame period into thirds. Furthermore, the pattern voltages Va to Vc have the same effective value over a predetermined period (=two frame periods). That is, in this embodiment, each of the pattern voltages Va to Vc has a signal level of "1" for one frame period and a signal level of "0" for one frame period over two frame periods.

[0067] Next, the operation of the embodiment will be described in detail. In the following explanation, the operation will be described so that the dimming pattern PTN shown in FIG. 6(a) is changed to the states of frames FM0 to FM3 shown in FIGS. 6(b) to 6(e).

[0068] FIG. 8 is a timing chart (part 1) corresponding to an operation example of the first embodiment. (Period corresponding to frame FM0) First, in the period corresponding to frame FM0, the arithmetic circuit 24 applies the pattern voltage Vc to the row electrode EX1, and applies the pattern voltage Vb to the row electrodes EX2 and EX3.

[0069] Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrodes EY1 to EY4, and a pattern voltage Va to the column electrode EY5.

[0070] As a result, the pattern voltage Vc is applied to the dimming regions R(1,1) to R(1,4) from the corresponding row electrodes, and the pattern voltage Vb is applied to the corresponding column electrodes. Therefore, the dimming regions R(1,1) to R(1,4) are in the ON state for 2 / 3 of the frame period of frame FM0, and are in the OFF state for 1 / 3 of the frame period of frame FM0. Therefore, during the period corresponding to frame FM0, the dimming regions R(1,1) to R(1,4) are effectively in the ON state (transmitting state).

[0071] Furthermore, the dimming region R(1,5) receives a pattern voltage Vc from the corresponding row electrode and a pattern voltage Va from the corresponding column electrode. Therefore, the dimming region R(1,5) is in the ON state for ⅔ of the frame period of frame FM0 and in the OFF state for ⅓ of the frame period of frame FM0. Therefore, during the period corresponding to frame FM0, the dimming region R(1,5) is effectively in the ON state (transmitting state).

[0072] Furthermore, to dimming region R(2,5) and dimming region R(3,5), pattern voltage Vb is applied from the corresponding row electrode, and pattern voltage Va is applied from the corresponding column electrode. Therefore, dimming region R(2,5) and dimming region R(3,5) are in the ON state for 2 / 3 of the frame period of frame FM0, and are in the OFF state for 1 / 3 of the frame period of frame FM0, and dimming region R(2,5) and dimming region R(3,5) are effectively in the ON state (transmitting state).

[0073] Furthermore, to the dimming regions R(2,5) and R(3,5), a pattern voltage Vb is applied from the corresponding row electrode, and a pattern voltage Va is applied from the corresponding column electrode. Therefore, the dimming regions R(2,5) and R(3,5) are in the ON state for ⅔ of the frame period of frame FM0, and are in the OFF state for ⅓ of the frame period of frame FM0. Therefore, during the period corresponding to frame FM0, the dimming regions R(2,5) and R(3,5) are effectively in the ON state (transmitting state).

[0074] Furthermore, to the dimming region R(2,1) to dimming region R(2,4) and the dimming region R(3,1) to dimming region R(3,4), a pattern voltage Vb is applied from the corresponding row electrode, and a pattern voltage Vb is applied from the corresponding column electrode. Therefore, the dimming region R(2,1) to dimming region R(2,4) and the dimming region R(3,1) to dimming region R(3,4) are in the off state for the entire frame period of frame FM0. Therefore, during the period corresponding to frame FM0, the dimming region R(2,1) to dimming region R(2,4) and the dimming region R(3,1) to dimming region R(3,4) are effectively in the off state (light-blocking state).

[0075] First, for ease of understanding, the operation of the dimming regions R(1,1) to R(1,5) corresponding to the row electrode EX1 and column electrodes EY1 to EY5 will be described.

[0076] (Period corresponding to frame FM1) Next, in the period corresponding to frame FM1, the arithmetic circuit 24 applies the pattern voltage Vc to the row electrode EX1, and applies the pattern voltage Vb to the row electrodes EX2 and EX3. Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrodes EY1 to EY3, and applies a pattern voltage Va to the column electrodes EY4 and EY5.

[0077] As a result, the pattern voltage Vc is applied to the dimming regions R(1,1) to R(1,3) from the corresponding row electrodes, and the pattern voltage Vb is applied to the corresponding column electrodes. Therefore, the dimming regions R(1,1) to R(1,3) are in the ON state for ⅔ of the frame period of frame FM1, and are in the OFF state for ⅓ of the frame period of frame FM1. Therefore, during the period corresponding to frame FM1, the dimming regions R(1,1) to R(1,3) are effectively in the ON state (transmitting state).

[0078] Furthermore, to the dimming region R(1,4) and the dimming region R(1,5), a pattern voltage Vc is applied from the corresponding row electrode, and a pattern voltage Va is applied from the corresponding column electrode. Therefore, the dimming region R(1,4) and the dimming region R(1,5) are in the ON state for ⅔ of the frame period of the frame FM1, and are in the OFF state for ⅓ of the frame period of the frame FM1. Therefore, during the period corresponding to the frame FM1, the dimming region R(1,4) and the dimming region R(1,5) are effectively in the ON state (transmitting state).

[0079] Furthermore, a pattern voltage Vb is applied to dimming region R(2,4), dimming region R(2,5), dimming region R(3,4), and dimming region R(3,5) from the corresponding row electrodes, and a pattern voltage Va is applied to dimming region R(2,4), dimming region R(2,5), dimming region R(3,4), and dimming region R(3,5) from the corresponding column electrodes, so that dimming region R(2,4), dimming region R(2,5), dimming region R(3,4), and dimming region R(3,5) are in the ON state for two-thirds of the frame period of frame FM1 and in the OFF state for one-third of the frame period of frame FM1. Therefore, during the period corresponding to frame FM1, dimming region R(2,4), dimming region R(2,5), dimming region R(3,4), and dimming region R(3,5) are effectively in the ON state (transmitting state).

[0080] Furthermore, to the dimming region R(2,1) to dimming region R(2,3) and the dimming region R(3,1) to dimming region R(3,3), a pattern voltage Vb is applied from the corresponding row electrode, and a pattern voltage Vb is applied from the corresponding column electrode. Therefore, the dimming region R(2,1) to dimming region R(2,3) and the dimming region R(3,1) to dimming region R(3,3) are in the off state for the entire frame period of frame FM1. Therefore, during the period corresponding to frame FM1, the dimming region R(2,1) to dimming region R(2,3) and the dimming region R(3,1) to dimming region R(3,3) are effectively in the off state (light-blocking state).

[0081] (Period corresponding to frame FM2) Next, in the period corresponding to frame FM2, the arithmetic circuit 24 applies the pattern voltage Vc to the row electrode EX1, and applies the pattern voltage Vb to the row electrodes EX2 and EX3. Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to each of the column electrodes EY1 and EY2, and applies a pattern voltage Va to each of the column electrodes EY3 to EY5.

[0082] As a result, pattern voltage Vc is applied to dimming region R(1,1) and dimming region R(1,2) from the corresponding row electrodes, and pattern voltage Vb is applied to dimming region R(1,1) and dimming region R(1,2) from the corresponding column electrodes. Therefore, dimming region R(1,1) and dimming region R(1,2) are in the ON state for ⅔ of the frame period of frame FM2, and are in the OFF state for ⅓ of the frame period of frame FM2. Therefore, dimming region R(1,1) and dimming region R(1,2) are effectively in the ON state (transmitting state) during the period corresponding to frame FM2.

[0083] Furthermore, to dimming regions R(1,3) to R(1,5), pattern voltage Vc is applied from the corresponding row electrode, and pattern voltage Va is applied from the corresponding column electrode. Therefore, dimming regions R(1,3) to R(1,5) are in the ON state for ⅔ of the frame period of frame FM2, and are in the OFF state for ⅓ of the frame period of frame FM2. Therefore, dimming regions R(1,3) to R(1,5) are effectively in the ON state (transmitting state) during the period corresponding to frame FM2.

[0084] Furthermore, to dimming region R(2,3) through dimming region R(2,5) and dimming region R(3,3) through dimming region R(3,5), pattern voltage Vb is applied from the corresponding row electrode, and pattern voltage Va is applied from the corresponding column electrode. Therefore, dimming region R(2,3) through dimming region R(2,5) and dimming region R(3,3) through dimming region R(3,5) are in the ON state for two-thirds of the frame period of frame FM2, and are in the OFF state for one-third of the frame period of frame FM2. Therefore, during the period corresponding to frame FM2, dimming region R(2,3) through dimming region R(2,5) and dimming region R(3,3) through dimming region R(3,5) are effectively in the ON state (transmitting state).

[0085] Furthermore, to dimming regions R(2,1) and R(2,2) and dimming regions R(3,1) and R(3,2), pattern voltage Vb is applied from the corresponding row electrodes, and pattern voltage Vb is applied from the corresponding column electrodes. Therefore, dimming regions R(2,1) and R(2,2) and dimming regions R(3,1) and R(3,2) are in the off state for the entire frame period of frame FM2. Therefore, during the period corresponding to frame FM2, dimming regions R(2,1) and R(2,2) and dimming regions R(3,1) and R(3,2) are effectively in the off state (light-blocking state).

[0086] (Period corresponding to frame FM3) Next, in the period corresponding to frame FM3, the arithmetic circuit 24 applies the pattern voltage Vc to the row electrode EX1, and applies the pattern voltage Vb to the row electrodes EX2 and EX3. Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY1, and applies a pattern voltage Va to the column electrodes EY2 to EY5.

[0087] As a result, the pattern voltage Vc is applied to the dimming region R(1,1) from the corresponding row electrode, and the pattern voltage Vb is applied to the corresponding column electrode. Therefore, the dimming region R(1,1) is in the ON state for ⅔ of the frame period of frame FM3, and in the OFF state for ⅓ of the frame period of frame FM3. Therefore, during the period corresponding to frame FM3, the dimming region R(1,1) is effectively in the ON state (transmitting state).

[0088] Furthermore, dimming regions R(1,2) to R(1,5) have pattern voltage Vc applied from the corresponding row electrodes and pattern voltage Va applied from the corresponding column electrodes. Therefore, they are in the ON state for 2 / 3 of the frame period of frame FM3 and in the OFF state for 1 / 3 of the frame period of frame FM0. Therefore, dimming regions R(1,2) to R(1,5) are effectively in the ON state (transmitting state) during the period corresponding to frame FM3.

[0089] Furthermore, to dimming region R(2,2) to dimming region R(2,5) and dimming region R(3,2) to dimming region (3,5), pattern voltage Vb is applied from the corresponding row electrode, and pattern voltage Va is applied from the corresponding column electrode. Therefore, they are in the ON state for 2 / 3 of the frame period of frame FM3, and in the OFF state for 1 / 3 of the frame period of frame FM3. Therefore, during the period corresponding to frame FM3, dimming region R(2,2) to dimming region R(2,5) and dimming region R(3,2) to dimming region (3,5) are effectively in the ON state (transmitting state).

[0090] Furthermore, pattern voltage Vb is applied to dimming region R(2,1) and dimming region R(3,1) from the corresponding row electrodes, and pattern voltage Vb is applied to dimming region R(2,1) and dimming region R(3,1) from the corresponding column electrodes. Therefore, dimming region R(2,1) and dimming region R(3,1) are effectively in the off state (light-blocking state) for the entire frame period of frame FM3.

[0091] Then, when the processing of the above-described consecutive frames FM0 to FM3 is completed, if the periods during which the dimming regions R(1,1) to R(1,5), R(2,5), and R(3,5) were in the on state (light-transmitting state), i.e., the relative on periods of dimming regions R(1,1) to R(1,5), R(2,5), and R(3,5), are set to "1" and the relative on periods are calculated for each dimming region, the relative on periods of dimming regions R(2,1) and R(3.1) will be "0." In other words, dimming regions R(2,1) and R(3.1) become regions with a gradation level of 0.

[0092] Similarly, the relative on-period of the dimming region R(2,2) and the dimming region R(3.2) is 0.1. In other words, the dimming region R(2,2) and the dimming region R(3.2) are regions with a gradation level of 1 / 4. The relative ON period of the dimming region R(2,3) and the dimming region R(3.3) is 0.2. That is, the dimming region R(2,3) and the dimming region R(3.3) are regions with a gradation level of 2 / 4.

[0093] The relative ON period of the dimming region R(2,4) and the dimming region R(3.4) is 0.4. That is, the dimming region R(2,4) and the dimming region R(3.4) are regions with a gradation level of 3 / 4. As described above, according to this embodiment, intermediate gradation display can be achieved by controlling the length of the relative ON period in the repetitive period.

[0094] FIG. 9 is a timing chart (part 2) corresponding to the operation example of the first embodiment. In FIG. 9, a polarity inversion signal POL whose signal level inverts every frame as shown in graph (a) is input from the arithmetic circuit 24 to the row electrode drive circuit 22 and the column electrode drive circuit 23. The polarity inversion signal POL is a signal for inverting the polarity of the pattern voltages Va, Vb, and Vc. When a DC component is applied to the dimming device, the contrast between the on state (transmitting state) and the off state (blocking state) in each dimming region may decrease. By inverting the polarity of the pattern voltages Va, Vb, and Vc, the DC component can be canceled.

[0095] In FIG. 9, graphs (b) to (d) represent the pattern voltages Va, Vb, and Vc shown in FIG. First, the operation of the light control device 20 in the frame period corresponding to the frame FM0 will be described. As shown at time t1, at the timing when the polarity inversion signal POL becomes "H" level, the frame period corresponding to the frame FM0 starts, and the pattern voltages Va, Vb, and Vc are in a non-inverted state. In the frame period (=period from time t1 to time t4) corresponding to frame FM0, the pattern voltage Vc is selected as the pattern voltage for the first row to be applied to the row electrode EX1, as shown in graph (e) of FIG. Similarly, in the frame period corresponding to frame FM0 (=the period from time t1 to time t4), the pattern voltage applied to the column electrode EY1 corresponding to the first column is selected to be the pattern voltage Vb, as shown in graph (f) of FIG. Furthermore, in the frame period corresponding to frame FM0, the pattern voltage Vb is selected as the pattern voltage applied to the column electrode EY2 corresponding to the second column, as shown in graph (g) of FIG. Furthermore, in the frame period corresponding to frame FM0, the pattern voltage Vb is selected as the pattern voltage to be applied to the column electrode EY3 corresponding to the third column, as shown in graph (h) of FIG. Furthermore, in the frame period corresponding to frame FM0, the pattern voltage Vb is selected as the pattern voltage to be applied to the column electrode EY4 corresponding to the fourth column, as shown in graph (i) of FIG. In contrast to these, in the frame period corresponding to frame FM0, the pattern voltage for the fifth column applied to the column electrode EY5 corresponding to the fifth column is selected to be the pattern voltage Va, as shown in graph (j) of FIG.

[0096] In the following description, in the non-inverted state, the pattern voltages Va, Vb, and Vc have a high potential side voltage of VX (volts: for example, +3 volts) and a low potential side voltage of 0 (volts). Also, in the inverted state, the pattern voltages Va, Vb, and Vc have a high potential side voltage of 0 (volts) and a low potential side voltage of -VX (volts: for example, -3 volts).

[0097] By applying the pattern voltages, a voltage equivalent to the potential difference between pattern voltages Vc and Vb is applied via row electrode EX1 and column electrode EY1 to dimming region R(1,1) corresponding to row 1, column 1, as shown in graph (k) of Fig. 9. That is, a voltage of -VX (volts) is applied during the period from time t1 to time t2, a voltage of 0 (volts) is applied during the period from time t2 to time t3, and a voltage of +VX (volts) is applied during the period from time t3 to time t4.

[0098] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Vb is applied to dimming region R(1,2) corresponding to row 1, column 2 via row electrode EX1 and column electrode EY2. That is, a voltage of -VX (volts) is applied during the period from time t1 to time t2, a voltage of 0 (volts) is applied during the period from time t2 to time t3, and a voltage of +VX (volts) is applied during the period from time t3 to time t4.

[0099] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Vb is applied to dimming region R(1,3) corresponding to row 1, column 3 via row electrode EX1 and column electrode EY3. That is, a voltage of -VX (volts) is applied during the period from time t1 to time t2, a voltage of 0 (volts) is applied during the period from time t2 to time t3, and a voltage of +VX (volts) is applied during the period from time t3 to time t4.

[0100] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Vb is applied to dimming region R(1,4) corresponding to the first row and fourth column via row electrode EX1 and column electrode EY4. That is, a voltage of -VX (volts) is applied during the period from time t1 to time t2, a voltage of 0 (volts) is applied during the period from time t2 to time t3, and a voltage of +VX (volts) is applied during the period from time t3 to time t4.

[0101] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Va is applied to dimming region R(1,5) corresponding to the first row, fifth column via row electrode EX1 and column electrode EY5. That is, a voltage of 0 (volts) is applied during the period from time t1 to time t2, a voltage of +VX (volts) is applied during the period from time t2 to time t3, and a voltage of +VX (volts) is applied during the period from time t3 to time t4.

[0102] Next, the operation during the frame period corresponding to frame FM1 will be described. At time t4, the polarity inversion signal POL is inverted and goes to the "L" level, at which point the frame period corresponding to the frame FM1 begins, and the pattern voltages Va, Vb, and Vc are inverted.

[0103] In the frame period (=the period from time t4 to time t7) corresponding to frame FM1, the pattern voltage Vc (inverted pattern voltage Vc) is selected as the pattern voltage of the first row to be applied to the row electrode EX1, as shown in graph (e) of FIG. 9.

[0104] Similarly, in the frame period corresponding to frame FM1, the pattern voltage Vb (inverted pattern voltage Vb) is selected as the pattern voltage applied to the column electrode EY1 corresponding to the first column, as shown in graph (f) of FIG.

[0105] In addition, in the frame period corresponding to frame FM1, the pattern voltage Vb (inverted pattern voltage Vb) is selected as the pattern voltage applied to the column electrode EY2 corresponding to the second column, as shown in graph (g) of FIG.

[0106] Furthermore, in the frame period corresponding to frame FM1, the pattern voltage Vb (inverted pattern voltage Vb) is selected as the pattern voltage applied to the column electrode EY3 corresponding to the third column, as shown in graph (h) of FIG. In addition, in the frame period corresponding to frame FM1, the pattern voltage Va (inverted pattern voltage Va) is selected as the pattern voltage applied to the column electrode EY4 corresponding to the fourth column, as shown in graph (i) of FIG. In addition, in the frame period corresponding to frame FM1, the pattern voltage for the fifth column that is applied to the column electrode EY5 corresponding to the fifth column is selected to be the pattern voltage Va, as shown in graph (j) of FIG.

[0107] By applying the pattern voltages, a voltage equivalent to the potential difference between pattern voltages Vc and Vb is applied via row electrode EX1 and column electrode EY1 to dimming region R(1,1) corresponding to row 1, column 1, as shown in graph (k) of Fig. 9. That is, a voltage of +VX (volts) is applied during the period from time t4 to time t5, a voltage of 0 (volts) is applied during the period from time t5 to time t6, and a voltage of -VX (volts) is applied during the period from time t6 to time t7.

[0108] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Vb is applied to dimming region R(1,2) corresponding to row 1, column 2 via row electrode EX1 and column electrode EY2. That is, a voltage of -VX (volts) is applied during the period from time t4 to time t5, a voltage of 0 (volts) is applied during the period from time t5 to time t6, and a voltage of +VX (volts) is applied during the period from time t6 to time t7.

[0109] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Vb is applied to dimming region R(1,3) corresponding to row 1, column 3 via row electrode EX1 and column electrode EY3. That is, a voltage of -VX (volts) is applied during the period from time t4 to time t5, a voltage of 0 (volts) is applied during the period from time t5 to time t6, and a voltage of +VX (volts) is applied during the period from time t6 to time t7.

[0110] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Va is applied to dimming region R(1,4) corresponding to the first row, fourth column via row electrode EX1 and column electrode EY4. That is, a voltage of 0 (volts) is applied during the period from time t4 to time t5, a voltage of −VX (volts) is applied during the period from time t5 to time t6, and a voltage of −VX (volts) is applied during the period from time t6 to time t7.

[0111] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Va is applied to dimming region R(1,5) corresponding to the first row, fifth column via row electrode EX1 and column electrode EY5. That is, a voltage of 0 (volts) is applied during the period from time t4 to time t5, a voltage of −VX (volts) is applied during the period from time t5 to time t6, and a voltage of −VX (volts) is applied during the period from time t6 to time t7.

[0112] Next, the operation during the frame period corresponding to frame FM2 will be described. At time t7, the polarity inversion signal POL is inverted and goes to the "H" level, at which point the frame period corresponding to frame FM2 begins, and the pattern voltages Va, Vb, and Vc again go to the non-inverted state.

[0113] In the frame period corresponding to frame FM2 (=the period from time t7 to time t10), the pattern voltage Vc (inverted pattern voltage Vc) is selected as the pattern voltage of the first row to be applied to the row electrode EX1, as shown in graph (e) of FIG. 9.

[0114] Similarly, in the frame period corresponding to frame FM2, the pattern voltage Vb is selected as the pattern voltage applied to the column electrode EY1 corresponding to the first column, as shown in graph (f) of FIG.

[0115] Furthermore, in the frame period corresponding to frame FM2, the pattern voltage Vb is selected as the pattern voltage applied to the column electrode EY2 corresponding to the second column, as shown in graph (g) of FIG.

[0116] Furthermore, in the frame period corresponding to frame FM2, the pattern voltage Va is selected as the pattern voltage to be applied to the column electrode EY3 corresponding to the third column, as shown in graph (h) of FIG. In addition, in the frame period corresponding to frame FM2, the pattern voltage Va is selected as the pattern voltage to be applied to the column electrode EY4 corresponding to the fourth column, as shown in graph (i) of FIG. In addition, in the frame period corresponding to frame FM2, the pattern voltage for the fifth column that is applied to the column electrode EY5 corresponding to the fifth column is selected to be the pattern voltage Va, as shown in graph (j) of FIG.

[0117] By applying the pattern voltages, a voltage equivalent to the potential difference between pattern voltages Vc and Vb is applied via row electrode EX1 and column electrode EY1 to dimming region R(1,1) corresponding to row 1, column 1, as shown in graph (k) of Fig. 9. That is, a voltage of -VX (volts) is applied during the period from time t7 to time t8, a voltage of 0 (volts) is applied during the period from time t8 to time t9, and a voltage of +VX (volts) is applied during the period from time t9 to time t10.

[0118] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Vb is applied to dimming region R(1,2) corresponding to row 1, column 2 via row electrode EX1 and column electrode EY2. That is, a voltage of -VX (volts) is applied during the period from time t7 to time t8, a voltage of 0 (volts) is applied during the period from time t8 to time t9, and a voltage of +VX (volts) is applied during the period from time t9 to time t10.

[0119] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Va is applied via row electrode EX1 and column electrode EY3 to dimming region R(1,3) corresponding to row 1, column 3. That is, a voltage of 0 (volts) is applied during the period from time t7 to time t8, and a voltage of +VX (volts) is applied during the period from time t8 to time t10.

[0120] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Va is applied to dimming region R(1,4) corresponding to the first row and fourth column via row electrode EX1 and column electrode EY4. That is, a voltage of 0 (volts) is applied during the period from time t7 to time t8, and a voltage of +VX (volts) is applied during the period from time t8 to time t10.

[0121] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Va is applied to dimming region R(1,5) corresponding to the first row and fifth column via row electrode EX1 and column electrode EY5. That is, a voltage of 0 (volts) is applied during the period from time t7 to time t8, and a voltage of +VX (volts) is applied during the period from time t8 to time t10.

[0122] Next, the operation during the frame period corresponding to frame FM3 will be described. At time t10, the polarity inversion signal POL is inverted and goes to the "L" level, at which point the frame period corresponding to frame FM3 begins, and the pattern voltages Va, Vb, and Vc are again inverted.

[0123] In the frame period (=the period from time t10 to time t13) corresponding to frame FM3, the pattern voltage Vc (inverted pattern voltage Vc) is selected as the pattern voltage of the first row to be applied to the row electrode EX1, as shown in graph (e) of FIG.

[0124] Similarly, in the frame period corresponding to frame FM3, the pattern voltage Vb is selected as the pattern voltage applied to the column electrode EY1 corresponding to the first column, as shown in graph (f) of FIG.

[0125] In addition, in the frame period corresponding to frame FM3, the pattern voltage Va is selected as the pattern voltage applied to the column electrode EY2 corresponding to the second column, as shown in graph (g) of FIG.

[0126] Furthermore, in the frame period corresponding to frame FM3, the pattern voltage Va is selected as the pattern voltage to be applied to the column electrode EY3 corresponding to the third column, as shown in graph (h) of FIG.

[0127] In addition, in the frame period corresponding to frame FM3, the pattern voltage Va is selected as the pattern voltage to be applied to the column electrode EY4 corresponding to the fourth column, as shown in graph (i) of FIG.

[0128] In addition, in the frame period corresponding to frame FM3, the pattern voltage for the fifth column that is applied to the column electrode EY5 corresponding to the fifth column is selected to be the pattern voltage Va, as shown in graph (j) of FIG.

[0129] By applying the pattern voltages, a voltage equivalent to the potential difference between pattern voltages Vc and Vb is applied via row electrode EX1 and column electrode EY1 to dimming region R(1,1) corresponding to row 1, column 1, as shown in graph (k) of Fig. 9. That is, a voltage of +VX (volts) is applied during the period from time t10 to time t11, a voltage of 0 (volts) is applied during the period from time t11 to time t12, and a voltage of -VX (volts) is applied during the period from time t12 to time t13.

[0130] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Vb is applied to dimming region R(1,2) corresponding to row 1, column 2 via row electrode EX1 and column electrode EY2. That is, a voltage of 0 (volts) is applied during the period from time t10 to time t11, and a voltage of −VX (volts) is applied during the period from time t11 to time t13.

[0131] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Va is applied via row electrode EX1 and column electrode EY3 to dimming region R(1,3) corresponding to row 1, column 3. That is, a voltage of 0 (volts) is applied during the period from time t10 to time t11, and a voltage of −VX (volts) is applied during the period from time t11 to time t13. 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Va is applied via row electrode EX1 and column electrode EY4 to dimming region R(1,4) corresponding to the first row and fourth column. That is, a voltage of 0 (volts) is applied during the period from time t10 to time t11, and a voltage of −VX (volts) is applied during the period from time t11 to time t13.

[0132] 9, a voltage equivalent to the potential difference between pattern voltage Vc and pattern voltage Va is applied to dimming region R(1,5) corresponding to the first row, fifth column via row electrode EX1 and column electrode EY5. That is, a voltage of 0 (volts) is applied during the period from time t10 to time t11, and a voltage of −VX (volts) is applied during the period from time t11 to time t13. As a result of the above operation, the gradation level is all set to 1 in the dimming regions R(1,1) to R(1,5).

[0133] Next, the operations of the second and third lines of the first embodiment will be described. In this case, FIG. 10 is a timing chart corresponding to an example of operation of the second row, second column to fourth column of the first embodiment. Here, since the operations in the second and third lines are the same as those in the first embodiment, only the operation in the second line will be explained.

[0134] (Period corresponding to frame FM0) First, in the period corresponding to frame FM0 (time t1 to time t4), the arithmetic circuit 24 applies the pattern voltage Vb to the row electrode EX2. Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrodes EY1 to EY4. As a result, pattern voltage Vb is applied to dimming regions R(2,1) to R(2,4) from the corresponding row electrode EX2, and pattern voltage Vb is applied from the corresponding column electrodes EY1 to EY4. Therefore, the potential difference between dimming regions R(2,1) to R(2,4) is 0 volts throughout the entire frame period of frame FM0 (time t1 to time t4). Therefore, dimming regions R(2,1) to R(2,4) are effectively in the off state (light-blocking state) during the period corresponding to frame FM0.

[0135] On the other hand, although not shown, the pattern voltage Vb is applied to the dimming region R(2,5) from the corresponding row electrode EX2, and the pattern voltage Va is applied to the corresponding column electrode EY5. Therefore, the dimming region R(2,5) is in the ON state for ⅔ of the frame period of frame FM0, and in the OFF state for ⅓ of the frame period of frame FM0. Therefore, the dimming region R(2,5) is effectively in the ON state (transmitting state) during the period corresponding to frame FM0.

[0136] (Period corresponding to frame FM1) Next, in the period corresponding to frame FM1 (time t4 to time t7), the arithmetic circuit 24 applies the pattern voltage Vb to the row electrode EX2. Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrodes EY1 to EY3, and applies a pattern voltage Va to the column electrodes EY4 and EY5.

[0137] As a result, to dimming region R(2,1) to dimming region R(2,3), pattern voltage Vb is applied from the corresponding row electrode EX2, and pattern voltage Vb is applied from the corresponding column electrodes EY1 to EY3. Therefore, the potential difference is 0 volts throughout the entire period corresponding to frame FM1 (time t1 to time t4). Therefore, dimming region R(2,1) to dimming region R(2,3) are effectively in the off state (light-blocking state) during the period corresponding to frame FM1.

[0138] On the other hand, although not shown, for dimming region R(2,4) and dimming region R(2,5), a pattern voltage Vb is applied from the corresponding row electrode EX2, and a pattern voltage Va is applied from the corresponding column electrode EY4 and column electrode EY5. Therefore, dimming region R(2,4) and dimming region R(2,5) are in the ON state for ⅔ of the frame period of frame FM0, and are in the OFF state for ⅓ of the frame period of frame FM0. Therefore, during the period corresponding to frame FM1, dimming region R(2,4) and dimming region R(2,5) are effectively in the ON state (transmitting state).

[0139] (Period corresponding to frame FM2) Next, in the period corresponding to frame FM2 (time t7 to time t10), the arithmetic circuit 24 applies the pattern voltage Vb to the row electrode EX2. Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrodes EY1 to EY2, and a pattern voltage Va to the column electrodes EY3 to EY5.

[0140] As a result, pattern voltage Vb is applied to dimming region R(2,1) through dimming region R(2,2) from the corresponding row electrode EX2, and pattern voltage Vb is applied to the corresponding column electrodes EY1 through EY2. Therefore, dimming region R(2,1) through dimming region R(2,2) have a potential difference of 0 volts throughout the entire frame period of frame FM2 (time t7 through time t10). Therefore, dimming region R(1,1) through dimming region R(1,2) are effectively in the off state (light-blocking state) during the period corresponding to frame FM2.

[0141] On the other hand, for dimming region R(2,3) to dimming region R(2,5), although not shown, a pattern voltage Vb is applied from the corresponding row electrode EX2 and a pattern voltage Va is applied from the corresponding column electrodes EY3 to EY5 during the period corresponding to frame FM2. Therefore, dimming region R(2,3) to dimming region R(2,5) are in the ON state for ⅔ of the frame period of frame FM2 and in the OFF state for ⅓ of the frame period of frame FM2. Therefore, dimming region R(2,3) to dimming region R(2,5) are effectively in the ON state (transmitting state) during the period corresponding to frame FM2.

[0142] (Period corresponding to frame FM3) Next, in the period corresponding to frame FM3 (time t10 to time t13), the arithmetic circuit 24 applies the pattern voltage Vb to the row electrode EX2. Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY1, and applies a pattern voltage Va to the column electrodes EY2 to EY5.

[0143] As a result, the pattern voltage Vb is applied to the dimming region R(2,1) from the corresponding row electrode EX2, and the pattern voltage Vb is applied from the corresponding column electrodes EY1-EY2. Therefore, the potential difference is 0 volts throughout the entire frame period of frame FM3, and the dimming region R(2,1) is effectively in the OFF state (light-blocking state).

[0144] On the other hand, for the dimming regions R(2,2) to R(2,5), the pattern voltage Vb is applied from the corresponding row electrode EX2, and the pattern voltage Va is applied from the corresponding column electrodes EY2 to EY5.

[0145] Therefore, dimming regions R(2,2) to R(2,5) are in the ON state for ⅔ of the frame period of frame FM3, and are in the OFF state for ⅓ of the frame period of frame FM3. Therefore, dimming regions R(2,3) to R(2,5) are effectively in the ON state (transmitting state) during the period corresponding to frame FM3.

[0146] As a result of the above operation, the relative ON period of the dimming region R(2,1) and the dimming region R(3,1) becomes 0, and the gradation level=0. Furthermore, in the dimming region R(2,2) and the dimming region R(3,2), the relative ON period is 0.1, and the gradation level is 1 / 4.

[0147] Furthermore, in the dimming region R(2,3) and the dimming region R(3,3), the relative on-period is 0.2, and the gradation level is 2 / 4. Furthermore, in the dimming region R(2,4) and the dimming region R(3,4), the relative on period is 0.4, and the gradation level is 3 / 4.

[0148] Furthermore, the dimming region R(2,5) and the dimming region R(3,5) have a relative ON period of 1 and a gradation level=1. As described above, according to the first embodiment, halftones can be displayed without complicating the control, and power consumption can be reduced and dimming performance can be improved despite the use of active matrix control.

[0149] (2) Second embodiment In the first embodiment described above, the dimming device performed dimming processing on a frame-by-frame basis for frames FM0 to FM3, but in the second embodiment, dimming processing is performed for each of multiple (in this second embodiment, three) sub-frames SF0 to SF2 that make up each of frames FM0 to FM3.

[0150] That is, in the second embodiment, the light control device performs light control processing on four sub-frames SF0 included in frames FM0 to FM3, and then performs light control processing on four sub-frames SF1 included in frames FM0 to FM3.

[0151] Furthermore, the light control device then performs light control processing on the four sub-frames SF2 included in frames FM0 to FM3, and then performs light control processing on the four sub-frames SF3 included in frames FM0 to FM3.

[0152] After the dimming process for the subframe SF3 is completed, the dimming device repeats the dimming process again from the subframe SF0.

[0153] FIG. 11 is an operation timing chart (part 1) of the second embodiment. First, regarding the operation of the second embodiment, the operation of the first column corresponding to the column electrode EX1 will be described.

[0154] (Period corresponding to subframe SF0) In the period corresponding to the subframe SF0 (time t1 to time t5), the arithmetic circuit 24 applies the pattern voltage Vc to the row electrode EX1. Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY1 during a period corresponding to the subframe SF0.

[0155] As a result, the pattern voltage Vc is applied to the dimming region R(1,1) from the corresponding row electrode EX1, and the pattern voltage Vb is applied to the corresponding column electrode EY1. Therefore, the potential difference is -VX volts throughout the entire period of subframe SF0. ​​Therefore, during the period corresponding to subframe SF0, the dimming region R(1,1) is effectively in the ON state (transmitting state).

[0156] Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY2 during the period from time t1 to time t4, and applies a pattern voltage Va during the period from time t4 to time t5, within the period corresponding to the subframe SF0.

[0157] As a result, to the dimming region R(1,2), a pattern voltage Vc is applied from the corresponding row electrode EX1 during the period corresponding to subframe SF0, a pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t1 to time t4, and a pattern voltage Va is applied during the period from time t4 to time t5. Therefore, within the period of subframe SF0, the potential difference during the period from time t1 to time t4 is -VX volts, and the potential difference during the period from time t4 to time t5 is 0 volts. Therefore, during the period corresponding to subframe SF0, the dimming region R(1,2) effectively has a relative on-period of 0.9.

[0158] Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY3 during the period from time t1 to time t3, and applies a pattern voltage Va to the column electrode EY3 during the period from time t3 to time t5, within the period corresponding to the subframe SF0.

[0159] As a result, to the dimming region R(1,3), a pattern voltage Vc is applied from the corresponding row electrode EX1 during the period corresponding to subframe SF0, a pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t1 to time t3, and a pattern voltage Va is applied during the period from time t3 to time t5. Therefore, within the period of subframe SF0, the potential difference during the period from time t1 to time t3 is -VX volts, and the potential difference during the period from time t3 to time t5 is 0 volts. Therefore, during the period corresponding to subframe SF0, the dimming region R(1,3) effectively has a relative on-period of 0.8.

[0160] Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY4 during the period from time t1 to time t2, and applies a pattern voltage Va to the column electrode EY4 during the period from time t2 to time t5, within the period corresponding to the subframe SF0.

[0161] As a result, in the dimming region R(1,4), a pattern voltage Vc is applied from the corresponding row electrode EX1 during the period corresponding to subframe SF0 (time t1 to time t5), a pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t1 to time t2, and a pattern voltage Va is applied during the period from time t2 to time t5. Therefore, during the period corresponding to subframe SF0 (time t1 to time t5), the potential difference during the period from time t1 to time t2 is -VX volts, and the potential difference during the period from time t23 to time t5 is 0 volts. Therefore, during the period corresponding to subframe SF0, the dimming region R(1,4) effectively has a relative on-period of 0.6.

[0162] Furthermore, the arithmetic circuit 24 applies a pattern voltage Va to the column electrode EY5 during a period corresponding to the subframe SF0.

[0163] As a result, the pattern voltage Vc is applied to the dimming region R(1,5) from the corresponding row electrode EX1, and the pattern voltage Va is applied to the corresponding column electrode EY5. Therefore, the potential difference is 0 volts throughout the entire period of subframe SF0. ​​Therefore, the dimming region R(1,5) is effectively in the OFF state (light-blocking state) during the period corresponding to subframe SF0.

[0164] (Period corresponding to subframe SF1) During the period corresponding to the subframe SF1 (time t5 to time t9), the arithmetic circuit 24 also applies the pattern voltage Vc to the row electrode EX1. Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY1 during a period corresponding to the subframe SF1.

[0165] As a result, the pattern voltage Vc is applied to the dimming region R(1,1) from the corresponding row electrode EX1, and the pattern voltage Vb is applied to the corresponding column electrode EY1. Therefore, the potential difference is 0 volts throughout the entire period of subframe SF1. Therefore, the dimming region R(1,1) is effectively in the OFF state (light-blocking state) during the period corresponding to subframe SF1.

[0166] Furthermore, the arithmetic circuit 24 applies the pattern voltage Vb to the column electrode EY2 during the period from time t5 to time t8, and applies the pattern voltage Va during the period from time t8 to time t9, within the period corresponding to the subframe SF1.

[0167] As a result, to dimming region R(1,2), pattern voltage Vc is applied from the corresponding row electrode EX1 during the period corresponding to subframe SF1, pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t5 to time t8, and pattern voltage Va is applied during the period from time t8 to time t9. Therefore, within the period of subframe SF1, the potential difference during the period from time t5 to time t8 is 0 volts, and the potential difference during the period from time t8 to time t9 is +VX volts. Therefore, during the period corresponding to subframe SF1, dimming region R(1,2) effectively has a relative on-period of 0.1.

[0168] Furthermore, the arithmetic circuit 24 applies the pattern voltage Vb to the column electrode EY3 during the period from time t5 to time t7, and applies the pattern voltage Va during the period from time t7 to time t9, within the period corresponding to the subframe SF1.

[0169] As a result, to dimming region R(1,3), pattern voltage Vc is applied from the corresponding row electrode EX1 during the period corresponding to subframe SF1, pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t5 to time t7, and pattern voltage Va is applied during the period from time t7 to time t9. Therefore, within the period of subframe SF1, the potential difference during the period from time t5 to time t7 is 0 volts, and the potential difference during the period from time t3 to time t5 is +VX volts. Therefore, during the period corresponding to subframe SF1, dimming region R(1,3) effectively has a relative on-period of 0.2.

[0170] Furthermore, the arithmetic circuit 24 applies the pattern voltage Vb to the column electrode EY4 during the period from time t5 to time t6, and applies the pattern voltage Va to the column electrode EY4 during the period from time t6 to time t9, within the period corresponding to the subframe SF1.

[0171] As a result, to dimming region R(1,4), pattern voltage Vc is applied from the corresponding row electrode EX1 during the period corresponding to subframe SF1, pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t5 to time t6, and pattern voltage Va is applied during the period from time t6 to time t9. Therefore, within the period of subframe SF1, the potential difference during the period from time t5 to time t6 is 0 volts, and the potential difference during the period from time t23 to time t5 is +VX volts. Therefore, during the period corresponding to subframe SF1, dimming region R(1,4) effectively has a relative on-period of 0.4.

[0172] Furthermore, the arithmetic circuit 24 applies a pattern voltage Va to the column electrode EY5 during a period corresponding to the subframe SF1. As a result, the pattern voltage Vc is applied to the dimming region R(1,5) from the corresponding row electrode EX1, and the pattern voltage Va is applied to the corresponding column electrode EY5. Therefore, the potential difference is +VX volts throughout the entire period of subframe SF1. Therefore, the dimming region R(1,5) is effectively in the ON state (transmitting state) during the period corresponding to subframe SF1.

[0173] (Period corresponding to subframe SF2) During the period corresponding to the subframe SF2 (time t9 to time t13), the arithmetic circuit 24 also applies the pattern voltage Vc to the row electrode EX1.

[0174] Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY1 during a period corresponding to the subframe SF2. As a result, a pattern voltage Vc is applied to the dimming region R(1,1) from the corresponding row electrode EX1, and a pattern voltage Vb is applied to the corresponding column electrode EY1. Therefore, the potential difference is +VX volts throughout the entire period of subframe SF2. Therefore, during the period corresponding to subframe SF2, dimming region R(1,1) is effectively in the ON state (transmitting state).

[0175] Furthermore, the arithmetic circuit 24 applies the pattern voltage Vb to the column electrode EY2 during the period from time t9 to time t12, and applies the pattern voltage Va during the period from time t12 to time t13, within the period corresponding to the subframe SF2.

[0176] As a result, to dimming region R(1,2), pattern voltage Vc is applied from the corresponding row electrode EX1 during the period corresponding to sub-frame SF2, pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t9 to time t12, and pattern voltage Va is applied during the period from time t2 to time t13. Therefore, during the period of sub-frame SF2, the potential difference during the period from time t9 to time t12 is +VX volts, and the potential difference during the period from time t8 to time t9 is +VX volts. Therefore, during the period corresponding to sub-frame SF2, dimming region R(1,2) is effectively in the on state (transmitting state).

[0177] Furthermore, the arithmetic circuit 24 applies the pattern voltage Vb to the column electrode EY3 during the period from time t9 to time t11, and applies the pattern voltage Va to the column electrode EY3 during the period from time t11 to time t13, during the period corresponding to the subframe SF2.

[0178] As a result, to the dimming region R(1,3), a pattern voltage Vc is applied from the corresponding row electrode EX1 during the period corresponding to sub-frame SF2, a pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t9 to time t11, and a pattern voltage Va is applied during the period from time t11 to time t13. Therefore, during the period of sub-frame SF2, the potential difference during the period from time t9 to time t11 is +VX volts, and the potential difference during the period from time t11 to time t13 is +VX volts. Therefore, during the period corresponding to sub-frame SF2, the dimming region R(1,3) is effectively in the on state (transmitting state).

[0179] Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY4 during the period from time t9 to time t10 within the period corresponding to the subframe SF2 (time t9 to time t13), and applies a pattern voltage Va to the column electrode EY4 during the period from time t10 to time t13.

[0180] As a result, to the dimming region R(1,4), a pattern voltage Vc is applied from the corresponding row electrode EX1 during the period corresponding to sub-frame SF2, a pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t9 to time t10, and a pattern voltage Va is applied during the period from time t10 to time t13. Therefore, during the period of sub-frame SF2, the potential difference during the period from time t9 to time t10 is +VX volts, and the potential difference during the period from time t10 to time t13 is +VX volts. Therefore, during the period corresponding to sub-frame SF2, the dimming region R(1,4) is effectively in the on state (transmitting state).

[0181] Furthermore, the arithmetic circuit 24 applies a pattern voltage Va to the column electrode EY5 during a period corresponding to the subframe SF2. As a result, the pattern voltage Vc is applied to the dimming region R(1,5) from the corresponding row electrode EX1, and the pattern voltage Va is applied to the corresponding column electrode EY5. Therefore, the potential difference is +VX volts throughout the entire period of subframe SF2. Therefore, during the period corresponding to subframe SF2, the dimming region R(1,5) is effectively in the ON state (transmitting state).

[0182] (Period corresponding to subframe SF3) Furthermore, the periods corresponding to subframe SF3 (time t13 to time t17), subframe SF4 (time t17 to time t21), and subframe SF5 (time t21 to t25) simply have waveforms in which the signs of the pattern voltages Va, Vb, and Vc and the signs of the potential differences are inverted from those of the periods corresponding to subframes SF0, SF1, and SF2, respectively, and therefore detailed explanations thereof will be omitted.

[0183] FIG. 12 is a second operation timing chart of the second embodiment. Next, the operation of the second column corresponding to the column electrode EX2 in the second embodiment will be described.

[0184] (Period corresponding to subframe SF0) In the period corresponding to the subframe SF0 (time t1 to time t5), the arithmetic circuit 24 applies the pattern voltage Vb to the row electrode EX2, as shown in graph (e) of FIG.

[0185] Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY2 from time t1 to time t4 during the period corresponding to the subframe SF0, and applies a pattern voltage Va to the column electrode EY2 from time t4 to time t5, as shown in graph (f) of FIG.

[0186] As a result, pattern voltage Vb is applied to dimming region R(2,2) from the corresponding row electrode EX1, and pattern voltage Vb is applied from the corresponding column electrode EY2 from time t1 to time t4. Therefore, as shown in graph (g) of FIG. 12, the potential difference is 0 volts from time t1 to time t4.

[0187] Furthermore, from time t4 to time t5, the pattern voltage Va is applied from the corresponding column electrode EY2. Therefore, as shown in graph (g) of Figure 12, the potential difference is +VX volts from time t4 to time t5. Therefore, in the period corresponding to subframe SF0, the dimming region R(2,2) effectively has a relative on-period of 0.9.

[0188] In addition, the calculation circuit 24 applies a pattern voltage Vb to the column electrode EY3 during the period from time t1 to time t3, and applies a pattern voltage Va to the column electrode EY3 during the period from time t3 to time t5, as shown in graph (h) of Figure 12, during the period corresponding to the subframe SF0.

[0189] As a result, to dimming region R(2,3), pattern voltage Vb is applied from corresponding row electrode EX3 during the period corresponding to subframe SF0, pattern voltage Vb is applied from corresponding column electrode EY3 during the period from time t1 to time t3, and pattern voltage Va is applied during the period from time t3 to time t5. Therefore, within the period of subframe SF0, the potential difference during the period from time t1 to time t3 is 0 volts, and the potential difference during the period from time t3 to time t5 is +VX volts. Therefore, during the period corresponding to subframe SF0, dimming region R(2,3) effectively has a relative on-period of 0.8.

[0190] In addition, the calculation circuit 24 applies a pattern voltage Vb to the column electrode EY4 during the period from time t1 to time t2, and applies a pattern voltage Va to the column electrode EY4 during the period from time t2 to time t5, as shown in graph (j) of Figure 12, during the period corresponding to the subframe SF0.

[0191] As a result, in dimming region R(2,4), pattern voltage Vb is applied from corresponding row electrode EX2 during the period corresponding to subframe SF0, pattern voltage Vb is applied from corresponding column electrode EY1 during the period from time t1 to time t2, and pattern voltage Va is applied during the period from time t2 to time t5. Therefore, as shown in graph (k) of FIG. 12, during the period corresponding to subframe SF0, the potential difference during the period from time t1 to time t2 is 0 volts, and the potential difference during the period from time t2 to time t5 is +VX volts. Therefore, during the period corresponding to subframe SF0, dimming region R(2,4) effectively has a relative on-period of 0.6.

[0192] Although not shown, the arithmetic circuit 24 also applies a pattern voltage Va to the column electrode EY5 during a period corresponding to the subframe SF0. As a result, the pattern voltage Vb is applied to the dimming region R(2,5) from the corresponding row electrode EX21, and the pattern voltage Va is applied to the corresponding column electrode EY5. Therefore, the potential difference is +VX volts throughout the entire period of subframe SF0. ​​Therefore, during the period corresponding to subframe SF0, the dimming region R(2,5) is effectively in the ON state (transmitting state).

[0193] (Period corresponding to subframe SF1) In the second embodiment, the same operation as in subframe SF0 is performed in the period corresponding to subframe SF1 (time t5 to time t9), and therefore a detailed description thereof will be omitted.

[0194] (Period corresponding to subframe SF2) Next, the operation in subframe SF2 will be described. In the period corresponding to the subframe SF2 (time t9 to time t13), the arithmetic circuit 24 applies the pattern voltage Vb to the row electrode EX2, as shown in graph (e) of FIG.

[0195] Furthermore, the arithmetic circuit 24 applies a pattern voltage Vb to the column electrode EY2 from time t9 to time t12, and a pattern voltage Va to the column electrode EY2 from time t12 to time t13, during the period corresponding to the subframe SF2, as shown in graph (f) of FIG. 12.

[0196] As a result, pattern voltage Vb is applied to dimming region R(2,2) from the corresponding row electrode EX2, and from time t9 to time t12, pattern voltage Vb is applied from the corresponding column electrode EY2. Therefore, as shown in graph (g) of FIG. 12, the potential difference is 0 volts during the period from time t9 to time t12.

[0197] Furthermore, from time t12 to time t13, the pattern voltage Va is applied from the corresponding column electrode EY2. Therefore, as shown in graph (g) in Figure 12, the potential difference is 0 volts from time t9 to time t12. Therefore, during the period corresponding to subframe SF2, dimming region R(2,2) is effectively in the OFF state (light-blocking state).

[0198] In addition, the calculation circuit 24 applies a pattern voltage Vb to the column electrode EY3 during the period from time t9 to time t11, and applies a pattern voltage Va to the column electrode EY3 during the period from time t11 to time t13, as shown in graph (h) of Figure 12, during the period corresponding to subframe SF2.

[0199] As a result, to the dimming region R(2,3), the pattern voltage Vb is applied from the corresponding row electrode EX3 during the period corresponding to sub-frame SF2, the pattern voltage Vb is applied from the corresponding column electrode EY3 during the period from time t9 to time t11, and the pattern voltage Va is applied during the period from time t11 to time t13. Therefore, the potential difference is 0 volts throughout the entire period of sub-frame SF2. Therefore, during the period corresponding to sub-frame SF2, the dimming region R(2,3) is effectively in the OFF state (light-blocking state).

[0200] In addition, the calculation circuit 24 applies a pattern voltage Vb to the column electrode EY4 during the period corresponding to subframe SF2 from time t9 to time t10, and applies a pattern voltage Va to the column electrode EY4 during the period from time t10 to time t13, as shown in graph (j) of Figure 12.

[0201] As a result, to the dimming region R(2,4), the pattern voltage Vb is applied from the corresponding row electrode EX2 during the period corresponding to sub-frame SF2, the pattern voltage Vb is applied from the corresponding column electrode EY1 during the period from time t9 to time t10, and the pattern voltage Va is applied during the period from time t10 to time t13. Therefore, as shown in graph (k) of FIG. 12, the potential difference is 0 volts throughout the entire period of sub-frame SF2. Therefore, during the period corresponding to sub-frame SF2, the dimming region R(2,4) is effectively in the off state (light-blocking state).

[0202] Although not shown, the arithmetic circuit 24 also applies a pattern voltage Va to the column electrode EY5 during a period corresponding to the subframe SF2. As a result, the pattern voltage Vb is applied to the dimming region R(2,5) from the corresponding row electrode EX21, and the pattern voltage Va is applied to the corresponding column electrode EY5. Therefore, the potential difference is +VX volts throughout the entire period of subframe SF2. Therefore, during the period corresponding to subframe SF2, the dimming region R(2,5) is effectively in the ON state (transmitting state).

[0203] (Period corresponding to subframe SF3) Furthermore, the periods corresponding to subframe SF3 (time t13 to time t17), subframe SF4 (time t17 to time t21), and subframe SF5 (time t21 to t25) simply have waveforms in which the signs of the pattern voltages Va, Vb, and Vc and the signs of the potential differences are inverted from those of the periods corresponding to subframes SF0, SF1, and SF2, respectively, and therefore detailed explanations thereof will be omitted.

[0204] As explained above, the control of the second embodiment also makes it possible to perform the same operation as in the first embodiment.

[0205] [3] Third embodiment In the above first and second embodiments, the frame periods of frames FM0 to FM3 in the repeating period have been described as being constant, but since the speed of the on / off operation of the dimming area of ​​the dimming panel 21 constituting the dimming device 20 changes depending on the temperature, the same gradation display cannot always be achieved when the ambient temperature changes.

[0206] Therefore, in the third embodiment, a temperature detection circuit 50 is provided to detect the ambient temperature, so that a constant gradation display can always be performed in accordance with the ambient temperature. FIG. 13 is a schematic configuration block diagram of a light control system including a light control device according to the third embodiment. In FIG. 13, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the detailed description thereof is incorporated herein. The light control system 1A of the third embodiment has a temperature detection circuit 50, and the temperature detection circuit 50 outputs to the arithmetic circuit 24 temperature data STH corresponding to the detected ambient temperature.

[0207] FIG. 14 is a diagram illustrating the operation of the third embodiment. In FIG. 14, the vertical axis represents the relative ratio of each frame period of frames FM0 to FM3 to the repetition period. In FIG. 14, the area where the relative ratio is constant, indicated by the up and down arrows, is where the ratio of the frame periods of frames FM0 to FM3 employed in the first and second embodiments is: FM0:FM1:FM2:FM3=0.6:0.2:0.1:0.1 This is the temperature range (normal temperature range) corresponding to the case of

[0208] In a temperature region where the temperature is lower than the normal temperature region (the region on the left side in Figure 14), the calculation circuit 24 controls the ratio of the frame period of frame FM0 to be lower and the ratio of the frame periods of frames FM1 to FM3 to be higher, thereby effectively achieving the same gray scale display as in the normal temperature region.

[0209] On the other hand, in a temperature region where the temperature is higher than the normal temperature region (the region on the right side in Figure 14), the calculation circuit 24 controls the ratio of the frame period of frame FM0 to the ratio of the frame periods of frames FM1 to FM3 to increase, thereby effectively achieving the same gray scale display as in the normal temperature region.

[0210] As a result, according to the third embodiment, even if the ambient temperature of the place where the light control device 20 is installed changes, it is possible to always perform a constant gray scale display.

[0211] Although it is possible to obtain the same effect by lengthening the repetition period, this increases the risk of flicker, so in the third embodiment, a method is adopted in which the repetition period remains constant while the ratio of the frame period is changed. In the above explanation, only the ratio of the frame period is changed, but it is also possible to vary the voltage applied to the dimming region so as to always display a constant gray level.

[0212] [4] Fourth embodiment The light control device 20 according to the first to third embodiments can also be applied to a display device 100 as shown in FIG. FIG. 15 is a schematic configuration block diagram of a display device to which the light control devices according to the first to third embodiments are applied.

[0213] The display device 100 includes an analysis device 10 , a transparent display 101 , and a light control device 20 . The light control device 20 is any one of the light control devices 20 according to the first to third embodiments. The analysis device 10 has the same configuration as the analysis device 10 shown in FIG. 1, but is preferably configured to perform analysis optimized for the transparent display 101.

[0214] The transparent display 101 has a two-dimensional array of unit areas each having a transparent area and a light-emitting area. Each light-emitting area has a plurality of light-emitting pixels (e.g., R pixels, G pixels, and B pixels). The R pixels, G pixels, and B pixels emit light corresponding to red (R), green (G), and blue (B), respectively. As a result, the transparent display 101 can display an image and transmit external light from behind.

[0215] The analysis device 10 receives a request command CMD regarding image display and dimming from a higher-level controller, analyzes the request corresponding to the request command CMD, generates an image signal SGR and supplies it to the transparent display 101, and generates a dimming signal SDM and supplies it to the dimming device 20.

[0216] The transparent display 101 displays a predetermined image on the display screen in response to the image signal SGR. Here, the image is not limited to a picture or a photograph, but also includes a character string and the like. The dimming device 20 individually sets each of the plurality of dimming regions R to a light-transmitting state, a light-blocking state, or a halftone state in response to the dimming signal SDM.

[0217] As a result, the image displayed on the transparent display 101, which corresponds to the area that the light control device 20 has made transparent, is displayed in its original color. Furthermore, the image displayed on the transparent display 101 corresponding to the area that is in the light-blocking state by the light control device is displayed dark and becomes almost invisible.

[0218] Furthermore, the image displayed on the transparent display 101, which corresponds to the area where the dimming device has set the halftone state, will be displayed brighter or darker than other areas depending on the halftone, making it possible to make the area where an image that you want the user to focus on is displayed stand out more than other areas or make it appear to be flashing, or conversely, make the area where an image containing information that is not necessarily required is displayed less noticeable than other areas where you want the user to pay attention.

[0219] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0220] 1. 1A dimming system 10 Analysis device 20. Dimmer 21 Dimming Panel 22 Row electrode drive circuit 23 Column electrode drive circuit 24 Arithmetic circuit 25 Reference voltage generation circuit 26 Timing generation circuit 31 Photochromic Layer 32, 33 board 50 Temperature detection circuit 100 display device EX1~EX3 row electrode EY1~EY5 row electrode Va~Vc pattern voltage

Claims

1. a light control panel including: a plurality of row electrodes extending in a first direction; a plurality of column electrodes extending in a second direction intersecting the first direction; and a light control layer having a plurality of light control regions partitioned in a matrix by the plurality of row electrodes and the plurality of column electrodes; a dimming control device that controls application of one of a plurality of pattern voltages having predetermined voltage waveforms to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the gradation of each of the plurality of dimming regions; the dimming control device selects a pattern voltage to be applied to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the gradation of each of the plurality of dimming regions in each of a plurality of frame periods, the frame periods being different from one another and constituting a repeating period that indicates a period that is a repeating unit for controlling dimming; Dimmer.

2. the dimming control device controls the polarity of a pattern voltage applied during each of the frame periods constituting the repeating period so that the polarity of the pattern voltage applied during the frame period is inverted between an even-numbered frame period and an odd-numbered frame period; The light control device according to claim 1 .

3. The pattern voltages are binary signals, and are set to have the same effective value. The light control device according to claim 1 .

4. A pattern of a difference voltage between two pattern voltages selected for one dimming region and applied in one frame period is set to transition between a voltage that puts the dimming region into a light-shielding state and a voltage that puts the dimming region into a light-transmitting state. The light control device according to claim 1 .

5. The voltage for blocking the dimming region is set to 0 volts. The light control device according to claim 4 .

6. the dimming control device receives a dimming signal that specifies the pattern voltages to be applied to the column electrodes among the plurality of pattern voltages and specifies the pattern voltages to be supplied to the row electrodes, and generates a column control signal and a row control signal in response to the dimming signal; a column electrode drive circuit that drives the plurality of column electrodes in response to the column control signal; a row electrode drive circuit that drives the plurality of row electrodes in response to the row control signal; Further equipped The light control device according to claim 1 .

7. The dimmer has two frame periods in which the polarity of a voltage waveform is inverted, the dimming control device further generates a polarity signal indicating a polarity of the frame period; the column electrode drive circuit drives the plurality of column electrodes in response to the column control signal and the polarity signal; The row electrode drive circuit drives the row electrodes in response to the row control signal and the polarity signal. The light control device according to claim 6 .

8. The pixel electrode driving circuit further includes a reference voltage generating circuit that generates a reference voltage and supplies the reference voltage to the column electrode driving circuit and the row electrode driving circuit. The light control device according to claim 6 .

9. A transparent display and a light control device disposed on the rear side of the transparent display and capable of controlling light transmittance; Equipped with The light control device includes a light control panel, The light control panel includes a plurality of row electrodes extending in a first direction; a plurality of column electrodes extending in a second direction intersecting the first direction; a light-control layer having a plurality of light-control regions partitioned in a matrix by the plurality of row electrodes and the plurality of column electrodes; a dimming control device that controls application of one of a plurality of pattern voltages having predetermined voltage waveforms to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the gradation of each of the plurality of dimming regions, the dimming control device selects a pattern voltage to be applied to each of the plurality of row electrodes and the plurality of column electrodes in accordance with the gradation of each of the plurality of dimming regions in each of a plurality of frame periods, the frame periods being different from one another and constituting a repeating period that indicates a period that is a repeating unit for controlling dimming; Display device.

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