Photoelectric conversion device, photoelectric conversion system, movable body, apparatus, and driving method

Abstract

To provide a technique that can reduce a deterioration in image quality due to variations of an output node in a floating state.SOLUTION: A photoelectric conversion device of the present invention comprises a plurality of pixels arranged over a plurality of rows and a plurality of columns, a plurality of column circuits corresponding respectively to the plurality of columns; and a control unit. The column circuit has a comparison circuit that has a first input node to which pixel signals from the plurality of pixels on a corresponding column are input and a second input node to which a reference signal is input, and a buffer circuit that has an output node outputting the reference signal to the comparison circuit on the corresponding column. The control unit can control the potentials of the output nodes in the plurality of buffer circuits to be a predetermined potential.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, a photoelectric conversion system, a moving body, a device, and a driving method. [Background technology]

[0002] Photoelectric conversion devices equipped with column-parallel AD converters, each with an analog-to-digital (AD) conversion unit for each pixel column, are known. A typical column-parallel AD converter converts a pixel signal into digital data by using a comparator circuit to compare the pixel signal with a reference signal whose level changes over time and counting the time from the start of the comparison until the output signal of the comparator circuit is inverted. Patent Document 1 describes a photoelectric conversion device configured to shorten the settling time of the reference signal by connecting a buffer circuit between the reference signal line and the comparator circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-111095 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the photoelectric conversion device described in Patent Document 1, no consideration was given to how to deal with the output node itself that becomes floating when a part of the buffer circuit between the reference signal line and the comparison circuit is powered off.

[0005] An object of the present invention is to provide a technique capable of reducing deterioration in image quality due to fluctuations in output nodes that become floating. [Means for solving the problem]

[0006] A first aspect of the present invention is a photoelectric conversion device comprising a plurality of pixels arranged across a plurality of rows and a plurality of columns, a plurality of column circuits corresponding to the plurality of columns, and a control unit, wherein the column circuits have a comparison circuit having a first input node to which pixel signals from the plurality of pixels in the corresponding column are input and a second input node to which a reference signal is input, and a buffer circuit having an output node that outputs the reference signal to the comparison circuit in the corresponding column, and wherein the control unit is capable of controlling the potential of the output node of each of the plurality of buffer circuits to a predetermined potential.

[0007] A second aspect of the present invention is a photoelectric conversion system comprising a photoelectric conversion device and a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

[0008] A third aspect of the present invention is a mobile body equipped with a photoelectric conversion device, characterized in that the mobile body has a control unit that controls the movement of the mobile body using a signal output by the photoelectric conversion device.

[0009] A fourth aspect of the present invention is an apparatus characterized by having a photoelectric conversion device and at least one of an optical device corresponding to the photoelectric conversion device, a control device that controls the photoelectric conversion device, a processing device that processes signals output from the photoelectric conversion device, a display device that displays information obtained by the photoelectric conversion device, a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on information obtained by the photoelectric conversion device.

[0010] A fifth aspect of the present invention is a method for driving a photoelectric conversion device, the photoelectric conversion device comprising: a control unit; a comparison circuit having a first input node to which pixel signals from the pixels of the corresponding column are input and a second input node to which a reference signal is input; and a buffer circuit having an output node to output the reference signal to the comparison circuit of the corresponding column; wherein the control unit controls the buffer circuit between a first state in which the buffer circuit operates and a second state in which the power consumption of the buffer circuit is less than that of the first state; and wherein the control unit sets the potential of the output node of the buffer circuit to a predetermined potential during a period in which the buffer circuit is controlled to the second state. [Effects of the Invention]

[0011] According to the present invention, it is possible to reduce deterioration in image quality due to fluctuations in the output node of a buffer circuit that is floating. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a circuit block diagram according to a first embodiment. [Figure 2] FIG. 2 is a configuration diagram of a unit pixel according to the first embodiment. [Figure 3] 2 is a configuration example of a column circuit unit according to the first embodiment. [Figure 4] 2 is a configuration example of a buffer circuit according to the first embodiment. [Figure 5] 1 shows an example of connection between a buffer circuit and a comparison circuit according to the first embodiment. [Figure 6] FIG. 1 is a timing chart (part 1) in the first embodiment. [Figure 7] FIG. 2 is a timing chart (part 2) in the first embodiment. [Figure 8] FIG. 10 is a readout row scanning diagram according to the second embodiment. [Figure 9] FIG. 10 is a diagram illustrating a photoelectric conversion system according to a third embodiment. [Figure 10] FIG. 10 is a diagram illustrating a photoelectric conversion system and a moving object according to a fourth embodiment. [Figure 11] 10A and 10B are diagrams illustrating a range image sensor according to a fifth embodiment. [Figure 12] 10A and 10B are diagrams illustrating an endoscopic surgery system according to a sixth embodiment. [Figure 13] FIG. 13 is a diagram illustrating smart glasses according to a seventh embodiment. [Figure 14] FIG. 13 is a diagram illustrating an electronic device according to an eighth embodiment. [Figure 15] FIG. 13 is a diagram illustrating a device according to a ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. (First embodiment) In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, the embodiments are not limited to image pickup devices and can be applied to other examples of photoelectric conversion devices. For example, a distance measurement device (a device that measures distance using focus detection or TOF (Time Of Flight)) or a photometry device (a device that measures the amount of incident light) can be used. The block configuration of an imaging device to which the present invention is applied will be described with reference to FIG. 1, the imaging device 100 according to this embodiment includes a pixel region 10, a vertical drive circuit 30, and an output line drive circuit section 40. The imaging device 100 also includes a column circuit section 50, a reference signal generation circuit 50A, a horizontal drive circuit 60, a signal processing section 70, an output circuit 80, and a system control section 90 (sometimes simply referred to as a control section).

[0014] The pixel region 10 has a plurality of unit pixels 12 (sometimes simply referred to as a plurality of pixels) arranged in a matrix across a plurality of rows and a plurality of columns. Each of the plurality of unit pixels 12 includes a photoelectric conversion unit formed of a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. In addition to effective pixels that output pixel signals corresponding to the amount of incident light, the pixel region 10 may also include optical black pixels whose photoelectric conversion units are shielded from light, dummy pixels that do not output signals, and the like. The number of rows and columns of the pixel array arranged in the pixel region 10 is not particularly limited.

[0015] In each row of the pixel region 10, a control line 14 is arranged extending in a first direction (the horizontal direction in FIG. 1). Each of the control lines 14 is connected to the unit pixels 12 aligned in the first direction and serves as a signal line common to these unit pixels 12. The first direction in which the control lines 14 extend is sometimes referred to as the row direction or horizontal direction. Each of the control lines 14 may include multiple signal lines. The control lines 14 are connected to a vertical drive circuit 30.

[0016] In each column of the pixel region 10, a vertical output line 16 is arranged, extending in a second direction (the vertical direction in FIG. 1 ) intersecting the first direction. Each vertical output line 16 is connected to unit pixels 12 aligned in the second direction and serves as a signal line common to these unit pixels 12. The second direction in which the vertical output lines 16 extend is sometimes referred to as the column direction or vertical direction. Each vertical output line 16 includes a plurality of output lines. The vertical output line 16 is connected to an output line driving circuit unit 40.

[0017] The vertical drive circuit 30 is a control circuit that receives control signals supplied from the system control unit 90, generates control signals for driving the unit pixels 12, and supplies the control signals to the unit pixels 12 via control lines 14. The vertical drive circuit 30 may include logic circuits such as a shift register and an address decoder. The vertical drive circuit 30 sequentially supplies control signals to the control lines 14 of each row, thereby sequentially driving the unit pixels 12 in the pixel region 10 row by row.

[0018] Signals read out from the unit pixels 12 row by row are input to an output line driving circuit section 40 via vertical output lines 16 provided in each column of the pixel region 10. The output line driving circuit section 40 has a plurality of driving circuits 41 provided corresponding to each of the plurality of output lines constituting the vertical output lines 16 in each column of the pixel region 10. The output line driving circuit section 40 is a control circuit that receives control signals supplied from the system control section 90 and has the function of controlling the connection between the pixel region 10 and the column circuit section 50 and the potential of the vertical output lines 16.

[0019] The column circuit section 50 is provided corresponding to each of the multiple output lines constituting the vertical output line 16 of each column of the pixel region 10, and has multiple column circuits 51, each including a processing circuit and a signal holding circuit. The processing circuits have the function of performing predetermined signal processing on pixel signals output via the corresponding output lines. Examples of signal processing performed by the processing circuits include amplification processing, correction processing using correlated double sampling (CDS), and analog-to-digital conversion (AD conversion). The signal holding circuits function as memory for holding pixel signals processed by the processing circuits.

[0020] The reference signal generation circuit 50A is connected to the column circuit section 50. The reference signal generation circuit 50A receives a control signal output from the system control section 90, generates a reference signal to be used for AD conversion, and is connected to each column circuit 51 in the column circuit section 50. The reference signal to be used for AD conversion may be a signal that has a predetermined amplitude according to the range of the pixel signal and whose signal level changes over time. The reference signal is not particularly limited, but for example, a ramp signal whose signal level increases or decreases over time may be applied.

[0021] The counter circuit 50B is connected to the column circuit section 50. The counter circuit 50B performs a counting operation in response to a control signal output from the system control section 90, and has a function of outputting a count signal indicating the count value to the column circuit section 50. The counter circuit 50B starts its counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal generation circuit 50A starts to change.

[0022] The horizontal drive circuit 60 has a function of receiving a control signal supplied from the system control unit 90, generating a control signal for reading out pixel signals from the column circuit unit 50, and supplying the control signal to the column circuit unit 50. The horizontal drive circuit 60 sequentially scans the column circuits 51 of the column circuit section 50, and sequentially outputs the pixel signals held in each of them to the signal processing section 70. The horizontal drive circuit 60 can include logic circuits such as a shift register and an address decoder.

[0023] The signal processing unit 70 has a function of performing predetermined signal processing on pixel signals transferred from the column circuit unit 50. Examples of processing performed by the signal processing unit 70 include arithmetic processing, amplification processing, and correction processing using CDS.

[0024] The output circuit 80 has an external interface circuit and is a circuit for outputting the signal processed by the signal processing unit 70 to the outside of the imaging device 100. The external interface circuit provided in the output circuit 80 is not particularly limited. For example, an LVDS (Low Voltage Differential Signaling) circuit, an SLVS (Scalable Low Voltage Signaling) circuit, etc. can be used. These SerDes (Serializer / Deserializer) transmission circuits can be applied. .

[0025] The system control unit 90 is a control circuit that generates control signals for controlling the operation of the vertical drive circuit 30, the output line drive circuit unit 40, the column circuit unit 50, the horizontal drive circuit 60, etc., and supplies the control signals to each functional block. Note that the control signals for controlling the operation of the vertical drive circuit 30, the output line drive circuit unit 40, the column circuit unit 50, the horizontal drive circuit 60, etc., do not necessarily have to be supplied from the system control unit 90, and at least some of these control signals may be supplied from outside the imaging device 100. In FIG. 1, the signal paths are shown below the pixel region 10, but this is not limiting, and circuits related to the signal paths may also be arranged above the pixel region 10.

[0026] Next, a configuration example of a unit pixel 12 in the imaging device according to this embodiment will be described with reference to Fig. 2. Fig. 2 shows a unit pixel 12(m,n) arranged in the mth row and nth column out of the multiple unit pixels 12 that make up the pixel region 10. Here, m is an integer from 1 to M, and n is an integer from 1 to N. The other unit pixels 12 that make up the pixel region 10 may have the same circuit configuration as the unit pixel 12(m,n).

[0027] As shown in FIG. 2, the unit pixel 12(m,n) may be configured with a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The unit pixel 12(m,n) may have a microlens and a color filter arranged on the optical path of incident light leading to the photoelectric conversion element PD. The microlens focuses the incident light onto the photoelectric conversion element PD. The color filter selectively transmits light of a predetermined color. The photoelectric conversion element PD is, for example, a photodiode.

[0028] The photoelectric conversion element PD has an anode connected to a reference voltage node and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A node FD, to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected, is a so-called floating diffusion portion. The floating diffusion portion includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion. The floating diffusion capacitance may include pn junction capacitance, wiring capacitance, etc.

[0029] The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a node to which a power supply voltage (voltage VDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the vertical output line 16n.

[0030] In the circuit configuration of FIG. 2, the control line 14m of each row is connected to the gate of the transfer transistor M1, the reset The vertical drive circuit 30 supplies a control signal TXm to the gate of the transfer transistor M1 of the unit pixel 12 in the m-th row. The vertical drive circuit 30 supplies a control signal RSTm to the gate of the reset transistor M2 of the unit pixel 12 in the m-th row. The vertical drive circuit 30 supplies a control signal SELm to the gate of the select transistor M4 of the unit pixel 12 in the m-th row. When each transistor is an N-type MOS transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical drive circuit 30. On the other hand, the corresponding transistor turns off when a low-level control signal is supplied from the vertical drive circuit 30.

[0031] In this embodiment, the description will be made assuming that electrons, among the electron-hole pairs generated in the photoelectric conversion element PD by incident light, are used as signal charges. When electrons are used as signal charges, each transistor constituting the unit pixel 12 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is opposite to that described in this embodiment. Note that the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be referred to by the reverse names.

[0032] The photoelectric conversion element PD converts incident light into an electric charge in an amount corresponding to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When the transfer transistor M1 is turned on, it transfers the electric charge held by the photoelectric conversion element PD to the node FD. The electric charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of electric charge transferred from the photoelectric conversion element PD due to charge-voltage conversion by the floating diffusion capacitance.

[0033] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the vertical output line 16n. The amplification transistor M3 has a configuration in which a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source (a driving circuit 41, described later) (not shown) via the selection transistor M4. The amplification transistor M3 then forms an amplifier unit (source follower circuit) with its gate serving as an input node. This causes the amplification transistor M3 to output a signal based on the voltage of node FD to the vertical output line 16n via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 form an output unit that outputs a pixel signal according to the amount of charge held at node FD.

[0034] The reset transistor M2 has a function of controlling the supply of a voltage (voltage VDD) to the FD node for resetting the node FD as a charge storage unit. When the reset transistor M2 is turned on, it resets the node FD to a voltage corresponding to the voltage VDD. At this time, it is also possible to reset the photoelectric conversion element PD to a voltage corresponding to the voltage VDD by simultaneously turning on the transfer transistor M1. By appropriately controlling the transfer transistor M1, reset transistor M2, and selection transistor M4, a signal corresponding to the reset voltage of the node FD and a signal corresponding to the amount of light incident on the photoelectric conversion element PD are read out from each unit pixel 12. The unit pixel 12 of this embodiment has one photoelectric conversion element PD arranged therein. However, a plurality of photoelectric conversion elements may share one node FD. Also, the configuration is not limited to this.

[0035] 3 illustrates a plurality of column circuits 51 that make up the column circuit section 50. For example, the column circuit 51 is made up of a buffer circuit 56, a comparison circuit 54, a memory section 55, capacitors C1 and C2, and switches SW1, SW2, and SW3.

[0036] The buffer circuit 56 has an input node and an output node. The input node of the buffer circuit 56 is connected to a reference signal line 57. A reference signal VRAMP is supplied to the input node of the buffer circuit 56 from the reference signal generation circuit 50A via the reference signal line 57. The output node of the buffer circuit 56 is connected to one electrode of a capacitor C2. A switch SW1 is connected between the connection node between the buffer circuit 56 and the capacitor C2 and GND. Control signals SHT1 and SHT2 are supplied to the switches SW1 provided at the output nodes of each of the multiple buffer circuits independently from the system control unit 90 via signal lines 58 and 59.

[0037] The comparison circuit 54 is configured, for example, by a differential amplifier circuit, and has a non-inverting input node (+), an inverting input node (-), a non-inverting output node (+), and an inverting output node (-). The inverting input node of the comparison circuit 54 is connected to the other electrode of the capacitor C1. The signal VOUT is supplied to the inverting input node (sometimes referred to as the first input node) of the comparison circuit 54 from the vertical output line 16 via the capacitor C1.

[0038] A non-inverting input node (sometimes referred to as a second input node) of the comparison circuit 54 is connected to the other electrode of the capacitor C2. A reference signal VRAMP is supplied to the non-inverting input node of the comparison circuit 54 from a reference signal line 57 via a buffer circuit 56 and the capacitor C2. A switch SW2 is connected between the inverting input node and the non-inverting output node of the comparison circuit 54. A switch SW3 is connected between the non-inverting input node and the inverting output node of the comparison circuit 54. The switches SW2 and SW3 are controlled by a control signal AZ supplied from the system control unit 90 via an AZ signal line 52. The switches SW2 and SW3 are reset switches for resetting the threshold voltage of the comparison circuit 54.

[0039] The comparator circuit 54 compares the level of the signal VOUT supplied from the vertical output line 16 via the capacitor C1 with the level of the reference signal VRAMP supplied from the reference signal line 57 via the buffer circuit 56 and the capacitor C2, and outputs a signal according to the comparison result. For example, the comparator circuit 54 outputs a High-level signal when the level of the reference signal VRAMP is lower than the level of the signal VOUT. On the other hand, the comparator circuit 54 outputs a Low-level signal when the level of the reference signal VRAMP is higher than the level of the signal VOUT. Note that the relationship between the magnitude of the input signal and the level of the output signal may be reversed.

[0040] The comparison circuit 54 is not limited to the configuration shown in the figure, as long as it has a node to which a pixel signal is input and a node to which a reference signal is input, and is capable of performing an offset clamp operation to set an offset based on the voltages of the pixel signal and the reference signal.

[0041] The memory unit 55 holds the count value indicated by the count signal COUNT supplied from the counter circuit 50B as digital data of the pixel signal at the timing when the non-inverting output node level of the comparator circuit 54 is inverted. The held digital data is transferred to the signal processing unit 70 via the horizontal output line 62 sequentially for each column in response to a control signal supplied from the horizontal drive circuit 60. Note that the function of the counter circuit 50B may be configured to be provided inside the memory unit 55.

[0042] FIG. 4 shows an example of a buffer circuit 56. The buffer circuit 56 has P-type transistors MP1, MP2, MP3, and MP4. The source of the P-type transistor MP1 is connected to a node to which a power supply voltage (voltage VDD) is supplied. The drain of the P-type transistor MP1 is connected to the source of the P-type transistor MP2. The drain of the P-type transistor MP2 is connected to the source of the P-type transistor MP3. The drain of the P-type transistor MP3 is connected to the source of the P-type transistor MP4. The drain of the P-type transistor MP4 is connected to the reference voltage node. An operation enable signal EN controlled by the system control unit 90 (control unit) is supplied to the gate of the P-type transistor MP1. When the operation enable signal EN is at a first level (low level), the buffer circuit 56 is in a power-on state. On the other hand, when the operation enable signal EN is at a second level (high level), the buffer circuit 56 is in a power-off state. Note that this power-off state includes, but is not limited to, a state in which the source and drain of the P-type transistor MP1 are non-conductive. In other words, the power-off state also includes a state in which the current flowing between the source and drain of the P-type transistor MP1 is less than that in the power-on state. A bias voltage VB is supplied to the gate of the P-type transistor MP2. A bias voltage VC is supplied to the gate of the P-type transistor MP3. The gate of the P-type transistor MP4 is the input node IN of the buffer circuit 56. The connection node between the drain of the P-type transistor MP3 and the source of the P-type transistor MP4 is the output node OUT of the buffer circuit 56. The P-type transistor MP3 has a configuration in which a bias voltage VC is supplied to its gate, and operates as a cascode transistor. The P-type transistor MP3 forms a source follower together with the P-type transistor MP2, which operates as a current source, and buffers the signal (reference signal VRAMP) supplied from the input node IN and outputs it from the output node OUT. In other words, the buffer circuit 56 buffers the reference signal VRAMP and outputs it to the comparison circuit 54.

[0043] In particular, when thinning out column circuits, power saving may be achieved by powering off unused column circuits. For example, a switch SW1 is provided at each output node of the buffer circuit 56 (see FIG. 3). SW1 has the function of fixing the output node of the buffer circuit 56 to GND. While FIG. 3 illustrates an example where the output node is fixed to GND, this does not necessarily have to be GND; depending on the configuration of the buffer circuit 56, it may be VDD or an intermediate potential. In this specification, "power-off" includes, but is not limited to, zero power consumption. That is, "power-off" also includes setting a state of power consumption lower than the power-on state. Setting a state of power consumption lower than the power-on state can shorten the time required for the column circuit to change from the power-off state to the power-on state compared to setting the power consumption to zero. Furthermore, "power-off" of a column circuit includes, but is not limited to, powering off all components of the column circuit. For example, it also includes a case where the buffer circuit in the column circuit is powered off while other circuits, such as a comparator circuit, are powered on. In the embodiment described below, in the power-off state of the column circuit, it is sufficient that at least the buffer circuit 56 is set to consume less power than in the power-on state. However, as described above, the power-off state of the column circuit requires that at least the buffer circuit 56 is in the power-off state, and the comparison circuit 54 may also be in the power-off state. Furthermore, in this specification, the state in which the buffer circuit 56 operates may be referred to as a first state, and the state in which the power consumption of the buffer circuit 56 is less than in the first state may be referred to as a second state.

[0044] Here, in a case where some column circuits are thinned out to save power, for example, the odd-numbered column circuits 51a and 51c are power-on columns, and the even-numbered column circuits 51b and 51d are power-off columns. That is, one of the even-numbered and odd-numbered column circuits is powered on, while the other is powered off. In this case, the outputs of the buffer circuits 56 in the column circuits 51b and 51d are floating. For example, if potential fluctuations in the column circuit 51a are picked up and crosstalk occurs in the column circuit 51c, this may cause noise degradation. Therefore, turning on the switch SW1 prevents the floating state, thereby reducing image quality degradation. The imaging device 100 of this embodiment may be configured such that all of the above-described circuit blocks are arranged on a single substrate, or may be configured as a stacked type in which multiple substrates are stacked, with separate circuit blocks formed on each substrate.

[0045] Furthermore, the output node of the buffer circuit 56 has capacitive coupling with the input gate (reference signal VRAMP). That is, capacitive coupling with the reference signal VRAMP exists across all columns. When transitioning from an all-column power-on state to column circuit thinning operation, some column circuits are powered off, which can change the amount of capacitive coupling associated with the reference signal VRAMP. This changes the rate at which the reference signal VRAMP changes over time (slope operation), which can prevent accurate AD conversion and result in degradation of image quality. Next, this state will be described.

[0046] 5 shows a column circuit 51b. The column circuit 51b is a power-off column in a thinning-out operation, and the system control unit 90 can control a switch SW1 that fixes the potential of the output node of the buffer circuit 56 to a specific potential by a control signal SHT2 via a signal line 59. Here, the output node of the buffer circuit 56 is denoted as node A, and the potential is denoted as Va. Node A is connected to a capacitor C2, and the node on the other side of the comparison circuit 54 is denoted as B, and the potential is denoted as Vb.

[0047] Next, a case where the imaging device 100 transitions from operation using all column circuits to thinning operation will be described with reference to FIG. 6. Here, in MODE, the non-thinning (N) period represents the period when all column circuits are used, and the thinning (1) and thinning (2) periods represent the periods when thinning operation is performed. Also, the control signals TX, RES, SEL, SHT1, SHT2, and AZ are assumed to be at a high level to turn on transistors or switches, and at a low level to turn off transistors or switches. The signal VOUT of the vertical output line 16 is indicated by a dashed line.

[0048] Just before time t0, the control signal SEL (not shown) for the target row is at a high level. As a result, the selection transistors M4 of the pixels 12 belonging to that row are turned on, and each of these pixels 12 is ready to output a pixel signal to the vertical output line 16 of the corresponding column. During the period from time t0 to time t1, the vertical drive circuit 30 controls the control signal RES for the readout target row to a high level. As a result, the reset transistors M2 of the pixels 12 belonging to that row are turned on, and the node FD is reset to a voltage corresponding to the voltage VDD. A signal Vdark having a voltage corresponding to the reset voltage of the node FD is output to the vertical output line 16.

[0049] Furthermore, during the period from time t0 to time t2, the system control unit 90 controls the control signal AZ to a high level. This turns on the switches SW2 and SW3 of the column circuit 51 of each column, and the inverting input node and the non-inverting input node of the comparison circuit 54 are reset to a reset level voltage. That is, at time t2, one electrode of the capacitor C1 is at the reset level voltage of the signal VOUT, and the other electrode of the capacitor C1 is at the reset level voltage of the comparison circuit 54. Furthermore, one electrode of the capacitor C2 is at the reference voltage of the reference signal VRAMP, and the other electrode of the capacitor C2 is at the reset level voltage of the comparison circuit 54. The threshold voltage of the comparison circuit 54 is reset to a voltage corresponding to the potential difference between the reset level voltage of the signal VOUT and the reference voltage of the reference signal VRAMP.

[0050] The threshold voltage of the comparator circuit 54 is a voltage corresponding to the difference between the signal level of the pixel signal and the signal level of the reference signal when the level of the comparison signal output from the comparator circuit 54 changes. That is, the comparator circuit 54 outputs a comparison signal that indicates a different level when the difference between the signal level of the pixel signal and the signal level of the reference signal is smaller than the threshold voltage and larger than the threshold voltage. At time t2, the system control unit 90 controls the control signal AZ to a low level. This turns off the switches SW2 and SW3 of the column circuit 51 of each column, clamping the reset level of the signal VOUT to the capacitor C1, and clamping the reset level of the reference signal VRAMP to the capacitor C2. The reference level corresponding to the reference voltage of is clamped.

[0051] At time t3, the reference signal generation circuit 50A increases the reference signal VRAMP from the base voltage to a predetermined start voltage. Then, at time t4, a slope operation that changes over time begins. The counter circuit 50B also begins counting up at the same time as the slope operation begins, and supplies a count signal COUNT indicating the count value to the column circuit 51 of each column via the count signal line 53.

[0052] The comparator circuit 54 compares the level of the signal VOUT input via the capacitor C1 with the level of the reference signal VRAMP input via the capacitor C2. The comparator circuit 54 then inverts the level of its output signal when the magnitude relationship between the level of the signal VOUT and the level of the reference signal VRAMP changes, for example, at time t5. As a result, as described above, the digital data is stored in the memory unit 55 and sequentially transferred to the signal processor 70.

[0053] Subsequently, during the period from time t6 to time t7, the vertical drive circuit 30 controls the control signal TX of the row to be read out to a high level. This turns on the transfer transistor M1 of the unit pixel 12 belonging to that row, and the charge accumulated in the photoelectric conversion element PD during the predetermined exposure period is transferred to the node FD. As a result, the voltage of the node FD decreases in accordance with the amount of charge transferred from the photoelectric conversion element PD, and the potential of the signal VOUT output to the vertical output line 16 also decreases to Vlight. A signal VOUT (pixel signal at the light signal level) with a voltage corresponding to the voltage of the node FD is output to the vertical output line 16.

[0054] At time t8, the reference signal generation circuit 50A starts a slope operation in which the reference signal VRAMP changes over time. The counter circuit 50B starts counting up simultaneously with the start of the slope operation and supplies a count signal COUNT indicating the count value to the column circuit 51 of each column via the count signal line 53. The comparison circuit 54 compares the level of the signal VOUT input via the capacitor C1 with the level of the reference signal VRAMP input via the capacitor C2. The comparison circuit 54 then inverts the level of its output signal when the magnitude relationship between the level of the signal VOUT and the level of the reference signal VRAMP changes, for example, at time t9. As a result, as described above, the digital data is stored in the memory unit 55 and sequentially transferred to the signal processing unit 70.

[0055] The digital data of the pixel signals thus obtained is subjected to correction processing using correlated double sampling in the downstream signal processing unit 70. In the correction processing using correlated double sampling, the digital data of the pixel signals at the reset level is subtracted from the digital data of the pixel signals at the optical signal level, and noise components superimposed on the pixel signals at the optical signal level are removed.

[0056] This series of operations is repeated until time t9. FIG. 6 shows a case where the thinning-out operation is started after the series of operations from time t0 to time t9 (MODE transitions from the Nth row, which is not in the thinning-out operation, to the 1st row, which is in the thinning-out operation). At this time, the comparison circuit 54 and the buffer circuit 56 included in the column circuits 51b and 51d, which are not used in the thinning-out operation, are powered off by a power control signal (not shown). At this time, the output node A of the buffer circuit 56 in the column circuits 51b and 51d is floating. In other words, without the function of fixing the potential using the switch SW1 as in this embodiment (as when the control signals SHT1 and SHT2 shown in FIG. 6 are always low), the floating of the output node A may cause degradation of image quality. When the comparison circuit 54 is powered off, the inverting output node becomes VDD. At this time, when the AZ signal line 52 becomes high, the potential Vb of the node B (non-inverting input node) on the comparison circuit 54 side also becomes VDD. Since the output node A of the buffer circuit 56 is floating, the potential Va is reduced to Va1 by capacitive coupling due to the capacitance C2. It swings up.

[0057] As described above, the output node of the buffer circuit 56 has capacitive coupling with the input gate (reference signal VRAMP). The capacitive coupling of the reference signal VRAMP differs between the power-on column and the power-off column. For the power-off column, the reference signal generation circuit 50A drives the wiring in a state where it has capacitive coupling with Va1. At time t11, a reset level comparison is performed based on the reference signal VRAMP from the reference signal generation circuit 50A. Next, at time t12, the reference signal VRAMP begins a slope operation for comparing the optical signal level. However, when the reference signal VRAMP drops to a certain potential, as at time t13, the P-type transistor MP4 (whose input gate is the reference signal VRANP) in the buffer circuit 56 turns on. This causes the potential Va1 of the output node A, which had been floating, to drop to Va2 (≒GND). This changes the amount of capacitive coupling with the reference signal VRAMP, and the slope amount that changes over time also changes (as shown by the dashed line of the reference signal VRAMP after time t13).

[0058] For example, the comparator circuit 54 should have inverted the output signal level at time t14, but instead inverted it at time t15. As a result, the slope of the reference signal VRAMP, which changes over time at the reset level and the optical signal level, differs, and correct correction processing using correlated double sampling is not performed.

[0059] Next, the operation of the second row of the thinning operation will be explained. At time t16, when the control signal AZ goes high, node B (non-inverting input node) on the comparison circuit 54 side of the power-off column is set to VDD during the first row of the thinning operation. Therefore, even when the output node A of the buffer circuit 56 is floating, it is not significantly affected by the swing. Therefore, time t17 when the comparison circuit 54 inverts the level of the output signal for the reset level and time t18 when the comparison circuit 54 inverts the level of the output signal for the optical signal level are determined by the amount of slope due to the same time change in the reference signal VRAMP. As a result, only the first row of the thinning operation produces a peculiar output, causing degradation of image quality.

[0060] In FIG. 7, the operation of switch SW1 prevents the output nodes of buffer circuits 56 in column circuits 51b and 51d from floating. The same operational pulses as in FIG. 6 will not be described here. Control signals SHT1 and SHT2 are supplied via signal lines 58 and 59. While control signal SHT1 is constantly supplied at a low level via signal line 58, signal line 59, which supplies control signal SHT2, switches from a low level to a high level at time t10. As a result, output nodes A of buffer circuits 56 in column circuits 51b and 51d are fixed to GND when SW1 is turned on. At time t10, control signal AZ goes high, and node B (non-inverting input node) on the comparison circuit 54 side of the power-off column becomes VDD. However, because output node A of buffer circuit 56 is fixed by switch SW1, potential Va does not fluctuate due to capacitive coupling caused by capacitor C2. That is, even in the first row of the thinning operation, the slope operation of the reference signal VRAMP is the same during the reset level comparison operation and the optical signal level comparison operation, so correction processing by correct correlated double sampling can be performed. This is also the same for the second and subsequent rows of the thinning operation, so as a result, it is possible to obtain the effect of reducing image quality degradation.

[0061] Although the timing for powering off the column circuit 51 for the thinning operation is described as time t10, this is not limited to this, and similarly, the timing for setting the control signal SHT2 to high level is not limited to time t10. For example, after powering off, the control signal SHT2 is set to high level before the slope operation of the reference signal VRAMP used in the first AD conversion for the reset level. This makes it possible to align the slope operation of the reference signal VRAMP in the comparison operation between the reset level and the optical signal level.

[0062] Furthermore, in this embodiment, the buffer circuit 56 is configured with P-type transistors, but this is not limited to this and a configuration using N-type transistors may also be used. Furthermore, the slope shape is not limited to one in which the potential decreases over time. Therefore, as described above, the potential fixed by the switch SW1 is not limited to GND, but can also be VDD or a predetermined intermediate potential, making it possible to select an optimal combination in accordance with the configuration of the buffer circuit 56 and the comparison circuit 54.

[0063] Furthermore, the reference signal VRAMP to be supplied is not limited to one type, and for example, two types with different slope amounts that change over time may be supplied. In this case, each column circuit 51 may be provided with a buffer circuit 56 for the reference signal VRAMP with each type of slope amount.

[0064] (Second embodiment) The present disclosure is also applicable to a configuration in which a single column has multiple vertical output lines and multiple rows of image signals are scanned and read out in parallel as display image signals and sensing image signals. In this case, the column circuit unit 50 is provided with column circuits 51 corresponding to the number of vertical output lines for display image signals and vertical output lines for sensing image signals. FIG. 8 shows row scanning of display image signals and sensing image signals. 800 indicates scanning of display image signals (e.g., referred to as a first scan), and 801 indicates scanning of sensing image signals (e.g., referred to as a second scan). The first scan is scanning for reading signals from unit pixels 12 in some of the multiple rows, and the second scan is scanning for reading signals from unit pixels 12 in another part of the multiple rows. The period from the start to the end of the second scan is shorter than the period from the start to the end of the first scan. Furthermore, multiple second scans are performed during the period from the start to the end of the first scan. The signal read by this second scan can be used to detect whether flicker is occurring in the captured scene. The signal read by the second scan can be used for various purposes, including not only flicker detection but also moving object detection. During the period from time t80 to time t81 indicated by 802, scanning of the display image signal is not performed, and the column circuits that read the display image signal are powered off. In this case, the aforementioned image quality degradation may occur in the sensing image at time t80. Therefore, by fixing the output node of the buffer circuit 56, it is possible to achieve both the effect of reducing image quality degradation and high functionality.

[0065] The photoelectric conversion system, the mobile object, and the device according to the embodiment will be described below.

[0066] (Third embodiment) The photoelectric conversion system according to this embodiment will be described with reference to Fig. 9. Fig. 9 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0067] The imaging devices (examples of photoelectric conversion devices) described in the first and second embodiments can be applied to various photoelectric conversion systems. A photoelectric conversion system includes at least the photoelectric conversion device according to the above embodiments and a signal processing unit that processes signals output from the photoelectric conversion device. Examples of devices to which such photoelectric conversion systems can be applied include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, sensors, and measuring instruments. Furthermore, camera modules equipped with an optical system such as a lens and a photoelectric conversion device are also included in devices to which photoelectric conversion systems are applied. FIG. 9 illustrates a block diagram of a digital still camera as an example of such devices.

[0068] 9 includes a photoelectric conversion device 2504 to which the photoelectric conversion device of each of the above-described embodiments is applied, and a lens 2502 that forms an optical image of a subject on the photoelectric conversion device 2504. The photoelectric conversion system also includes a lens 2502 that can change the amount of light passing through the lens 2502. The lens 2502 includes a diaphragm 2503 for focusing light and a barrier 2501 for protecting the lens 2502. The lens 2502 and the diaphragm 2503 form an optical system that focuses light onto a photoelectric conversion device 2504. The photoelectric conversion device 2504 is the photoelectric conversion device according to any of the above embodiments, and converts the optical image formed by the lens 2502 into an electrical signal.

[0069] The photoelectric conversion system also includes a signal processing unit 2507, which is an image generating unit that generates an image by processing an output signal output from the photoelectric conversion device 2504. The signal processing unit 2507 performs various corrections and compressions as necessary to output image data. The signal processing unit 2507 may be formed on the same semiconductor substrate on which the photoelectric conversion device 2504 is provided, or may be formed on a semiconductor substrate separate from the photoelectric conversion device 2504. Furthermore, the photoelectric conversion device 2504 and the signal processing unit 2507 may be formed on the same semiconductor substrate.

[0070] The photoelectric conversion system further includes a memory unit 2510 for temporarily storing image data, and an external interface unit (external I / F unit) 2513 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 2512 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 2511 for recording or reading out data from the recording medium 2512. The recording medium 2512 may be built into the photoelectric conversion system or may be detachable.

[0071] The photoelectric conversion system further includes an overall control / calculation unit 2509 that performs various calculations and controls the entire digital still camera, and a timing generation unit 2508 that outputs various timing signals to the photoelectric conversion device 2504 and the signal processing unit 2507. Here, timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the photoelectric conversion device 2504 and the signal processing unit 2507 that processes the output signal output from the photoelectric conversion device 2504.

[0072] The photoelectric conversion device 2504 outputs the imaging signal to the signal processing unit 2507. The signal processing unit 2507 performs predetermined signal processing on the imaging signal output from the photoelectric conversion device 2504 and outputs image data. The signal processing unit 2507 generates an image using the imaging signal.

[0073] As described above, according to this embodiment, a photoelectric conversion system can be realized to which the photoelectric conversion device according to any one of the above embodiments is applied.

[0074] (Fourth embodiment) The photoelectric conversion system and the mobile object of this embodiment will be described with reference to Figures 10(A) and 10(B). Figure 10(A) is a diagram showing the configuration of the photoelectric conversion system of this embodiment, and Figure 10(B) is a diagram showing the configuration of the mobile object of this embodiment.

[0075] FIG. 10A shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 2600 includes a photoelectric conversion device 2610. The photoelectric conversion device 2610 is the photoelectric conversion device described in any of the above embodiments. The photoelectric conversion system 2600 includes an image processing unit 2612 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 2610. The photoelectric conversion system 2600 also includes a distance acquisition unit 2616 that calculates the distance to an object, and a collision determination unit 2618 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the distance acquisition unit 2616 may acquire distance information to the object using ToF (Time Of Flight), or may acquire distance information using parallax information, etc. In other words, the distance information is information related to parallax, defocus amount, distance to the object, etc. The collision determination unit 2618 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware or a software module. It may be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or by a combination of these.

[0076] The photoelectric conversion system 2600 is connected to a vehicle information acquisition device 2620 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 2600 is also connected to an ECU 2630, which is a control device (control unit) that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 2618. The photoelectric conversion system 2600 is also connected to an alarm device 2640 that issues an alarm to the driver based on the determination result of the collision determination unit 2618. For example, if the determination result of the collision determination unit 2618 indicates a high possibility of a collision, the ECU 2630 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 2640 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0077] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 2600. Fig. 10(B) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 2650). A vehicle information acquisition device 2620 sends instructions to the photoelectric conversion system 2600 or the photoelectric conversion device 2610. This configuration can further improve the accuracy of distance measurement.

[0078] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system can be applied not only to automobiles and other vehicles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generator that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generator can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, an aircraft's propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0079] (Fifth embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 11. Fig. 11 is a block diagram showing an example of the configuration of a range image sensor, which is the photoelectric conversion system of this embodiment.

[0080] 11, the distance image sensor 2701 is configured to include an optical system 2707, a photoelectric conversion device 2708, an image processing circuit 2704, a monitor 2705, and a memory 2706. The distance image sensor 2701 can obtain a distance image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected toward the subject from a light source device 2709 and reflected from the surface of the subject.

[0081] The optical system 2707 is configured to have one or more lenses, and guides image light (incident light) from the subject to the photoelectric conversion device 2708, forming an image on the light receiving surface (sensor section) of the photoelectric conversion device 2708.

[0082] The photoelectric conversion device 2708 is the photoelectric conversion device of each of the above-described embodiments, and a distance signal indicating a distance determined from a light reception signal output from the photoelectric conversion device 2708 is supplied to the image processing circuit 2704.

[0083] The image processing circuit 2704 calculates the distance based on the distance signal supplied from the photoelectric conversion device 2708. Then, the distance image (image data) obtained by this image processing is supplied to a monitor 2705 for display, or supplied to a memory 2706 for storage (recording).

[0084] In the range image sensor 2701 configured in this way, by applying the above-described photoelectric conversion device, it is possible to obtain, for example, a more accurate range image as the pixel characteristics improve.

[0085] (Sixth embodiment) The photoelectric conversion system of this embodiment will be described with reference to Fig. 12. Fig. 12 is a diagram showing an example of the schematic configuration of an endoscopic surgery system, which is the photoelectric conversion system of this embodiment.

[0086] 12 shows a state in which an operator (doctor) 2831 is performing surgery on a patient 2832 on a patient bed 2833 using an endoscopic surgery system 2850. As shown in the figure, the endoscopic surgery system 2850 is composed of an endoscope 2800, a surgical tool 2810, and a cart 2834 on which various devices for endoscopic surgery are mounted.

[0087] The endoscope 2800 is composed of a lens barrel 2801, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 2832, and a camera head 2802 connected to the base end of the lens barrel 2801. In the example shown in the figure, the endoscope 2800 is configured as a so-called rigid lens barrel having a rigid lens barrel 2801, but the endoscope 2800 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0088] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 2801. A light source device 2803 is connected to the endoscope 2800. Light generated by the light source device 2803 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 2801, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 2832. Note that the endoscope 2800 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0089] An optical system and a photoelectric conversion device are provided inside the camera head 2802, and light reflected from the observation object (observation light) is focused onto the photoelectric conversion device by the optical system. The observation light is captured by the photoelectric conversion device, and an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image, is generated. The photoelectric conversion device may be any of the photoelectric conversion devices described in the above-described embodiments. The image signal is transmitted as RAW data to a camera control unit (CCU) 2835.

[0090] The CCU 2835 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 2800 and the display device 2836. Furthermore, the CCU 2835 receives an image signal from the camera head 2802 and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0091] The display device 2836, under the control of the CCU 2835, displays an image based on the image signal that has been subjected to image processing by the CCU 2835.

[0092] The light source device 2803 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 2800 with irradiation light when photographing an operation site or the like.

[0093] The input device 2837 is an input interface for the endoscopic surgery system 2850. A user can input various information and instructions to the endoscopic surgery system 2850 via the input device 2837.

[0094] The treatment tool control device 2838 controls the driving of the energy treatment tool 2812 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0095] The light source device 2803 that supplies illumination light to the endoscope 2800 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 2803. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 2802 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0096] Furthermore, the driving of the light source device 2803 may be controlled so as to change the intensity of the light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 2802 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining these images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0097] The light source device 2803 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation utilizes, for example, the wavelength dependency of light absorption in body tissue. Specifically, by irradiating light with a narrower band than the light (i.e., white light) used in normal observation, a specific tissue, such as blood vessels on the surface of a mucous membrane, can be photographed with high contrast. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto a body tissue and observing the fluorescence from the body tissue, or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 2803 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0098] (Seventh embodiment) The photoelectric conversion system of this embodiment will be described with reference to FIGS. 13(A) and 13(B). FIG. 13(A) illustrates glasses 2900 (smart glasses) which are the photoelectric conversion system of this embodiment. The glasses 2900 have a photoelectric conversion device 2902. The photoelectric conversion device 2902 is the photoelectric conversion device described in each of the above embodiments. A display device including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 2901. The photoelectric conversion device 2902 may be one or more. A combination of multiple types of photoelectric conversion devices may also be used. The arrangement position of the photoelectric conversion device 2902 is not limited to that shown in FIG. 13(A).

[0099] The glasses 2900 further include a control device 2903. The control device 2903 functions as a power source that supplies power to the photoelectric conversion device 2902 and the display device. The control device 2903 also controls the operations of the photoelectric conversion device 2902 and the display device. The lens 2901 is formed with an optical system for focusing light onto the photoelectric conversion device 2902.

[0100] FIG. 13(B) illustrates glasses 2910 (smart glasses) according to one application example. The mirror 2910 includes a control device 2912, which is equipped with a photoelectric conversion device corresponding to the photoelectric conversion device 2902 and a display device. A lens 2911 includes an optical system for projecting light emitted from the photoelectric conversion device in the control device 2912 and the display device, and an image is projected onto the lens 2911. The control device 2912 functions as a power source for supplying power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device may include a gaze detection unit that detects the wearer's gaze. Infrared light may be used for gaze detection. The infrared light emitting unit emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit with a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. By including a reduction unit that reduces light from the infrared light emitting unit to the display unit in a planar view, degradation of image quality is reduced.

[0101] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0102] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0103] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the photoelectric conversion device.

[0104] Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0105] The display area may also include a first display area and a second display area different from the first display area, and a high-priority area may be determined from the first display area and the second display area based on line-of-sight information. The first display area and the second display area may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0106] Note that AI may be used to determine the first field of view area and areas with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from an image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0107] When display control is performed based on visual recognition detection, the present invention is preferably applied to smart glasses that further include a photoelectric conversion device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0108] (Eighth embodiment) The above-described photoelectric conversion device and photoelectric conversion system may be applied to electronic devices such as so-called smartphones and tablets.

[0109] 14(A) and 14(B) are diagrams showing an example of an electronic device 3000 equipped with a photoelectric conversion device. Fig. 14(A) shows the front side of the electronic device 3000, and Fig. 14(B) shows the back side of the electronic device 3000.

[0110] 14(A), a display 3010 for displaying an image is disposed in the center of the surface of electronic device 3000. Further, along the upper side of the surface of electronic device 3000, front cameras 3021 and 3022 using photoelectric conversion devices, an IR light source 3030 for emitting infrared light, and a visible light source 3040 for emitting visible light are disposed.

[0111] Also, as shown in Figure 14(B), rear cameras 3051 and 3052 using photoelectric conversion devices, an IR light source 3060 that emits infrared light, and a visible light source 3070 that emits visible light are arranged along the upper edge of the back of the electronic device 3000.

[0112] By applying the above-described photoelectric conversion device to the electronic device 3000 configured as described above, it is possible to capture higher quality images, for example. The photoelectric conversion device can also be applied to other electronic devices, such as infrared sensors, distance measurement sensors using active infrared light sources, security cameras, and personal or biometric authentication cameras. This can improve the accuracy and performance of these electronic devices.

[0113] (Ninth embodiment) A photoelectric conversion system according to the ninth embodiment will be described with reference to Fig. 15. Fig. 15 is a block diagram showing a schematic configuration of a photoelectric conversion system SYS, which is a photoelectric conversion system according to the ninth embodiment. The photoelectric conversion system SYS includes at least a photoelectric conversion device according to any of the above embodiments and a signal processing unit that processes a signal output from the photoelectric conversion device.

[0114] The photoelectric conversion system SYS is an information terminal having a camera or a photographing function. The photoelectric conversion system SYS is constructed using a photoelectric conversion device IS. The photoelectric conversion device IS may further include a package PKG that houses an imaging device IC. The package PKG may include a base to which the imaging device IC is fixed and a lid that faces the imaging device IC. The package PKG may include a connecting member (a member that connects terminals provided on the base with terminals provided on the imaging device IC). The photoelectric conversion device IS may also mount multiple imaging device ICs side by side in a common package PKG. Furthermore, the photoelectric conversion device IS may also mount an imaging device IC and other semiconductor device ICs stacked on top of each other in a common package PKG.

[0115] The photoelectric conversion system SYS may include an optical system OU (optical device) that forms an image on the photoelectric conversion device IS. The photoelectric conversion system SYS may also include at least one of a control device CU, a processing device PU, a display device DU, and a memory device MU. The control device CU controls the photoelectric conversion device IS, and the processing device PU processes signals obtained from the photoelectric conversion device IS. The display device DU displays images obtained from the photoelectric conversion device IS, and the memory device MU stores images obtained from the photoelectric conversion device IS.

[0116] (others) Although various devices have been described in the above embodiments, a mechanical device may also be provided. The mechanical device in the camera can drive optical components for zooming, focusing, and shutter operation. Alternatively, the mechanical device in the camera can move a photoelectric conversion device for vibration reduction.

[0117] The equipment may also be transportation equipment such as a vehicle, a ship, or an aircraft. The device can be used as a mobile device. The device as a transportation device is suitable for transporting the photoelectric conversion device or for assisting and / or automating driving (operation) using a photographing function. The processing device for assisting and / or automating driving (operation) can perform processing to operate the mechanical device as a mobile device based on information obtained by the photoelectric conversion device.

[0118] The embodiments described above can be modified as appropriate without departing from the spirit and scope of the present invention. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto.

[0119] The disclosure of this embodiment includes the following configuration. (Configuration 1) a plurality of pixels arranged across a plurality of rows and a plurality of columns; a plurality of column circuits respectively corresponding to the plurality of columns; Control unit and Equipped with The column circuitry includes: a comparison circuit having a first input node to which pixel signals from a plurality of pixels in a corresponding column are input, and a second input node to which a reference signal is input; a buffer circuit having an output node for outputting the reference signal to the comparator circuit of a corresponding column; and the control unit is capable of controlling the potential of the output node of each of the plurality of buffer circuits to a predetermined potential. A photoelectric conversion device characterized by: (Configuration 2) during a period in which the power consumption of the buffer circuit of a portion of the plurality of column circuits is controlled to be lower than the power consumption of the buffer circuit of another portion of the plurality of column circuits, the control unit controls the potential of the output node of the buffer circuit included in the portion of the column circuits to the predetermined potential; 2. The photoelectric conversion device according to configuration 1, (Configuration 3) during a period in which the power consumption of the buffer circuit included in one of the odd-numbered columns and the even-numbered columns among the plurality of column circuits is controlled to be less than the power consumption of the buffer circuit included in the other of the odd-numbered columns and the even-numbered columns, the control unit controls the potential of the output node of the buffer circuit included in the one of the column circuits to the predetermined potential; 3. The photoelectric conversion device according to configuration 1 or 2. (Configuration 4) A signal line for inputting a control signal for controlling the potential of the output node of the buffer circuit to the predetermined potential to the some column circuits is independent from a signal line for inputting the control signal to the other some column circuits. 4. The photoelectric conversion device according to configuration 2 or 3. (Configuration 5) The predetermined potential is GND. 5. The photoelectric conversion device according to any one of configurations 1 to 4. (Configuration 6) After controlling the power consumption of the buffer circuit of the partial column circuit to be less than the power consumption of the buffer circuit of the other partial column circuit, the output node of the buffer circuit of the partial column circuit is fixed to the predetermined potential before the slope operation of the reference signal starts. 6. The photoelectric conversion device according to any one of configurations 2 to 5. (Configuration 7) During a period in which a first scan is being performed to read out signals from pixels in some rows of the plurality of rows, a second scan is being performed to read out signals from pixels in another part of rows of the plurality of rows, and a period from the start to the end of the second scan is shorter than a period from the start to the end of the first scan. 7. The photoelectric conversion device according to any one of configurations 1 to 6. (Configuration 8) The photoelectric conversion device according to any one of configurations 1 to 7, a signal processing unit that generates an image using a signal output from the photoelectric conversion device; A photoelectric conversion system comprising: (Configuration 9) A moving object including the photoelectric conversion device according to any one of configurations 1 to 7, a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device; A moving object characterized by: (Configuration 10) The photoelectric conversion device according to any one of configurations 1 to 7, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and a mechanical device that operates based on information obtained by the photoelectric conversion device; At least one of An apparatus characterized by having: (Configuration 11) A method for driving a photoelectric conversion device, the photoelectric conversion device comprising: a plurality of pixels arranged across a plurality of rows and a plurality of columns; a plurality of column circuits respectively corresponding to the plurality of columns; Control unit and Equipped with The column circuitry includes: a comparison circuit having a first input node to which pixel signals from a plurality of pixels in a corresponding column are input, and a second input node to which a reference signal is input; a buffer circuit having an output node that outputs the reference signal to the comparator circuit of a corresponding column; The control unit controlling the buffer circuit to a first state in which the buffer circuit operates and a second state in which the power consumption of the buffer circuit is less than that of the first state; A method for driving a photoelectric conversion device, comprising setting a potential of an output node of the buffer circuit to a predetermined potential while the buffer circuit is controlled to the second state. [Explanation of symbols]

[0120] 12 unit pixels 54 Comparison circuit 56 Buffer circuit 90 System control section 100 Imaging device (photoelectric conversion device)

Claims

1. a plurality of pixels arranged across a plurality of rows and a plurality of columns; a plurality of column circuits respectively corresponding to the plurality of columns; Control unit and Equipped with The column circuitry includes: a comparison circuit having a first input node to which pixel signals from a plurality of pixels in a corresponding column are input, and a second input node to which a reference signal is input; a buffer circuit having an output node for outputting the reference signal to the comparator circuit of a corresponding column; and the control unit is capable of controlling the potential of the output node of each of the plurality of buffer circuits to a predetermined potential. A photoelectric conversion device characterized by:

2. during a period in which the power consumption of the buffer circuit of a portion of the plurality of column circuits is controlled to be lower than the power consumption of the buffer circuit of another portion of the plurality of column circuits, the control unit controls the potential of the output node of the buffer circuit included in the portion of the column circuits to the predetermined potential; 2. The photoelectric conversion device according to claim 1.

3. during a period in which the power consumption of the buffer circuit included in one of the odd-numbered columns and the even-numbered columns among the plurality of column circuits is controlled to be less than the power consumption of the buffer circuit included in the other of the odd-numbered columns and the even-numbered columns, the control unit controls the potential of the output node of the buffer circuit included in the one of the column circuits to the predetermined potential; 2. The photoelectric conversion device according to claim 1.

4. A signal line for inputting a control signal for controlling the potential of the output node of the buffer circuit to the predetermined potential to the some column circuits is independent from a signal line for inputting the control signal to the other some column circuits.

3. The photoelectric conversion device according to claim 2.

5. The predetermined potential is GND.

2. The photoelectric conversion device according to claim 1.

6. After controlling the power consumption of the buffer circuit of the partial column circuit to be less than the power consumption of the buffer circuit of the other partial column circuit, the output node of the buffer circuit of the partial column circuit is fixed to the predetermined potential before the slope operation of the reference signal starts.

3. The photoelectric conversion device according to claim 2.

7. During a period in which a first scan is being performed to read out signals from pixels in some rows of the plurality of rows, a second scan is being performed to read out signals from pixels in another part of rows of the plurality of rows, and a period from the start to the end of the second scan is shorter than a period from the start to the end of the first scan.

2. The photoelectric conversion device according to claim 1.

8. The photoelectric conversion device according to any one of claims 1 to 7, a signal processing unit that generates an image using a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

9. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 7, a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device; A moving object characterized by:

10. The photoelectric conversion device according to any one of claims 1 to 7, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and a mechanical device that operates based on information obtained by the photoelectric conversion device; At least one of An apparatus characterized by having:

11. A method for driving a photoelectric conversion device, the photoelectric conversion device comprising: a plurality of pixels arranged across a plurality of rows and a plurality of columns; a plurality of column circuits respectively corresponding to the plurality of columns; Control unit and Equipped with The column circuitry includes: a comparison circuit having a first input node to which pixel signals from a plurality of pixels in a corresponding column are input, and a second input node to which a reference signal is input; a buffer circuit having an output node that outputs the reference signal to the comparator circuit of a corresponding column; The control unit controlling the buffer circuit to a first state in which the buffer circuit operates and a second state in which the power consumption of the buffer circuit is less than that in the first state; A method for driving a photoelectric conversion device, comprising the steps of: setting a potential of an output node of the buffer circuit to a predetermined potential while the buffer circuit is controlled to the second state.

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