Semiconductor device

Abstract

To provide a semiconductor device with favorable electrical characteristics, to provide a highly reliable semiconductor device, and to provide a semiconductor device with stable electrical characteristics.SOLUTION: A semiconductor device includes a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order over the first insulating layer. The second insulating layer has a stacked-layer structure in which a first insulating film, a second insulating film, and a third insulating film are stacked in this order, and the first insulating film, the second insulating film, and the third insulating film each contain an oxide. The first insulating film includes a portion in contact with the semiconductor layer. The semiconductor layer contains indium, gallium, and oxygen and includes a region with an indium content percentage higher than a gallium content percentage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. Regarding the device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and the like. , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof Semiconductor devices function by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used in transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the ratio of indium to that of gallium, the field effect mobility (simply called mobility) can be improved. A semiconductor device with enhanced mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. By improving some of the production facilities for transistors using polycrystalline silicon and amorphous silicon, This allows for the use of metal oxide transistors, which reduces capital investment. The capacitor has a higher field effect mobility than amorphous silicon, so it can be used in the drive circuit. A high-performance display device can be realized. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. An object of one embodiment of the present invention is to provide a highly reliable semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device with stable electrical characteristics. An object of the present invention is to provide a highly reliable display device.

[0007] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from the description, drawings, claims, etc. [Means for solving the problem]

[0008] One embodiment of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor device has a first insulating layer, a semiconductor layer, a second insulating layer, and a first conductive layer. The second insulating layer is made up of a first insulating film, a second insulating film, and a third insulating film. The insulating film has a laminated structure in which a first insulating film, a second insulating film, and The first insulating film has a portion in contact with the semiconductor layer. The semiconductor layer contains indium and oxygen.

[0009] In the above, the semiconductor layer preferably does not contain gallium.

[0010] In the above, the semiconductor layer preferably contains zinc.

[0011] Another aspect of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer. The semiconductor device has a semiconductor layer, a second insulating layer, and a first insulating layer on a first insulating layer. The conductive layers are stacked in this order. The second insulating layer is made up of a first insulating film, a second insulating film, and and a third insulating film are laminated in this order, and the first insulating film, the second insulating film, The insulating film and the third insulating film each contain an oxide. The semiconductor layer includes indium, gallium, and oxygen, and The region has a higher content of sodium than gallium.

[0012] In the above, the semiconductor layer preferably contains zinc. Preferably, the zinc content is higher than the gallium content.

[0013] Another aspect of the present invention is a semiconductor device including a first insulating layer, a second insulating layer, a first semiconductor layer, and a second insulating layer. The semiconductor device has a first insulating layer, a second semiconductor layer, and a first conductive layer. A dielectric layer, a first semiconductor layer, a second insulating layer, and a first conductive layer are stacked in this order. The second insulating layer is formed by laminating a first insulating film, a second insulating film, and a third insulating film in this order. The first insulating film, the second insulating film, and the third insulating film each have a laminated structure The first insulating film includes an oxide. The first insulating film has a portion in contact with the first semiconductor layer. The first semiconductor layer The first semiconductor layer contains indium and oxygen, and the second semiconductor layer contains indium, zinc, and gallium. The first semiconductor layer contains indium and oxygen, and the second semiconductor layer contains indium. It has a region with a high content of

[0014] In the above, the first semiconductor layer preferably contains zinc and gallium. The first semiconductor layer has a gallium content lower than an indium content, and Preferably, the first layer has a region in which the zinc content is higher than the gallium content. The semiconductor layer of the first semiconductor layer has a region where the zinc content is equal to that of the second semiconductor layer or a region where the zinc content is equal to that of the second semiconductor layer. It is preferable that the semiconductor layer has a region higher than the semiconductor layer.

[0015] In the above, a metal oxide layer is provided between the second insulating layer and the first conductive layer. In this case, the metal oxide layer is preferably made of aluminum, hafnium, indium, It is preferable that the metal oxide contains one or more elements selected from gallium and zinc. The metal oxide layer preferably contains indium, and the metal oxide layer and the first semiconductor layer It is preferable that the content of indium is approximately equal.

[0016] In the above, the first insulating film is formed under conditions where the film formation rate is lower than that of the second insulating film. It is preferable that the membrane is made of a material having a high molecular weight.

[0017] In addition, in the above, a second conductive layer and a third insulating layer instead of the first insulating layer are provided. In this case, the second conductive layer is preferably connected to the first semiconductor layer via the third insulating layer. The third insulating layer has an overlapping region, and the third insulating layer has a fourth insulating film, a fifth insulating film, a sixth insulating film, and It is preferable that the seventh insulating film has a laminated structure in which the seventh insulating film is laminated in this order. The fourth insulating film, the fifth insulating film, and the sixth insulating film each contain nitrogen. It is preferred that it contains

[0018] In the above, the seventh insulating film contains silicon oxide, and the fourth insulating film and the fifth insulating film contain silicon oxide. The insulating film and the sixth insulating film each preferably contain silicon nitride. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, a semiconductor device with stable electrical characteristics can be provided. Alternatively, a highly reliable display device can be provided.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0021] [Figure 1] 1A and 1B are diagrams illustrating examples of the structure of a transistor. [Figure 2] 2A and 2B are diagrams illustrating examples of the structure of a transistor. [Figure 3] 3A to 3C are diagrams illustrating examples of transistor structures. [Figure 4] 4A to 4C are diagrams illustrating examples of transistor structures. [Figure 5]5A to 5C are diagrams illustrating examples of transistor structures. [Figure 6] 6A to 6C are diagrams illustrating examples of transistor structures. [Figure 7] 7A to 7D are diagrams illustrating examples of transistor structures. [Figure 8] 8A to 8D are diagrams illustrating examples of transistor structures. [Figure 9] 9A to 9E illustrate a method for manufacturing a transistor. [Figure 10] 10A to 10D illustrate a method for manufacturing a transistor. [Figure 11] 11A and 11B illustrate a method for manufacturing a transistor. [Figure 12] 12A to 12D illustrate a method for manufacturing a transistor. [Figure 13] 13A to 13C are top views of the display device. [Figure 14] FIG. 14 is a cross-sectional view of the display device. [Figure 15] FIG. 15 is a cross-sectional view of the display device. [Figure 16] FIG. 16 is a cross-sectional view of the display device. [Figure 17] FIG. 17 is a cross-sectional view of the display device. [Figure 18] Fig. 18(A) is a block diagram of a display device, and Fig. 18(B) and Fig. 18(C) are circuit diagrams of the display device. [Figure 19] 19A, 19C, and 19D are circuit diagrams of the display device, and FIG. 19B is a timing chart. [Figure 20] 20(A) and 20(B) are diagrams showing configuration examples of a display module. [Figure 21] 21(A) and 21(B) are diagrams showing configuration examples of electronic devices. [Figure 22]22A to 22E are diagrams showing configuration examples of electronic devices. [Figure 23] 23A to 23G are diagrams showing configuration examples of electronic devices. [Figure 24] 24A to 24D are diagrams showing configuration examples of electronic devices. [Figure 25] 25A to 25D show the Id-Vg characteristics of transistors, and FIG. 25E shows the reliability test results of the transistors. [Figure 26] 26A is a graph showing the Id-Vg characteristics of a transistor, and FIG. 26B is a graph showing the reliability test results of the transistor. [Figure 27] FIG. 27 shows the results of TDS analysis. [Figure 28] 28(A) and 28(B) are diagrams showing the results of TDS analysis. [Figure 29] 29(A) to 29(C) are diagrams showing the results of ESR measurements. [Figure 30] 30A is a graph showing the Id-Vg characteristics of a transistor, and FIG. 30B is a graph showing the reliability test results of the transistor. [Figure 31] 31A is a graph showing the Id-Vg characteristics of a transistor, and FIG. 31B is a graph showing the reliability test results of the transistor. [Figure 32] 32A is a graph showing the Id-Vg characteristics of a transistor, and FIG. 32B is a graph showing the reliability test results of the transistor. [Figure 33] 33A is a conceptual diagram of a split structure, and FIG 33B is a diagram showing the density of states of an oxide semiconductor having a split structure. [Figure 34] Fig. 34(A) is a conceptual diagram of a Ga-O structure, and Fig. 34(B) is a diagram showing the densities of state of an oxide semiconductor having a Ga-O structure. [Figure 35] 35(A) and 35(B) are diagrams showing energy changes in the reaction pathway. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] In addition, in each drawing described in this specification, the size, layer thickness, or area of ​​each component may be may be exaggerated for clarity.

[0024] In addition, the ordinal numbers "first," "second," and "third" used in this specification and the like refer to components. This is added to avoid confusion and is not intended to limit the number.

[0025] In addition, in this specification, the terms "above" and "below" that indicate the arrangement of the components are the same. The positional relationship of the components is used for convenience in explaining the drawings. The relative positions of the elements change depending on the direction in which each element is depicted. The student is not limited to the words and phrases explained in the book, but can use appropriate phrases depending on the situation.

[0026] In this specification and the like, the functions of the source and the drain of a transistor are different. When using polarity transistors or when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain are sometimes used interchangeably. It is possible to do so.

[0027] In this specification, the channel length direction of a transistor is the direction in which the source region and the drain region are connected. This refers to one of the directions parallel to the line connecting the channel area with the shortest distance. The length direction of the transistor is one of the directions of current flowing through the semiconductor layer when the transistor is in the on state. The channel width direction corresponds to the direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction may be one. It may not be fixed.

[0028] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0029] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchanged with "conductive film" and "insulating layer." The term "insulating film" may be used interchangeably in some cases.

[0030] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also known as a cut-off state). Unless otherwise specified, for an n-channel transistor, the voltage V between the gate and source gs is the threshold voltage V th(For p-channel transistors, V th Higher than (i) This refers to a state.

[0031] In this specification, a display panel, which is one aspect of a display device, displays (outputs) an image or the like on a display surface. Therefore, a display panel is one aspect of an output device.

[0032] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Integrated Circuit) or TCP (Tape Carrier Packet ge) or a connector such as COG (Chip On Ground) is attached to the board. IC (Integrated Circuit) was implemented using the Glass method, etc. When referring to a display panel module, display module, or simply a display panel, There is.

[0033] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images and the like on a display surface. The function of displaying the information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. It also functions as a touch sensor to detect when something is touching the screen. A rule is one form of input / output device.

[0034] The touch panel is, for example, a display panel (or display device) with a touch sensor, The touch panel can also be called a display panel (or display device) with a touch function. Alternatively, the display panel may have a touch sensor panel. It may also be configured to have a touch sensor function inside or on the surface.

[0035] In addition, in this specification, a touch panel substrate on which a connector or IC is mounted is referred to as a touch panel. , touch panel module, display module, or simply touch panel. be.

[0036] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described. In particular, in this embodiment, as an example of a semiconductor device, a semiconductor layer in which a channel is formed is A transistor including an oxide semiconductor will be described.

[0037] [Configuration example 1] [Configuration Example 1-1] FIG. 1A is a schematic cross-sectional view of a transistor 10 taken along the channel length direction.

[0038] The transistor 10 comprises an insulating layer 103, a semiconductor layer 108, an insulating layer 110, and a metal oxide semiconductor layer. The semiconductor device has a material layer 114 and a conductive layer 112. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode.

[0039] When a conductive film containing a metal or an alloy is used as the conductive layer 112, the electrical resistance can be reduced. Note that the conductive layer 112 may be a conductive film containing oxide.

[0040] The metal oxide layer 114 has a function of supplying oxygen into the insulating layer 110. When a conductive film containing an easily oxidized metal or alloy is used as 112, the metal oxide Layer 114 is a barrier layer that prevents the conductive layer 112 from being oxidized by oxygen in the insulating layer 110. The metal oxide layer 114 may be removed before the conductive layer 112 is formed. By removing the insulating layer 110, the conductive layer 112 and the insulating layer 110 may be in contact with each other.

[0041] The insulating layer 103 is preferably formed of an insulating film containing an oxide. It is preferable to use an oxide film on the portion in contact with the base layer 108.

[0042] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. The semiconductor layer 108 preferably contains at least indium and oxygen. When 108 contains indium oxide, the carrier mobility can be increased. For example, a transistor that can pass a larger current than one that uses amorphous silicon. This can be achieved.

[0043] A region of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region. The semiconductor layer 108 also has a pair of low-resistance regions 108n sandwiching a channel forming region. The low-resistance region 108n is preferably a region having a higher carrier concentration than the channel formation region. These regions function as source and drain regions.

[0044] The low resistance region 108n is a region with a lower resistance and a higher carrier concentration than the channel formation region. The region may be a region with a large amount of oxygen vacancies, a region with a high hydrogen concentration, or a region with a high impurity concentration. I can say that.

[0045] The insulating layer 110 is made up of an insulating film 110a, an insulating film 110b, and an insulating film 110c from the insulating layer 103 side. The insulating film 110a has a laminated structure in which the insulating film 110b and the insulating film 110c are laminated in this order. The insulating film 110c has a region in contact with the channel forming region. The insulating film 110b is located between the insulating film 110a and the insulating film 110c.

[0046] The insulating films 110a, 110b, and 110c are each an insulating film containing oxide. In this case, the insulating film 110a, the insulating film 110b, and the insulating film 110 It is preferable that the films c are formed successively using the same film forming apparatus.

[0047] The insulating films 110a, 110b, and 110c are made of, for example, silicon oxide. silicon oxide film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, oxide Contains one or more of magnesium film, lanthanum oxide film, cerium oxide film, and neodymium oxide film An insulating layer may be used.

[0048] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a stacked structure of oxide insulating films. The insulating layer 110 may have a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 is preferably an insulating film capable of releasing oxygen. For example, the insulating layer 110 may be formed in an oxygen atmosphere. The insulating layer 110 is subjected to a heat treatment or a plasma treatment in an oxygen atmosphere. Oxygen is supplied to the insulating layer 110 by forming an oxide film in an oxygen atmosphere. It is also possible.

[0049] The insulating films 110a, 110b, and 110c are formed by, for example, a sputtering method. Chemical Vapor Deposition (CVD) method, Vacuum evaporation, pulsed laser deposition (PLD) on) method, Atomic Layer Deposition (ALD) method The CVD method can be plasma chemical vapor deposition (P There are ECVD (Plasma Enhanced CVD) and thermal CVD methods.

[0050] In particular, the insulating films 110a, 110b, and 110c are formed by plasma CVD. It is preferable to form the

[0051] Since the insulating film 110a is formed on the semiconductor layer 108, it is necessary to form the insulating film 110a on the semiconductor layer 108 as close to the semiconductor layer 108 as possible. It is preferable that the film is formed under conditions that do not cause damage. For example, the film formation speed (film formation The film can be formed under conditions where the deposition rate (also called deposition rate) is sufficiently low.

[0052] For example, a silicon oxynitride film is formed as the insulating film 110a by plasma CVD. In this case, by forming the semiconductor layer 108 under low power conditions, damage to the semiconductor layer 108 can be minimized. It can be made smaller.

[0053] The deposition gas used to deposit the silicon oxynitride film is, for example, a silicon-containing gas such as silane or disilane. deposition gases including nitrates and oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. In addition to the source gas, argon, helium, Alternatively, a diluent gas such as nitrogen may be included.

[0054] For example, the ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter simply referred to as the flow rate ratio) By reducing the thickness, the deposition rate can be reduced, and a dense film with few defects can be formed. can.

[0055] The insulating film 110b is a film formed under conditions of a higher film formation rate than the insulating film 110a. This makes it possible to improve productivity.

[0056] For example, the insulating film 110b is formed under the condition that the flow rate ratio of the deposition gas is higher than that of the insulating film 110a. By doing so, it is possible to form a film under conditions where the film formation rate is increased.

[0057] The insulating film 110c has reduced defects on its surface and is able to absorb impurities such as water contained in the air. For example, similar to the insulating film 110a, The film can be formed under conditions where the film formation rate is sufficiently low.

[0058] In addition, since the insulating film 110c is formed on the insulating film 110b, it is The insulating film 110c has little effect on the semiconductor layer 108 when it is formed. The insulating film 110c can be deposited under higher power conditions than the insulating film 110a. By reducing the amount ratio and depositing the film at a relatively high power, a dense film with reduced surface defects can be obtained. It is possible.

[0059] That is, the film formation rate of the insulating film 110b is the highest, and the film formation rate of the insulating film 110a and the insulating film 110c is the highest. The insulating layer 110 can be formed using stacked films formed under conditions in which the temperature is lower in this order. The insulating layer 110 is also etched under the same conditions in wet etching or dry etching. The etching rate at this temperature is highest for the insulating film 110b, and The values ​​decrease in order.

[0060] The insulating film 110b is formed thicker than the insulating films 110a and 110c. It is preferable that the insulating film 110b, which has the fastest film-forming rate, is formed thick. The time required for the film formation process can be reduced.

[0061] Here, the boundary between the insulating film 110a and the insulating film 110b, and the boundary between the insulating film 110b and the insulating film 110 The boundaries of c are sometimes unclear, so in Figure 1(A) and other figures, these boundaries are indicated by dashed lines. Since the insulating film 110a and the insulating film 110b have different film densities, Transmission electron microscope (TEM) of the cross section of In microscopy images, these boundaries are identified as differences in contrast. Similarly, the boundary between the insulating film 110b and the insulating film 110c can also be observed. This can sometimes be observed as a difference in contrast.

[0062] Here, the composition of the semiconductor layer 108 will be described. The semiconductor layer 108 is composed of at least an insulator. It is preferable that the semiconductor layer 108 contains a metal oxide containing sodium and oxygen. In addition, the semiconductor layer 108 may contain zinc. stomach.

[0063] The semiconductor layer 108 is typically made of indium oxide or indium zinc oxide (In -Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, IGZO and Indium tin oxide (In-Sn oxide) can also be used. In addition, semiconductors, such as indium tin oxide containing silicon, can also be used. Materials that can be used for the body layer 108 will be described in more detail below.

[0064] The composition of the semiconductor layer 108 has a significant effect on the electrical characteristics and reliability of the transistor 10. For example, increasing the indium content in the semiconductor layer 108 The mobility is improved, and a transistor with high field-effect mobility can be realized.

[0065] Here, one of the indicators for evaluating the reliability of a transistor is the gate voltage when an electric field is applied to the gate. Gate Bias Stress Test (GBT) Among them, there is a test to check the gate potential against the source and drain potentials. A test in which a positive potential is applied and the material is kept at a high temperature is called PBTS (Positive Bias Test). s Temperature Stress) test, with a negative potential applied to the gate, The test held at high temperature is called NBTS (Negative Bias Temperature Test). It is also called the PB Stress test, which is performed under the condition of irradiating light such as white LED light. The TS test and NBTS test were performed using PBTIS (Positive Bias Test Indicator) mperature Illumination Stress) test, NBTIS(N egative Bias Temperature Illumination St This is called a ress test.

[0066] In particular, in an n-type transistor using an oxide semiconductor, When the gate is placed in the state where current flows, a positive potential is applied to the gate. The amount of variation in threshold voltage is one of the important indicators of transistor reliability. This becomes:

[0067] Here, the composition of the semiconductor layer 108 does not contain gallium or has a gallium content of By using a metal oxide film with low resistance, the amount of variation in threshold voltage during PBTS testing is reduced. In addition, when gallium is contained, the composition of the semiconductor layer 108 can be adjusted to include indium. It is preferable to make the gallium content smaller than the gallium content. Therefore, a highly efficient transistor can be realized.

[0068] One of the factors that causes the threshold voltage fluctuation in the PBTS test is the difference between the semiconductor layer and the gate insulating layer. The defect level at or near the interface is one of the causes. The higher the defect level density, the higher the PB Degradation in the TS test becomes significant. Gallium oxide in the area of ​​the semiconductor layer that contacts the gate insulating layer By reducing the content of Zn, it is possible to suppress the generation of the defect levels.

[0069] Gallium-free or low gallium content suppresses PBTS degradation The reason why this can be achieved is considered to be, for example, as follows: Gallium attracts oxygen more easily than other metal elements (e.g., indium and zinc). Therefore, the metal oxide film containing a large amount of gallium and the insulating layer 11 containing oxide are At the interface with the insulating layer 110, gallium combines with excess oxygen in the insulating layer 110, and the carriers It is assumed that this makes it easier to generate trap sites (electrons in this case). When a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer. This may cause the threshold voltage to fluctuate.

[0070] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, the In atoms A metal oxide film having a higher atomic ratio than that of Ga can be applied to the semiconductor layer 108. In addition, a metal oxide film in which the atomic ratio of Zn is higher than the atomic ratio of Ga can be used. In other words, the atomic ratio of the metal elements is In>Ga and Zn>Ga. Preferably, a filling metal oxide film is applied to the semiconductor layer 108 .

[0071] For example, the semiconductor layer 108 may have an atomic ratio of metal elements of In:Ga:Zn=2:1: 3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn =4:2:4.1, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, I n:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=5: A metal oxide film having a ratio of 2:5 or thereabouts can be used.

[0072] When a metal oxide film containing indium and gallium is used as the semiconductor layer 108, The ratio of the number of gallium atoms to the number of atoms of the metal element contained in the metal oxide (atomic ratio) is , greater than 0 and less than 50%, preferably 0.05% or more and 30% or less, more preferably 0. It can be 1% or more and 15% or less, more preferably 0.1% or more and 5% or less. By including gallium in the semiconductor layer 108, oxygen deficiency is less likely to occur. It plays a key role.

[0073] Alternatively, a metal oxide film that does not contain gallium may be used as the semiconductor layer 108. For example, In this case, an In—Zn oxide can be applied to the semiconductor layer 108. In this case, the metal oxide film By increasing the ratio of the number of In atoms to the number of metal element atoms contained in On the other hand, the number of atoms of the metal element contained in the metal oxide can be increased. By increasing the atomic ratio of Zn to SiO, a metal oxide film with high crystallinity can be obtained. Fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved. 8 may be applied to a metal oxide film that does not contain gallium or zinc, such as indium oxide. By using a metal oxide film that does not contain gallium, it is possible to The variation in threshold voltage can be made extremely small.

[0074] The transistor 10 according to one embodiment of the present invention includes a semiconductor layer 108 containing gold with a low gallium content. A metal oxide film containing no gallium or a metal oxide film containing no gallium is applied, and further, a semiconductor layer 10 The insulating film 110a in contact with the upper surface of the semiconductor layer 108 reduces damage to the semiconductor layer 108. Therefore, the boundary between the semiconductor layer 108 and the insulating layer 110 is Therefore, the defect level density in the surface is reduced, and the transistor 10 has high reliability. can.

[0075] Although gallium has been described as a representative example here, the element M (M is , aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium , titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium selected from the group consisting of aluminum, neodymium, hafnium, tantalum, tungsten, and magnesium In particular, M is gallium, aluminum, It is preferable that the metal oxide is one or more selected from the group consisting of yttrium, yttrium, and tin.

[0076] In particular, the semiconductor layer 108 contains a metal oxide in which the atomic ratio of In is higher than the atomic ratio of the element M. It is preferable to apply a film of Zn. It is preferable to apply an oxide film.

[0077] The semiconductor layer 108 is preferably formed using a crystalline metal oxide film. For example, CAAC (c-axis aligned crystal) structure and polycrystalline structure, which will be described later A metal oxide film having a microcrystalline structure or the like can be used. By using the film for the semiconductor layer 108, the defect level density in the semiconductor layer 108 can be reduced, A highly reliable semiconductor device can be realized.

[0078] As the semiconductor layer 108 has higher crystallinity, the density of defect states in the film can be reduced. A transistor that can pass a large current by using a metal oxide film with low crystallinity This can be achieved.

[0079] When forming a metal oxide film by sputtering, the substrate temperature (stage temperature) during film formation The higher the crystallinity, the more highly crystalline the metal oxide film can be formed. The higher the ratio of the flow rate of oxygen gas to the total deposition gas used (also called the oxygen flow rate ratio), the better the deposition efficiency. A highly crystalline metal oxide film can be formed.

[0080] [Configuration Example 1-2] FIG. 1B is a schematic cross-sectional view of the transistor 10A. The main difference compared to the transistor 10 is that the configuration of the semiconductor layer 108 is different.

[0081] The semiconductor layer 108 of the transistor 10A is formed by stacking the semiconductor layer 108 from the insulating layer 103 side. The semiconductor layer 108a and the semiconductor layer 108b are stacked. It is preferable that metal oxide films are used for the layers 108a and 108b.

[0082] For simplicity, the low resistance region of the semiconductor layer 108a and the low resistance region of the semiconductor layer 10 The low resistance region 108n and the low resistance region 8b are collectively referred to as low resistance region 108n, and are indicated by the same hatching pattern. In reality, the composition of the semiconductor layer 108a and the composition of the semiconductor layer 108b are different. Therefore, the electrical resistivity, carrier concentration, oxygen vacancy amount, hydrogen concentration, and the like of the low resistance region 108n are The impurity concentration may differ.

[0083] The semiconductor layer 108b is in contact with the upper surface of the semiconductor layer 108a and the lower surface of the insulating film 110a. The semiconductor layer 108b is made of the same material as that used for the semiconductor layer 108 in the above-described configuration example 1-1. A metal oxide film capable of forming the metal oxide film can be applied.

[0084] On the other hand, the semiconductor layer 108a is a metal oxide having a higher atomic ratio of gallium than the semiconductor layer 108b. A nitride film can be used.

[0085] Gallium has a stronger bond with oxygen than indium, so a high atomic ratio of gallium By using a thin metal oxide film for the semiconductor layer 108a, oxygen vacancies are less likely to be formed. If there are many oxygen vacancies in the conductor layer 108a, the electrical characteristics and reliability of the transistor will be deteriorated. Therefore, the semiconductor layer 108a is preferably made of a gallium atom rather than a gallium atom. By using a metal oxide film with a high molecular weight ratio, it is possible to produce a highly reliable transistor with good electrical properties. It can achieve a current of 10A.

[0086] More specifically, the semiconductor layer 108a is a gold layer containing indium, gallium, and zinc. The atomic ratio of gallium is higher than that of the semiconductor layer 108b. A metal oxide film having a region in which the atomic ratio of sodium is lower than that of the semiconductor layer 108b is preferably used. In other words, the semiconductor layer 108b can be made of a material having a lower conductivity than the semiconductor layer 108a. In comparison, the atomic ratio of indium is high and the atomic ratio of gallium is low. A metal oxide film can be used.

[0087] The semiconductor layer 108a may have a region in which the atomic ratio of zinc is equal to that of the semiconductor layer 108b. or a metal oxide film having a region in which the atomic ratio of zinc is lower than that of the semiconductor layer 108b. It is preferable.

[0088] The semiconductor layer 108a may have an atomic ratio of metal elements of In:Ga:Zn=1: 1:1, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:4, In:Ga: Zn=1:3:6, In:Ga:Zn=2:2:1, or a metal oxide having a ratio of these values ​​in the vicinity A nitride film can be used.

[0089] Typically, the semiconductor layer 108a contains metal elements in an atomic ratio of In:Ga:Zn=1:1: The semiconductor layer 108b is formed by using a metal oxide film having an atomic ratio of I n:Ga:Zn=4:2:3, In:Ga:Zn=5:1:6, or gold in the vicinity of these It is preferable to use a metal oxide film.

[0090] In addition, by using a metal oxide film in which oxygen deficiency is unlikely to occur as the semiconductor layer 108a, This can reduce the deterioration in the NBTIS test described above.

[0091] The transistor 10A shown in FIG. 1B includes a semiconductor layer 108a located on the insulating layer 103 side. By using a metal oxide film with a relatively high gallium content, Furthermore, the semiconductor layer 108b located on the insulating layer 110 side is provided with gallium. By using a metal oxide film with a low gallium content or no gallium content, the semiconductor layer 1 The interface defect density between the silicon dioxide layer 108 and the insulating layer 110 is reduced. This transistor has both extremely high electrical characteristics and extremely high reliability.

[0092] Here, it is preferable to form the semiconductor layer 108b thinner than the semiconductor layer 108a. Even if the semiconductor layer 108b is an extremely thin film, for example, 0.5 nm or more and 10 nm or less, the insulating On the other hand, the density of defects at the interface with the insulating layer 110 can be reduced. By making the body layer 108a relatively thick, a more reliable transistor can be realized. can be done.

[0093] For example, the thickness of the semiconductor layer 108a is 1.5 times or more and 2 times or more the thickness of the semiconductor layer 108b. 0 times or less, preferably 2 times or more and 15 times or less, and more preferably 3 times or more and 10 times or less. The thickness of the semiconductor layer 108b is preferably 0.5 nm or more and 30 nm or less. The thickness is preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 10 nm or less. stomach.

[0094] The semiconductor layer 108a and the semiconductor layer 108b are formed of the above-described crystalline metal oxide film. It is preferable to use a highly crystalline gold film for both the semiconductor layer 108a and the semiconductor layer 108b. Alternatively, a metal oxide film having low crystallinity may be used. The semiconductor layer 108a and the semiconductor layer 108b may have different crystallinity. The semiconductor layer 108a may be a film having higher crystallinity than the semiconductor layer 108b. The semiconductor layer 108a and the semiconductor layer 108b may be a film having higher crystallinity than the semiconductor layer 108a. The crystallinity of the metal oxide film used for 108b is important to ensure the required electrical characteristics and reliability of the transistor. The thickness can be determined based on the properties of the material and the specifications of the film forming apparatus.

[0095] [Configuration Example 1-3] FIG. 2A is a schematic cross-sectional view of the transistor 10B. The transistor 10 differs from the transistor 10 in that the insulating layer 103 has a different structure and the conductive layer 106 is different from the transistor 10. The main difference is that

[0096] The conductive layer 106 is connected to the semiconductor layer 108, the insulating layer 110, and the metal oxide layer 111 via the insulating layer 103. The conductive layer 106 has a region overlapping with the first gate electrode 114 and the conductive layer 112. The insulating layer 103 functions as a first gate insulating layer (also referred to as a back gate electrode). At this time, the conductive layer 112 functions as a second gate electrode, and the insulating layer 110 functions as a second gate electrode. It functions as a gate insulating layer.

[0097] For example, transistor 10B can be configured by applying the same potential to conductive layer 112 and conductive layer 106. This allows a larger current to flow when the transistor is on. The transistor 10B has a threshold voltage control layer in one of the conductive layers 112 and 106. and the other applies a potential for controlling the on and off states of the transistor 10B. You can also give.

[0098] The insulating layer 103 is made up of an insulating film 103a, an insulating film 103b, and an insulating film 103c from the conductive layer 106 side. The insulating film 103a has a laminated structure in which the conductive layer 103c and the insulating film 103d are laminated. 6. The insulating film 103d is in contact with the semiconductor layer .

[0099] The insulating layer 103 functioning as the second gate insulating layer has a high withstand voltage and a small film stress. The conductive layer 106 has a low resistance to hydrogen and water release, has few defects in the film, and It is preferable to satisfy one or more of the above requirements, and to suppress the diffusion of metal elements. It is most preferable to satisfy

[0100] Among the four insulating films included in the insulating layer 103, the insulating film 103a located on the conductive layer 106 side The insulating films 103b and 103c are preferably insulating films containing nitrogen. On the other hand, an insulating film containing oxygen may be used for the insulating film 103d in contact with the semiconductor layer 108. Furthermore, the four insulating films of the insulating layer 103 are each formed by a plasma CVD apparatus. It is preferable to use a film forming method in which films are continuously formed without being exposed to the atmosphere.

[0101] The insulating films 103a, 103b, and 103c are made of, for example, silicon nitride. Nitrogen-containing insulating films such as silicon nitride oxide films, aluminum nitride films, and hafnium nitride films The insulating film 103c may be a film that can be used for the insulating layer 110. An insulating film that can be used can be used.

[0102] The insulating films 103a and 103c can prevent impurities from diffusing from below. The insulating film 103a is preferably a dense film. The insulating film 103c can block the hydrogen and water contained in the insulating film 103b. Therefore, the insulating film 103a and the insulating film 103c are preferably made of a material other than the insulating film 103a. An insulating film formed under conditions with a lower film formation rate than 03b can be applied.

[0103] On the other hand, the insulating film 103b is formed under conditions of low stress and high film formation speed. In addition, the insulating film 103b is preferably thicker than the insulating films 103a and 103c. It is preferable that the thickness of the insulating layer 14 is also large.

[0104] For example, the insulating film 103a, the insulating film 103b, and the insulating film 103c are each subjected to plasma When a silicon nitride film formed by CVD is used, the insulating film 103b is thicker than the other two insulating films. Therefore, the film density is lower than that of the insulating layer 103. In microscopic images, these can be observed as differences in contrast, and can sometimes be distinguished. The boundary between the insulating film 103a and the insulating film 103b, and the boundary between the insulating film 103b and the insulating film 103 The boundaries of c may be unclear, so in Figure 2(A) and other figures, these boundaries are indicated by dashed lines. is doing.

[0105] The insulating film 103d in contact with the semiconductor layer 108 has a surface on which impurities such as water are adsorbed. It is preferable to make a dense insulating film that is resistant to water and hydrogen. For example, the insulating film 103d may be Therefore, an insulating film similar to the insulating film 110c of the insulating layer 110 can be used.

[0106] The conductive layer 106 is made of a metal film or an alloy whose constituent elements are unlikely to diffuse into the insulating layer 103. In the case where a film is used, the insulating film 103a is not provided, and the insulating film 103b and the insulating film 103c are provided. , and the insulating film 103d may be stacked.

[0107] The insulating layer 103 having such a stacked structure makes it possible to realize a highly reliable transistor. It can be realized.

[0108] [Configuration Example 1-4] FIG. 2B is a schematic cross-sectional view of the transistor 10C. The transistor 10A illustrated in Configuration Example 1-2 is replaced with the transistor illustrated in Configuration Example 1-3. This is an example in which the conductive layer 106 and insulating layer 103 shown in FIG. 10B are applied.

[0109] By adopting such a configuration, a transistor with good electrical characteristics and extremely high reliability can be obtained. This can be realized.

[0110] [Configuration example 2] A more specific example of the configuration of a transistor will be described below.

[0111] [Configuration Example 2-1] 3A is a top view of the transistor 100, and FIG. 3B is a top view of the transistor 100 shown in FIG. 3(C) corresponds to a cross-sectional view taken along the dashed line A1-A2 shown in FIG. 3(A). It corresponds to a cross-sectional view of the cut surface taken along the dashed line B1-B2. Some of the components of the transistor 100 (such as the gate insulating layer) are omitted in the illustration. The dashed line A1-A2 direction is the channel length direction, and the dashed line B1-B2 direction is the channel width direction. In addition, the top view of the transistor will be the same as that of FIG. Similarly, some of the components are omitted in the drawings.

[0112] The transistor 100 is provided on a substrate 102, an insulating layer 103, a semiconductor layer 108, an insulating layer 109, a semiconductor layer 109a, and a semiconductor layer 109b. The semiconductor device includes an edge layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 118, etc. The dielectric layer 108 is provided on the insulating layer 103. The insulating layer 110 is provided on the upper surface of the insulating layer 103, The metal oxide layer 114 and the conductive layer 115 are provided in contact with the upper surface and side surfaces of the semiconductor layer 108. The layer 112 is stacked in this order on the insulating layer 110, and the portion overlapping with the semiconductor layer 108 is The insulating layer 118 is formed on the top surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the conductive layer 116. The conductive layer 112 is provided to cover the upper surface of the conductive layer 112 .

[0113] The insulating layer 103 is made up of an insulating film 103a, an insulating film 103b, and an insulating film 103c from the substrate 102 side. The insulating layer 110 has a laminated structure in which a semiconductor The insulating film 110a, the insulating film 110b, and the insulating film 110c are stacked from the layer 108 side. It has a layered structure.

[0114] As shown in FIGS. 3A and 3B, the transistor 100 includes an insulating layer 118 The conductive layer 120a and the conductive layer 120b may be disposed on the conductive layer 120a. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. The openings 141a and 120b are formed in the insulating layer 118 and the insulating layer 110, respectively. is electrically connected to the low resistance region 108n through the opening 141b.

[0115] A portion of the conductive layer 112 functions as a gate electrode. A portion of the insulating layer 110 functions as a gate insulator. The transistor 100 has a gate electrode provided on the semiconductor layer 108. It is a so-called top-gate transistor.

[0116] The conductive layer 112 and the metal oxide layer 114 are processed so that their top surface shapes roughly match each other. It has been done.

[0117] In this specification, the phrase "the upper surface shapes are roughly the same" means that there is at least a small difference between the layers. For example, the upper and lower layers may have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where part of the surface is processed using the same mask pattern. The shells do not overlap, and the upper layer is sometimes located inside the lower layer, and sometimes the upper layer is sometimes located outside the lower layer. In this case too, it is said that "the top surface shapes roughly match."

[0118] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is It functions as a barrier film that prevents oxygen contained therein from diffusing toward the conductive layer 112. The metal oxide layer 114 is formed by diffusing hydrogen and water contained in the conductive layer 112 to the insulating layer 110 side. The metal oxide layer 114 also functions as a barrier film to prevent, for example, at least the insulating layer 11 It is preferable to use a material that is less permeable to oxygen and hydrogen than 0.

[0119] The metal oxide layer 114 allows the conductive layer 112 to easily absorb oxygen, such as aluminum or copper. Even if a thin metal material is used, oxygen does not diffuse from the insulating layer 110 to the conductive layer 112. Even when the conductive layer 112 contains hydrogen, the conductive layer 112 Therefore, it is possible to prevent hydrogen from diffusing into the semiconductor layer 108 via the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It is possible.

[0120] The metal oxide layer 114 can be made of an insulating material or a conductive material. If the metal oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. If the metal oxide layer 114 is conductive, it functions as a part of the gate electrode.

[0121] The metal oxide layer 114 is made of an insulating material having a higher dielectric constant than silicon oxide. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable. It is preferable to use a film such as a PET film, since the driving voltage can be reduced.

[0122] The metal oxide layer 114 may be, for example, indium oxide or indium tin oxide (ITO). or silicon-containing indium tin oxide (ITSO), In particular, conductive oxides containing indium are preferred because of their high conductivity. .

[0123] The metal oxide layer 114 may be an oxide material containing one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use the same type of metal oxide layer 114 as the semiconductor layer 108. By applying metal oxide films formed using sputtering targets, equipment can be standardized. This is preferable because it can

[0124] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering device, it is formed in an atmosphere containing oxygen gas. This allows oxygen to be suitably added to the insulating layer 110 and the semiconductor layer 108.

[0125] The semiconductor layer 108 has a region overlapping with the conductive layer 112 and a pair of low-resistance regions sandwiching the region. The region of the semiconductor layer 108 that overlaps with the conductive layer 112 is the region of the transistor 1 On the other hand, the pair of low resistance regions 108n function as a channel forming region of the transistor. These serve as the source and drain regions of the gate electrode 100.

[0126] The low resistance region 108n is a region having a lower resistance and a higher carrier concentration than the channel formation region. High oxygen vacancy density regions, high impurity concentration regions, or n-type regions. It can be said that.

[0127] The low-resistance region 108n of the semiconductor layer 108 is a region containing an impurity element. Examples of elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and aluminum. Typical examples of rare gases include helium and neon. , argon, krypton, and xenon. In particular, they may contain boron or phosphorus. It is preferable that two or more of these elements are contained.

[0128] As will be described later, the process of doping the low resistance region 108n with impurities is performed by masking the conductive layer 112. As a barrier, the insulating layer 110 can be interposed therebetween.

[0129] The low resistance region 108n has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×1 0 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5x 10 22 atoms / cm 3Less than 1×10, more preferably 20 atoms / cm 3 End , 1×10 22 atoms / cm 3 It is preferred to include a region in which:

[0130] The concentration of impurities contained in the low resistance region 108n can be measured by, for example, secondary ion mass spectrometry (SIM) Secondary Ion Mass Spectrometry (S) and X-ray photoelectron X-ray Photoelectron Spectroscopy (XPS) When XPS analysis is used, the surface side or By combining ion sputtering from the backside and XPS analysis, the concentration in the depth direction was You can find out the degree distribution.

[0131] In addition, in the low resistance region 108n, the impurity element is present in an oxidized state. For example, boron, phosphorus, magnesium, aluminum, and silicon are used as impurity elements. It is preferable to use an element that is easily oxidized, such as silicon. Since the oxidized state of the fluorine-containing compound can be stably present by bonding with oxygen in the semiconductor layer 108, it can be easily oxidized in the subsequent process. When exposed to high temperatures (for example, above 400°C, above 600°C, or above 800°C) Even if there is an impurity element, the desorption is suppressed. As a result, many oxygen vacancies are generated in the low resistance region 108n. The low resistance region 108n has an extremely low resistance. It becomes an anti-state.

[0132] For example, when boron is used as the impurity element, the boron contained in the low resistance region 108n This is evident from the XPS analysis, where the B2O3 bond is This can be confirmed by observing the spectral peaks caused by the SiO2. Spectral peaks due to the existence of elemental boron are not observed or are not measurable. The peak intensity is so low that it is buried in the background noise observed near the lower limit of the and becomes smaller.

[0133] The insulating layer 110 is formed in a region in contact with the channel forming region of the semiconductor layer 108, i.e., the conductive layer 1 The insulating layer 110 has a region overlapping with the low resistance region 10 of the semiconductor layer 108. The conductive layer 112 has a region that is in contact with the conductive layer 8n and does not overlap with the conductive layer 112.

[0134] The region of the insulating layer 110 that overlaps with the low-resistance region 108n contains the above-described impurity element. At this time, the impurity elements in the insulating layer 110 may be present in the same manner as in the low-resistance region 108n. It is preferable that such easily oxidized elements exist in a state bonded with oxygen. Since it can bond with oxygen in the layer 110 and exist stably in an oxidized state, it can be easily used in a later process at high temperatures. In particular, the insulating layer 110 is prevented from being desorbed even when heated. When oxygen that can be separated (also called excess oxygen) is contained, the excess oxygen and the impurity element Oxygen is supplied from the insulating layer 110 to the low resistance region 108n to bond and stabilize it. In addition, the part of the insulating layer 110 containing the impurity element in an oxidized state can be suppressed. Since the portion is in a state where oxygen is difficult to diffuse, the insulating layer 110 is Oxygen is prevented from being supplied to the low resistance region 108n via the low resistance region 108n. It is also possible to prevent the resistance of the capacitor from increasing.

[0135] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, inorganic insulating materials such as oxides or nitrides can be used. Specific examples include silicon oxide, silicon oxynitride, silicon nitride, and silicon nitride oxide. , aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium An inorganic insulating material such as ammonium aluminate can be used.

[0136] [Configuration Example 2-2] 4A is a top view of the transistor 100A, and FIG. 4B is a top view of the transistor 100B. 4(C) is a cross-sectional view of the channel length direction of the transistor 100A, and FIG. 4(D) is a cross-sectional view of the channel width direction of the transistor 100A. 1 is a cross-sectional view in the direction of the arrow.

[0137] The transistor 100A has a conductive layer 106 between a substrate 102 and an insulating layer 103. The main difference from the configuration example 2-1 is that the conductive layer 106 is made of the semiconductor layer 108 and the conductive layer 112. It has an overlapping area with.

[0138] In the transistor 100A, the conductive layer 112 is a second gate electrode (top gate electrode). The conductive layer 106 functions as a first gate electrode (also called a bottom gate electrode). A part of the insulating layer 110 functions as a second gate insulating layer. A part of the insulating layer 103 functions as a first gate insulating layer.

[0139] The portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 is It functions as a channel formation region. For ease of explanation, the semiconductor layer 108 The portion overlapping with the conductive layer 112 is sometimes called a channel forming region. The portion that does not overlap with the conductive layer 102 but overlaps with the conductive layer 106 (the portion including the low resistance region 108n) is also A channel can be formed.

[0140] As shown in FIG. 4C, the conductive layer 106 is formed by a metal oxide layer 114 and an insulating layer 110. and electrically connected to the conductive layer 112 through an opening 142 provided in the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to be given the same potential. can be done.

[0141] The conductive layer 106 is made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, when a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. This is preferable because it can be done easily.

[0142] As shown in FIGS. 4A and 4C, the conductive layer 11 2 and the conductive layer 106 preferably protrude outward beyond the edge of the semiconductor layer 108. At this time, as shown in FIG. 4(C), the entire semiconductor layer 108 in the channel width direction is insulated. The structure is such that the layer 110 and the insulating layer 103 are interposed between the conductive layer 112 and the conductive layer 106 .

[0143] With this configuration, the semiconductor layer 108 is subjected to an electric field generated by the pair of gate electrodes. In this case, the conductive layer 106 and the conductive layer 112 are electrically surrounded by the same material. It is preferable to apply a potential to the semiconductor layer 108. This induces a channel in the semiconductor layer 108. Since the electric field can be effectively applied, the on-current of the transistor 100A can be increased. This also makes it possible to miniaturize the transistor 100A.

[0144] The conductive layer 112 and the conductive layer 106 may not be connected to each other. A constant potential is applied to one of the gate electrodes of the transistor 100A, and a signal for driving the transistor 100A is applied to the other gate electrode. At this time, the potential applied to one of the gate electrodes of the transistor 100 It is also possible to control the threshold voltage when A is driven by the other gate electrode.

[0145] [Configuration Example 2-3] 5A is a top view of the transistor 100B, and FIG. 5B is a top view of the transistor 100C. 5(C) is a cross-sectional view of the transistor 100B in the channel length direction, and FIG. 5(D) is a cross-sectional view of the transistor 100B in the channel width direction. 1 is a cross-sectional view in the direction of the arrow.

[0146] The transistor 100B has an insulating property in comparison with the transistor 100 illustrated in Configuration Example 2-1. The main differences are the different configuration of the edge layer 110 and the presence of the insulating layer 116 .

[0147] The insulating layer 110 is formed so that the top surface shape thereof roughly matches that of the conductive layer 112 and the metal oxide layer 114. The insulating layer 110 is formed by processing, for example, a conductive layer 112 and a metal oxide layer 114. The insulating film can be formed by processing the insulating film using a resist mask.

[0148] The insulating layer 116 is formed by insulating the conductive layer 112, the metal oxide layer 114, and the insulating layer 116 of the semiconductor layer 108. The insulating layer 116 is provided in contact with the upper surface and side surfaces that are not covered by the insulating layer 10. The top surface of the layer 103, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the side surface of the conductive layer 112 It is provided to cover the top and sides.

[0149] The insulating layer 116 has a function of lowering the resistance of the low-resistance region 108n. The insulating layer 116 is formed by heating during or after the formation of the insulating layer 116. An insulating film capable of supplying impurities into the region 108n can be used. By heating the insulating layer 116 during or after its formation, an oxide is formed in the low resistance region 108n. An insulating film capable of generating electron vacancies can be used.

[0150] For example, the insulating layer 116 may function as a source of impurities to the low resistance region 108n. In this case, the insulating layer 116 can be formed of an insulating film that can release hydrogen by heating. It is preferable that such an insulating layer 116 is formed in contact with the semiconductor layer 108. By this, impurities such as hydrogen are supplied to the low resistance region 108n, and the low resistance region 108n is made low resistance. It can be made resistant.

[0151] The insulating layer 116 is formed by using a deposition gas containing an impurity element such as a hydrogen element. In addition, the insulating layer 116 is preferably formed at a high temperature. Therefore, a large amount of impurity elements can be effectively supplied to the semiconductor layer 108. The film formation temperature is, for example, 200°C or higher and 500°C or lower, preferably 220°C or higher and 450°C or lower. °C or less, and more preferably 250°C or more and 400°C or less.

[0152] In addition, the insulating layer 116 is formed under reduced pressure and by heating, so that the insulating layer 116 is This can promote the desorption of oxygen from the region that will become the low-resistance region 108n. By supplying impurities such as hydrogen to the semiconductor layer 108 formed in the low resistance region 108, The carrier density in n increases, and the resistance of the low-resistance region 108n can be more effectively reduced. can.

[0153] The insulating layer 116 may be made of, for example, silicon nitride, silicon nitride oxide, or silicon oxide nitride. An insulating film containing a nitride, such as aluminum nitride or aluminum nitride oxide, is preferably used. In particular, silicon nitride has blocking properties against hydrogen and oxygen, Preventing both the diffusion of hydrogen from the outside into the semiconductor layer and the desorption of oxygen from the semiconductor layer to the outside This makes it possible to realize a highly reliable transistor.

[0154] The insulating layer 116 also has the function of absorbing oxygen in the semiconductor layer 108 and generating oxygen vacancies. In particular, the insulating layer 116 may be made of a metal such as aluminum nitride. It is particularly preferred to use metal nitrides.

[0155] When metal nitrides are used, aluminum, titanium, tantalum, tungsten, It is preferable to use nitrides of chromium or ruthenium. In particular, nitrides of aluminum or titanium are used. For example, when aluminum is used as a sputtering target, The nitride film was formed by reactive sputtering using a gas containing nitrogen as the deposition gas. By appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of deposition gas, the aluminum film can be formed with extremely The film has exceptionally high insulating properties and extremely high blocking properties against hydrogen and oxygen. Therefore, an insulating film containing such a metal nitride is provided in contact with a semiconductor layer. By doing so, not only can the resistance of the semiconductor layer be reduced, but oxygen is also released from the semiconductor layer. Furthermore, hydrogen can be suitably prevented from diffusing into the semiconductor layer.

[0156] When aluminum nitride is used as the metal nitride, the insulating material containing the aluminum nitride It is preferable that the thickness of the layer is 5 nm or more. Even with such a thin film, hydrogen and oxygen This allows for both high blocking properties against elements and the function of reducing the resistance of the semiconductor layer. The thickness of the insulating layer may be any thickness, but in consideration of productivity, it is preferably 500 nm or less. is preferably 200 nm or less, more preferably 50 nm or less.

[0157] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x (x is greater than 0 (x is a real number of 2 or less, preferably, x is a real number of 0.5 or more and 1.5 or less) This makes it possible to obtain a film having excellent insulating properties and excellent thermal conductivity. This allows for improved dissipation of heat generated when the transistor 100B is driven. Cut.

[0158] Alternatively, an aluminum titanium nitride film, a titanium nitride film, or the like is used as the insulating layer 116. It is possible.

[0159] By providing such an insulating layer 116 in contact with the low resistance region 108n, the insulating layer 116 Oxygen in the low resistance region 108n is absorbed to form oxygen vacancies in the low resistance region 108n. Furthermore, after forming such an insulating layer 116, a heat treatment can be performed to obtain a low resistance insulating layer. A large number of oxygen vacancies can be formed in the resistive region 108n, which can promote low resistance. In addition, when a film containing a metal oxide is used for the insulating layer 116, the insulating layer 116 can be formed as a semiconductor. As a result of absorbing oxygen in the layer 108, an insulating layer is formed between the insulating layer 116 and the low resistance region 108n. In some cases, a layer containing an oxide of a metal element (e.g., aluminum) contained in 116 is formed. be.

[0160] Here, when a metal oxide film containing indium is used as the semiconductor layer 108, a low resistance A region where indium oxide is precipitated near the interface of the region 108n on the insulating layer 116 side, or In some cases, regions with high indium concentration are formed. This results in extremely low resistance. A resistive region 108n can be formed. The presence of such a region can be used, for example, for X-ray photodetection. X-ray Photoelectron Spectroscopy (XPS) It may be possible to observe this using analytical methods such as

[0161] [Configuration Example 2-4] 6A is a top view of the transistor 100C, and FIG. 6B is a top view of the transistor 100C. 6(C) is a cross-sectional view of the transistor 100C in the channel length direction, and FIG. 6(D) is a cross-sectional view of the transistor 100C in the channel width direction. 1 is a cross-sectional view in the direction of the arrow.

[0162] The transistor 100C is a transistor 100B illustrated in Configuration Example 2-3. This is an example in which a conductive layer 106 functioning as a first gate electrode is provided, as illustrated in FIG. .

[0163] With such a structure, a transistor with high on-state current can be obtained. can be a transistor whose threshold voltage can be controlled.

[0164] [Modification 1 of Configuration Example 2] In the above-described configuration examples 2-1 to 2-4, the semiconductor layer 108 is shown as a single layer. The layer 108 preferably has a laminated structure in which a semiconductor layer 108a and a semiconductor layer 108b are laminated. I wish.

[0165] The transistor 100_a shown in FIG. 7A is the same as the transistor 100_a illustrated in Configuration Example 2-1. 7A is an example in which the semiconductor layer 108 of FIG. The cross section in the channel length direction is shown on the left side, and the cross section in the channel width direction is shown on the right side. do.

[0166] Similarly, the transistor 100A_a shown in FIG. 7B and the transistor 100B_a shown in FIG. 7(D) are transistors 100B_a and 100C_a shown in FIG. The semiconductor layer 108 of the transistor 100A, the transistor 100B, or the transistor 100C is This is an example of a laminated structure.

[0167] [Modification 2 of Configuration Example 2] As described above, the metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 is After oxygen is supplied to the insulating layer 110, it can also be removed.

[0168] The transistor 100_b shown in FIG. 8A is the same as the transistor 100 illustrated in FIG. 0_a, where the metal oxide layer 114 is removed.

[0169] Similarly, the transistor 100A_b shown in FIG. 8B and the transistor 100A_b shown in FIG. 8(D) are transistors 100B_b and 100C_b shown in FIG. In the transistor 100A_a, the transistor 100B_a, or the transistor 100C_a 10, this is an example in which the metal oxide layer 114 has been removed.

[0170] [Production method example 1] An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below. The transistor 100A illustrated in Configuration Example 2-2 will be used as an example for explanation.

[0171] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device are formed by sputtering. Chemical Vapor Deposition (CVD) method , vacuum evaporation, pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method The CVD method can be a plasma chemical vapor deposition (PE CVD (Plasma Enhanced CVD) and thermal CVD. One of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD). There is a method called ic CVD.

[0172] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray application, inkjet, dispensing, screen printing, offset Printing, doctor knife, slit coating, roll coating, curtain coating, knife coating It can be formed by the following methods.

[0173] Furthermore, when processing the thin films that make up the semiconductor device, photolithography and other methods are used. Other methods include nanoimprinting, sandblasting, and lift-off. The thin film may be processed by a method such as a masking method. The island-shaped thin film may be directly formed by the film method.

[0174] There are two typical photolithography methods: A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the photomask after forming a photosensitive thin film. Then, the thin film is processed into a desired shape by performing development.

[0175] In photolithography, the light used for exposure is, for example, i-line (wavelength 365 nm), It uses g-ray (wavelength 436 nm), h-ray (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may also be performed by immersion exposure. Using extreme ultraviolet (EUV) light and X-rays, Also, instead of light used for exposure, an electron beam can be used. The use of light, X-rays or electron beams is preferred because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask It is unnecessary.

[0176] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as these can be used.

[0177] 9A to 11B show the steps of manufacturing the transistor 100A. The cross sections in the channel length direction and the channel width direction are shown side by side.

[0178] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a gate electrode. A functional conductive layer 106 is formed (FIG. 9(A)).

[0179] At this time, as shown in FIG. 9(A), the edge of the conductive layer 106 is pressed so as to have a tapered shape. This improves the step coverage of the insulating layer 103 to be formed next. This can be done.

[0180] In addition, by using a conductive film containing copper as the conductive film to be the conductive layer 106, the wiring resistance can be reduced. For example, when applied to a large display device or a high-resolution display device, In this case, it is preferable to use a conductive film containing copper. Even when a conductive film containing copper is used, the insulating layer 103 prevents copper from diffusing to the semiconductor layer 108 side. Since this suppresses the occurrence of the problem, a highly reliable transistor can be realized.

[0181] [Formation of insulating layer 103] Subsequently, the insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 9(B) The insulating layer 103 is formed by using a PECVD method, an ALD method, a sputtering method, or the like. It is possible.

[0182] Here, the insulating layer 103 includes an insulating film 103a, an insulating film 103b, an insulating film 103c, and an insulating film 103d are formed by laminating them.

[0183] In particular, it is preferable that each insulating film constituting the insulating layer 103 be formed by the PECVD method. The insulating layer 103 can be formed by the same method as described in the above-mentioned Configuration Example 1.

[0184] After the insulating layer 103 is formed, a treatment for supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere can be performed. Alternatively, oxygen is supplied to the insulating layer 103 by plasma ion doping or ion implantation. That's fine.

[0185] [Formation of Semiconductor Layer 108] Subsequently, a metal oxide film 108f is formed on the insulating layer 103 (FIG. 9(C)).

[0186] The metal oxide film 108f is formed by a sputtering method using a metal oxide target. It is preferable to do so.

[0187] It is preferable that the metal oxide film 108f be a dense film with as few defects as possible. In addition, the metal oxide film 108f is a high-purity film in which impurities such as hydrogen and water are reduced as much as possible. In particular, it is preferable that the metal oxide film 108f is a crystalline metal oxide. It is preferred to use a membrane.

[0188] In addition, when forming a metal oxide film, oxygen gas and an inert gas (e.g., helium gas) are used. The metal oxide film may be formed by mixing the gas with a gas such as argon gas or xenon gas. The higher the ratio of oxygen gas to the total deposition gas (hereinafter referred to as the oxygen flow ratio), This makes it possible to improve the crystallinity of the metal oxide film, thereby realizing a highly reliable transistor. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. It may be a transistor.

[0189] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and the denser the metal oxide film. On the other hand, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the metal. It may be an oxide film.

[0190] The conditions for forming the metal oxide film are that the substrate temperature is between room temperature and 250° C., preferably between room temperature and 250° C. The substrate temperature may be set to a temperature of from room temperature to 140°C. For example, it is preferable to set the substrate temperature to be equal to or higher than room temperature and lower than 140° C., as this increases productivity. The metal oxide film is formed at room temperature or without any intentional heating. This allows the crystallinity to be reduced.

[0191] In addition, before the metal oxide film 108f is formed, water and hydrogen adsorbed on the surface of the insulating layer 103 are removed. Among the treatments for removing organic substances and the like and the treatment for supplying oxygen into the insulating layer 103, For example, it is preferable to carry out at least one of the following: Alternatively, a plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, treatment may be carried out under an atmosphere containing an oxidizing gas such as nitrous oxide (NO). Oxygen may be supplied to the insulating layer 103 by plasma treatment using nitrous oxide gas. When the plasma treatment containing oxygen is performed, organic substances on the surface of the insulating layer 103 are suitably removed. After such treatment, the surface of the insulating layer 103 is exposed to the atmosphere. It is preferable to deposit the metal oxide film 108f continuously without forming the second metal oxide film 108a.

[0192] In addition, when the semiconductor layer 108 has a laminated structure in which a plurality of semiconductor layers are laminated, After forming the metal oxide film on the surface, the next It is preferable to form a metal oxide film.

[0193] Subsequently, a part of the metal oxide film 108f is etched to form the island-shaped semiconductor layer 1 Form 08 (Figure 9(D)).

[0194] The metal oxide film 108f can be processed by wet etching or dry etching. In this case, an insulating layer that does not overlap with the semiconductor layer 108 may be used. A part of the insulating layer 103 may be etched and thinned. In some cases, the insulating film 103d is removed by etching, and the surface of the insulating film 103c is exposed. .

[0195] Here, after the metal oxide film 108f is formed or processed into the semiconductor layer 108, heating is performed. By the heat treatment, the metal oxide film 108f or the semiconductor layer 10 It is possible to remove hydrogen or water contained in the catalyst or adsorbed on the surface. The heat treatment improves the film quality of the metal oxide film 108f or the semiconductor layer 108 (for example, This may result in reduced defects, improved crystallinity, etc.

[0196] Furthermore, the metal oxide film 108f or the semiconductor layer 103 is removed by the heat treatment. Oxygen can be supplied to the semiconductor layer 8. In this case, heat treatment is performed before processing into the semiconductor layer 108. It is more preferable to do so.

[0197] The temperature of the heat treatment is typically 150°C or higher but lower than the distortion point of the substrate, or 200°C or higher but lower than the distortion point of the substrate. 00℃ or less, or 250℃ to 450℃ or 300℃ to 450℃ It is possible.

[0198] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After heating in an atmosphere containing oxygen, the material may be heated in a dry air atmosphere. It is preferable that the atmosphere for the heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment is preferably carried out in an electric furnace or an RTA (Rapid Thermal Annealing) furnace. By using an RTA device, the heating time can be shortened. It is possible.

[0199] If the heat treatment is unnecessary, it may not be performed. It may be used in combination with the heat treatment to be carried out in a later step. In some cases, the heat treatment may be performed in a process such as a film formation process.

[0200] [Formation of insulating layer 110] Subsequently, the insulating layer 110 is formed to cover the insulating layer 103 and the semiconductor layer 108 (FIG. 9( E)).

[0201] Here, the insulating layer 110 includes an insulating film 110a, an insulating film 110b, and an insulating film 110c. c is laminated to form a

[0202] In particular, it is preferable that each insulating film constituting the insulating layer 110 be formed by the PECVD method. The method of forming each layer constituting the insulating layer 110 can be the same as that of the first configuration example. This can be done.

[0203] Furthermore, before the insulating layer 110 is formed, the surface of the semiconductor layer 108 is subjected to plasma treatment. By the plasma treatment, impurities such as water adsorbed on the surface of the semiconductor layer 108 are removed. Therefore, the impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced. Since the impurities in the semiconductor layer 1 can be reduced, a highly reliable transistor can be realized. The surface of the semiconductor layer 108 is exposed to the air during the period from the formation of the semiconductor layer 108 to the formation of the insulating layer 110. In some cases, plasma treatment is suitable. For example, oxygen, ozone, nitrogen, nitrous oxide, The plasma treatment and the formation of the insulating layer 110 can be carried out under an atmosphere of argon or the like. The film is preferably formed continuously without being exposed to the atmosphere.

[0204] Here, it is preferable to perform heat treatment after the insulating layer 110 is formed. This makes it possible to remove hydrogen or water contained in the insulating layer 110 or adsorbed on the surface. In addition, defects in the insulating layer 110 can be reduced.

[0205] The conditions for the heat treatment may be as described above.

[0206] If the heat treatment is unnecessary, it may not be performed. It may be used in combination with the heat treatment to be carried out in a later step. In some cases, the heat treatment may be performed in a process such as a film formation process.

[0207] [Formation of Metal Oxide Film 114f] Subsequently, a metal oxide film 114f is formed on the insulating layer 110 (FIG. 10(A)).

[0208] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. It is preferable to form the film by sputtering in an atmosphere containing oxygen. Oxygen can be supplied to the insulating layer 110 when the metal oxide film 114f is formed.

[0209] The metal oxide film 114f is formed by an oxide film containing the same metal oxide as that of the semiconductor layer 108. When forming the film by a sputtering method using a target, the above description is applicable. can be done.

[0210] For example, the metal oxide film 114f is formed under the following conditions: oxygen is used as the film-forming gas; The metal oxide film may be formed by reactive sputtering using a metal target. When aluminum is used as the base, an aluminum oxide film is formed. can be done.

[0211] When forming the metal oxide film 114f, the total flow rate of the film forming gas introduced into the film forming chamber of the film forming apparatus is The higher the oxygen flow rate ratio to the total oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the greater the insulating layer 1 The oxygen supplied in the 10 can be increased. The oxygen flow ratio or oxygen partial pressure can be increased, for example, to 5 0% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 100% or less, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure in the film formation chamber as close to 100% as possible.

[0212] In this way, the metal oxide film 114f is formed by sputtering in an atmosphere containing oxygen. By forming the metal oxide film 114f, oxygen is supplied to the insulating layer 110. In addition, it is possible to prevent oxygen from being released from the insulating layer 110. 10 can trap an extremely large amount of oxygen.

[0213] After the metal oxide film 114f is formed, heat treatment is preferably performed. The oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108. By heating the insulating layer 110 with the insulating layer 114f covering it, the oxide is released from the insulating layer 110 to the outside. This prevents oxygen from being released from the semiconductor layer 108, and allows a large amount of oxygen to be supplied to the semiconductor layer 108. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0214] The conditions for the heat treatment may be as described above.

[0215] If the heat treatment is unnecessary, it may not be performed. It may be used in combination with the heat treatment to be carried out in a later step. In some cases, the heat treatment may be performed in a process such as a film formation process.

[0216] After the metal oxide film 114f is formed or after the heat treatment, the metal oxide film 114 f may be removed.

[0217] [Formation of opening 142] Subsequently, the metal oxide film 114f, the insulating layer 110, and a part of the insulating layer 103 are etched. By this, an opening 142 reaching the conductive layer 106 is formed (FIG. 10(B)). The conductive layer 106 and the conductive layer 112 to be formed later are electrically connected through the opening 142. It can continue.

[0218] [Formation of Conductive Layer 112 and Metal Oxide Layer 114] Subsequently, a conductive film 112f that will become the conductive layer 112 is formed on the metal oxide film 114f ( Figure 10(C)).

[0219] The conductive film 112f is preferably made of a low-resistance metal or alloy material. The conductive film 112f is made of a material that does not easily release hydrogen and from which hydrogen does not easily diffuse. It is preferable to use a material that is not easily oxidized as the conductive film 112f. is preferred.

[0220] For example, the conductive film 112f is formed by sputtering using a sputtering target containing a metal or an alloy. It is preferable to form the film by sputtering.

[0221] For example, the conductive film 112f may be a conductive film that is resistant to oxidation and hydrogen diffusion, and a low-resistance It is preferable to form a laminated film by laminating a conductive film having a conductive layer.

[0222] Subsequently, the conductive film 112f and the metal oxide film 114f are partially etched to form the conductive film 112f. The conductive layer 112 and the metal oxide layer 114 are formed. It is preferable to process each of the layers f using the same resist mask. The conductive layer 112 after etching is used as a hard mask to etch the metal oxide film 114f. That's fine.

[0223] The conductive film 112f and the metal oxide film 114f are etched by wet etching in particular. It is preferable to use the rubbing method.

[0224] This forms the conductive layer 112 and the metal oxide layer 114 whose top surface shapes are roughly the same. It is possible.

[0225] In this way, the top and side surfaces of the semiconductor layer 108 and the insulating layer 110 are removed without etching. By using a structure in which the insulating layer 103 covers the semiconductor layer 112f, etc., the semiconductor layer 112f is not etched during etching. This can prevent the dielectric layer 108 and the insulating layer 103 from being partially etched and thinned. .

[0226] [Fueling of impurity elements] Next, the conductive layer 112 is used as a mask to implant impurities into the semiconductor layer 108 through the insulating layer 110. A process of supplying (also called adding or injecting) the element 140 is carried out (FIG. 10(D)). As a result, a low resistance region 108n is formed in the region of the semiconductor layer 108 that is not covered with the conductive layer 112. At this time, the conductive layer 112 is formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 112. The impurity element 140 is not supplied because the mask 112 serves as a mask.

[0227] The impurity element 140 is preferably supplied by plasma ion doping or ion implantation. These methods can be used to measure the concentration profile in the depth direction by ion acceleration. The plasma ion doping can be controlled with high precision by adjusting the voltage and dose. By using this method, productivity can be improved. By using this, the purity of the impurity element to be supplied can be increased.

[0228] In the supplying process of the impurity element 140, the interface between the semiconductor layer 108 and the insulating layer 110, is a portion of the semiconductor layer 108 near the interface, or a portion of the insulating layer 110 near the interface. It is preferable to control the treatment conditions so that the highest concentration is obtained. The method supplies the impurity element 140 at an optimum concentration to both the semiconductor layer 108 and the insulating layer 110. It is possible.

[0229] The impurity elements 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, Examples include aluminum, magnesium, silicon, and rare gases. Representative examples include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon. It's nice.

[0230] As a source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, typically B2H6 gas or BF3 gas can be used. In addition, when supplying phosphorus, PH3 gas can be typically used. Alternatively, a mixed gas obtained by diluting these source gases with a rare gas may be used.

[0231] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases can be used. In addition, the ion source is not limited to gas, and solids or liquids vaporized by heating can also be used. good.

[0232] The addition of the impurity element 140 affects the composition, density, thickness, etc. of the insulating layer 110 and the semiconductor layer 108. This can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the above.

[0233] For example, when adding boron by ion implantation or plasma ion doping, The acceleration voltage is, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, more preferably 100 kV or more and 50 kV or less. Preferably, the voltage can be in the range of 10 kV to 50 kV. Ba1×10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, preferably 1 x10 14 ions / cm 2 5x10 or more 16 ions / cm 2 Below, more preferably 1 x10 15 ions / cm 2 That's it, 3 x 10 16 ions / cm 2 The following range should be met: can be done.

[0234] In addition, when phosphorus ions are added by ion implantation or plasma ion doping, The acceleration voltage is, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less. The voltage can be set to a value in the range of 40 kV or more and 80 kV or less, more preferably in the range of 40 kV or more and 80 kV or less. For example, 1 x 10 13 ions / cm 2 More than 1×10 17 ions / cm 2 Below, I prefer Or 1 x 10 14 ions / cm 2 5x10 or more 16 ions / cm 2 The following is more preferred: Or 1 x 10 15 ions / cm 2 3x10 or more 16 ions / cm 2 The range is as follows: It is possible.

[0235] The method of supplying the impurity element 140 is not limited to this, and may be, for example, a plasma treatment or A treatment utilizing thermal diffusion by heating may also be used. In the case of a plasma treatment method, the added Plasma is generated in a gas atmosphere containing impurity elements, and plasma processing is performed. The plasma generating device may be a drive device. Etching equipment, ashing equipment, plasma CVD equipment, high density plasma CVD equipment, etc. can be used.

[0236] In one embodiment of the present invention, the impurity element 140 is supplied to the semiconductor layer 108 through the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystallinity, impurities can be Damage to the semiconductor layer 108 during the supply of the element 140 is reduced, and the crystallinity is not impaired. Therefore, the increase in electrical resistance due to the decrease in crystallinity can be prevented. This is preferable in such cases.

[0237] [Formation of insulating layer 118] Subsequently, the insulating layer 11 is formed over the insulating layer 110, the metal oxide layer 114, and the conductive layer 112. 8 is formed (Figure 11(A)).

[0238] When the insulating layer 118 is formed by the plasma CVD method, if the film formation temperature is too high, the low resistance The impurities contained in the region 108n and the like are introduced into the peripheral region including the channel formation region of the semiconductor layer 108. There is a risk of diffusion, and the electrical resistance of the low resistance region 108n may increase. The deposition temperature of the insulating layer 118 may be determined taking these factors into consideration.

[0239] For example, the temperature at which the insulating layer 118 is formed is preferably 150° C. or higher and 400° C. or lower. The temperature is preferably 180°C or higher and 360°C or lower, more preferably 200°C or higher and 250°C or lower. By forming the insulating layer 118 at a low temperature, a transistor with a short channel length can be obtained. Even if there is a problem, good electrical properties can be imparted.

[0240] After the insulating layer 118 is formed, heat treatment may be performed. In some cases, the region 108n can be made more stable and have a lower resistance. By performing the heat treatment, the impurity element 140 is diffused appropriately and locally uniformed, and the A low-resistance region 108n having a concentration gradient of impurity elements can be formed. If the temperature is too high (for example, 500° C. or higher), the impurity element 140 may enter the channel forming region. This may lead to deterioration of the electrical characteristics and reliability of the transistor.

[0241] The conditions for the heat treatment may be as described above.

[0242] If the heat treatment is unnecessary, it may not be performed. It may be used in combination with the heat treatment to be carried out in a later step. In the case where there is a step (for example, a film formation step) in the process, the step may be combined with the heat treatment.

[0243] [Formation of Openings 141a and 141b] Subsequently, the insulating layer 118 and the insulating layer 110 are partially etched to form a low resistance region 1. Openings 141a and 141b are formed to reach the substrate 08n.

[0244] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is formed and processed into a desired shape to form the conductive layer 120a and the conductive layer 120b. (Figure 11(B)).

[0245] Through the above steps, the transistor 100A can be manufactured. When the stencil 100A is applied to the pixels of a display device, a protective insulating layer, a planarizing layer, A step of forming at least one of the pixel electrodes and the wiring may be added.

[0246] This concludes the description of Example 1 of the manufacturing method.

[0247] Note that when the transistor 100 illustrated in Configuration Example 2-1 is manufactured, the above manufacturing method The steps of forming the conductive layer 106 and the opening 142 in Example 1 can be omitted. The transistor 100 and the transistor 100A are formed on the same substrate through the same process. It can be achieved.

[0248] [Production method example 2] Hereinafter, an example in which some steps are different from the above-mentioned Example 1 of the manufacturing method will be described. The transistor 100C illustrated in Example 2-4 will be described as an example.

[0249] In the following, explanations of the same parts as in the above-mentioned Example 1 of the manufacturing method will be omitted, and only the different parts will be explained. The following will explain this in detail.

[0250] First, in the same manner as in the above-mentioned Example 1 of Manufacturing Method, the conductive layer 106, the insulating layer 103, the semiconductor layer 108, and the insulating layer 109 are formed. The edge layer 110, the metal oxide film 114f, and the conductive film 112f are formed in this order. A cross-sectional view of the device is shown in FIG.

[0251] Subsequently, the conductive film 112f and the metal oxide film 114f are partially etched to form the conductive layer 1 12 and a metal oxide layer 114 are formed, and then a part of the insulating layer 110 is etched to form a semiconductor layer. A part of the conductor layer 108 is exposed (FIG. 12(B)). This allows the top surface shape to roughly match. A conductive layer 112, a metal oxide layer 114, and an insulating layer 110 can be formed.

[0252] The insulating layer 110 is etched using a resist mask for etching the conductive film 112f. The insulating layer 110 is preferably etched using the conductive film 112f and the gold film. This may be done in the same step as etching the conductive film 112f and the metal oxide film 114f. After etching the oxide film 114f, etching is performed by a different etching method. You may also use the

[0253] For example, the conductive film 112f and the metal oxide film 114f are etched on a wafer using the same etchant. After etching by hot etching, the insulating layer 110 is etched by dry etching. In particular, the conductive film 112f and the metal oxide film 114f can be dry etched. When processed by etching, a reaction product containing metal is generated, and the semiconductor layer 10 8 and the insulating layer 110. Therefore, before etching the insulating layer 110, The conductive film 112f and the metal oxide film 114f are processed by wet etching. is preferred.

[0254] Depending on the etching conditions, the conductive layer 112, the metal oxide layer 114, and the insulating layer 116 may be removed. For example, the edges of the conductive layer 112 may be closer to the edge of the insulating layer 110 than the edge of the insulating layer 110. At least one end of the metal oxide layer 114 is located inside or outside. This may be the case.

[0255] Furthermore, when the insulating layer 110 is etched, a part of the exposed semiconductor layer 108 is also etched. At this time, the semiconductor layer 108 may be thinned by the thickness of the low resistance region 108n. , it can be thinner than the thickness of the channel forming region.

[0256] In addition, when the insulating layer 110 is etched, a part of the insulating layer 103 that is not covered with the semiconductor layer 108 is For example, the insulating film 103d of the insulating layer 103 may be etched and thinned. There may also be losses.

[0257] Next, an insulating layer 116 is formed on the exposed portion of the semiconductor layer 108, followed by an insulating The insulating layer 116 is formed on the semiconductor layer 108 (FIG. 12(C)). The exposed portion has a low resistance, forming a low resistance region 108n.

[0258] The insulating layer 116 is formed by emitting an impurity element having a function of reducing the resistance of the semiconductor layer 108. In particular, a silicon nitride film capable of releasing hydrogen can be used. It is preferable to use an inorganic insulating film such as a silicon nitride oxide film or a silicon oxynitride film. At this time, by using a plasma CVD method using a film formation gas containing hydrogen, the insulating layer 11 This is preferable because hydrogen can be supplied to the semiconductor layer 108 during the deposition of the film 6.

[0259] For example, when silicon nitride is used as the insulating layer 116, silicon such as silane is used. The mixed gas containing nitrogen such as ammonia and nitrous oxide is used as the deposition gas. It is preferable to form the silicon nitride film by the PECVD method used in the above. It is preferable that hydrogen is contained in the insulating layer 116. This allows the hydrogen in the insulating layer 116 to Diffusion into the layer 108 makes it easier to reduce the resistance of a portion of the semiconductor layer 108.

[0260] Alternatively, an insulating film having a function of generating oxygen vacancies in the semiconductor layer 108 may be used. In particular, it is preferable to use an insulating film containing a metal nitride. A sputtering target is used to form a mixture of nitrogen gas and a dilution gas such as a rare gas. It is preferable to form the film by reactive sputtering using a film gas. By controlling the flow rate ratio of the film-forming gases, it becomes easy to control the film quality of the insulating layer 116. .

[0261] For example, the insulating layer 116 is formed by reactive sputtering using an aluminum target. When using an aluminum nitride film formed by the above method, the ratio of the flow rate of nitrogen gas to the total flow rate of the film-forming gas is The amount is 30% or more and 100% or less, preferably 40% or more and 100% or less, more preferably 50% or more. It is preferable that the ratio is 100% or more and 100% or less.

[0262] Here, the insulating layer 116 and the insulating layer 118 are formed successively without being exposed to the air. is preferred.

[0263] After the insulating layer 116 or the insulating layer 118 is formed, heat treatment may be performed. The heat treatment can promote the reduction in resistance of the low-resistance region 108n.

[0264] The conditions for the heat treatment may be as described above.

[0265] If the heat treatment is unnecessary, it may not be performed. It may be used in combination with the heat treatment to be carried out in a later step. In some cases, the heat treatment may be performed in a process such as a film formation process.

[0266] Subsequently, an opening 141 is formed in the insulating layer 118 and the insulating layer 116, reaching the low resistance region 108n. a and an opening 141b are formed.

[0267] Subsequently, the conductive layer 120a and the conductive layer 120b are formed on the insulating layer 118 in the same manner as in Manufacturing Method Example 1. b is formed (Figure 12(D)).

[0268] Through the above steps, the transistor 100C can be manufactured.

[0269] In addition, when manufacturing the transistor 100B illustrated in Configuration Example 2-3, the above manufacturing method The steps of forming the conductive layer 106 and the opening 142 in Example 2 can be omitted. The transistors 100B and 100C are fabricated on the same substrate through the same process. It can be formed into.

[0270] [Components of semiconductor device] The components included in the semiconductor device of this embodiment will be described below.

[0271] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, single crystals made of silicon or silicon carbide are Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates The substrate 102 may be a plate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, a substrate having a semiconductor element formed thereon may be referred to as the substrate 102. It may be used.

[0272] In addition, a flexible substrate is used as the substrate 102, and a semiconductor device is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the semiconductor device. After a semiconductor device is partially or entirely completed on the substrate, it is separated from the substrate 102 and placed on another substrate. In this case, the semiconductor device is mounted on a substrate having poor heat resistance or a flexible substrate. It can also be reproduced on boards.

[0273] [Conductive film] The conductive layer 112 and the conductive layer 106 function as a gate electrode, and the source electrode or drain electrode. The conductive layer 120a functions as one of the drain electrodes, and the conductive layer 120b functions as the other. b is chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, A metal element selected from the group consisting of zinc, manganese, nickel, iron, and cobalt, or the above-mentioned gold. The alloys are made of metal elements or alloys that combine the above-mentioned metal elements. It can be achieved.

[0274] In addition, the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b contain In. -Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti -Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. An oxide conductor or a metal oxide film can also be applied.

[0275] Here, an oxide conductor (OC) will be described. For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. When the metal oxide is heated, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. The metal oxide that has been made conductive can be called an oxide conductor.

[0276] In addition, as the conductive layer 112, a conductive film containing the oxide conductor (metal oxide) and a metal Alternatively, a laminated structure of a conductive film containing a metal or an alloy may be used. In this case, the insulating layer that functions as a gate insulating film is It is preferable to apply a conductive film containing an oxide conductor to the side in contact with the edge layer.

[0277] The conductive layers 112, 106, 120a, and 120b are made of the above-mentioned gold. Among the group elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is particularly preferable to use a tantalum nitride film. The tantalum nitride film has electrical conductivity and high barrier properties against copper, oxygen, and hydrogen. Since the conductive film in contact with the semiconductor layer 108 has a low hydrogen release property and releases little hydrogen from itself, Alternatively, it can be suitably used as a conductive film in the vicinity of the semiconductor layer 108 .

[0278] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The atomic ratio of the metal elements in the sputtering target used is In:M:Zn=1: 1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Z n=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M :Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In :M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1: 7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5: Examples include 2:5.

[0279] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 can be easily formed with crystallinity. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. The ratio of the number of atoms may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], film formation The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. This may be the case.

[0280] When the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, it means In When Ga is 4, this includes the case where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. In addition, when describing that the atomic ratio is In:Ga:Zn=5:1:6 or in the vicinity, When n is 5, Ga is greater than 0.1 and less than or equal to 2, and Zn is greater than or equal to 5 and less than or equal to 7. It also includes cases where the atomic ratio is In:Ga:Zn=1:1:1 or in the vicinity. When mounting, when In is 1, Ga is greater than 0.1 and not more than 2, and Zn is 0. This includes cases where the value is greater than 1 and less than or equal to 2.

[0281] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0282] The semiconductor layer 108 preferably has a non-single-crystal structure. This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure, which will be described later. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0283] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0284] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystalline structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with a CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which it is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0285] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, CAAC-OS has no clear grain boundaries, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. Crystallinity can be reduced by the inclusion of impurities or the generation of defects. It can be said that CAAC- is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Oxide semiconductors containing an OS have stable physical properties. Oxide semiconductors are heat resistant and highly reliable.

[0286] In crystallography, the three axes that make up the unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the layer structure. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis intersecting the layers is the The c-axis is generally defined as the plane of the crystal. Graphite is classified as a hexagonal crystal, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure The crystal of InGaZnO4 can be classified as a hexagonal system, and the a-axis and The a and b axes are parallel to the plane direction of the layer, and the c axis is perpendicular to the layer (i.e., the a and b axes).

[0287] An oxide semiconductor film with a microcrystalline structure (microcrystalline oxide semiconductor film) is observed by TEM. In some cases, it may not be possible to clearly identify the crystal parts in the microcrystalline oxide semiconductor film. The crystal part to be formed has a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm to 10 nm or 1 nm to 3 nm are often An oxide semiconductor film having nanocrystals (nc) is called nc-OS. (nanocrystalline oxide semiconductor) film In addition, the grain boundaries of the nc-OS film can be clearly seen in the TEM image. It may not be possible.

[0288] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the device, the crystal plane is analyzed using the out-of-plane method. In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that of the crystalline part. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam (for example, 50 nm or larger) When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less). When electron beam diffraction (also called nanobeam electron diffraction) is performed using the electron beam (bottom), a circle is drawn. A bright area (ring-shaped) is observed, and multiple spots are observed within the ring-shaped area. may be observed.

[0289] The nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the S film, there is no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film The defect density of the nc-OS film is higher than that of the CAAC-OS film. Compared to the OS film, the carrier density is higher and the electron mobility may be higher. A transistor including an -OS film can exhibit high field-effect mobility.

[0290] The nc-OS film can be formed with a smaller oxygen flow rate than the CAAC-OS film. In addition, the nc-OS film can be formed at a low temperature compared to the CAAC-OS film. For example, the nc-OS film can be formed by lowering the substrate temperature. A state where the temperature is relatively low (for example, below 130°C) or the substrate is not heated. Since it can be used to form films on large glass substrates or resin substrates, This allows for increased productivity.

[0291] An example of the crystal structure of a metal oxide is described below. The substrate temperature was set at 100°C or higher. The metal oxide formed by sputtering is nc (nano c) crystal structure) or CAAC structure, or a mixture of these. On the other hand, metal oxides formed at room temperature (RT) tend to have a structure similar to that shown in Fig. The NC crystal structure is easily formed. Includes temperatures when no heating is used.

[0292] [Metal oxide composition] Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0293] CAAC (c-axis aligned crystal) is an example of a crystal structure. CAC (Cloud-Aligned Composite) represents the functionality or material An example of the composition of the fee is shown below.

[0294] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconductor properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the functions of the two complementary to each other, the switching function (On / Off) is realized. The function of activating the CAC-OS or CAC-metal oxide can be added. In CAC-OS or CAC-metal oxide, each function is separated. By combining these, the functions of both can be maximized.

[0295] In addition, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a bell. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0296] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0297] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0298] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0299] The above is the explanation of the configuration of the metal oxide.

[0300] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0301] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0302] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described. We will explain about this.

[0303] [Configuration example] 13A shows a top view of a display device 700. The display device 700 includes a sealant 712 The first substrate 701 and the second substrate 705 are bonded together. 1, the second substrate 705, and the area sealed by the sealant 712, the first substrate 70 1, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided. The pixel portion 702 is provided with a plurality of display elements.

[0304] In addition, an FPC 716 (FP C: Flexible printed circuit) is connected to the FPC terminal 7 The FPC terminal portion 708 and the signal line 710 are connected by the FPC 716. 7, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706. Various signals are supplied to each of these.

[0305] A plurality of gate driver circuit sections 706 may be provided. The path section 706 and the source driver circuit section 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is mounted on the first substrate 70. 1 or can be mounted on FPC716.

[0306] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor can be a transistor that is a semiconductor device of one embodiment of the present invention. do.

[0307] Examples of display elements provided in the pixel portion 702 include a liquid crystal element and a light-emitting element. The liquid crystal elements used include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. In addition, LEDs (Light Emitting Diodes) can be used as light emitting elements. Diode), OLED (Organic LED), QLED (Quantum-do Examples of self-luminous light-emitting elements include LEDs, semiconductor lasers, etc. MEMS (Micro Electro Mechanical Systems) using optical interference or optical sensing l Systems) elements, microcapsule type, electrophoresis type, electrowet Display elements that use the LCD technology or the electronic liquid powder technology (registered trademark) can be used. It can also be done as follows.

[0308] The display device 700A shown in FIG. 13B has a flexible substrate instead of the first substrate 701. A display device to which a resin layer 743 is applied and which can be used as a flexible display This is an example.

[0309] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in the region P1 in FIG. 13(B), the pixel section 702 and the resin layer 743 The pair of gate driver circuit sections 706 are connected to the pixel section 7 The gate driver circuit section 706 is provided on both sides of the pixel section 702. The portion is provided along an arc-shaped contour.

[0310] The resin layer 743 has a protruding shape at the portion where the FPC terminal portion 708 is provided. In addition, a part of the resin layer 743 including the FPC terminal portion 708 is on the back side in the region P2 in FIG. By folding back a part of the resin layer 743, the FPC 716 can be attached to the pixel area. The display device 700A can be mounted on the back side of the display device 702 so that the display device 700A can be mounted on the electronic device. This allows for space saving for electronic devices.

[0311] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. The source driver circuit section 704 in FIG. 00A includes a protection circuit, a buffer circuit, a demultiplexer, The configuration may include at least one of a crossover circuit, a crossover circuit, and the like.

[0312] The display device 700B shown in FIG. 13C is suitable for use in electronic devices having large screens. For example, television equipment, monitor equipment, personal computer Computers (including laptops and desktops), tablets, digital signage It can be suitably used in the following cases:

[0313] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuits. It has a section 722.

[0314] The plurality of source driver ICs 721 are attached to respective FPCs 723. In addition, the plurality of FPCs 723 have terminals on one side connected to the first substrate 701 and terminals on the other side connected to the printed circuit board. The FPC 723 is bent to connect the printed circuit board 7 24 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby reducing the space required for the electronic device. It is possible to pace things up.

[0315] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize electronic devices with narrow frames.

[0316] By adopting such a configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. In addition, the resolution can be increased to 4K2K or 8K4K. This makes it possible to realize a display device with extremely high resolution.

[0317] [Cross-section example] Below, we will discuss configurations using liquid crystal elements and EL elements as display elements. 14 to 17. Note that FIGS. 14 to 16 are the same as those in FIG. 13(A) 13(B) is a cross-sectional view taken along the dashed line QR in FIG. 14 and 15 are cross-sectional views of the display device 700A taken along the dashed line ST. 16 and 17 show a configuration using a liquid crystal element as a display element, and FIG. 18 shows a configuration using an EL element. do.

[0318] [Explanation of common parts of the display device] The display device shown in FIGS. 14 to 17 includes a wiring portion 711, a pixel portion 702, and a The wiring section 711 has a driver circuit section 704 and an FPC terminal section 708. , and a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit section 704 includes a transistor 752. In FIG. The case without element 790 is shown.

[0319] The transistor 750 and the transistor 752 are the same as those described in Embodiment 1. can be applied.

[0320] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. The holding time of the image signal can be extended, and the interval between writing of the image signal etc. can also be set to be longer. Since the frequency of refresh operations can be reduced, power consumption can be reduced.

[0321] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a display device. By using this in a device, the switching transistor in the pixel section and the driver used in the drive circuit section can be The transistors can be formed on the same substrate, i.e., a silicon wafer. It is also possible to configure the display device without using a drive circuit formed by the above method, thereby reducing the number of components in the display device. In addition, by using a transistor that can be driven at high speed in the pixel portion, High quality images can be provided.

[0322] The capacitor 790 shown in FIGS. 14, 16, and 17 is a third capacitor included in the transistor 750. The lower electrode is formed by processing the same film as the gate electrode in 1, and the same metal oxide as the semiconductor layer. and an upper electrode formed by processing a material. The resistance between the lower electrode and the upper electrode is low, similar to the source region and the drain region. A part of the insulating film that functions as the first gate insulating layer of the transistor 750 is provided in the That is, the capacitor 790 has an insulating film sandwiched between a pair of electrodes, which functions as a dielectric film. The upper electrode is a stacked structure in which the source electrode and drain electrode of the transistor are formed. The electrodes are connected to wiring obtained by processing the same film as the electrodes.

[0323] In addition, a planarization insulating film is formed on the transistor 750, the transistor 752, and the capacitor 790. A veneer 770 is provided.

[0324] The transistor 750 included in the pixel portion 702 and the transistor 750 included in the source driver circuit portion 704 are A transistor having a different structure from the transistor 752 may be used. A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. The gate driver circuit section 706 may also be configured to use a source driver. As in the driver circuit section 704, a transistor having the same structure as the transistor 750 may be used. Alternatively, transistors with different structures may be used.

[0325] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. It is made of the same conductive film as the electrodes. At this time, a low-resistance material such as a material containing copper elements is used. When used, there is little signal delay due to wiring resistance, and it is possible to display on a large screen, so it is preferred. I wish.

[0326] The FPC terminal portion 708 includes wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 78, and a The wiring 760 is connected to the FPC 71 through an anisotropic conductive film 780. 7. Here, the wiring 760 is electrically connected to a terminal of the transistor 750 or The source electrode and the drain electrode of the transistor 752 are formed using the same conductive film.

[0327] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used. When a substrate that can be used is used, water or a water-soluble substance is provided between the first substrate 701 and the transistor 750 or the like. It is preferable to provide an insulating layer having barrier properties against elements.

[0328] On the second substrate 705 side, there are a light-shielding film 738, a colored film 736, and an insulating film in contact with these. A velum 734 is provided.

[0329] [Configuration example of a display device using a liquid crystal element] The display device 700 shown in FIG. 14 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive layer The conductive layer 774 is a second The conductive layer 772 is provided on the substrate 705 side and functions as a common electrode. The conductive layer is electrically connected to a source electrode or a drain electrode of the transistor 750. A film 772 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0330] The conductive layer 772 can be formed using a material that transmits or reflects visible light. The transparent material may be, for example, an oxide material containing indium, zinc, tin, or the like. As the reflective material, for example, a material containing aluminum, silver, etc. is used. It is good.

[0331] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the liquid crystal display device becomes a transmissive type. In the case of a transmissive liquid crystal display device, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided to sandwich the liquid crystal element.

[0332] The display device 700 shown in FIG. 15 includes a liquid crystal element 77 of a horizontal electric field type (for example, FFS mode). 5 is used as a common electrode. A conductive layer 774 is provided. An electric field generated between the conductive layer 772 and the conductive layer 774 The alignment state of the liquid crystal layer 776 can be controlled.

[0333] In FIG. 15, a holding container is formed by a laminated structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitance element, and the aperture ratio can be increased. It is possible.

[0334] Although not shown in FIGS. 14 and 15, an alignment film in contact with the liquid crystal layer 776 may be provided. In addition, optical members (optical substrates) such as polarizing members, phase difference members, and anti-reflection members may be used. , and light sources such as backlights and sidelights can be provided as appropriate.

[0335] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a polymer dispersion liquid, or the like. Crystal (PDLC: Polymer Dispersed Liquid Crystal) , Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When the in-plane switching system is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used.

[0336] The liquid crystal element mode is TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-S witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optically Compensated Biref ringence mode, ECB (Electrically Controlled Birefringence mode, guest-host mode, etc. .

[0337] In addition, the liquid crystal layer 776 uses a polymer dispersed liquid crystal or a polymer network liquid crystal, A scattering type liquid crystal can also be used. In this case, black and white display is performed without providing the colored film 736. Alternatively, a colored film 736 may be used to perform color display.

[0338] In addition, as a driving method of the liquid crystal element, a time-series additive color mixture method is used to display colors. A split display method (also called a field sequential driving method) may be applied. In this case, the colored film 736 may not be provided. For example, it is necessary to provide sub-pixels that exhibit the respective colors R (red), G (green), and B (blue). This has the advantage of improving the pixel aperture ratio and increasing the resolution. do.

[0339] [Display device using light-emitting elements] The display device 700 shown in FIG. 16 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer The EL layer 786 includes an organic compound. The light-emitting element has a light-emitting material such as an inorganic compound.

[0340] The luminescent materials include fluorescent materials, phosphorescent materials, and thermally activated delayed fluorescence (TDF). ctivated delayed fluorescence (TADF) materials, inorganic Compounds (quantum dot materials, etc.) can be used.

[0341] In the display device 700 shown in FIG. 16, a conductive layer 772 is formed on a planarization insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788. The light-emitting element 782 emits light toward the conductive layer 772. a bottom emission structure in which light is emitted from the bottom of the conductive layer 772 and the conductive film 788; It may also be a dual emission structure.

[0342] The colored film 736 is provided at a position overlapping the light emitting element 782. 8 is a portion overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 70 4. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. The EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, by coloring. In this case, the colored film 736 may not be provided.

[0343] FIG. 17 shows the configuration of a display device that can be suitably applied to a flexible display. FIG. 17 is a cross section taken along dashed line ST in the display device 700A shown in FIG. 13(B). Figure.

[0344] The display device 700A shown in FIG. 17 includes a support substrate instead of the first substrate 701 shown in FIG. It has a structure in which a plate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated. The transistor 750, the capacitor 790, and the like are formed on an insulating layer 744 provided on a resin layer 743. It is set up in.

[0345] The support substrate 745 is a substrate containing organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The resin layer 74 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. 3 and a support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is It is preferably thinner than the support substrate 745 .

[0346] 17, the display device 700A shown in FIG. 17 has a support substrate 705 instead of the second substrate 705 shown in FIG. The protective layer 740 is bonded to the sealing film 732. The protective layer 740 may be a glass substrate or a resin film. Examples of such optical components include polarizing plates and scattering plates, and input devices such as touch sensor panels. A configuration in which two or more of these are stacked may also be applied.

[0347] The EL layer 786 of the light-emitting element 782 is an island on the insulating film 730 and the conductive layer 772. The EL layer 786 is formed so that each sub-pixel emits a different color. Therefore, color display can be realized without using the colored film 736. The protective layer 741 is provided to cover the light emitting element 782. The protective layer 741 protects the light emitting element 782 from inclusions such as water. The protective layer 741 has a function of preventing diffusion of impurities. It is also preferable to use a laminated structure including at least one inorganic insulating film and at least one organic insulating film. preferable.

[0348] 17 shows a bendable region P2. In the region P2, the support substrate 7 45, in addition to the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. The bendable region P2 is provided with as little inorganic insulating film as possible, and a conductive film containing a metal or alloy is provided. By stacking only layers containing organic materials and layers containing organic materials, cracks do not occur when the material is bent. In addition, by not providing the support substrate 745 in the region P2, an extremely small A portion of the display device 700A can be bent with a small radius of curvature.

[0349] [Configuration example in which an input device is provided on a display device] In addition, an input device may be provided to the display device 700 or the display device 700A shown in FIGS. The input device may be, for example, a touch sensor.

[0350] For example, the sensor types include capacitance type, resistive film type, surface acoustic wave type, and infrared type. Various methods can be used, such as electrical, optical, and pressure-sensitive methods. Or, two or more of these can be used. may be used in combination.

[0351] The touch panel has a so-called in-cell structure in which the input device is formed between a pair of substrates. The touch panel and the input device are formed on the display device 700, that is, a so-called on-cell type touch panel. or an input device attached to the display device 700, so-called out-cell type touch panel. There are panels etc.

[0352] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0353] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0354] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0355] The display device shown in FIG. 18A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 50 6 and a terminal portion 507. Note that the protection circuit 506 may not be provided. .

[0356] The transistors included in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. The protection circuit 506 can also be formed using the transistor of one embodiment of the present invention. may be applied.

[0357] The pixel section 502 is a plurality of pixels arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The display device has a plurality of pixel circuits 501 for driving a number of display elements.

[0358] The driver circuit unit 504 is a gate driver that outputs scanning signals to the gate lines GL_1 to GL_X. A data driver 504a supplies data signals to the data lines DL_1 through DL_Y. The gate driver 504a includes at least one driver circuit, such as a source driver 504b. The source driver 504b may also have a shift register. It is also constructed using a shift register etc. The switch driver 504b may be configured as a

[0359] The terminal unit 507 is used to input power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals for connecting the power supply to the power source are provided.

[0360] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 The protection circuit 506 shown in FIG. For example, the gate line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, indicates various wirings such as the data line DL which is the wiring between the source driver 504b and the pixel circuit 501. is connected to.

[0361] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film) circuit board) by COG or TAB (Tape Automated Bonding) The LED 502 may be mounted on the substrate on which the pixel portion 502 is provided.

[0362] 18(A) may be replaced with the pixel circuits 501 shown in FIG. 18(B) or FIG. The configuration shown in FIG. 8(C) can be used.

[0363] The pixel circuit 501 shown in FIG. 18B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 also includes a data line DL_n, a gate line GL _m, a potential supply line VL, etc. are connected.

[0364] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0365] The pixel circuit 501 shown in FIG. 18C includes a transistor 552 and a transistor 5 The pixel circuit 501 includes a pixel 504, a capacitor 562, and a light-emitting element 572. The data line DL_n, the gate line GL_m, the potential supply line VL_a, and the potential supply line VL_b are is connected.

[0366] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. The other terminal is supplied with a low power supply potential VSS. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the light-emitting element 572. The brightness of the light emitted from 72 is controlled.

[0367] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0368] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0369] (Fourth embodiment) In the following, a pixel circuit having a memory for correcting the gradation displayed in the pixel and a The transistors exemplified in Embodiment 1 will be described below. The present invention can be applied to transistors used in pixel circuits.

[0370] [Circuit configuration] 19A shows a circuit diagram of the pixel circuit 400. The pixel circuit 400 includes a transistor M The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. The wiring S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0371] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, and The other terminal is connected to one electrode of the capacitor C1. The gate of the transistor M2 is connected to the wiring. G2, one of the source and drain is connected to the wiring S2, and the other is connected to the other electrode of the capacitor C1, and 401 and 402, respectively.

[0372] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal element, or MEMS (Micro Electro Mechanical Systems) EMS) elements, etc. can be applied.

[0373] The node connecting the transistor M1 and the capacitor C1 is connected to the node N1, and the transistor M2 is connected to the node N2. The node connecting to the path 401 is node N2.

[0374] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. Furthermore, by turning off the transistor M2, the voltage of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via capacitor M1, capacitive coupling via capacitor C1 This allows the potential of the node N2 to be changed in accordance with the change in the potential of the node N1.

[0375] Here, one or both of the transistors M1 and M2 may be The transistor using an oxide semiconductor, as exemplified in 1, can be used. Therefore, the potential of the node N1 or N2 is maintained for a long period of time due to the extremely low off-state current. In addition, when the period for which the potential of each node is held is short (specifically, when In cases where the frequency is 30 Hz or more, transistors using semiconductors such as silicon A star may also be used.

[0376] [Drive method example] Next, an example of a method of operating the pixel circuit 400 will be described with reference to FIG. (B) is a timing chart relating to the operation of the pixel circuit 400. For ease of understanding, various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, The influence of the threshold voltage of the transistor and the like is not taken into consideration.

[0377] In the operation shown in FIG. 19B, one frame period is divided into a period T1 and a period T2. T1 is a period during which a potential is written to node N2, and T2 is a period during which a potential is written to node N1. It is a period.

[0378] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the wiring S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supply.

[0379] The node N1 is connected to the line S1 via the transistor M1. ref is given. The node N2 is supplied with a first data potential V w is given. Therefore, the potential difference V across the capacitance C1 w -V ref is maintained.

[0380] [Period T2] Subsequently, in a period T2, a potential that turns on the transistor M1 is applied to the wiring G1. A potential that turns off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. It may be in a locking state.

[0381] The node N1 is supplied with a second data potential V data is given. At this time, due to the capacitive coupling of the capacitor C1, the second data potential V data Depending on node N 2 changes by a potential dV. w and electricity In FIG. 19B, the potential dV is a positive value. However, it may be a negative value. dat a is the potential V ref It may be lower.

[0382] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is Data potential V data The potential is close to

[0383] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential supplied to the line 401 can be generated, the gradation can be corrected in the pixel circuit 400. It will be possible to do this.

[0384] The pixel circuit 400 can also be supplied with a source driver connected to the wiring S1 and the wiring S2. For example, when a light emitting element is used, it is possible to generate a potential that exceeds the maximum potential. It is possible to display high dynamic range (HDR) images. In this case, overdrive driving or the like can be realized.

[0385] [Application example] [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 19C includes a circuit 401LC. has a liquid crystal element LC and a capacitor C2.

[0386] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitor C2, and the other electrode connected to the Potential V com2 The capacitor C2 is connected to the wiring where the other electrode is at potential V com1 Connect with the wiring given.

[0387] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted. Cut.

[0388] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, Overdrive operation allows for high-speed display, and liquid crystal materials with high drive voltage are used. In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the deterioration state of the liquid crystal element LC.

[0389] [Example using light-emitting element] The pixel circuit 400EL shown in FIG. 19D includes a circuit 401EL. includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0390] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the node N2 and one electrode of the capacitor C2. One of the rains is at potential V H The other is one electrode of the light-emitting element EL, and The capacitor C2 is connected to the other electrode at a potential V com Connect with the wiring given. The other electrode of the light-emitting element EL is at a potential V L Connect with the wiring given.

[0391] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0392] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. H and potential V L The value of can be changed as appropriate.

[0393] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, it is possible to realize, for example, HDR display. In addition, by supplying a correction signal to the wiring S1 or wiring S2, the transistor M3 and It is also possible to correct variations in the electrical characteristics of the light-emitting element EL.

[0394] The circuit is not limited to the circuits illustrated in FIGS. 19(C) and 19(D), and may include other transistors or A configuration in which capacitance or the like is added may also be adopted.

[0395] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0396] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. and explain.

[0397] The display module 6000 shown in FIG. 20(A) includes an upper cover 6001 and a lower cover 6002. Between the display device 6006 and the frame 6009, the FPC 6005 is connected. The device has a main board 6010 and a battery 6011.

[0398] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 realizes a display module with extremely low power consumption. It is possible.

[0399] The upper cover 6001 and the lower cover 6002 are designed to fit the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0400] The display device 6006 may have a function as a touch panel.

[0401] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0402] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. It has a signal processing circuit, a battery control circuit, etc.

[0403] FIG. 20B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. is.

[0404] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is enclosed by an upper cover 6001 and a lower cover 6002. The region has a pair of light guide portions (light guide portion 6017a, light guide portion 6017b).

[0405] The display device 6006 is connected to a printed circuit board 6010 and a battery via a frame 6009. The display device 6006 and the frame 6009 are provided so as to overlap with the light guide unit 6011. 017a and fixed to the light guiding portion 6017b.

[0406] Light 6018 emitted from the light emitting unit 6015 is guided to the display device 600 by the light guiding unit 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. A touch operation is detected when the light 6018 is blocked by a detection object such as an illustration. It is possible.

[0407] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. It is possible to obtain information about the position where the touch operation was performed.

[0408] The light emitting unit 6015 can use a light source such as an LED element, and in particular, can emit infrared light. It is preferable to use a light source that emits light. A photoelectric element that receives light and converts it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0409] The light emitting section 6015 and the light guiding section 6017a and the light guiding section 6017b transmit light 6018. The light receiving unit 6016 can be disposed below the display device 6006, and external light is received by the light receiving unit 601. 6 and prevent the touch sensor from malfunctioning. By using a resin that allows wires to pass through, malfunction of the touch sensor can be more effectively suppressed.

[0410] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0411] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described. Reveal.

[0412] The electronic device 6500 shown in FIG. 21(A) is a mobile phone that can be used as a smartphone. It is a mobile information terminal.

[0413] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, and a 504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display unit 6502 has a touch panel function.

[0414] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0415] FIG. 21B is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0416] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501. The space surrounded by the protective member 6510 is provided with a display panel 6511, an optical member 6512, a tab The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. There are.

[0417] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. The flannel 6513 is fixed by an adhesive layer (not shown).

[0418] In addition, in the area outside the display portion 6502, a part of the display panel 6511 is folded back. In addition, the FPC6515 is connected to the folded part. The 6515 is mounted with IC6516. The FPC6515 is a printed circuit board 6 517.

[0419] A flexible display panel according to one embodiment of the present invention is applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. 1 is extremely thin, so it can accommodate a large-capacity battery 6518 while keeping the thickness of the electronic device small. It is also possible to fold back a part of the display panel 6511 and attach an FPC to the back of the pixel area. By arranging the connection part with 6515, it is possible to realize electronic devices with narrow bezels.

[0420] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0421] (Embodiment 7) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described. and explain.

[0422] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and a large screen It is possible to make an electronic device that is compatible with both.

[0423] The display unit of the electronic device according to one embodiment of the present invention may be configured to display, for example, full high-definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0424] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, mobile phones, Examples of such devices include mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0425] An electronic device to which one aspect of the present invention is applied may be installed on the interior or exterior walls of a house or building, or the interior of a car or the like. It can be incorporated along a flat or curved surface of the packaging or exterior.

[0426] FIG. 22(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0427] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0428] The camera 8000 may have the lens 8006 and the housing integrated together.

[0429] The camera 8000 can be operated by pressing the shutter button 8004 or by using the touch panel. An image can be captured by touching the display portion 8002.

[0430] The housing 8001 has a mount with electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as

[0431] The finder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. .

[0432] The housing 8101 is configured to mount the camera 8000 by a mount that engages with the mount of the camera 8000. The finder 8100 is attached to the camera 8000. It can be displayed on the display unit 8102.

[0433] The button 8103 has a function such as a power button.

[0434] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device of one embodiment of the present invention can be applied. It may be La 8000.

[0435] FIG. 22B is a diagram showing the appearance of the head mounted display 8200.

[0436] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0437] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movements of the user's eyes and eyelids. It can be used as a step.

[0438] In addition, the attachment part 8201 has a flow sensor that moves in accordance with the movement of the user's eyeball at a position where it comes into contact with the user. A plurality of electrodes capable of detecting the current passing through the sensor may be provided, and the sensor may have a function of recognizing the line of sight. In addition, the device may have a function of monitoring the pulse of the user by measuring the current flowing through the electrodes. The mounting part 8201 is equipped with various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function to display the user's biological information, and the head of the user may have a function to display the user's biological information. The display unit 8204 may have a function of changing the image displayed on the display unit 8204 in accordance with the user's movements.

[0439] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0440] 22(C), 22(D), and 22(E) show the head mounted display 83 8 is a diagram showing the appearance of the head-mounted display 8300. The head-mounted display 8300 includes a housing 8301 and It has a display portion 8302 , a band-shaped fixture 8304 , and a pair of lenses 8305 .

[0441] A user can view the display on the display unit 8302 through the lens 8305 . If the display unit 8302 is curved, the user can feel a high sense of presence. In addition, it is preferable to display different images in different areas of the display unit 8302 through the lens 8304. By viewing through 305, it is possible to perform a three-dimensional display using parallax. The configuration is not limited to one display unit 8302, but two display units 8302 may be provided, and one of the display units may be One display unit may be arranged for each eye.

[0442] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of this invention has extremely high definition. Even if the image is enlarged using the lens 8305, the pixels are not visible to the user, and the image is displayed more clearly. This makes it possible to display images with a higher sense of reality.

[0443] The electronic devices shown in FIGS. 23A to 23G include a housing 9000, a display portion 9001, a screen Speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), It has 9008, etc.

[0444] The electronic devices shown in FIGS. 23A to 23G have various functions. Function to display various information (still images, videos, text images, etc.) on the display, touch panel function , calendar, date or time display functions, various software (programs) a function to control processing by wireless communication, a program recorded on a recording medium, or The electronic device can have the function of reading and processing data. The electronic device may have a variety of functions, including but not limited to the above. In addition, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external). It has functions such as saving the captured image to a memory card (built-in to the camera or the internal memory) and displaying the captured image on the display. It may be possible.

[0445] The electronic devices shown in FIGS. 23A to 23G will be described in detail below.

[0446] FIG. 23A is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more It is possible to incorporate.

[0447] 23(B) is a perspective view showing a portable information terminal 9101. For example, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple surfaces. (See FIG. 23B.) An example of displaying three icons 9050 is shown in the figure. 051 can also be displayed on another surface of the display unit 9001. An example of the information 9051 is , notifications of incoming emails, SNS, phone calls, etc., subject of emails and SNS, sender Name, date and time, battery level, antenna reception strength, etc. An icon 9050 or the like may be displayed in the position where 51 is displayed.

[0448] 23(C) is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 is , and has the function of displaying information on three or more surfaces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different surfaces. The person holds the mobile information terminal 9102 in the breast pocket of his / her clothes. The user can also check the information 9053 displayed in a position that can be observed from above. The display can be checked without taking the mobile information terminal 9102 out of a pocket, and for example, a telephone call can be made. You can decide whether to accept it or not.

[0449] 23(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The display unit 9001 can be used as a smart watch, for example. The display surface is curved, and the display can be performed along the curved display surface. In addition, the mobile information terminal 9200 can communicate with, for example, a wireless headset. Therefore, hands-free calling is also possible. The terminal 9006 can transmit data to and from other information terminals and can also charge the device. Charging can also be performed by wireless power supply.

[0450] 23(E), 23(F), and 23(G) show a foldable portable information terminal 92. 23(E) is a perspective view showing the mobile information terminal 9201 in an unfolded state, Figure 23(G) shows the folded state, and Figure 23(F) shows the state from either Figure 23(E) or Figure 23(G). The portable information terminal 9201 is in a folded state. It is highly portable and has a seamless, wide display area when unfolded, making it easy to see the display. The display unit 9001 of the portable information terminal 9201 is connected by a hinge 9055. For example, the display unit 9001 has a curvature radius of 1 mm or less. It can be bent up to 150mm.

[0451] FIG. 24A shows an example of a television device. The television device 7100 has a housing 7 The display unit 7500 is built into the housing 7101. 101 is shown as a supported configuration.

[0452] The television device 7100 shown in FIG. 24A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or a display unit 75. A touch panel is applied to the television device 7100, and the television device 7100 can be operated by touching the touch panel. The remote control device 7111 may have a display unit in addition to the operation buttons.

[0453] The television device 7100 may be a television broadcast receiver or a network connection device. The communication device may include:

[0454] FIG. 24B shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, and a The housing 7211 includes a display unit 7500 and an external connection port 7214. It is embedded.

[0455] In Fig. 24(C) and Fig. 24(D), a digital signage An example of a digital sign is shown below.

[0456] The digital signage 7300 shown in FIG. 24C includes a housing 7301, a display unit 7500, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0457] FIG. 24(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7500.

[0458] The larger the display 7500, the more information can be displayed at once, and the closer it is to the human eye. It is easy to attach to the surface, which has the effect of increasing the advertising effectiveness of advertisements, for example.

[0459] It is preferable that the display unit 7500 be configured as a touch panel so that a user can operate it. This will enable the information to be used not only for advertising purposes but also for route information, traffic information, and commercial facility guidance information. It can also be used to provide information that users are looking for.

[0460] Also, as shown in FIG. 24(C) and FIG. 24(D), the digital signage 7300 The digital signage 7400 is displayed on an information terminal device 7 such as a smartphone carried by a user. 311 via wireless communication. The information of the advertisement to be displayed may be displayed on the screen of the information terminal 7311. By operating the buttons, the display on the display unit 7500 can be switched.

[0461] In addition, the Digital Signage 7300 or Digital Signage 7400 can be used with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0462] The display portion 7500 in FIGS. 24A to 24D includes a display device according to one embodiment of the present invention. can be applied.

[0463] Although the electronic device of this embodiment has a display unit, the present invention can also be applied to electronic devices that do not have a display unit. One embodiment of the present invention can also be applied to the above.

[0464] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Example]

[0465] In the following, transistors with different semiconductor layer configurations are fabricated, and their electrical characteristics and reliability are evaluated. The results of the evaluation of the effectiveness are explained below.

[0466] [Sample preparation] The structure of the manufactured transistor can be based on the structure of the transistor 100 described in Embodiment 1. In this case, the same process as that for the transistor 100A having a back gate electrode is used. The transistor 100 was fabricated in this manner.

[0467] First, a tungsten film with a thickness of approximately 100 nm was formed on a glass substrate by sputtering. This was then processed to obtain a first gate electrode. A first silicon nitride film having a thickness of about 240 nm, a second silicon nitride film having a thickness of about 60 nm, and a A silicon oxynitride film with a thickness of approximately 3 nm was formed by laminating it using the plasma CVD method.

[0468] The first silicon nitride film was formed by adjusting the flow rates of silane gas, nitrogen gas, and ammonia gas to 2. 90sccm, 2000sccm, 2000sccm, pressure 200Pa, film formation power 3 The film was formed under the conditions of 1000 W and a substrate temperature of 350°C.

[0469] The second silicon nitride film was formed by increasing the flow rates of silane gas, nitrogen gas, and ammonia gas to 2. The flow rates were 1000 sccm, 2000 sccm, and 100 sccm, the pressure was 100 Pa, and the film formation power was 20 The film was formed under the conditions of 100 W and a substrate temperature of 350°C.

[0470] The silicon oxynitride film was grown using silane gas and nitrous oxide gas at flow rates of 20 sccm each. , 3000sccm, pressure 40Pa, film formation power 3000W, substrate temperature 350℃ The film was formed as follows.

[0471] Next, a metal oxide film having a thickness of about 30 nm is formed on the first gate insulating layer, and this is heated. Here, five samples (samples) were prepared under different conditions for forming the metal oxide film. Samples A1 to A5 were prepared.

[0472] In the sample A1, the atomic ratio of the metal elements is In:Ga:Zn=5:1:6 [atomic ratio]. As shown in the figure, a metal oxide film was formed by sputtering using a metal oxide target. The deposition gas used was a mixture of argon and oxygen gases, with the oxygen gas flow rate set at 2%. The film formation was carried out without heating the substrate.

[0473] In the sample A2, the atomic ratio of the metal elements is In:Ga:Zn=4:2:3 [atomic ratio]. As shown in the figure, a metal oxide film was formed by sputtering using a metal oxide target. The deposition gas used was a mixture of argon and oxygen gases, with the flow rate of oxygen gas set at 10 %. The film was formed without heating the substrate.

[0474] In sample A3, the atomic ratio of metal elements is In:Ga:Zn=1:1:1 [atomic ratio]. As shown in the figure, a metal oxide film was formed by sputtering using a metal oxide target. The deposition gas used was a mixture of argon and oxygen gases, with the oxygen gas flow rate set at 30. %. The film was formed without heating the substrate.

[0475] In sample A4, the atomic ratio of metal elements is In:Ga:Zn=1:3:4 [atomic ratio]. As shown in the figure, a metal oxide film was formed by sputtering using a metal oxide target. The deposition gas used was a mixture of argon and oxygen gases, with the flow rate of oxygen gas set at 10 %. The film was formed without heating the substrate.

[0476] Sample A5 is a sample in which a first metal oxide film and a second metal oxide film are laminated. The atomic ratio of the metal elements is In:Ga:Zn=1:1:1 [atomic ratio]. A first metal oxide film with a thickness of approximately 25 nm was deposited by sputtering using an oxide target. The atomic ratio of the metal elements was In:Ga:Zn=5:1:6 [atomic ratio]. A sputtering method using a metal oxide target was used to deposit a film with a thickness of approximately 5 nm. The second metal oxide film was formed using a mixture of argon and oxygen gases as the film-forming gas. The flow rate of oxygen gas was set to 30% for the first metal oxide film and 40% for the second metal oxide film. The deposition was carried out without heating the substrate.

[0477] After the semiconductor layer was formed, a heat treatment was carried out at 350°C for 1 hour in a nitrogen gas atmosphere. Thereafter, heat treatment was carried out at 350° C. for 1 hour in a mixed atmosphere of nitrogen gas and oxygen gas.

[0478] Next, as a second gate insulating layer, a first silicon oxynitride film having a thickness of about 5 nm and a thickness of A second silicon oxynitride film having a thickness of about 140 nm and a third silicon oxynitride film having a thickness of about 5 nm. The films were formed by plasma CVD.

[0479] The first silicon oxynitride film was formed by setting the flow rates of silane gas and nitrous oxide gas to 24 s ccm, 18000sccm, pressure 200Pa, film formation power 130W, substrate temperature 350 The film was formed under the conditions of ℃.

[0480] The second silicon oxynitride film was formed by setting the flow rates of silane gas and nitrous oxide gas to 200 sccm, 4000sccm, pressure 300Pa, film formation power 750W, substrate temperature 350 The film was formed under the conditions of ℃.

[0481] The third silicon oxynitride film was formed by setting the flow rates of silane gas and nitrous oxide gas to 20 s ccm, 3000sccm, pressure 40Pa, film formation power 500W, substrate temperature 350℃ The film was formed under the conditions.

[0482] Next, a metal oxide film with a thickness of about 20 nm is deposited on the second gate insulating layer by sputtering. The metal oxide film was formed with the atomic ratio of metal elements being In:Ga:Zn=4: A metal oxide target was used in an oxygen-containing atmosphere to achieve a 2:3 atomic ratio. Then, the substrate was subjected to a heat treatment at 350°C for one hour in a nitrogen atmosphere.

[0483] Next, a molybdenum film with a thickness of approximately 100 nm was deposited on the metal oxide film by sputtering. After that, the molybdenum film and the metal oxide film were partially removed by etching, and the second A gate electrode and a metal oxide layer were obtained.

[0484] Next, using the second gate electrode as a mask, an addition process of boron as an impurity element is performed. The impurity was added using a plasma ion doping device. The gas used was B2H6 gas.

[0485] Next, a silicon oxynitride film approximately 300 nm thick is applied as a protective insulating layer to cover the transistor. Then, a protective insulating layer and a part of the second gate insulating layer were formed by plasma CVD. The opening is made by etching, and a molybdenum film is formed by sputtering. The source and drain electrodes were obtained by processing. Then, a planarization layer with a thickness of about 1.5 μm was formed. An acrylic film was formed and heat-treated in a nitrogen atmosphere at 250°C for one hour. .

[0486] By the above process, Sample A, each having a transistor formed on a glass substrate, A1 to A5 were obtained.

[0487] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistor fabricated above were measured.

[0488] The measurement conditions for the Id-Vg characteristics of a transistor are the voltage applied to the gate electrode (hereinafter referred to as The gate voltage (Vg) is applied from -15V to +20V in 0.25V increments. In addition, the voltage applied to the source electrode (hereinafter referred to as the source voltage (Vs)) was set to 0 V (c omm), and the voltage applied to the drain electrode (hereinafter also referred to as drain voltage (Vd)) is , 0.1V and 10V.

[0489] The measured transistor had a design value of 3 μm channel length and 50 μm channel width. The transistors had a single gate structure, and 20 measurements were taken for each sample.

[0490] [Reliability assessment] Next, a GBT test was carried out to evaluate the reliability of the transistor. The substrate on which the transistor is formed is kept at 60°C, and the source and drain of the transistor are A voltage of 0 V was applied to the input and 20 V or -20 V to the gate, and this state was maintained for one hour. Here, the PBTS test and the NBTIS test are shown in particular. In the experiment, the sample was irradiated with white LED light of approximately 10,000 lx.

[0491] [Result 1] 25A to 25D show the measured Id-Vg characteristics of the transistors. In the figure, two Id-Vg characteristics with different drain voltages (Vd) and I The field effect mobility (μFE) calculated from the d-Vg characteristics is also shown.

[0492] 25(A) to 25(D) show samples A1, A2, and The Id-Vg characteristics of samples A3 and A4 are shown in the figures and the following explanations. In order to simply indicate the composition of the metal oxide film corresponding to each sample, IGZO(516) It is written as, etc.

[0493] As shown in Figures 25(A) to 25(D), in the on-state, the current The maximum current value that can be achieved is the highest for sample A1, followed by sample A2, sample A3, and sample A4. This is presumably related to the In content. In material A4, the variation in electrical characteristics was greater than in the other conditions.

[0494] FIG. 25(E) shows the results of the PBTS test and the NBTIS test for samples A1 to A4. The change in threshold voltage (ΔVth) before and after the change is shown in FIG. The magnitude of ΔVth varies greatly depending on the composition of the semiconductor layer.

[0495] In the PBTS test, the variation of the threshold voltage was smallest in sample A1 (i.e., The tendency for the resistance to increase is seen in the order of sample A2, sample A3, and sample A4. In particular, sample A4 showed a significantly larger variation in threshold voltage than the other samples. .

[0496] On the other hand, in the NBTIS test, the threshold voltage of sample A1 was significantly lower than that of the other samples. Although the fluctuation is slightly large, the fluctuation is maintained below 2 V for all samples, which is satisfactory. It can be seen that this shows good reliability.

[0497] From the above results, it can be seen that the reliability of the transistor is affected by the metal oxide film used in the semiconductor layer. It has been confirmed that the lower the gallium content in the transistor, the more reliable the transistor can be. In particular, by using a metal oxide film with a low gallium content, it was possible to pass the PBTS test. It was confirmed that the amount of variation in threshold voltage can be reduced. The zinc content is greater than the gallium content, and the zinc content is less than the gallium content. By using a metal oxide film with a larger capacitance than that of the conventional semiconductor, it is possible to achieve both high field-effect mobility and high reliability. It was found that it is possible to realize a transistor with this structure.

[0498] [Result 2] Next, the Id-Vg characteristics of sample A5 are shown in Figure 26(A). As described above, sample A5 has the following characteristics: The semiconductor layer is a first metal oxide film (IGZO(111)) on which a second metal oxide film (IG This is a transistor using a stacked film of ZO(516)).

[0499] As shown in FIG. 26(A), sample A5 has a higher ZnO content than sample A1 (IGZO(516)). It was confirmed that sample A5 exhibited good electrical properties with little variation. 3 (IGZO(111)), it exhibits a higher on-state current and a higher field-effect mobility. Confirmed.

[0500] FIG. 26(B) shows the results of ΔVth before and after the reliability test of sample A5. For comparison, the results of Samples A1 and A3 are listed side by side.

[0501] Focusing on the PBTS test, the variation in threshold voltage of sample A5 was smaller than that of sample A1. In the NBTIS test, the threshold voltage was smaller than that of sample A3. In other words, in sample A5, the metal oxide film was used as a single film. It was found that the reliability was significantly higher than that of the conventional method.

[0502] Here, the factors that cause the threshold voltage fluctuation in the PBTS test are the gate insulating layer and the semiconductor One of the reasons is thought to be the defect level at or near the interface with the silicon layer. Therefore, from the results of FIG. 26(B), it is clear that the metal oxide film located on the gate insulating layer side is By placing a metal oxide film with a higher gallium content than the gallium content, the gate insulation This suggests that the defect level at or near the interface between the layer and the semiconductor layer can be reduced.

[0503] In addition, oxygen deficiency in the semiconductor layer is a factor that causes fluctuations in the threshold voltage in the NBTIS test. One of the reasons is thought to be the defect level caused by the loss. The results show that the second metal oxide film in contact with the gate insulating layer has a higher gallium content than the first metal oxide film. By stacking a high-density first metal oxide film, the density of such defect levels can be reduced. Furthermore, this suggests that gallium is more oxygen-efficient than indium and zinc. Considering that gallium is easily bonded to oxygen, the first metal oxide film containing a relatively large amount of gallium It is assumed that defects are less likely to occur.

[0504] In addition, in sample A5, the content of gallium is low and the second gold is relatively prone to oxygen deficiency. The thickness of the metal oxide film is made sufficiently thinner than that of the first metal oxide film, and the thickness of the metal oxide film is made sufficiently thinner than that of the first metal oxide film by heat treatment. As a result, sufficient oxygen is supplied from the gate insulating layer. The defects are sufficiently reduced, and as shown in FIG. 26(A), the variations are small and the traces are good. It is presumed that transistor characteristics have been obtained.

[0505] From the above results, it can be seen that the indium content is higher than the gallium content in the gate insulating layer. a second metal oxide film having a higher gallium content than the first metal oxide film; By using a semiconductor layer in which a first metal oxide film with high conductivity is laminated, extremely good electrical properties and It was found that it is possible to realize a transistor with extremely high reliability. [Example]

[0506] In this example, samples were prepared under different film formation conditions for the metal oxide layer formed on the insulating layer. , Thermal Desorption Spectroscopy (TDS) The results of evaluating the amount of oxygen and argon desorption from the insulating layer using ionization explain.

[0507] [Sample preparation] First, an insulating layer was formed on a glass substrate, similar to the second gate insulating layer shown in Example 1. Under these conditions, a first silicon oxynitride film with a thickness of about 5 nm and a second silicon oxynitride film with a thickness of about 130 nm were formed. The silicon oxynitride film and the third silicon oxynitride film having a thickness of about 5 nm were respectively formed by plasma The film was formed by the CVD method.

[0508] Subsequently, a heat treatment was carried out at 370° C. for 1 hour in a nitrogen atmosphere.

[0509] Next, a metal oxide film with a thickness of approximately 20 nm was formed on the insulating layer by sputtering. The metal oxide film was formed with the atomic ratio of metal elements In:Ga:Zn=4:2:4.1[ A metal oxide target having a [atomic ratio] was used.

[0510] Here, five samples (samples B1 to B2) were prepared using different deposition gases for the metal oxide film deposition. B5) were prepared.

[0511] Samples B1 to B4 are samples using a mixed gas of argon gas and oxygen gas as the deposition gas. For sample B1, the ratio of the flow rate of oxygen gas to the total flow rate of film-forming gas (hereinafter referred to as the flow rate ratio) was Sample B1 is a sample with a flow rate ratio of 10%. Sample B2 is a sample with a flow rate ratio of 30%. Sample B3 is a sample with an oxygen gas flow rate of 50%. Sample B4 is a sample with an oxygen gas flow rate of 50%. The flow rate ratio was 70%. Sample B5 was formed using only oxygen gas. This corresponds to a flow rate ratio of 100% for oxygen gas.

[0512] Next, each sample was heated at 370°C for 1 hour in a mixed atmosphere of oxygen and nitrogen gas. The heat treatment was carried out.

[0513] Thereafter, the metal oxide film was removed from each sample by wet etching.

[0514] Through the above steps, samples B1 to B5 were fabricated.

[0515] [TDS analysis] The TDS analysis was carried out on each of the above samples B1 to B5. The heating rate was 1 / min.

[0516] Figure 27 shows the results of TDS analysis of each sample. The results for a mass-to-charge ratio (M / z) of 32, which corresponds to argon, and a mass-to-charge ratio of 40, which corresponds to argon, are shown in Table 1. The horizontal axis is the substrate temperature (Sub. Temp.), The vertical axis is the detection intensity.

[0517] As shown in Figure 27, in each sample, oxygen molecules Significant desorption was confirmed, with a peak appearing in the range of 200°C to 250°C. The higher the oxygen flow rate ratio during deposition of the metal oxide film, the greater the amount of oxygen desorbed from the insulating layer. was confirmed.

[0518] On the other hand, significant desorption of argon was confirmed in the range of approximately 250 to 450°C. There is a peak in the range of 50 to 400°C. It was confirmed that the higher the ratio, the smaller the amount of argon desorption. Since almost no argon desorption was observed under the condition of 100% ratio, TD It is suggested that the argon desorbed in the S analysis originates from the deposition gas of the metal oxide film.

[0519] Figures 28(A) and 28(B) are the results calculated from the TDS analysis results shown in Figure 27. The quantitative results of desorption of oxygen molecules and argon are shown below. are.

[0520] As shown in FIG. 28(A), the higher the oxygen flow rate ratio during the deposition of the metal oxide film, the more the insulating layer It can be seen that the amount of desorbed oxygen molecules increases. When the metal oxide film is used as a metal insulating layer, the oxygen flow rate can be increased during film formation. It was confirmed that a large amount of oxygen could be supplied to the semiconductor layer.

[0521] In addition, from FIG. 28(B), the amount of argon desorbed from the insulating layer is also the same as that of the metal oxide film. It was confirmed that this can be controlled by the oxygen flow rate ratio during film formation. [Example]

[0522] In this example, samples (samples C1 to C4) having a stacked structure of an insulating film and a metal oxide film were prepared. The influence of the metal oxide film on the insulating film was evaluated.

[0523] [Sample preparation] First, a first silicon nitride film with a thickness of about 50 nm and a second silicon nitride film with a thickness of about 200 nm were formed on a quartz substrate. A second silicon nitride film, a third silicon nitride film about 50 nm thick, and an oxide film about 3 nm thick. A silicon nitride film was formed by laminating it using the plasma CVD method.

[0524] The first silicon nitride film was formed by adjusting the flow rates of silane gas, nitrogen gas, and ammonia gas to 2. The flow rates were 1000 sccm, 2000 sccm, and 100 sccm, the pressure was 100 Pa, and the film formation power was 20 The film was formed under the conditions of 100 W and a substrate temperature of 350°C.

[0525] The second silicon nitride film was formed by increasing the flow rates of silane gas, nitrogen gas, and ammonia gas to 2. 90sccm, 2000sccm, 2000sccm, pressure 200Pa, film formation power 3 The film was formed under the conditions of 1000 W and a substrate temperature of 350°C.

[0526] The third silicon nitride film was formed by increasing the flow rates of silane gas, nitrogen gas, and ammonia gas to 2. The flow rates were 1000 sccm, 2000 sccm, and 100 sccm, the pressure was 100 Pa, and the film formation power was 20 The film was formed under the conditions of 100 W and a substrate temperature of 350°C.

[0527] The silicon oxynitride film was grown using silane gas and nitrous oxide gas at flow rates of 20 sccm each. , 3000sccm, pressure 40Pa, film formation power 3000W, substrate temperature 350℃ The film was formed.

[0528] Subsequently, a metal oxide film having a thickness of about 30 nm was formed on the silicon oxynitride film. The atomic ratio of metal elements for the deposition of the oxide film is In:Ga:Zn=4:2:4.1 [atomic ratio A metal oxide film was formed by sputtering using a metal oxide target of The deposition gas used was a mixture of argon and oxygen gases, with the flow rate of oxygen gas set at 10 The film was formed under a pressure of 0.6 Pa and a power of 2.5 kW, and the substrate was heated. It went without a hitch.

[0529] Next, a heat treatment was performed. Sample C2 was heated at 350°C for 1 hour in a nitrogen gas atmosphere. After the heat treatment, the sample was heated at 350°C for 1 hour in a mixed atmosphere of nitrogen and oxygen gas. Sample C3 was heat treated at 370°C for 1 hour in a nitrogen gas atmosphere. Thereafter, heat treatment was carried out at 370° C. for 1 hour in a mixed atmosphere of nitrogen gas and oxygen gas. Sample C4 was heat-treated at 400°C for 1 hour in a nitrogen gas atmosphere, and then The specimen C1 was heat-treated at 400°C for 1 hour in a mixed atmosphere of silicon and oxygen gas. No heat treatment was performed. The mixed atmosphere of nitrogen gas and oxygen gas was nitrogen gas:oxygen gas. = 4:1 (volume ratio).

[0530] [ESR measurement] Next, electron spin resonance (ESR) ) was used to evaluate samples C1 to C4.

[0531] The ESR measurement was performed at a temperature of 85 K and with a high-frequency power of 9.2 GHz (microwave power The magnetic field was set to 10 mW, and the direction of the magnetic field was parallel to the film surface of the sample. The detection limit was 3.5 × 10 17 spins / cm 3 It was.

[0532] The ESR spectra of samples C1 to C4 are shown in FIG. 29(A). The horizontal axis indicates the g-factor, and the vertical axis indicates the ESR signal intensity (ESR s As shown in Figure 29(A), sample C1 has a signal intensity. Samples C2, C3, and C4 were below the detection limit.

[0533] An enlarged view of the ESR spectrum of sample C1 is shown in Figure 29(B). The peroxide radicals (POR) in silicon nitride films ) and the signal due to nitrogen dioxide (NO2) in the silicon oxynitride film. It is believed that overlapping signals were observed.

[0534] Here, the signal due to peroxide radicals is an asymmetric signal with a g value of around 2.00. On the other hand, the signal due to nitrogen dioxide (NO2) is due to the nuclear spin of nitrogen. The signal splits into three, and the three signals have g values ​​around 2.04 and 2.00, respectively. It is observed around 1.96.

[0535] For reference, the ES of a reference sample (Ref.) in which a silicon oxynitride film is formed on a quartz substrate The R spectrum is shown in FIG. 29(C). FIG. 29(C) shows the R spectrum of the silicon oxynitride film. This is a typical example of a signal caused by nitrogen dioxide (NO2). As shown, the ESR spectrum of sample C1 shows a signal caused by peroxide radicals (POR). It is thought that the signal due to nitrogen dioxide (NO2) overlaps with the null signal.

[0536] In addition, based on the shape of the signal caused by nitrogen dioxide (NO2), the nitrogen dioxide of sample C1 The spin density of the signal due to NO2 was calculated to be 9.9 × 10 18 sp ins / cm 3 The signal due to peroxide radicals (POR) was Signals due to oxidizing radicals (POR) and nitrogen dioxide (NO2) The spin density could not be calculated due to the overlapping of the spins.

[0537] From the above, when forming a metal oxide film on a silicon oxynitride film, Peroxide radicals (POR) are formed in the coating, and the POR is then heated. It was also found that the nitrogen dioxide (NO2 ) was found to be reduced by heat treatment. [Example]

[0538] In this example, a transistor according to one embodiment of the present invention was manufactured, and its electrical characteristics and reliability were evaluated. The results of the evaluation will be explained.

[0539] [Sample preparation] The structure of the manufactured transistor is the same as that of the transistor 100 illustrated in Embodiment 1. In other words, here, a transistor having a back gate electrode is used. The transistor 100A and the transistor 100 without a back gate electrode were fabricated in the same process. was produced.

[0540] First, a tungsten film with a thickness of approximately 100 nm was formed on a glass substrate by sputtering. This was then processed to obtain a first gate electrode. A first silicon nitride film having a thickness of about 240 nm, a second silicon nitride film having a thickness of about 60 nm, and a A silicon oxynitride film having a thickness of about 5 nm was formed by laminating it using the plasma CVD method.

[0541] The first to third silicon nitride films were formed under the same conditions as in Example 1 above.

[0542] Subsequently, a metal oxide film is formed on the first gate insulating layer in a single layer or by laminating the metal oxide film to a total thickness of about The metal oxide film was formed to a thickness of 30 nm and processed to obtain a semiconductor layer. Samples were prepared under five different conditions with different compositions.

[0543] Samples D1 and E1 have an atomic ratio of metal elements In:Ga:Zn=1:1:1 [atomic The metal oxide was deposited by sputtering using a metal oxide target so that the ratio of the metal oxide to the A mixed gas of argon gas and oxygen gas was used as the deposition gas. The flow rate ratio was set to 30%. The film was formed without heating the substrate.

[0544] Samples D2 to D5 and Samples E2 to E5 are made of a first metal oxide film having a thickness of about 25 nm. The samples consisted of a thin film and a second metal oxide film with a thickness of approximately 5 nm. The first metal oxide film was formed under the same conditions. A metal oxide target was used so that the atomic ratio was In:Ga:Zn=1:1:1. The metal oxide film was formed by sputtering using argon gas and oxygen gas. The flow rate of oxygen gas was set to 30%. It went without any problems.

[0545] Samples D2 and E2 are second metal oxide films in which the atomic ratio of metal elements is In:G. A metal oxide target was used for sputtering so that the atomic ratio of a:Zn was 4:2:3. The metal oxide film was formed by the deposition method. The deposition gas was a mixture of argon gas and oxygen gas. The mixed gas was used, and the flow rate ratio of oxygen gas was set to 10%. In addition, the deposition of the second metal oxide film was performed without exposing the first metal oxide film to the atmosphere after the deposition of the first metal oxide film. It went on continuously without a hitch.

[0546] Samples D3 and E3 are second metal oxide films in which the atomic ratio of metal elements is In:G. A metal oxide target was used for sputtering so that the atomic ratio of a:Zn was 5:1:6. The metal oxide film was formed by the deposition method. The deposition gas was a mixture of argon gas and oxygen gas. The mixed gas was used, and the flow rate of oxygen gas was set to 2%. The film was formed without heating the substrate. The second metal oxide film was formed by exposing the first metal oxide film to the atmosphere after the first metal oxide film was formed. It continued without a hitch.

[0547] Samples D4 and E4 are second metal oxide films in which the atomic ratio of metal elements is In:Z. Gold was deposited by sputtering using a metal oxide target with an atomic ratio of n=2:3. A mixed gas of argon gas and oxygen gas was used as the deposition gas. The flow rate ratio of the nitrogen gas was set to 2%. The film was formed without heating the substrate. The deposition of the second metal oxide film is carried out continuously after the deposition of the first metal oxide film without exposing it to the atmosphere. It was.

[0548] Samples D5 and E5 are second metal oxide films in which the atomic ratio of metal elements is In:S Sputtering using a metal oxide target with n:Si=80:9:11 [atomic ratio] The metal oxide film was formed by the deposition method. The deposition gas was a mixture of argon gas and oxygen gas. The gas used was oxygen gas with a flow rate of 6%. The film was formed without heating the substrate. Ta.

[0549] After the semiconductor layer was formed, it was subjected to a heat treatment at 350°C for 1 hour in a nitrogen gas atmosphere. The substrate was subjected to a heat treatment at 350° C. for 1 hour in a mixed atmosphere of nitrogen gas and oxygen gas.

[0550] Next, as a second gate insulating layer, a first silicon oxynitride film having a thickness of about 5 nm and a thickness of A second silicon oxynitride film having a thickness of about 140 nm and a third silicon oxynitride film having a thickness of about 5 nm. The films were formed by plasma CVD.

[0551] The first to third silicon oxynitride films were formed under the same conditions as in Example 1 above.

[0552] Subsequently, a metal oxide film was formed on the second gate insulating layer by sputtering. Here, the metal oxide film was formed under the following two conditions.

[0553] In the samples D1 to D5, a metal oxide film with a thickness of about 20 nm was formed. The atomic ratio of the metal elements in the film was In:Ga:Zn=4:2:3. A metal oxide target was used and the treatment was carried out in an oxygen-containing atmosphere.

[0554] In the samples E1 to E5, a metal oxide film with a thickness of about 5 nm was formed. Using an aluminum target, reactive sputtering was performed in an oxygen-containing atmosphere. The film was formed.

[0555] After forming the metal oxide film, it is heat-treated at 350°C for one hour in an atmosphere containing nitrogen and oxygen. It was done.

[0556] Next, a molybdenum film with a thickness of approximately 100 nm was deposited on the metal oxide film by sputtering. After that, the molybdenum film was removed by etching, and the second gate electrode and the metal In Samples D1 to D5, a molybdenum film and a metal oxide film were formed. On the other hand, in the samples E1 to E5, only the molybdenum film was removed by etching. Removed.

[0557] Next, using the second gate electrode as a mask, an addition process of boron as an impurity element is performed. The impurity was added using a plasma ion doping device. The gas used was B2H6 gas.

[0558] Next, a silicon oxynitride film approximately 300 nm thick is applied as a protective insulating layer to cover the transistor. Then, a protective insulating layer and a part of the second gate insulating layer were formed by plasma CVD. The opening is made by etching, and a molybdenum film is formed by sputtering. The source and drain electrodes were obtained by processing. Then, a planarization layer with a thickness of about 1.5 μm was formed. An acrylic film was formed and heat-treated in a nitrogen atmosphere at 250°C for one hour. .

[0559] By the above steps, samples D1 to D5 each having a transistor formed on a glass substrate were obtained. , and samples E1 to E5 were obtained.

[0560] [Transistor Id-Vg characteristics] Next, the Id-Vg characteristics of the transistor fabricated above were measured.

[0561] The measurement conditions for the Id-Vg characteristics of a transistor are the voltage applied to the gate electrode (hereinafter referred to as The gate voltage (Vg) is applied from -15V to +20V in 0.25V increments. In addition, the voltage applied to the source electrode (hereinafter referred to as the source voltage (Vs)) was set to 0 V (c omm), and the voltage applied to the drain electrode (hereinafter also referred to as drain voltage (Vd)) is , 0.1V and 10V.

[0562] The measured transistors had channel lengths of 1.5 μm, 2 μm, and 3 μm. The transistor was fabricated with the three conditions of 0.1 μm and a design value of the channel width of 50 μm. For D1 to D5, single gate transistors are used. For samples E1 to E5, single-gate transistors and dual-gate (D The number of measurements was 20 for each sample.

[0563] [Reliability assessment] Next, a GBT test was carried out to evaluate the reliability of the transistor. The substrate on which the transistor is formed is kept at 60°C, and the source and drain of the transistor are A voltage of 0 V was applied to the input and 20 V or -20 V to the gate, and this state was maintained for one hour. Here, the PBTS and NBTIS tests are shown in particular. The sample was irradiated with white LED light of approximately 10,000 lx.

[0564] [Result 1] FIG. 30A shows the transistors of Samples D1 to D5. In each figure, the Id-Vg characteristics of two different drain voltages (Vd) are shown. The field-effect mobility (μFE) calculated from the Id-Vg characteristics and the Id-Vg characteristics at Vd=10V was calculated. The figures are shown together.

[0565] In FIG. 30(A) and the following description, the composition and For convenience, we will use IGZO(111), IGZO(423), and IGZO(516 ), InZnO(2:3), ITSO, etc.

[0566] As shown in Figure 30(A), all samples had a small channel length of 1.5 μm. Even though it was a transistor, good characteristics were confirmed. Compared with D1, samples D2 to D5 with a stacked structure have the same Vg in the on-state. The result was that a large current could be passed through the electrode.

[0567] FIG. 30(B) shows the results of the PBTS test and the NBTIS test for samples D1 to D5. The amount of change in threshold voltage (ΔVth) before and after the test is shown.

[0568] Focusing on the PBTS test, ΔVth of sample D1 was the largest, and samples D2 to D5 In this case, ΔVth was half or less compared to sample D1.

[0569] On the other hand, when we look at the NBTIS test, specimens D4 and D5 have a ΔV Although th is slightly higher, the fluctuation is maintained below 2V in all cases, indicating good reliability. We can see that.

[0570] [Result 2] FIG. 31A shows the Id-Vg characteristics of the transistors of Samples E1 to E5. In samples E1 to E5, similar to samples D1 to D5, all samples were excellent. Excellent electrical properties have been obtained.

[0571] FIG. 31(B) shows the results of ΔVth before and after the reliability test for samples E1 to E5. There are.

[0572] Sample E1 had a large ΔVth in the PBTS test. This is because the In comparison, the metal oxide film formed on the gate insulating layer is different, which reduces the amount of oxygen entering the semiconductor layer. One of the reasons is thought to be a lack of supply.

[0573] However, in samples E2 to E5 in which the semiconductor layers have a stacked structure, the As a result, the ΔVth for the PBTS test was significantly reduced. The lower the gallium content of the metal oxide film, the smaller the ΔVth for the PBTS test. There was a tendency for this to occur.

[0574] On the other hand, in the NBTIS test, the amount of variation was small in all cases, but the amount of variation was particularly large in sample E4. It can be seen that is extremely small.

[0575] [Result 3] 32(A) and 32(B) show the dual gates in the samples E1 to E5. The results for transistors are shown.

[0576] As shown in Figure 32(A), the dual-gate transistor has a higher current density than the single-gate transistor. It can be seen that the variation in transistor characteristics is extremely small compared to the conventional method.

[0577] Furthermore, as shown in FIG. 32(B), in dual-gate transistors, NBTI is particularly It was confirmed that ΔVth for the S test was suppressed.

[0578] From the above results, it is clear that the indium content is higher than the gallium content in the gate insulating layer. a second metal oxide film having a thickness higher than that of the first metal oxide film and a thickness higher than that of the second metal oxide film and containing gallium; By using a semiconductor layer stacked with a first metal oxide film with a high conductivity, extremely good electrical properties are achieved. It was found that it is possible to realize a transistor with extremely high reliability. By applying a metal oxide film that does not contain gallium to the metal oxide film of 2, extremely good results were obtained. It was found that it was possible to realize a transistor that combines excellent electrical characteristics with extremely high reliability. In addition, gallium in the metal oxide film in contact with the gate insulating layer is This suggests that this is a factor in deterioration. [Example]

[0579] [Considerations on threshold voltage fluctuations during PBTS testing] In this example, the fluctuation of the threshold voltage in the PBTS test was considered. In particular, a metal oxide film having excess oxygen and a high gallium content is used for the semiconductor layer 108. Therefore, the reason for the large variation in threshold voltage in the PBTS test can be explained from the first principles. The following explanation will be given using the results of calculations.

[0580] The reason for the large variation in threshold voltage in the PBTS test is that electron trapping The formation of acceptor defects that release electrons and the disappearance of donor defects that release electrons are expected. Here, we consider the mechanism by which the threshold voltage fluctuation increases in the PBTS test. We focus on the formation of acceptor-type defects.

[0581] Here, the calculation model and calculation conditions used in the calculations performed below will be explained.

[0582] As a calculation model, In-Ga with In:Ga:Zn:O=1:1:1:4 [atomic ratio] A region corresponding to six atomic layers was cut out from the crystal structure of Zn-oxide. The total number of atoms is 56. If the structure is such that the total number of atoms included in the calculation model is 57 atoms.

[0583] Next, a vacuum layer was placed in the c-axis direction of the above region. In other words, the structure of the calculation model was It is a slab structure that has periodicity in the b-axis direction but no periodicity in the c-axis direction. The layer located on the top surface of the slab structure is made of either Ga or Zn, or both. The layer was composed of O and

[0584] The calculations were performed using the first-principles calculation software VASP (The Vienna Ab ini The tio simulation package was used. The calculation conditions are shown in Table 1. The Dipole Layer method was used to correct the vacuum layer. .

[0585] [Table 1]

[0586] In addition, the calculations related to the reaction paths explained below use the NEB (Natural Energy Boundary) method, which is a chemical reaction path search method. The Nudged Elastic Band (NEB) method is used. This is a method to find the state with the lowest energy among the states connecting the states. The height (energy difference) from the state where the energy is lowest to the state where the energy is lowest is called the reaction barrier. Let's say.

[0587] The above is an explanation of the calculation model and calculation conditions used in the calculations that will be performed hereinafter.

[0588] Next, defects before the PBTS test (also called the initial state) and defects during the PBTS test ( In this example, we will explain the defect candidates of the initial state and the final state. The defect in the state is a defect related to excess oxygen. It is placed on the top layer of the structure.

[0589] The initial state is a structure without electron traps. Assume a structure in which two oxygen atoms exist at the oxygen site. The structure that exists is sometimes called a split structure. Figure 33(A) shows the concept of a split structure. The figure is shown.

[0590] Figure 3 shows the density of states obtained by performing calculations on a calculation model with a split structure. 3(B). In FIG. 33(B), the horizontal axis is energy [eV]. The vertical axis is the density of states (DOS) [states / eV]. The horizontal axis is adjusted to 0 eV.

[0591] From Figure 33(B), the quasi-Fermi level is located above the intra-gap level (high energy side). Therefore, the split structure does not trap electrons, that is, it is not an acceptor. Therefore, the computational model with the split structure is set as the initial state.

[0592] The final state is a structure that traps electrons (acceptor-type defects). Assuming a structure in which oxygen is bonded to a gallium atom and has a dangling bond, The structure in which oxygen is bonded to a gallium atom and has a dangling bond is called G This is sometimes called the aO structure. Figure 34(A) shows a conceptual diagram of the Ga—O structure.

[0593] The density of states obtained by performing calculations on a calculation model with a Ga-O structure is shown in Figure 34. In FIG. 34(B), the horizontal axis is energy [eV]. The vertical axis is the density of states (DOS) [states / eV]. The horizontal axis is adjusted so that the highest level occupied by the electrons (the highest level occupied by the electrons) is 0 eV.

[0594] From Figure 34(B), the quasi-Fermi level is located below the intra-gap level (low energy side). In other words, acceptor defects are formed. Therefore, the Ga-O structure Therefore, the Ga-O structure The computational model is the final state.

[0595] Next, we investigated the difference in composition of the top surface of the calculation model before and after the PBTS test. The energy change in the reaction path from the initial state to the final state during the test, and the relationship between the initial state and the final state The change in the energy relationship between the states is evaluated using calculations.

[0596] It is assumed that the transistor is in an off state before the PBTS test. Before the PBTS test, no carriers were excited in the metal oxide film. The state under test is assumed to be the ON state. , carriers are excited in the metal oxide film.

[0597] The carriers are formed by hydrogen entering oxygen vacancies (V O H) is formed Therefore, in this calculation, one V O By placing H, The PBTS test is reproduced. O H is near the bottom surface of the calculation model, and is composed of In and O. The oxygen atoms were placed at the oxygen sites located in the constituent layers.

[0598] Here, two models with different compositions at the top surface of the model (calculation model 1A and Compared with calculation model 1A, calculation model 2A is This model assumes a metal oxide film with a high gallium content. In nitride films, the top surface of the film is likely to consist of a layer with a high gallium content. Therefore, compared with calculation model 1A, calculation model 2A has the top surface of the model as gallium. Specifically, the calculation model 1A is composed of a layer with a high content of Ga:Zn:O. = 1:1:2 [atomic ratio]. The top surface of the calculation model 2A is G This is a model composed of a:O=1:1 [atomic ratio]. In calculation model 2A, I A layer consisting of Ga and Zn is sandwiched between the top layer and the layer consisting of Ga and Zn. By substituting Zn for Ga in the layer composed of O or one or both of them, The atomic ratio in calculation model 2A is made consistent with that in calculation model 1A.

[0599] Using calculation model 1A, the energy change in the reaction pathway from the initial state to the final state, The results of calculating the energy relationship between the initial and final states are also explained.

[0600] The initial state is the calculation model 1A in which one split structure is placed in the model, and the final state is This is the calculation model 1A in which one Ga-O structure is placed in the model. and PBTS tests, the energy in the reaction pathway from the initial state to the final state The energy change was calculated using the NEB method. The calculation conditions were the same as those shown in Table 1. Ta.

[0601] Figure 35(A) shows the reaction from the initial state to the final state when using calculation model 1A. The calculation results of the energy change along the pathway are shown in Figure 35(A). In Figure 35(A), the horizontal axis indicates the reaction pathway. The left side of the figure is the initial state, and the right side is the final state. The dashed line in Figure 35(A) is the calculated value assuming the time before the PBTS test. The solid line in Figure 35(A) is the calculation result assuming the PBTS test. be.

[0602] Figure 35(A) shows that the results are better when the PBTS test is in progress than when the PBTS test is in progress. In this case, the reaction barrier is lowered and the final state is stabilized. In both the cases before and during the PBTS test, the initial energy The value of the energy of the initial state was smaller than that of the final state. Therefore, the threshold voltage in the PBTS test is The amount of fluctuation is estimated to be small.

[0603] Next, using calculation model 2A, the energy in the reaction path from the initial state to the final state is calculated. The energy change and the energy relationship between the initial state and the final state are calculated as follows: We will explain about this.

[0604] Figure 35(B) shows the reaction from the initial state to the final state when using calculation model 2A. The calculation results of the energy change along the pathway are shown in Figure 35(B). In Figure 35(B), the horizontal axis indicates the reaction pathway. The left side of the figure is the initial state, and the right side is the final state. The dashed line in Figure 35(B) is the calculated value assuming the time before the PBTS test. The solid line in Figure 35(B) is the calculation result assuming the PBTS test. be.

[0605] Figure 35(B) shows that the results are better when the PBTS test is in progress than when the PBTS test is in progress. In the case of PBT, the reaction barrier is lowered and the final state is stabilized. In the case of S test, the final energy value is higher than the initial energy value. This suggests that the final state is more stable than the initial state. Therefore, it is estimated that the variation in threshold voltage in the PBTS test is large. .

[0606] From the above, by using a metal oxide film with a high gallium content for the semiconductor layer 108, In other words, it is estimated that the fluctuation of the threshold voltage will be large. By using a metal oxide film with a low gallium content for the semiconductor layer 108, It is estimated that the amount of variation in the threshold voltage in the [Explanation of symbols]

[0607] 10, 10A-C: transistor, 100, 100A-C: transistor, 102: base Plate, 103: insulating layer, 103a-d: insulating film, 106: conductive layer, 108, 108a, b: Semiconductor layer, 108f: metal oxide film, 108n: low resistance region, 110: insulating layer, 110a -c: insulating film, 112: conductive layer, 112f: conductive film, 114: metal oxide layer, 114f: Metal oxide film, 116: insulating layer, 118: insulating layer, 120a, b: conductive layer, 140: impurity Physical elements, 141a, b, 142: opening

Claims

[Claim 1] a first insulating layer, a second insulating layer, a semiconductor layer, and a first conductive layer; the semiconductor layer, the second insulating layer, and the first conductive layer are stacked in this order on the first insulating layer; the second insulating layer has a laminated structure in which a first insulating film, a second insulating film, and a third insulating film are laminated in this order, and the first insulating film, the second insulating film, and the third insulating film each contain an oxide; the first insulating film has a portion in contact with the semiconductor layer, the semiconductor layer contains indium oxide; Semiconductor device.

Images