Image processing apparatus, mobile device, image processing method, and computer program

Abstract

To provide a photoelectric conversion device that can read out a result of accumulation in a short time during an accumulation period.SOLUTION: A photoelectric conversion device has: a plurality of pixels each including a sensor unit that generates pulses at a frequency in accordance with the frequency of photon reception, a counter that counts the number of the pulses, and a memory that stores a count value of the counter; and control means that performs control to: generate signals on the basis of the difference between a count value of the counter at the start of an accumulation period and a count value of the counter at the end of the accumulation period, has a first accumulation period and a second accumulation period in a full frame, the first accumulation period being shorter than the second accumulation period; and output the signals generated in the first accumulation period in a period from the end of the first accumulation period until the end of the second accumulation period.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, a moving body, a photoelectric conversion method, a computer program, and the like. [Background technology]

[0002] In recent years, photoelectric conversion devices have been developed that digitally count the number of photons incident on an avalanche photodiode (APD) and output the counted value from a pixel as a photoelectrically converted digital signal.

[0003] Furthermore, for example, Patent Document 1 describes a configuration in which a photoelectric conversion device having an APD can output multiple images whose accumulation periods overlap each other, thereby enabling continuous shooting even under low illumination. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 7223070 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when considering the image sensor of an in-vehicle camera installed on a moving object, for example, normal sensor driving performs recognition processing on a frame-by-frame basis, so in the case of 30 fps, for example, recognition processing can only be performed every 33.3 ms. Therefore, even if an object appears immediately after a frame change in an in-vehicle camera, recognition processing cannot be performed until the end of the frame.

[0006] In addition, in-vehicle cameras often have an accumulation period of at least 11 ms to suppress flicker caused by traffic lights, and by extending the accumulation period, especially in low light conditions, bright images are captured. However, because the accumulation period is long, subject blur occurs when capturing fast-moving objects, reducing the recognition rate.

[0007] Therefore, an object of the present invention is to provide a photoelectric conversion device that can read out the results of short-term accumulation midway. [Means for solving the problem]

[0008] A photoelectric conversion device according to one aspect of the present invention comprises: a sensor unit that emits pulses at a frequency corresponding to the frequency of receiving photons; a counter that counts the number of pulses; a plurality of pixels each including a memory for storing a count value of the counter; generating a signal based on a difference between the count values ​​of the counter at the start and end of an accumulation period; The image sensor is characterized by having a first accumulation period and a second accumulation period within a full frame, the first accumulation period being shorter than the second accumulation period, and having a control means that controls so that a signal generated during the first accumulation period is output between the end of the first accumulation period and the end of the second accumulation period. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a photoelectric conversion device that is capable of reading out the results of short-term accumulation midway. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating a configuration example of a photoelectric conversion element according to an embodiment of the present invention. [Figure 2] 2 is a diagram showing an example of the configuration of a sensor substrate 11. FIG. [Figure 3] 2 is a diagram showing an example of the configuration of a circuit board 21. FIG. [Figure 4] 2 and 3, the figure shows an equivalent circuit of the pixel 101 and the signal processing circuit 103 corresponding to the pixel 101. [Figure 5] 2 is a diagram schematically illustrating the relationship between the operation of an APD 201 and an output signal. FIG. [Figure 6]1 is a functional block diagram of a photoelectric conversion device 600 and a moving object 700 according to an embodiment. [Figure 7] 10 is a diagram for explaining a photoelectric conversion method performed by a camera control unit 605 according to an embodiment. FIG. [Figure 8] FIG. 10 is a diagram showing an example of an image of a plurality of divided frames. [Figure 9] FIG. 2 is a diagram illustrating a relationship between a memory circuit and a buffer according to an embodiment. [Figure 10] 10 is a flowchart showing details of an example of driving a photoelectric conversion element in the embodiment. [Figure 11] This is a continuation of the flowchart in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments. In each drawing, the same members or elements are designated by the same reference numerals, and duplicate descriptions will be omitted or simplified.

[0012] FIG. 1 is a diagram showing an example of the configuration of a photoelectric conversion element according to an embodiment of the present invention. The following description will be given taking as an example a photoelectric conversion device having a so-called stacked structure, in which the photoelectric conversion element 100 is configured by stacking and electrically connecting two substrates, a sensor substrate 11 and a circuit substrate 21. However, the photoelectric conversion element 100 may have a so-called non-stacked structure, in which the components included in the sensor substrate and the components included in the circuit substrate are arranged on a common semiconductor layer. The sensor substrate 11 includes a pixel region 12. The circuit substrate 21 includes a circuit region 22 that processes signals detected in the pixel region 12.

[0013] 2 is a diagram showing an example of the configuration of the sensor substrate 11. The pixel region 12 of the sensor substrate 11 includes a plurality of pixels 101 arranged two-dimensionally across multiple rows and columns. Each pixel 101 includes a photoelectric conversion unit 102 including an avalanche photodiode (hereinafter, referred to as APD).

[0014] Here, the photoelectric conversion unit 102 functions as a sensor unit that emits pulses at a frequency corresponding to the frequency of receiving photons. The number of rows and columns of the pixel array that forms the pixel region 12 is not particularly limited.

[0015] 3 is a diagram showing an example of the configuration of the circuit board 21. The circuit board 21 has a signal processing circuit 103 that processes charges photoelectrically converted by each photoelectric conversion unit 102 in FIG. 2, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit 111, a vertical signal line 113, a vertical scanning circuit 110, and an output circuit 114.

[0016] The vertical scanning circuit 110 receives control pulses supplied from the control pulse generating unit 115 and sequentially supplies the control pulses to a plurality of pixels arranged in the row direction. The vertical scanning circuit 110 uses logic circuits such as a shift register and an address decoder.

[0017] The signal output from the photoelectric conversion unit 102 of each pixel is processed by each signal processing circuit 103. The signal processing circuit 103 is provided with a counter, memory, etc., and digital values ​​are stored in the memory. In order to read the signal from the memory of each pixel where the digital signal is stored, the horizontal scanning circuit 111 inputs a control pulse that sequentially selects each column to the signal processing circuit 103.

[0018] A signal is output to the vertical signal line 113 from the signal processing circuit 103 of the pixel of the row selected by the vertical scanning circuit 110. The signal output to the vertical signal line 113 is output to the outside of the photoelectric conversion element 100 via the readout circuit 112 and the output circuit 114. The readout circuit 112 has a plurality of buffers built in, which are connected to each vertical signal line 113.

[0019] 2 and 3, a plurality of signal processing circuits 103 are arranged in an area overlapping the pixel area 12 in a plan view. A vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, an output circuit 114, and a control pulse generating unit 115 are arranged so as to overlap between an end of the sensor substrate 11 and an end of the pixel area 12 in a plan view.

[0020] In other words, the sensor substrate 11 has a pixel region 12 and a non-pixel region arranged around the pixel region 12. A vertical scanning circuit 110, a horizontal scanning circuit 111, a readout circuit 112, an output circuit 114, and a control pulse generating unit 115 are arranged in a region overlapping the non-pixel region in a plan view.

[0021] The arrangement of the vertical signal lines 113, the readout circuits 112, and the output circuits 114 is not limited to the example shown in Fig. 3. For example, the vertical signal lines 113 may be arranged extending in the row direction, and the readout circuits 112 may be arranged at the ends of the vertical signal lines 113. Furthermore, it is not necessary to provide one signal processing circuit 103 for each photoelectric conversion unit, and a configuration may be adopted in which one signal processing unit is shared by multiple photoelectric conversion units and performs signal processing sequentially.

[0022] FIG. 4 is a diagram showing an equivalent circuit of the pixel 101 in FIGS. 2 and 3 and the signal processing circuit 103 corresponding to the pixel 101. In FIG.

[0023] The APD 201 included in the photoelectric conversion unit 102 generates charge pairs in response to incident light through photoelectric conversion. One of the two nodes of the APD 201 is connected to a power supply line that supplies a drive voltage VL (first voltage). The other of the two nodes of the APD 201 is connected to a power supply line that supplies a drive voltage VH (second voltage) that is higher than the voltage VL.

[0024] In Figure 4, one node of the APD 201 is the anode, and the other node of the APD is the cathode. A reverse bias voltage is supplied to the anode and cathode of the APD 201 so that the APD 201 performs avalanche multiplication. With this voltage supplied, the charge generated by the incident light undergoes avalanche multiplication, generating an avalanche current.

[0025] When a reverse bias voltage is supplied, there are two modes: Geiger mode, in which the voltage difference between the anode and cathode is greater than the breakdown voltage, and linear mode, in which the voltage difference between the anode and cathode is close to or less than the breakdown voltage. An APD operating in Geiger mode is called a SPAD. In the case of a SPAD, for example, the voltage VL (first voltage) is -30V and the voltage VH (second voltage) is 1V.

[0026] The signal processing circuit 103 includes a quench element 202, a waveform shaping unit 210, a counter circuit 211, and a memory circuit 212. The quench element 202 is connected to a power supply line to which a drive voltage VH is supplied and one of the anode and cathode nodes of the APD 201.

[0027] The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the APD 201 and suppressing avalanche multiplication (quench operation).The quench element 202 also functions to return the voltage supplied to the APD 201 to the drive voltage VH by flowing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0028] 4 shows an example in which the signal processing circuit 103 includes a waveform shaping section 210, a counter circuit 211, and a memory circuit 212 in addition to the quench element 202. In FIG.

[0029] The waveform shaping unit 210 shapes the voltage change at the cathode of the APD 201 obtained when photons are detected, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 210. While Fig. 4 shows an example in which one inverter is used as the waveform shaping unit 210, a circuit in which multiple inverters are connected in series, or another circuit that has a waveform shaping effect, may also be used.

[0030] Counter circuit 211 counts the number of pulses output from waveform shaping unit 210 and holds the count value. When control pulse RES is supplied via drive line 213, the signal held in counter circuit 211 is reset. Here, counter circuit 211 generates a signal based on the difference between the count values ​​at the start and end of the accumulation period.

[0031] 3 is supplied to the memory circuit 212 via a drive line 214 (not shown in FIG. 3) in FIG. 4, and switches between electrical connection and disconnection between the counter circuit 211 and the vertical signal line 113. The memory circuit 212 functions as a memory that temporarily stores the count value of the counter, and outputs an output signal from the counter circuit 211 of the pixel to the vertical signal line 113.

[0032] Note that electrical connections may be switched by disposing a switch such as a transistor between the quench element 202 and the APD 201 or between the photoelectric conversion unit 102 and the signal processing circuit 103. Similarly, the supply of the voltage VH or the voltage VL to the photoelectric conversion unit 102 may be electrically switched using a switch such as a transistor.

[0033] 5 is a diagram schematically illustrating the relationship between the operation of the APD 201 and the output signal. The input side of the waveform shaping unit 210 is designated node A, and the output side is designated node B. Between time t0 and time t1, a potential difference of VH-VL is applied to the APD 201. When a photon is incident on the APD 201 at time t1, avalanche multiplication occurs in the APD 201, an avalanche multiplication current flows through the quench element 202, and the voltage at node A drops.

[0034] When the voltage drop amount further increases and the potential difference applied to the APD 201 decreases, the avalanche multiplication of the APD 201 stops as at time t2, and the voltage level of node A does not drop below a certain value.

[0035] After that, between time t2 and time t3, a current flows through node A to compensate for the voltage drop from voltage VL, and at time t3, node A settles to its original potential level. At this time, the part of the output waveform at node A that exceeds a certain threshold is shaped by waveform shaping unit 210 and output as a pulse signal at node B.

[0036] Next, a photoelectric conversion device 600 and a mobile object 700 according to an embodiment will be described. Fig. 6 is a functional block diagram of the photoelectric conversion device 600 and the mobile object 700 according to the embodiment. Note that some of the functional blocks shown in Fig. 6 are realized by causing a computer (not shown) included in the photoelectric conversion device 600 and the mobile object 700 to execute a computer program stored in a memory serving as a storage medium (not shown).

[0037] However, some or all of these functions may be implemented by hardware. Examples of hardware that can be used include dedicated circuits (ASICs) and processors (reconfigurable processors, DSPs). Furthermore, the functional blocks shown in Fig. 6 do not have to be built into the same housing, and may be configured as separate devices connected to each other via signal paths.

[0038] 1 to 5, an imaging optical system 601, an image processing unit 603, a recognition unit 604, a camera control unit 605, a storage unit 606, a communication unit 607, etc. The photoelectric conversion element 100 is configured by an avalanche photodiode for photoelectrically converting an optical image, as described in FIGS.

[0039] The photoelectric conversion device of the embodiment is mounted on a moving body 700, and a camera unit consisting of a set of an imaging optical system 601 and a photoelectric conversion element 100 is configured to capture images in at least one direction, for example, in front, behind, or to the side of the moving body. Note that a plurality of camera units may be provided on the moving body 700.

[0040] The image processing unit 603 generates a final image signal by performing image processing such as black level correction, gamma curve adjustment, noise reduction, digital gain adjustment, demosaic processing, and data compression on the image signal acquired by the photoelectric conversion element 100. If the photoelectric conversion element 100 has an on-chip color filter such as RGB, it is desirable for the image processing unit 603 to perform processing such as white balance correction and color conversion.

[0041] The output of the image processing unit 603 is supplied to a recognition unit 604, an ECU (Electric Control Unit) 701 of the moving object 700, and a camera control unit 605. The recognition unit 604 recognizes people, vehicles, etc. in the vicinity by performing image recognition based on the image signal, and issues a warning, etc. as necessary.

[0042] In this embodiment, the mobile body 700 is described using an example of an automobile, but the mobile body may be any mobile body such as an airplane, train, ship, drone, AGV, or robot.

[0043] The camera control unit 605 incorporates a CPU as a computer and a memory that stores a computer program, and controls each unit of the photoelectric conversion device 600 by the CPU executing the computer program stored in the memory.

[0044] The camera control unit 605 functions as a control means, and controls the length of the exposure period of each frame of the photoelectric conversion element 100 and the timing of the control signal CLK, for example, via a control pulse generation unit of the photoelectric conversion element 100.

[0045] The storage unit 606 includes a recording medium such as a memory card or a hard disk, and can store and read image signals. The communication unit 607 includes a wireless or wired interface, and outputs the generated image signals to the outside of the photoelectric conversion device 600 and receives various signals from the outside.

[0046] The ECU 701 incorporates a CPU as a computer and a memory that stores a computer program, and controls each part of the moving object 700 by the CPU executing the computer program stored in the memory.

[0047] The output of the ECU 701 is supplied to a vehicle control unit 702 and a display unit 703. The vehicle control unit 702 functions as a movement control means that drives, stops, controls the direction, etc. of the vehicle as a moving object based on the output of the ECU 701. The display unit 703 functions as a display means, and includes display elements such as a liquid crystal device or an organic EL, and is mounted on the moving object 700.

[0048] The display unit 703 displays images acquired by the photoelectric conversion element 100 and various information relating to the vehicle's running state and the like to the driver of the vehicle 700 using, for example, a GUI based on the output of the ECU 701 .

[0049] In addition, the image processing unit 603, the recognition unit 604, etc. in Figure 6 do not have to be mounted on the mobile body 700, and may be provided, for example, in an external terminal provided separately from the mobile body 700, for remotely controlling the mobile body 700 or for monitoring the movement of the mobile body.

[0050] 7 is a diagram for explaining a photoelectric conversion method by the camera control unit 605 according to the embodiment. In this embodiment, photoelectric conversion is periodically driven at, for example, 30 full frames per second. Furthermore, a frame corresponding to one vertical period having a length of 33.3 ms is called a full frame, and each of the four divisions of a full frame is called a frame.

[0051] That is, as shown in FIG. 7, a full frame 1 from time T0 to time T12 is divided into frames 1_1, 1_2, 1_3, and 1_4, each having an equal period (8.33 ms).

[0052] Frame 1_1 has an accumulation period (photoelectric conversion period) from start time T0 of full frame 1 to time T1, frame 1_2 has an accumulation period from time T0 to time T2, frame 1_3 has an accumulation period from time T0 to time T3, and frame 1_4 has an accumulation period from time T0 to time T4.

[0053] At time T0, the counter circuit 211 is reset, and count values ​​C1_1, C1_2, C1_3, and C1_4 are obtained from the counter circuit 211 at times T1 to T4, respectively.

[0054] The count values ​​C1_1, C1_2, C1_3, and C1_4 are temporarily stored in the memory circuit 212. The signals for one row temporarily stored in the memory circuit 212 are sequentially output from the photoelectric conversion elements via the buffer of the readout circuit 112.

[0055] As described above, according to this embodiment, the signals accumulated during the period of frame 1_1 are read out from time T1 to T2 and are promptly processed by the recognition unit 604. Therefore, image recognition can be performed promptly. Similarly, the signals accumulated during the periods of frame 1_2, frame 1_3, and frame 1_4 are sequentially read out from time T2 to T3, from T3 to T4, and from T4 to T1, respectively, and image recognition can be performed repeatedly.

[0056] FIG. 8 is a diagram showing an example of images of multiple divided frames. As shown in FIG. 8, the image of frame 1_1 is dark because the accumulation period is short, but there is little subject blur of a person who suddenly appears in front of the camera. On the other hand, the accumulation periods become longer in the order of frame 1_2, frame 1_3, and frame 1_4, so subject blur is more likely to occur. Note that stopped vehicles and white lines are less likely to blur, and the longer the accumulation period, the more likely the contrast is to improve.

[0057] In this manner, in this embodiment, there are a first accumulation period and a second accumulation period within a full frame, the first accumulation period is shorter than the second accumulation period, and the signal generated during the first accumulation period is controlled to be output between the end of the first accumulation period and the end of the second accumulation period.

[0058] In this embodiment, the first and second accumulation periods overlap, starting at the same time, and the end of the second accumulation period coincides with the end of a full frame, making the second accumulation period an integer multiple of the first accumulation period.

[0059] However, the second accumulation period does not need to be an integer multiple of the first accumulation period, as long as the second accumulation period is longer than the first accumulation period (the first accumulation period is shorter than the second accumulation period) and the second accumulation period ends after the first accumulation period also ends.

[0060] That is, an image with a short accumulation period and an image with a long accumulation period are created, and the timing at which the short accumulation period ends is set earlier than the timing at which the long accumulation period ends. As soon as the short accumulation period ends, that image is output and sent to a downstream recognition unit. The subject is recognized based on signals generated during at least the first accumulation period. The recognition unit 604 as a recognition means recognizes the subject based on signals generated during at least the first accumulation period.

[0061] Therefore, while conventionally image recognition was not possible until a full frame had elapsed, in this embodiment, image recognition can be performed after as little as a quarter full frame period, and for example, when a moving object is moving at high speed, obstacles and the like can be recognized quickly. Therefore, it becomes possible to apply the brakes quickly, or to avoid the obstacle early.

[0062] In addition, an image with a long accumulation period can improve contrast, and therefore can be used as a display image. That is, an image with a short accumulation period is suitable for quick subject recognition, and an image with a long accumulation period is suitable for a display image. In this way, the display device of this embodiment displays the signal generated during at least the second accumulation period as an image.

[0063] Furthermore, because this embodiment uses an APD, unlike a CMOS sensor, the accumulated charge does not deteriorate when read out, so accumulation periods can be overlapped. Also, because there is no readout noise, the original signal does not deteriorate no matter how many times it is read out from a single accumulation.

[0064] Fig. 9 is a diagram showing the relationship between memory circuits and buffers in an embodiment. Fig. 9 shows a state in which memory circuits 212 in signal processing circuit 103 in Fig. 3 are arranged in N rows and M columns, and each memory circuit is represented as memory 1-1 to memory NM. Also, buffer 1 to buffer M in Fig. 9 represent buffers included in read circuit 112 in Fig. 3. Output circuit 114 in Fig. 9 corresponds to output circuit 114 in Fig. 3.

[0065] Fig. 10 is a flowchart showing details of an example of driving a photoelectric conversion element in an embodiment, and Fig. 11 is a flowchart that follows Fig. 10. Note that the operations of the steps in the flowcharts of Fig. 10 and Fig. 11 are performed sequentially by a CPU or the like serving as a computer in the camera control unit 605 executing a computer program stored in memory.

[0066] 10, i is set to 1. Next, in step S102, the count value Count of the counter circuit 211 at time Ti is output to the memory circuit 212. At this time, output is performed simultaneously to all memory circuits. This operation corresponds to the operation at time T1 in FIG.

[0067] Next, set j = 1 in step S103, and in step S104, output the count value Count(j - k - i) in the memory circuit j - k in FIG. 9 to the buffer. At this time, output to the buffer simultaneously for columns 1 to M. This operation means the operation of taking in the count value of the first row in FIG. 9 into the buffer.

[0068] Next, set k = 1 in step S105, and in step S106, output the count value Count(j - k - i) of buffer k to the output circuit 114. This operation corresponds to the operation of reading out the signal of the buffer in the leftmost column in FIG. 9 from the output circuit.

[0069] Next, proceed to step S107 in FIG. 11 via A, and in step S107, determine whether k < M. If Yes, then in step S108, increment k by 1 as k = k + 1, and return to step S106 via B to perform the operation of step S106. This operation corresponds to the operation of reading out the signal of the buffer in the second column from the left in FIG. 9 from the output circuit.

[0070] If it becomes No in step S107, that is, if k = M, it means that the signal of the buffer in the Mth column in FIG. 9 has been read out from the output circuit. Next, proceed to step S109 and determine whether j < N. If Yes in step S109, then in step S110, increment j by 1 as j = j + 1, and return to step S104 via C. This corresponds to the operation for starting the reading of the next row.

[0071] If it is determined to be No in step S109, it means that the reading of all rows has ended. So, proceed to step S111 and determine whether j < 4. If it is determined to be Yes in step S111, then increment i by 1 as i = i + 1 and return to step S102 via D. This operation corresponds to the operation of starting the reading at the next time T2.

[0072] If the determination in step S111 is No, this means that the readout at time T4 is completed, so the process proceeds to step S113, where the counter circuit 211 is reset with a reset signal. This operation corresponds to the reset operation of the counter circuit 211 at time T4 in Fig. 7. In this way, the signals accumulated in the photoelectric conversion element 100 can be read out sequentially.

[0073] The present invention has been described in detail above based on its preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications are possible based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0074] For example, in the above embodiment, accumulation is performed for a minimum of 1 / 4 full frame period, but the length of the minimum accumulation period may be changed to, for example, 1 / 5 full frame period or 1 / 3 full frame period depending on the recognition accuracy of the recognition unit 604. Alternatively, the length of the minimum accumulation period may be changed depending on the brightness of the subject.

[0075] Furthermore, even if the readout cycle is set to every 1 / 4 full frame period, the counter circuit may be reset midway through the accumulation period of frame 1_1 in Fig. 7 depending on the brightness of the subject, the image recognition accuracy, etc. As a result, the effective accumulation period may be made shorter than the 1 / 4 full frame period.

[0076] Alternatively, the counter circuit may be reset once at time T1 in Fig. 7. This may adjust the count value read out at time T4. Note that this embodiment includes the following combinations.

[0077] (Configuration 1) A photoelectric conversion device characterized by having a plurality of pixels, each pixel having a sensor unit that emits pulses at a frequency corresponding to the frequency of receiving photons, a counter that counts the number of said pulses, and a memory that stores the count value of said counter, and a control means that generates a signal based on the difference between the count values ​​of said counter at the start and end of an accumulation period, has a first accumulation period and a second accumulation period within a full frame, said first accumulation period is shorter than said second accumulation period, and controls so that the signal generated in said first accumulation period is output between the end of said first accumulation period and the end of said second accumulation period.

[0078] (Configuration 2) The photoelectric conversion device according to configuration 1, wherein the first accumulation period and the second accumulation period overlap.

[0079] (Configuration 3) The photoelectric conversion device according to configuration 2, wherein the first accumulation period and the second accumulation period start simultaneously.

[0080] (Configuration 4) The photoelectric conversion device according to any one of configurations 1 to 3, wherein the end of the second accumulation period coincides with the end of a full frame.

[0081] (Configuration 5) The photoelectric conversion device according to any one of configurations 1 to 4, further comprising a recognition means for recognizing a subject based on a signal generated during at least the first accumulation period.

[0082] (Configuration 6) The photoelectric conversion device according to configuration 5, wherein the recognition means further recognizes the subject based on a signal generated during the second accumulation period.

[0083] (Configuration 7) The photoelectric conversion device according to any one of configurations 1 to 6, further comprising a display means for displaying, as an image, at least the signal generated during the second accumulation period.

[0084] (Configuration 8) The photoelectric conversion device according to any one of configurations 1 to 7, wherein the sensor section includes an avalanche photodiode.

[0085] (Configuration 9) The photoelectric conversion device according to any one of configurations 1 to 8, and a movement control means for controlling the movement of the moving body.

[0086] (Method) A photoelectric conversion method for performing photoelectric conversion using a plurality of pixels, each of which has a sensor unit that emits pulses at a frequency corresponding to the frequency of receiving photons, a counter that counts the number of said pulses, and a memory that stores the count value of said counter, characterized in that a signal is generated based on the difference between the count values ​​of said counter at the start and end of an accumulation period, and the photoelectric conversion method has a first accumulation period and a second accumulation period within a full frame, the first accumulation period is shorter than the second accumulation period, and the signal generated during the first accumulation period is controlled to be output between the end of the first accumulation period and the end of the second accumulation period.

[0087] (Program) A computer program for controlling the photoelectric conversion device according to any one of configurations 1 to 8 or each means of the moving body according to configuration 9 by a computer.

[0088] Note that a computer program that realizes part or all of the control in this embodiment and the functions of the above-described embodiment may be supplied to the photoelectric conversion device via a network or various storage media. Then, a computer (or a CPU, MPU, etc.) in the photoelectric conversion device may read and execute the program. In this case, the program and the storage medium storing the program constitute the present invention. [Explanation of symbols]

[0089] 11: Sensor board 12: Pixel area 21: Circuit board 22: Circuit area 100: Photoelectric conversion element 101: Pixel 102: Photoelectric conversion unit 103: Signal processing circuit 110: Vertical scanning circuit 111: Horizontal scanning circuit 112: Readout circuit 113: Vertical signal line 114: Output circuit 115: Control pulse generation unit 201: Avalanche photodiode 202: Quench element 210: Waveform shaping section 211: Counter circuit 212: Memory circuit 213: Drive line 600: Photoelectric conversion device 601: Imaging optical system 603: Signal processing unit 604: Recognition part 605: Camera control unit 606: Storage section 607: Communications Department

Claims

1. Setting means for setting a first period and a second period longer than the first period within one imaging cycle, A first acquisition means for acquiring a first signal generated by exposure during the first period, A second acquisition means for acquiring a second signal generated by exposure during the second period, Between the end of the first period and the end of the second period, an output means outputs the first signal to an image recognition process that recognizes a subject based on the signal, It has, The first period and the second period overlap, The first signal and the second signal are generated from the same pixel. An image processing apparatus characterized by the following:

2. The image processing apparatus according to claim 1, characterized in that the first period and the second period start simultaneously.

3. The image processing apparatus according to claim 1, characterized in that the end of the second period coincides with the end of one imaging cycle.

4. The image processing apparatus according to claim 1, characterized by having recognition means for recognizing an object based on signals generated in at least the first period.

5. The image processing apparatus according to claim 4, wherein the recognition means further recognizes the subject based on the signal generated during the second period.

6. The image processing apparatus according to claim 1, further comprising display means for displaying signals generated during at least the second period as an image.

7. An image processing apparatus according to any one of claims 1 to 6, A mobile body characterized by having a movement control means for controlling the movement of the mobile body.

8. A setting step of setting a first period and a second period longer than the first period within one imaging cycle, A first acquisition step of acquiring a first signal generated by exposure during the first period, A second acquisition step of acquiring a second signal generated by exposure during the second period, Between the end of the first period and the end of the second period, an output step is performed in which the first signal is output to an image recognition process that recognizes a subject based on the signal, It has, The first period and the second period overlap, The first signal and the second signal are generated from the same pixel. An image processing method characterized by the following:

9. A computer program for causing a computer to function as an image processing apparatus according to any one of claims 1 to 6 or as a means for a mobile body according to claim 7.

Images