System and method for scalable control of superconducting qubits

Abstract

A scalable two-dimensional surface code system comprises four sublattices of qubits, each selectively controlled by a set of analog lines. Eight sets of analog lines selectively control eight sets of qubit-to-qubit couplers. The qubits and couplers have a response homogenization device with a control structure for applying analog signals and a DAC for applying a static bias to the qubits and couplers. A second surface code layer compensates for defective qubits. A quantum processor and a method for moving data within the quantum processor are described. The quantum processor has a quantum logic unit with a plurality of physical qubits and couplers. The logic unit has a plurality of logical qubit blocks that constitute a two-local interaction register. A shift register block is provided having one or more logical qubit blocks and a merge block connecting adjacent logical qubit blocks. The shift register block is selectively and communicatively coupled to the two-local interaction register by the merge block.

Description

Technical Field

[0001] Cross - reference to Related Applications This patent application claims the benefit of priority of U.S. Patent Application No. 63 / 356,663, filed on June 29, 2022. This patent application also claims the benefit of priority of U.S. Patent Application No. 63 / 390,185, filed on July 18, 2022, and this patent application also claims the benefit of priority of U.S. Patent Application No. 63 / 448,414, filed on February 27, 2023. The entire disclosures of these are hereby incorporated by reference in their entirety.

[0002] Field The present disclosure generally relates to scalable control of superconducting qubits, and more particularly to scalable control of superconducting qubits implementing surface codes.

Background Art

[0003] Background Hybrid Computing Systems Including Quantum Processors A hybrid computing system can include a digital or classical computer communicatively coupled to an analog computer. In some embodiments, the analog computer is a quantum computer.

[0004] The digital computer can include a digital processor that can be used to execute classical digital processing tasks described in the present system and method. The digital computer can include at least one system memory, and the at least one system memory can be used to store various sets of computer or processor - readable instructions, application programs, and / or data.

[0005] A quantum computer can include a quantum processor that includes programmable elements such as qubits, couplers, and other devices. The quantum processor can take the form of a superconducting quantum processor. The superconducting quantum processor can include several superconducting qubits and associated local bias devices. The superconducting quantum processor can also include a coupler (also known as a coupling device) that selectively provides communicable couplings between the qubits. The qubits can be read out via a readout system, and the results can be communicated to a digital computer. The qubits and couplers can be controlled by a qubit control system and a coupler control system, respectively. In some embodiments, the qubit and coupler control systems can be used to perform quantum annealing on an analog computer.

[0006] The above examples of related art and the limitations related thereto are not exclusive and are intended to be illustrative. Other limitations of the related art will become apparent to those skilled in the art upon reading this specification and examining the drawings. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0007] SUMMARY A scalable control system is described. The system includes a first plurality of qubits, a second plurality of qubits, a third plurality of qubits, and a fourth plurality of qubits. The first, second, third, and fourth pluralities of qubits are arranged in a two-dimensional array. At least one qubit in the first plurality of qubits and at least one qubit in the second plurality of qubits are each communicably directly coupled to each of two qubits in the third plurality of qubits and each of two qubits in the fourth plurality of qubits. The system further includes a fourth plurality of qubits, a first set of analog lines communicably coupled to selectively provide an analog signal to each of the qubits in the first plurality of qubits, a second set of analog lines communicably coupled to selectively provide an analog signal to each of the qubits in the second plurality of qubits, a third set of analog lines communicably coupled to selectively provide an analog signal to each of the qubits in the third plurality of qubits, and a fourth set of analog lines communicably coupled to selectively provide an analog signal to each of the qubits in the fourth plurality of qubits. The system may further include a first plurality of couplers, where each coupler in the first plurality of couplers communicably directly couples each qubit in the first plurality of qubits to each qubit in the third plurality of qubits or each qubit in the second plurality of qubits to each qubit in the third plurality of qubits, and a second plurality of couplers, where each coupler in the second plurality of couplers communicably directly couples each qubit in the first plurality of qubits to each qubit in the fourth plurality of qubits or each qubit in the second plurality of qubits to each qubit in the fourth plurality of qubits. Each qubit in the first, second, third, and fourth pluralities of qubits may be a respective fluxonium qubit. Each fluxonium qubit may include a respective mechanical inductor, and the mechanical inductor includes a segment of a mechanical inductance material.Each qubit within the first, second, third, and fourth plurality of qubits can be a respective transmon qubit. Each qubit within the first and second plurality of qubits is each a data qubit, and each qubit within the third and fourth plurality of qubits is each a stabilizer qubit, and each stabilizer qubit is operable to perform a parity measurement on a nearest neighbor qubit. Each set of analog lines within the first, second, third, and fourth sets of analog lines can include respective ones of a first very high frequency (VHF) control line. The first VHF control line within the first set of analog lines is inductively coupled to the qubit body of each qubit within the first plurality of qubits to control rotation about an axis in the XY plane of the Bloch sphere, the first VHF control line within the second set of analog lines is inductively coupled to the qubit body of each qubit within the second plurality of qubits to control rotation about an axis in the XY plane of the Bloch sphere, the first VHF control line within the third set of analog lines is inductively coupled to the qubit body of each qubit within the third plurality of qubits to control rotation about an axis in the XY plane of the Bloch sphere, and the first VHF control line within the fourth set of analog lines is inductively coupled to the qubit body of each qubit within the fourth plurality of qubits to control rotation about an axis in the XY plane of the Bloch sphere. Each set of the first, second, third, and fourth sets of analog lines can further include respective ones of a second VHF control line and at least one respective analog bias line. Each of the second VHF control lines within the first set of analog lines is inductively coupled to the composite Josephson junction (CJJ) of each qubit within the first plurality of qubits to control rotation about the Z-axis of the Bloch sphere, each of the second VHF control lines within the second set of analog lines is inductively coupled to the CJJ of each qubit within the second plurality of qubits to control rotation about the Z-axis of the Bloch sphere, each of the second VHF control lines within the third set of analog lines is inductively coupled to the CJJ of each qubit within the third plurality of qubits to control rotation about the Z-axis of the Bloch sphere, and each of the second VHF control lines within the fourth set of analog lines is inductively coupled to the CJJ of each qubit within the fourth plurality of qubits to control rotation about the Z-axis of the Bloch sphere.Each analog bias line in at least one of the first, second, third, and fourth sets of analog lines can be inductively coupled to each composite Josephson junction (CCJJ) within each qubit of the first, second, third, and fourth plurality of qubits. For each qubit within the first, second, third, and fourth plurality of qubits, the system is communicatively coupled to each qubit body of each qubit within the first, second, third, and fourth plurality of qubits to apply an analog signal from one of the first, second, third, and fourth sets of analog lines to each of the qubits within the first, second, third, and fourth plurality of qubits, respectively, each of the first control structures operable to do so; communicatively coupled to each qubit body of each qubit within the first, second, third, and fourth plurality of qubits, each of the first digital / analog converters (DACs) operable to apply a static bias to each of the qubit bodies of each qubit within the first, second, third, and fourth plurality of qubits; communicatively coupled to each composite Josephson junction (CCJJ) of each qubit within the first, second, third, and fourth plurality of qubits, each of the second control structures operable to apply an analog signal from one of the first, second, third, and fourth sets of analog lines to each of the CCJJs of each qubit within the first, second, third, and fourth plurality of qubits, respectively; and communicatively coupled to each CCJJ of each qubit within the first, second, third, and fourth plurality of qubits, each of the second DACs operable to apply a static bias to each of the CCJJs of each qubit within the first, second, third, and fourth plurality of qubits.

[0008] A scalable control system is described. The system includes a first plurality of qubits, a second plurality of qubits, a third plurality of qubits, and a fourth plurality of qubits, wherein at least one qubit in the first plurality of qubits and at least one qubit in the second plurality of qubits are each communicatively directly coupled to each of two qubits in the third plurality of qubits and each of two qubits in the fourth plurality of qubits; a first plurality of couplers, wherein each coupler in the first plurality of couplers communicatively directly couples each qubit in the first plurality of qubits to each qubit in the third plurality of qubits or each qubit in the second plurality of qubits to each qubit in the third plurality of qubits; a second plurality of couplers, wherein each coupler in the second plurality of couplers communicatively directly couples each qubit in the first plurality of qubits to each qubit in the fourth plurality of qubits or each qubit in the second plurality of qubits to each qubit in the fourth plurality of qubits; a first set of analog coupler lines, wherein each line in the first set of analog coupler lines is coupled to selectively provide a first analog signal to each coupler in a first subset of the second plurality of couplers; a second set of analog coupler lines, wherein each line in the second set of analog coupler lines is coupled to selectively provide a second analog signal to each coupler in a second subset of the second plurality of couplers; a third set of analog coupler lines, wherein each line in the third set of analog coupler lines is coupled to selectively provide a third analog signal to each coupler in a third subset of the second plurality of couplers; a fourth set of analog coupler lines, wherein each line in the fourth set of analog coupler lines is coupled to selectively provide a fourth analog signal to each coupler in a fourth subset of the second plurality of couplers; a fifth set of analog coupler lines, wherein...Each line within the fifth set of analog coupler lines is coupled to selectively provide a fifth analog signal to each coupler within a first subset of the first plurality of couplers, the fifth set of analog coupler lines; and a sixth set of analog coupler lines, wherein each line within the sixth set of analog coupler lines is coupled to selectively provide a sixth analog signal to each coupler within a second subset of the first plurality of couplers, the sixth set of analog coupler lines; and a seventh set of analog coupler lines, wherein each line within the seventh set of analog coupler lines is coupled to selectively provide a seventh analog signal to each coupler within a third subset of the first plurality of couplers, the seventh set of analog coupler lines; and an eighth set of analog coupler lines, wherein each line within the eighth set of analog coupler lines is coupled to selectively provide an eighth analog signal to each coupler within a fourth subset of the first plurality of couplers, the eighth set of analog coupler lines. Each qubit within the first, second, third, and fourth pluralities of qubits can be a respective fluxonium qubit. Each fluxonium qubit can include a respective mechanical inductor, and the mechanical inductor can include a segment of a mechanical inductance material. Each qubit within the first, second, third, and fourth pluralities of qubits can be a respective transmon qubit. Each qubit within the first and second pluralities of qubits is a respective data qubit, and each qubit within the third and fourth pluralities of qubits is a respective stabilizer qubit, and each stabilizer qubit is operable to perform a parity measurement on a nearest neighbor qubit. Each analog line within the first, second, third, fourth, fifth, sixth, seventh, and eighth sets of analog coupler lines can include a respective first very high frequency (VHF) control line. Each VHF line within the first, second, third, fourth, fifth, sixth, seventh, and eighth sets of analog coupler lines can be operable to apply control pulses having low and high operating levels to each coupler within the first and second pluralities of couplers. Each analog line within the first, second, third, fourth, fifth, sixth, seventh, and eighth sets of analog coupler lines can further include at least one additional analog line. Each coupler within the first and second pluralities of couplers,The system may further include respective first digital / analog converters (DACs) communicatively coupled to respective coupler bodies of each coupler within the first and second pluralities of couplers and operable to apply a static bias to respective coupler bodies of each coupler within the first and second pluralities of couplers, respective control structures communicatively coupled to respective composite Josephson junctions (CCJJs) of each coupler within the first and second pluralities of couplers and operable to apply an analog signal from one of the first, second, third, fourth, fifth, sixth, seventh, and eighth sets of analog lines to respective CCJJs of each coupler within the first and second pluralities of couplers, and respective second DACs communicatively coupled to respective CCJJs of each coupler within the first and second pluralities of couplers and operable to apply a static bias to respective CCJJs of each coupler within the first and second pluralities of couplers.,

[0009] A method of operating a quantum processor is described. The quantum processor includes a first plurality of qubits, a second plurality of qubits, a third plurality of qubits, and a fourth plurality of qubits, wherein at least one qubit in the first plurality of qubits and at least one qubit in the second plurality of qubits are communicatively directly coupled to each of two qubits in the third plurality of qubits and to each of two qubits in the fourth plurality of qubits; a first plurality of couplers, each coupler of the first plurality of couplers providing a communicative direct coupling between one of the first plurality of qubits and one of the third plurality of qubits or between one of the second plurality of qubits and one of the third plurality of qubits; and a second plurality of couplers, each coupler of the second plurality of couplers providing a communicative direct coupling between one of the first plurality of qubits and one of the fourth plurality of qubits or between one of the second plurality of qubits and one of the fourth plurality of qubits. The method is executed by a digital processor communicatively coupled to the quantum processor.This method is to apply a pulse signal to a plurality of third and fourth qubits, thereby initializing the qubits in the plurality of third and fourth qubits to their respective ground states by applying the pulse signal, applying a Hadamard transformation to the qubits in the plurality of third qubits, using the qubits in the second plurality of qubits as controls and the qubits in the fourth plurality of qubits as targets to apply a first CNOT gate, and using the qubits in the first plurality of qubits as targets and the qubits in the third plurality of qubits as controls to apply a second CNOT gate simultaneously, using the qubits in the first plurality of qubits as controls and the qubits in the fourth plurality of qubits as targets to apply a third CNOT gate and using the qubits in the second plurality of qubits as targets and the qubits in the third plurality of qubits as controls to apply a fourth CNOT gate simultaneously, using the qubits in the first plurality of qubits as controls and the qubits in the fourth plurality of qubits as targets to apply a fifth CNOT gate and using the qubits in the second plurality of qubits as targets and the qubits in the third plurality of qubits as controls to apply a sixth CNOT gate simultaneously, using the qubits in the second plurality of qubits as controls and the qubits in the fourth plurality of qubits as targets to apply a seventh CNOT gate and using the qubits in the first plurality of qubits as targets and the qubits in the third plurality of qubits as controls to apply an eighth CNOT gate simultaneously, applying a Hadamard transformation to the qubits in the plurality of third qubits, and reading out each state of each of the qubits in the plurality of third and fourth qubits.The quantum processor may further include a first set of analog lines communicatively coupled to selectively provide a first analog signal to each qubit within a first plurality of qubits, a second set of analog lines communicatively coupled to selectively provide a second analog signal to each qubit within a second plurality of qubits, a third set of analog lines communicatively coupled to selectively provide a third analog signal to each qubit within a third plurality of qubits, a fourth set of analog lines communicatively coupled to selectively provide a fourth analog signal to each qubit within a fourth plurality of qubits, a first set of analog coupler lines, wherein each line within the first set of analog coupler lines is communicatively coupled to selectively provide an analog signal to each coupler within a first subset of a second plurality of couplers, a second set of analog coupler lines, wherein each line within the second set of analog coupler lines is communicatively coupled to selectively provide an analog signal to each coupler within a second subset of a second plurality of couplers, a third set of analog coupler lines, wherein each line within the third set of analog coupler lines is communicatively coupled to selectively provide an analog signal to each coupler within a third subset of a second plurality of couplers, a fourth set of analog coupler lines, wherein each line within the fourth set of analog coupler lines is communicatively coupled to selectively provide an analog signal to each coupler within a fourth subset of a second plurality of couplers, and each set of analog lines within the first, second, third, and fourth sets of analog lines includes respective very high frequency (VHF) control lines.Applying a signal to at least one qubit within the third and fourth plurality of qubits to initialize each to its respective ground state may include applying a large-amplitude ramp to the qubit body of each of at least one qubit within the third and fourth plurality of qubits via respective first VHF control lines. Applying a signal to at least one qubit within the third plurality of qubits includes applying an ultrashort signal to the qubit body of at least one qubit within the third plurality of qubits via respective VHF control lines. The quantum processor further comprises a fifth set of analog coupler lines, wherein each line within the fifth set of analog coupler lines is communicatively coupled to selectively provide an analog signal to each coupler within a first subset of the first plurality of couplers; a sixth set of analog coupler lines, wherein each line within the sixth set of analog coupler lines is communicatively coupled to selectively provide an analog signal to each coupler within a second subset of the first plurality of couplers; a seventh set of analog coupler lines, wherein each line within the seventh set of analog coupler lines is communicatively coupled to selectively provide an analog signal to each coupler within a third subset of the first plurality of couplers; and an eighth set of analog coupler lines, wherein each line within the eighth set of analog coupler lines is communicatively coupled to selectively provide an analog signal to each coupler within a fourth subset of the first plurality of couplers. Each analog line within the first to eighth sets of analog coupler lines includes a respective VHF line.Using qubits within a second plurality of qubits as controls and qubits within a fourth plurality of qubits as targets to apply a first CNOT gate and using qubits within a first plurality of qubits as targets and qubits within a third plurality of qubits as controls to apply a second CNOT gate simultaneously can include applying an ultra-short wave signal to the couplers within a first plurality of couplers via VHF lines within a fifth set of analog coupler lines and applying an ultra-short wave signal to the couplers within a second plurality of couplers via VHF lines within a first set of analog coupler lines. Using qubits within a first plurality of qubits as controls and qubits within a fourth plurality of qubits as targets to apply a third CNOT gate and using qubits within a second plurality of qubits as targets and qubits within a third plurality of qubits as controls to apply a fourth CNOT gate simultaneously can include applying an ultra-short wave signal to the couplers within a first plurality of couplers via VHF lines within a sixth set of analog coupler lines and applying an ultra-short wave signal to the couplers within a second plurality of couplers via VHF lines within a second set of analog coupler lines. Using qubits within a first plurality of qubits as controls and qubits within a fourth plurality of qubits as targets to apply a fifth CNOT gate and using qubits within a second plurality of qubits as targets and qubits within a third plurality of qubits as controls to apply a sixth CNOT gate simultaneously can include applying an ultra-short wave signal to the couplers within a first plurality of couplers via VHF lines within a seventh set of analog coupler lines and applying an ultra-short wave signal to the couplers within a second plurality of couplers via VHF lines within a third set of analog coupler lines.Using qubits within the second plurality of qubits as controls and qubits within the fourth plurality of qubits as targets to apply a seventh CNOT gate and using qubits within the first plurality of qubits as targets and qubits within the third plurality of qubits as controls to apply an eighth CNOT gate simultaneously can include applying an ultra-short wave signal to a coupler within the first plurality of couplers via a VHF line within an eighth set of analog coupler lines and applying an ultra-short wave signal to a coupler within the second plurality of couplers via a VHF line within a fourth set of analog coupler lines.

[0010] A quantum processor includes one or more quantum logic units, each quantum logic unit including a plurality of physical qubits, a plurality of couplers, each coupler providing a controllable coupling between a pair of the plurality of physical qubits, a plurality of logical qubits, each logical qubit including a subset of the plurality of physically coupled qubits, at least one of the plurality of logical qubits including one or more two-local interaction registers, a shift register including one or more of the plurality of logical qubits, and a plurality of merge blocks connecting two or more adjacent logical qubits of the plurality of logical qubits, the shift register being communicatively coupled selectively to the one or more two-local interaction registers by a merge block of the plurality of merge blocks. Each logical qubit may include one or more control lines providing a shared control bias to at least a subset of the physical qubits within each of the logical qubits. The shift register may include a plurality of logical qubits selectively coupled by one or more of the plurality of merge blocks. Each merge block of the plurality of merge blocks may include at least one line of physical qubits. Each merge block may include one or more control lines providing a shared control bias to at least one line of physical qubits. The plurality of physical qubits may include data qubits and error correction qubits. In use, the data qubits contain quantum computing information and the measurement qubits contain parity enforcers. The quantum processor may further include a memory block communicating with the shift register. The one or more two-local interaction registers may connect the shift register and the one or more memory blocks. The one or more two-local interaction registers may provide XX, XY, XZ, YY, YZ, and ZZ interactions. The one or more two-local interaction registers providing XY, XZ, YY, and YZ interactions may include rectangular logical qubits with mixed boundary conditions.One or more two-local interaction registers that provide XX and ZZ interactions can connect shift register stages to each other and connect the shift register stages to one or more memory blocks. The two-local interaction register that provides XX and ZZ interactions can include a merge block among a plurality of merge blocks. In use, the quantum processor can further include at least one error-corrected single qubit operation block that is not within the Clifford group. The at least one error-corrected single qubit operation block can include a magic state distillation module. The quantum processor can include two or more communicatively coupled quantum logic units.

[0011] An operation method in a quantum processor is described. The method includes inducing a signal on one or more target data block control lines, thereby initializing a target data block, where the target data block includes one or more logical qubits of a first set and the target data block is nominally empty; inducing a signal on one or more merge block control lines, thereby activating a merge block, where the merge block includes at least one line of physical qubits and the merge block connects the target data block to a source data block, and the source data block includes one or more logical qubits of a second set and contains data; running a plurality of surface code cycles across the target data block, the merge block, and the source data block, thereby moving data from the source data block to the target data block through the merge block; and measuring the one or more logical qubits of the second set including the source data block and the at least one line of physical qubits including the merge block. Running a plurality of surface code cycles may include running d surface code cycles, where d includes the minimum number of data qubits that must be bit-flipped or phase-flipped simultaneously to implement either a logical X operation or a logical Z operation.Data can move across a Z edge and perform a merge operation corresponding to a ZZ measurement. To perform the merge operation, the method can include inducing a signal on one or more target data block control lines to initialize a target data block, which can include inducing a signal on one or more target data block control lines to initialize one or more logical qubits of a first set to the |+> state, inducing a signal on one or more merge block control lines to activate a merge block, which can include inducing a signal on one or more merge block control lines to initialize at least one line of physical qubits of the merge block to the |+> state, and measuring a second set of logical qubits including a source data block and at least one line of physical qubits including the merge block, which can include measuring the second set of logical qubits including the source data block and at least one line of physical qubits including the merge block in the X basis. Data can move across an X edge and perform a merge operation corresponding to an XX measurement. To perform the merge operation, the method can include inducing a signal on one or more target data block control lines to initialize a target data block, which can include inducing a signal on one or more target data block control lines to initialize one or more logical qubits of a first set to the |0> state, inducing a signal on one or more merge block control lines to activate a merge block, which can include inducing a signal on one or more merge block control lines to initialize at least one line of physical qubits of the merge block to the |0> state, and measuring a second set of logical qubits including a source data block and at least one line of physical qubits including the merge block, which can include measuring the second set of logical qubits including the source data block and at least one line of physical qubits including the merge block in the Z basis. The method can further include measuring one or more of the logical qubits of the first set, where the one or more logical qubits have not received any data.Inducing a signal on one or more target data block control lines to initialize a target data block may include inducing the signal in a shift register, where the shift register includes one or more target data blocks. Inducing a signal on one or more target data block control lines to initialize a target data block may include inducing the signal in a two-local interaction register, where the two-local interaction register includes one or more target data blocks. Inducing a signal in a two-local interaction register may include inducing the signal in one of the XX, XY, XZ, YY, YZ, and ZZ interaction registers.

[0012] The quantum processor includes a first surface code layer and a second surface code layer. Each of the first and second surface code layers includes a first plurality of qubits, a second plurality of qubits, a third plurality of qubits, and a fourth plurality of qubits. The first, second, third, and fourth pluralities of qubits are arranged in a two-dimensional array. The second surface code layer includes a fourth plurality of qubits. The quantum processor also includes a plurality of interlayer couplers. Each coupler in the plurality of interlayer couplers communicatively directly couples one qubit each from the first plurality of qubits in the first surface code layer and the first plurality of qubits in the second surface code layer, one qubit each from the second plurality of qubits in the first surface code layer and the second plurality of qubits in the second surface code layer, one qubit each from the third plurality of qubits in the first surface code layer and the third plurality of qubits in the second surface code layer, and / or one qubit each from the fourth plurality of qubits in the first surface code layer and the fourth plurality of qubits in the second surface code layer. The quantum processor may further include a first plurality of couplers. Each coupler in the first plurality of couplers provides a communicable coupling either between one qubit each from the first plurality of qubits and one qubit each from the third plurality of qubits or between one qubit each from the second plurality of qubits and one qubit each from the third plurality of qubits. The quantum processor may further include a second plurality of couplers. Each coupler in the second plurality of couplers provides a communicable coupling either between one qubit each from the first plurality of qubits and one qubit each from the fourth plurality of qubits or between one qubit each from the second plurality of qubits and one qubit each from the fourth plurality of qubits. Each qubit in the first and second pluralities of qubits in the first and second surface code layers is a data qubit, and each qubit in the third and fourth pluralities of qubits in the first and second surface code layers is,Each is a stabilized qubit, and each qubit within the third and fourth pluralities of qubits in the first and second surface code layers is operable to perform a parity measurement on a nearest neighbor data qubit. Each of the first and second surface code layers is communicatively coupled selectively to each of the qubits within the first plurality of qubits to transmit an analog signal to each of the qubits within the first plurality of qubits, a first set of analog lines, and selectively communicatively coupled to each of the qubits within the second plurality of qubits to transmit an analog signal to each of the qubits within the second plurality of qubits, a second set of analog lines, and selectively communicatively coupled to each of the qubits within the third plurality of qubits to transmit an analog signal to each of the qubits within the third plurality of qubits, a third set of analog lines, and selectively communicatively coupled to each of the qubits within the fourth plurality of qubits to transmit an analog signal to each of the qubits within the fourth plurality of qubits, a fourth set of analog lines. Each of the first and second surface code layers may further include, respectively, a first set of analog coupler lines, each line within the first set of analog coupler lines being operable to transmit an analog signal to each of one of the first subsets of the second plurality of couplers, a first set of analog coupler lines, and a second set of analog coupler lines, each line within the second set of analog coupler lines being operable to transmit an analog signal to each of one of the second subsets of the second plurality of couplers, a second set of analog coupler lines, and a third set of analog coupler lines, each line within the third set of analog coupler lines being operable to transmit an analog signal to each of one of the third subsets of the second plurality of couplers, a third set of analog coupler lines, and a fourth set of analog coupler lines, each line within the fourth set of analog coupler lines being operable to transmit an analog signal to each of one of the fourth subsets of the second plurality of couplers, a fourth set of analog coupler lines, and a fifth set of analog coupler lines, each line within the fifth set of analog coupler lines beingA fifth set of analog coupler lines operable to transmit an analog signal to each one of a first subset of a first plurality of couplers, a sixth set of analog coupler lines, wherein each line within the sixth set of analog coupler lines is operable to transmit an analog signal to each one of a second subset of the first plurality of couplers, a seventh set of analog coupler lines, wherein each line within the seventh set of analog coupler lines is operable to transmit an analog signal to each one of a third subset of the first plurality of couplers, and an eighth set of analog coupler lines, wherein each line within the eighth set of analog coupler lines is operable to transmit an analog signal to each one of a fourth subset of the first plurality of couplers. Each set of analog lines within the first, second, third, and fourth sets of analog lines may include respective time-dependent control lines. Each line within the first, second, third, fourth, fifth, sixth, seventh, and eighth sets of analog coupler lines may include respective very high frequency (VHF) lines. The present quantum processor is operable to transmit an analog signal to an interlayer coupler between qubits within a first plurality of qubits in a first surface code layer and qubits within a first plurality of qubits in a second surface code layer, and to a first interlayer coupler control line operable to transmit an analog signal to an interlayer coupler between qubits within a third plurality of qubits in the first surface code layer and qubits within a third plurality of qubits in the second surface code layer, and to transmit an analog signal to an interlayer coupler between qubits within a second plurality of qubits in the first surface code layer and qubits within a second plurality of qubits in the second surface code layer, and a second interlayer coupler control line operable to transmit an analog signal to an interlayer coupler between qubits within a third plurality of qubits in the first surface code layer and qubits within a third plurality of qubits in the second surface code layer,Transmit an analog signal to an interlayer coupler between qubits in a second plurality of qubits in a first surface code layer and qubits in a second plurality of qubits in a second surface code layer, and operate to transmit the analog signal to an interlayer coupler between qubits in a third plurality of qubits in the first surface code layer and qubits in a third plurality of qubits in the second surface code layer. A third interlayer coupler control line, which transmits an analog signal to an interlayer coupler between qubits in a first plurality of qubits in a first surface code layer and qubits in a first plurality of qubits in a second surface code layer, and operates to transmit the analog signal to an interlayer coupler between qubits in a third plurality of qubits in the first surface code layer and qubits in a third plurality of qubits in the second surface code layer. A fourth interlayer coupler control line, which transmits an analog signal to an interlayer coupler between qubits in a second plurality of qubits in a first surface code layer and qubits in a second plurality of qubits in a second surface code layer, and operates to transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer. A fifth interlayer coupler control line, which transmits an analog signal to an interlayer coupler between qubits in a first plurality of qubits in a first surface code layer and qubits in a first plurality of qubits in a second surface code layer, and operates to transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer. A sixth interlayer coupler control line, which transmits an analog signal to an interlayer coupler between qubits in a first plurality of qubits in a first surface code layer and qubits in a first plurality of qubits in a second surface code layer, and operates to transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer. A seventh interlayer coupler control line, which transmits an analog signal to an interlayer coupler between qubits in a first plurality of qubits in a first surface code layer and qubits in a first plurality of qubits in a second surface code layer, and operates to transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer.Transmit the analog signal to an interlayer coupler between qubits in a second plurality of qubits in the first surface code layer and qubits in a second plurality of qubits in the second surface code layer, and transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer, and may further include an eighth interlayer coupler control line operable to do so, each coupler in the plurality of interlayer couplers further includes four adiabatic quantum flux parameton (aQFP) switches, and the aQFP switches selectively control the communicable coupling of the interlayer coupler to the qubits of the first and second surface code layers. Each of the first, second, third, fourth, fifth, sixth, seventh, and eighth interlayer coupler control lines may be respective VHF lines.,

[0013] A method of operating a quantum processor is described. The quantum processor includes a first surface code layer and a second surface code layer, each of the first and second surface code layers including a first plurality of qubits, a second plurality of qubits, a third plurality of qubits, and a fourth plurality of qubits, wherein each qubit in the first plurality of qubits and each qubit in the second plurality of qubits are each communicatively directly coupled to two respective qubits in the third plurality of qubits and two respective qubits in the fourth plurality of qubits, the first surface code layer and the second surface code layer, and a plurality of interlayer couplers, wherein each coupler of the plurality of interlayer couplers communicatively directly couples one of the qubits in the first surface code layer and each homogeneous qubit in the second surface code layer. The quantum processor has at least one defective qubit in the first surface code layer. The method is executed by a digital processor communicatively coupled to the quantum processor. The method includes deactivating the defective qubit in the first surface code layer, activating the homogeneous qubit in the second surface code layer by activating the interlayer coupler between the qubit in the first surface code layer communicatively directly coupled to the defective qubit and the homogeneous qubit in the second surface code layer, performing surface code calculations, and reading out the state of each qubit in the third and fourth pluralities of qubits. Each of the first and second surface code layers may further include each of a first plurality of couplers, wherein each coupler in the first plurality of couplers communicatively directly couples one of each of the first plurality of qubits and one of each of the third plurality of qubits or one of each of the second plurality of qubits and one of each of the third plurality of qubits, and each of a second plurality of couplers, wherein each coupler in the second plurality of couplers communicatively directly couples one of each of the first plurality of qubits and one of each of the fourth plurality of qubits or one of each of the second plurality of qubits and one of each of the fourth plurality of qubits. Deactivating the defective qubit in the first surface code layer isDeactivating the couplers in the first and second pluralities of couplers between the qubits in the third and fourth pluralities of qubits in the first surface code that are communicatively directly coupled to at least one defective qubit in the first plurality of qubits and the at least one defective qubit, and activating the homogeneous qubits in the second surface code layer may include activating the interlayer couplers between the qubits in the third and fourth pluralities of qubits in the first surface code layer that are communicatively directly coupled to at least one defective qubit in the first plurality of qubits and the respective qubits in the third and fourth pluralities of qubits in the second surface code layer, and activating the couplers in the first and second pluralities of couplers in the second surface code layer between the qubits in the third and fourth pluralities of qubits that are coupled to the activated interlayer couplers and the corresponding energy qubits in the first plurality of qubits in the first surface code layer that are coupled thereto. Performing surface code calculations includes applying a signal to the qubits in the third and fourth pluralities of qubits in the first surface code layer to initialize the ground states of the qubits in the third and fourth pluralities of qubits, applying a Hadamard transform to the qubits in the third plurality of qubits in the first surface code layer, applying a first SWAP gate between the first qubit among the qubits in the third plurality of qubits in the first surface code layer that is coupled to the activated interlayer coupler and each first qubit among the qubits in the third plurality of qubits in the second surface code layer, and first and second CNOT gates where the qubits in the second plurality of qubits in the first surface code layer are the controls and the qubits in the fourth plurality of qubits in the first surface code layer are the targets, and the qubits in the first plurality of qubits in the first surface code layer and the corresponding energy qubits in the first plurality of qubits in the second surface code layer are the targets.Applying the second CNOT gate simultaneously to the qubits in the third plurality of qubits in the first surface code layer and the first qubit in the third plurality of qubits in the second surface code layer, which are in control; applying a second SWAP gate between each of the first qubit among the qubits in the third plurality of qubits in the first surface code layer and the first qubit in the third plurality of qubits in the second surface code layer, which are coupled to the activated interlayer coupler; applying a third SWAP gate between the first qubit among the qubits in the fourth plurality of qubits in the first surface code layer and each of the first qubits in the fourth plurality of qubits in the second surface code layer for the first qubit among the qubits in the fourth plurality of qubits coupled to the activated interlayer coupler; applying a third CNOT gate where the qubits in the first plurality of qubits in the first surface code layer and the corresponding energy qubits in the first plurality of qubits in the second surface code layer are in control, and the qubits in the fourth plurality of qubits in the first surface code layer and the qubits in the fourth plurality of qubits in the second surface code layer are in target; applying the third CNOT gate and the fourth CNOT gate simultaneously where the qubits in the second plurality of qubits in the first surface code layer are in target and the qubits in the third plurality of qubits in the first surface code layer are in control; applying a fourth SWAP gate between the first qubit among the qubits in the fourth plurality of qubits in the first surface code layer and each of the first qubits in the fourth plurality of qubits in the second surface code layer for the first qubit among the qubits in the fourth plurality of qubits coupled to the activated interlayer coupler; applying a fifth SWAP gate between the qubits in the fourth plurality of qubits in the first surface code layer and each of the second qubits in the fourth plurality of qubits in the second surface code layer for the second qubit among the qubits in the fourth plurality of qubits coupled to the activated interlayer coupler; applying a fifth CNOT gate whereThe qubits within the first plurality of qubits in the first surface code layer and the corresponding energy qubits within the first plurality of qubits in the second surface code layer are control, and the qubits within the fourth plurality of qubits in the first surface code layer and the second qubits within the fourth plurality of qubits in the second surface code layer are targets. The fifth and sixth CNOT gates, where the qubits within the second plurality of qubits in the first surface code layer are targets and the qubits within the third plurality of qubits in the first surface code layer are control, simultaneously applying the sixth CNOT gate, and for the second qubit among the qubits within the third plurality of qubits coupled to the activated interlayer coupler, applying a seventh SWAP gate between the second qubit within the third plurality of qubits in the first surface code layer and each of the second qubits within the third plurality of qubits in the second surface code layer. The seventh CNOT gate, where the qubits within the first plurality of qubits in the first surface code layer are control and the qubits within the fourth plurality of qubits in the first surface code layer are targets, and the seventh and eighth CNOT gates, where the qubits within the second plurality of qubits in the first surface code layer and the corresponding energy qubits within the first plurality of qubits in the second surface code layer are targets and the qubits within the third plurality of qubits in the first surface code layer and the second qubits within the third plurality of qubits in the second surface code layer are control, simultaneously applying the eighth CNOT gate, and for the second qubit among the qubits within the third plurality of qubits coupled to the activated interlayer coupler, applying an eighth SWAP gate between the second qubit within the third plurality of qubits in the first surface code layer and each of the second qubits within the third plurality of qubits in the second surface code layer, and applying a Hadamard transform to the qubits within the third plurality of qubits. The quantum processor includes, for each of the first and second surface code layers, a first set of analog lines communicatively coupled selectively to the qubits within the first plurality of qubits to transmit an analog signal to each of the qubits within the first plurality of qubits.Optionally, it may further include a second set of analog lines communicatively coupled selectively to qubits within the second plurality of qubits to transmit an analog signal to each of the qubits within the second plurality of qubits, a third set of analog lines communicatively coupled selectively to qubits within the third plurality of qubits to transmit an analog signal to each of the qubits within the third plurality of qubits, and a fourth set of analog lines communicatively coupled selectively to qubits within the fourth plurality of qubits to transmit an analog signal to each of the qubits within the fourth plurality of qubits. Applying a signal to the qubits within the third and fourth pluralities of qubits to initialize the ground states of the qubits within the third and fourth pluralities of qubits may include applying a large amplitude ramp to each qubit body of each of the qubits within the third and fourth pluralities of qubits via one respective line of each of the third and fourth sets of analog lines. Applying a Hadamard transform to the qubits within the third plurality of qubits may include applying a Hadamard transform to the qubits within the third plurality of qubits via the third set of analog lines. Each of the first and second surface code layers of the quantum processor includes a first set of analog coupler lines, wherein each line within the first set of analog coupler lines is operable to transmit an analog signal to each one of a first subset of the second plurality of couplers, a second set of analog coupler lines, wherein each line within the second set of analog coupler lines is operable to transmit an analog signal to each one of a second subset of the second plurality of couplers, a third set of analog coupler lines, wherein each line within the third set of analog coupler lines is operable to transmit an analog signal to each one of a third subset of the second plurality of couplers, a fourth set of analog coupler lines, wherein each line within the fourth set of analog coupler lines is operable to transmit an analog signal to each one of a fourth subset of the second plurality of couplers, and a fifth set of analog coupler lines, whereinEach line within the fifth set of analog coupler lines is operable to transmit an analog signal to each one of a first subset of the first plurality of couplers, the fifth set of analog coupler lines, and the sixth set of analog coupler lines, wherein each line within the sixth set of analog coupler lines is operable to transmit an analog signal to each one of a second subset of the first plurality of couplers, the sixth set of analog coupler lines, and the seventh set of analog coupler lines, wherein each line within the seventh set of analog coupler lines is operable to transmit an analog signal to the first plurality, a seventh set of analog coupler lines and an eighth set of analog coupler lines, each operable to send to each one of a third subset of the couplers, the eighth set of analog coupler lines including lines each operable to send an analog signal to each one of a fourth subset of the first plurality of couplers. Applying the first CNOT gate and the second CNOT gate simultaneously may include applying an ultra-high frequency (VHF) signal to a coupler within a fifth plurality of couplers via a VHF line within a fifth set of analog coupler lines and applying an ultra-high frequency signal to a coupler within a second plurality of couplers via a VHF line within a first set of analog coupler lines. Applying the third CNOT gate and the fourth CNOT gate simultaneously may include applying an ultra-high frequency signal to a coupler within a first plurality of couplers via a VHF line within a sixth set of analog coupler lines and applying an ultra-high frequency signal to a coupler within a second plurality of couplers via a VHF line within a second set of analog coupler lines. Applying the fifth CNOT gate and the sixth CNOT gate simultaneously may include applying an ultra-high frequency signal to a coupler within a first plurality of couplers via a VHF line within a seventh set of analog coupler lines and applying an ultra-high frequency signal to a coupler within a second plurality of couplers via a VHF line within a third set of analog coupler lines. Applying the seventh CNOT gate and the eighth CNOT gate simultaneously may include applying an ultra-high frequency signal to a coupler within a first plurality of couplers via a VHF line within an eighth set of analog coupler lines and applying an ultra-high frequency signal to a coupler within a second plurality of couplers via a VHF line within a fourth set of analog coupler lines. The quantum processor is operable to send an analog signal to an interlayer coupler between qubits within a first plurality of qubits in a first surface code layer and qubits within a first plurality of qubits in a second surface code layer and to send an analog signal to an interlayer coupler between qubits within a third plurality of qubits in a first surface code layer and qubits within a third plurality of qubits in a second surface code layer, a first interlayer coupler control line,Transmit an analog signal to an interlayer coupler between qubits in a second plurality of qubits in a first surface code layer and qubits in a second plurality of qubits in a second surface code layer, and transmit the analog signal to an interlayer coupler between qubits in a third plurality of qubits in the first surface code layer and qubits in a third plurality of qubits in the second surface code layer. A second interlayer coupler control line operable to transmit an analog signal to an interlayer coupler between qubits in a second plurality of qubits in the first surface code layer and qubits in a second plurality of qubits in the second surface code layer, and transmit the analog signal to an interlayer coupler between qubits in a third plurality of qubits in the first surface code layer and qubits in a third plurality of qubits in the second surface code layer. A third interlayer coupler control line operable to transmit an analog signal to an interlayer coupler between qubits in a first plurality of qubits in the first surface code layer and qubits in a first plurality of qubits in the second surface code layer, and transmit the analog signal to an interlayer coupler between qubits in a third plurality of qubits in the first surface code layer and qubits in a third plurality of qubits in the second surface code layer. A fourth interlayer coupler control line operable to transmit an analog signal to an interlayer coupler between qubits in a second plurality of qubits in the first surface code layer and qubits in a second plurality of qubits in the second surface code layer, and transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer. A fifth interlayer coupler control line operable to transmit an analog signal to an interlayer coupler between qubits in a first plurality of qubits in the first surface code layer and qubits in a first plurality of qubits in the second surface code layer, and transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer. A sixth interlayer coupler control line operable to transmit an analog signal to an interlayer coupler between qubits in a first plurality of qubits in the first surface code layer and qubits in a first plurality of qubits in the second surface code layer, and transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer.Transmit an analog signal to an interlayer coupler between qubits in a first plurality of qubits in a first surface code layer and qubits in a first plurality of qubits in a second surface code layer, and transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer. A seventh interlayer coupler control line operable to do so, and an eighth interlayer coupler control line operable to transmit an analog signal to an interlayer coupler between qubits in a second plurality of qubits in the first surface code layer and qubits in a second plurality of qubits in the second surface code layer, and transmit the analog signal to an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer. Each coupler in the plurality of interlayer couplers may further include four adiabatic quantum flux parameton (aQFP) switches, and the aQFP switches selectively control the communicable coupling of the interlayer coupler to the qubits of the first and second surface code layers. Activating an interlayer coupler between qubits in a third plurality of qubits in the first surface code layer and qubits in a third plurality of qubits in the second surface code layer that are communicably directly coupled to at least one defective qubit in the first plurality of qubits, and activating an interlayer coupler between qubits in a fourth plurality of qubits in the first surface code layer and qubits in a fourth plurality of qubits in the second surface code layer that are communicably directly coupled to at least one defective qubit in the first plurality of qubits may include transmitting an analog signal to the interlayer coupler via the first, second, third, fourth, fifth, sixth, seventh, and eighth interlayer coupler control lines and the aQFP switches.,

[0014] Brief Description of Some of the Drawings In the drawings, the same reference numerals identify like elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve the visibility of the drawings. Further, the particular shapes of the drawn elements are not necessarily intended to convey any information regarding the actual shapes of the particular elements, and may simply have been selected for ease of recognition in the drawings.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21A

Figure 21B

Figure 21C

Figure 22A

Figure 22B

Figure 23

Figure 24A

Figure 24B

Figure 24C

Figure 24D

Figure 24E

Figure 24F

Figure 24G

Figure 24H

Figure 25A

Figure 25B

Figure 26A

Figure 26B

Figure 27A

Figure 27B

Mode for Carrying Out the Invention

[0016] Detailed Description In the following description, specific specific details are set forth in order to provide a complete understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details or using other methods, components, materials, etc. In some cases, well-known structures associated with digital and analog computer systems, server computers, and / or communication networks are not shown in detail or described in order to avoid unnecessarily obscuring the description of the embodiments.

[0017] Unless the context requires otherwise, throughout this specification and the following claims, the word "comprising" is synonymous with "including" and is inclusive or open-ended (i.e., it does not exclude additional unrecited elements or method acts).

[0018] References to "one embodiment" or "an embodiment" throughout this specification mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0019] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally employed in the sense of "and / or" unless the context clearly dictates otherwise.

[0020] The headings and abstracts of the disclosure provided in this specification are for convenience only and do not explain the scope or meaning of the embodiments.

[0021] Quantum computing Quantum processors can perform two broad types of quantum computing. The first type of quantum computing, called quantum annealing and / or adiabatic quantum computing, generally relies on the physical evolution of a quantum system. The second type of quantum computing, called gate model and / or circuit model quantum computing, relies on performing calculations with data using quantum gate operations. Surface codes refer to a particular implementation of error-corrected gate model or circuit model quantum computing (QC), in which logical qubits are encoded in a portion or patch of a two-dimensional lattice of physical qubits using a two-dimensional low-density parity-check scheme. The theoretical basis for two-dimensional surface codes can be found in the literature, for example, Daniel Gottesman (Gottesman, D., 1997, Stabilizer Codes and Quantum Error Correction, URL https: / / arxiv.org / abs / quant-ph / 9705052); Alexi Kitaev and Sergei Bravyi (Bravyi, S., and A. Kitaev, 2005, Phys. Rev. A 71, 022316); Emanuel Knill (Knill, E., 2004a, Fault-tolerant postselected quantum computation: Schemes, eprint 0402171); Robert Raussendorf and Jim Harrington (Raussendorf, R., and J. Harrington, 2007, Phys. Rev. Lett. 98, 190504); Austin Fowler et al. (Fowler, A. G. et al., 2012, Phys. Rev. A 86, 032324); and Daniel Litinski (Litinski, D., 2019, Quantum 3, 128, ISSN 2521-327X). Surface codes are a way to perform universal gate model quantum computing.See Horsman et al., Surface code quantum computing by lattice surgery, New Journal of Physics, Volume 14, December 2012.

[0022] Embodiments of surface codes generally use a number of physical qubits to form a single logical qubit with error correction. Many proposals for implementing universal quantum computing using surface codes, as discussed above, rely on the ability to apply any control sequence anywhere within a quantum processing unit (QPU), but these embodiments may not be feasible at large scale due to the demand for control lines. For example, some embodiments may use multiple control lines for each qubit and coupler, and as the number of qubits approaches the thousands, it can become unsustainable with respect to physical space and connection hardware. Additionally, control lines typically extend from room temperature to the quantum processor and can thus cause noise and processor heating. As discussed in more detail herein, in some embodiments, it may be beneficial to hardwire specific portions of the QPU to perform a given set of tasks. Embodiments of substantially arbitrary control may replace the use of multiple components for storing, moving, and manipulating data. The data manipulation components must facilitate at least one set of operations that satisfy the conditions of universality. The operations performed by the data manipulation components may be performed between logical qubits. For example, a merge operation may be performed between two code surfaces by turning on parity measurements between two patches of the surface code. "Merge" in this context refers to connecting logical qubits along shared edges such that the logical qubits interact according to a relationship defined by the construction of the merge block. The merging and splitting of logical qubits can entangle them, while lattice surgery can be used to move logical qubits and execute logic. Lattice surgery refers to a way of performing and combining planar surface codes as defined by Horsman et al. cited above.

[0023] Hybrid Computing System FIG. 1 shows a hybrid computing system 100 that includes a digital computer 102. As an example, the digital computer 102 includes one or more digital processors 106 that can be used to execute classical digital processing tasks. The digital computer 102 may further include at least one system memory 122 and at least one system bus 120 that couples various system components including the system memory 122 to the digital processor 106. The system memory 122 may store one or more sets of processor-executable instructions that can be referred to as modules 124.

[0024] The digital processor 106 can be any logical processing unit or circuit (e.g., an integrated circuit) such as one or more central processing units (“CPUs”), graphics processing units (“GPUs”), digital signal processors (“DSPs”), application specific integrated circuits (“ASICs”), field programmable gate arrays (“FPGAs”), programmable logic controllers (“PLCs”), etc., and / or combinations thereof.

[0025] In some embodiments, the computing system 100 includes an analog computer 104, and the analog computer 104 may include one or more quantum processors 126. The quantum processor 126 may include at least one superconducting integrated circuit. The digital computer 102 can communicate with the analog computer 104, for example, via a controller 118. Certain calculations can be performed by the analog computer 104 under the instructions of the digital computer 102, as will be described in more detail herein.

[0026] The digital computer 102 may include a user input / output subsystem 108. In some embodiments, the user input / output subsystem includes one or more user input / output components such as a display 110, a mouse 112, and / or a keyboard 114.

[0027] The system bus 120 may adopt any known bus structure or architecture, including a memory controller, a peripheral bus, and a local bus. The system memory 122 may include non-volatile memory, such as read-only memory ("ROM"), static random access memory ("SRAM"), flash NAND; and volatile memory, such as random access memory ("RAM").

[0028] The digital computer 102 may include other non-transitory computer or processor-readable storage media or non-volatile memory 116. The non-volatile memory 116 may take various forms, including a hard disk drive for reading and writing to a hard disk (e.g., a magnetic disk), an optical disk drive for reading and writing to a removable optical disk, and / or a solid state drive (SSD) for reading and writing to solid state media (e.g., NAND-based flash memory). The non-volatile memory 116 may communicate with the digital processor via the system bus 120 and may include an appropriate interface or controller 118 coupled to the system bus 120. The non-volatile memory 116 may function as long-term storage for the processor or computer-readable instructions, data structures, or other data (sometimes referred to as program modules or modules 124) of the digital computer 102. Although the digital computer 102 has been described as employing a hard disk, an optical disk, and / or a solid state storage medium, those skilled in the art will understand that other types of non-transitory non-volatile computer-readable media may be employed. Depending on the computer architecture, those skilled in the art will understand that both non-transitory volatile memory and non-transitory non-volatile memory may be employed. For example, data in volatile memory may be cached to non-volatile memory or to a solid state disk that employs integrated circuits to provide non-volatile memory.

[0029] Various processors or computer-readable and / or executable instructions, data structures, or other data may be stored in system memory 122. For example, system memory 122 may store instructions for communicating with remote clients and scheduling the use of resources including the resources of digital computer 102 and analog computer 104. Also for example, system memory 122 may store at least one of processor-executable instructions or data that, when executed by at least one processor, cause the at least one processor to execute various algorithms to execute instructions. In some embodiments, system memory 122 may store processor or computer-readable computational instructions and / or data for performing pre-processing, co-processing, and post-processing on analog computer 104. System memory 122 may store a set of analog computer interface instructions for interacting with analog computer 104. For example, system memory 122 may store processor or computer-readable instructions, data structures, or other data that, when executed by a processor or computer, cause the processor or computer to perform one, two or more, or all of the acts of method 900 of FIG. 9, method 1900 of FIG. 19, method 2500 of FIGS. 25A and 25B, method 2600 of FIGS. 26A and 26B, and method 2700 of FIGS. 27A and 27B.

[0030] Analog computer 104 may include at least one analog processor such as quantum processor 126. Analog computer 104 may be provided in a separated environment, for example, an environment that isolates internal elements of a quantum computer from heat, magnetic fields, and other external noise. The separated environment may include, for example, a refrigerator operable to cryogenically cool the analog processor to a temperature generally below 1K (about -272 °C), such as a dilution refrigerator.

[0031] The analog computer 104 may include programmable elements such as qubits, couplers, and other devices (also referred to herein as controllable devices). The qubits may be read out via the readout control system 128. The readout results may be sent to other computers or processor-readable intelligences of the digital computer 102. The qubits may be controlled via the qubit control system 130. The qubit control system 130 may include an on-chip digital / analog converter (DAC) and an analog line operable to apply a bias to a target device. The couplers that couple the qubits may be controlled via the coupler control system 132. The coupler control system 132 may include adjustment elements such as an on-chip DAC and an analog line. The qubit control system 130 and the coupler control system 132 can be used to control the behavior of one or more qubits and couplers based on signals including instructions provided by the digital computer 102. The programmable elements may be included in the quantum processor 126 in the form of an integrated circuit. The qubits and couplers may be located in a layer of the integrated circuit including a first material. Other devices such as the readout control system 128 may be located in other layers of the integrated circuit including a second material. According to the present disclosure, a quantum processor such as the quantum processor 126 may be designed to perform quantum annealing and / or adiabatic quantum computing or gate-model quantum computing, for example, according to the techniques described herein for performing error-corrected quantum computing (QC). Examples of quantum processors are described in U.S. Patent No. 7,533,068.

[0032] Two-dimensional surface code Surface codes are a particular implementation of error-corrected quantum computing (QC) in which logical qubits are encoded in portions or patches of a quadratic lattice of physical qubits using a two-dimensional low-density parity-check scheme. In the present disclosure and the appended claims, the term "logical qubit" is meant to denote a plurality of qubits linked together by coupling devices in a low-energy state such that all qubits in the logical qubit have the same spin value. In some embodiments, the ability of the surface code to identify errors lies in dividing the physical qubit lattice into four sublattices: a first sublattice contains a first plurality of qubits, also called data qubits (data A or DA) in this description and the appended claims; a second sublattice contains a second plurality of qubits, also called data qubits (data B or DB) in this description and the appended claims; and the third and fourth sublattices contain two groups of qubits called stabilizer qubits. Providing the two data qubit sublattices, i.e., data A and data B, is useful in building scalable technology and allows for a relatively sparse number of control lines. Data qubits are typically read only near the end of a computation or at least at the end of a subroutine of that computation. Stabilizer qubits are used to perform parity measurements on nearest-neighbor data qubits. Each data qubit inside a patch of the surface code is coupled to four stabilizer qubits, two of which measure the XXXX parity and are called X measurement (Mx) qubits, and two of which measure the ZZZZ parity and are called Z measurement (Mz) qubits. At the edges of a patch of the surface code, there are two local parity stabilizers corresponding to either XX parity measurement or ZZ parity measurement, and the alternating data qubits on the edge receive only three parity measurements. By measuring all stabilizers in repeated cycles, the entire set of data A and data B qubits is projected onto a quantum state that is a simultaneous eigenstate of the XXXX operator, the ZZZZ operator, the XX operator, and the ZZ operator. Errors are heralded by changes in the individual stabilizer results between successive cycles.Through the use of a stabilizer, advantageously, the constraints of the no-cloning theorem that would otherwise require explicitly measuring the data qubits to identify errors can be avoided.

[0033] The feature of the two-dimensional surface code is that there is no need to physically correct any identified errors in vivo. Instead, it suffices to track the identified errors with classical software and correct any final readings of the faulty physical qubits only after the corresponding logical qubit has been read.

[0034] Transmon qubit FIG. 2 is a schematic diagram of an exemplary embodiment of a superconducting qubit 200 according to the present disclosure. The superconducting qubit 200 is an example of a transmon qubit.

[0035] The superconducting qubit 200 includes a first superconducting island 202 (shown in thick line) and a second superconducting island 204 communicatively coupled by a DC superconducting quantum interference device (DC-SQUID) 206. The DC-SQUID 206 includes a Josephson junction 208 and a Josephson junction 210 coupled in parallel with each other via a superconducting loop. In some embodiments, the Josephson junctions 208 and 210 are symmetric junctions. A flux bias can be applied to the DC-SQUID 206 by the interface 212 to adjust the Josephson energy of the superconducting qubit 200. The superconducting qubit 200 also includes a shunt capacitor 214.

[0036] The superconducting qubit 200 can be controlled by a gate electrode capacitively communicatively coupled to the first superconducting island 202 by a gate capacitance 216 using a gate voltage supplied by a source 218. The superconducting qubit 200 can be coupled to a resonator that can be modeled by a lumped heat capacity 220, a lumped inductance 222, and an additional coupling capacitance 224.

[0037] Capacitively coupled transmon qubit There are three physical ways to directly couple any superconducting qubits to each other: galvanic coupling, inductive coupling, and capacitive coupling. Additionally, a resonant drive circuit can be added to one (or both) of the qubits forming a two-qubit gate. In one example embodiment, capacitive coupling can be used as a coupling method to couple multiple transmon qubits such as the superconducting qubit 200 of FIG. 2. Structures for implementing adjustable capacitive coupling are described in Yan et al. (Yan, F. et al., 2018, Phys. Rev. Applied 10, 054062). Entangling gates can be realized by capacitively coupling on-off pulses between a pair of resonant transmon qubits.

[0038] Fractional qubit To build a scalable quantum processor, not only high quantum coherence but also minimal crosstalk between qubits and high circuit density are desirable. Thus, it may be advantageous to construct an integrated stack consisting of multiple metal layers and dielectric spacer layers having the above characteristics.

[0039] One type of superconducting qubit known as a fractional qubit is in the form of a flux qubit having an extremely large body inductance called "superinductance". For a discussion of fractional qubits, see Manucharyan, V. E., et al., 2009, Science 326(5949), 113. One way to generate the superinductance of a fractional qubit is through a long chain of large Josephson junctions. However, it is also possible to fabricate superinductance from high kinetic inductance (KI) materials. Further details can be found in International Patent Application No. PCT / 2022 / 037457.

[0040] FIG. 3 is a schematic diagram of a superconducting qubit 300 of an example in which an array of Josephson junctions of a fractional quantum bit is replaced with a mechanical inductor. The superconducting qubit 300 includes a Josephson junction structure 301 and a segment of a mechanical inductance material 302. In this embodiment as an example, the Josephson junction structure 301 includes two Josephson junctions 304 and 305 that form a composite Josephson junction (CJJ). The Josephson junction structure 301 may alternatively include only one Josephson junction or may include a composite-composite Josephson junction (CCJJ). Those skilled in the art will understand that in certain embodiments, the Josephson junction structure 301 may include other structures, for example, an inductor in series with the Josephson junctions 304 and 305. The segment of the mechanical inductance material 302 may include niobium nitride (NbN), niobium titanium nitride (NbTiN), or titanium nitride (TiN).

[0041] Inductively coupled fractional quantum bits An adjustable inductive coupler (see, e.g., Harris, R., et al., A Compound Josephson Junction Coupler for Flux Qubits With Minimal Crosstalk, arXiv: 0904.3784v3 [cond-mat.supr-con], or U.S. Patent No. 8,174,305) can be employed to couple the fractional quantum bits. The adjustable inductive coupler can be switched on and off using a low-bandwidth pulse and can have a gate time shorter than 30 ns. Given the large anharmonicity of fractional quantum bits with KI material, it is relatively easy to create a entangling gate between a pair of resonant fractional quantum bits using pulsed inductive coupling.

[0042] VHF control of fractional quantum bits The design and fabrication of very high frequency (VHF) signal distribution both on-chip and off-chip is easier and more scalable than microwave frequencies due to lower interference with other devices. In this disclosure and the appended claims, the term "very high frequency" is used to denote the following frequency range: ω q / 2π ∈ 30 - 300 MHz. Therefore, in order to construct a practical quantum computing system, it is advantageous to use VHF signals to apply to quantum gates. For example, a modulated VHF signal can be applied to a qubit body to perform a rotation about an axis within the XY plane of the Bloch sphere. To perform a phase rotation about the Z-axis, a modulated VHF signal can be applied to a composite Josephson junction (CJJ) loop of a qubit, thereby oscillating ω q around its nominal zero-point. Since the ω q pair CJJ flux bias transfer curve is approximately exponential around the zero-point of typical device parameters, such modulated pulse control can be used to generate non-zero phases.

[0043] Homogenization and sharing of control signals As described in U.S. Patent No. 11,182,230 and as will be described below with reference to FIGS. 10 and 11, in-situ qubit homogenization techniques may be utilized so that multiple qubits can be controlled using shared template control signals carried by shared control lines. An in-situ adjustable transformer between each target device and the shared control line can then facilitate scalable control of a large patch of surface code, for example, by controlling multiple fluxonium qubits using a few VHF bias lines. Those template signals may be generated at room temperature, on a cryogenic support chip, and / or integrated into the fabric of a quantum processing unit (QPU).

[0044] Example of a quantum processor FIG. 4 is a schematic diagram of a portion of an example of a quantum processor 400 capable of implementing a 2D surface code according to the present system, the present device, and the present method. The quantum processor 400 may be, for example, all or part of the quantum processor 126 used in the hybrid computing system 100 of FIG. 1.

[0045] The quantum processor 400 shows an example implementation of an arrangement of physical qubits to provide one or more logical qubits. A logical qubit is a collection of one or more physical qubits that collectively act as a single qubit for the purpose of computation. In an example of a gate model quantum algorithm, a logical qubit acts as a single qubit for the purpose of quantum logic operations. However, as discussed below, many physical qubits are used to form a single logical qubit that provides quantum error correction and thus a more fault-tolerant logical qubit.

[0046] The quantum processor 400 includes four pluralities of qubits arranged in a two-dimensional lattice. In at least one implementation, the quantum processor 400 includes a plurality of fluxonium qubits having a high-KI material such as the superconducting qubit 300 of FIG. 3. In another implementation, the quantum processor 400 includes a plurality of transmon qubits such as the superconducting qubit 200 of FIG. 2. The quantum processor 400 includes a first plurality of qubits (the hatched and shaded qubits 401a, 401b, 401c, and 401d, collectively referred to as 401, mobilized for illustrative purposes), a second plurality of qubits (the gray qubits 402a, 402b, 402c, and 402d, collectively referred to as 402, mobilized for illustrative purposes), a third plurality of qubits (the black qubits 403a and 403b, collectively referred to as 403, mobilized for illustrative purposes), and a fourth plurality of qubits (the white qubits 404a and 404b, collectively referred to as 404, mobilized for illustrative purposes).

[0047] Each qubit in the first plurality of qubits 401 is directly communicably coupled to at least one qubit in the third plurality of qubits 403 and at least one qubit in the fourth plurality of qubits 404, and qubits in the first plurality of qubits 401 that are not disposed on the edge of the two-dimensional lattice are directly communicably coupled to two qubits in the third plurality of qubits 403 and two qubits in the fourth plurality of qubits 404.

[0048] Each qubit in the second plurality of qubits 402 is directly communicably coupled to at least one qubit in the third plurality of qubits 403 and at least one qubit in the fourth plurality of qubits 404, and qubits in the second plurality of qubits 402 that are not disposed on the edge of the two-dimensional lattice are directly communicably coupled to two qubits in the third plurality of qubits 403 and two qubits in the fourth plurality of qubits 404.

[0049] Each qubit in the third plurality of qubits 403 is directly communicably coupled to at least one qubit in the first plurality of qubits 401 and at least one qubit in the second plurality of qubits 402, and qubits in the third plurality of qubits 403 that are not disposed on the edge of the two-dimensional lattice are directly communicably coupled to two qubits in the first plurality of qubits 401 and two qubits in the second plurality of qubits 402.

[0050] Each qubit in the fourth plurality of qubits 404 is directly communicably coupled to at least one qubit in the first plurality of qubits 401 and at least one qubit in the second plurality of qubits 402, and qubits in the fourth plurality of qubits 404 that are not disposed on the edge of the two-dimensional lattice are directly communicably coupled to two qubits in the first plurality of qubits 401 and two qubits in the second plurality of qubits 402.

[0051] The first and second plurality of qubits 401 and 402 hold the quantum state of the logical qubit, while the third and fourth plurality of qubits 403 and 404 are used for error detection. The logical qubit can be used as a quantum memory and act as a physical qubit within an error correction quantum algorithm such as the surface code. As used herein, a logical qubit typically refers to a qubit formed from two or more physical qubits and used to solve problems. For example, in some embodiments, a logical qubit can be formed from two physical qubits and a coupler that couples those two physical qubits. In other embodiments, a logical qubit can include several physically coupled qubits together, thereby reducing the susceptibility of the quantum processor to noise.

[0052] The quantum processor 400 also includes a first plurality of couplers (couplers 405a and 405b shown in thick lines, collectively referred to as 405, mobilized for illustrative purposes) and a second plurality of couplers 406 (couplers 406a and 406b shown in normal lines, collectively referred to as 406, mobilized for illustrative purposes) that provide communicable couplings between pairs of qubits within a two-dimensional lattice. The first and second plurality of couplers 405 and 406 are disposed in the quantum processor 400 in a grid or two-dimensional array. These couplers can provide inductive coupling, capacitive coupling, galvanic two-dimensional coupling, or combinations thereof. The couplers 405 and 406 can be used as parity implementation couplers to find errors in data qubits by reading out faulty qubits. A parity implementation coupler is any coupler that is coupled such that the overall energy state of the system has two levels, namely, a level in which all connected qubits have an even number of qubits in a given state and a level in which all connected qubits have an odd number of qubits in a given state.

[0053] Each coupler within the first plurality of couplers 405 (also referred to as "x couplers" in this disclosure) provides a communicable coupling between one qubit within the third plurality of qubits 403 and one qubit within the first plurality of qubits 401 or between one qubit within the third plurality of qubits 403 and one qubit within the second plurality of qubits 402.

[0054] Each coupler within the second plurality of couplers 406 (also referred to as "z couplers" in this disclosure) provides a communicable coupling between one qubit within the fourth plurality of qubits 404 and one qubit within the first plurality of qubits 401 or between one qubit within the fourth plurality of qubits 404 and one qubit within the second plurality of qubits 402.

[0055] In the quantum processor 400, each qubit within the third plurality of qubits 403 that is not located at the edge of the quantum processor 400 is directly communicably coupled to four other qubits (i.e., two qubits from the first plurality of qubits 401 and two qubits from the second plurality of qubits 402) via four couplers from the first plurality of couplers 405. Each qubit within the fourth plurality of qubits 404 that is not located at the edge of the quantum processor 400 is directly communicably coupled to four other qubits (i.e., two qubits from the first plurality of qubits 401 and two qubits from the second plurality of qubits 402) via four couplers from the second plurality of couplers 406.

[0056] The parts of the quantum processor 400 are shown in FIG. 4 as including 16 qubits within a first plurality of qubits 401, 9 qubits within a second plurality of qubits 402, 12 qubits within a third plurality of qubits 403, 12 qubits in a fourth plurality of qubits 404, 48 couplers in a first plurality of couplers 405, and 48 couplers within a second plurality of couplers 406. However, the number of qubits and couplers shown in FIG. 4 is for illustrative purposes only, and those skilled in the art will understand that in other embodiments, the quantum processor 400 may include different numbers of qubits and couplers.

[0057] Surface code cycle The Hadamard gate (H gate or Hadamard transform) is a single-qubit gate that can be implemented by concatenating a rotation by π about the X axis of the Bloch sphere followed by a rotation by π / 2 about the Y axis. The truth table of this operation reveals that it maps the computational basis states (|0>; |1>) to symmetric and antisymmetric superposition states (|+>; |->) and vice versa. This operation is typically used to transform a given qubit state between the computational (Z) basis and the superposition (X) basis.

[0058] The CNOT gate is a two-qubit gate in which one qubit acts as a control qubit and the second qubit is a target qubit that is conditionally operated based on the state of the control device. The truth table of this operation reveals that when the control qubit is in the state |1>, the computational state of the target qubit is inverted. This produces a particularly interesting effect because when the control device is in a superposition state, the state of the target qubit will become entangled with the state of the control qubit. The basic operations that spread entanglement across a network of qubits include: starting with the control qubit in the state |0>, applying an H gate to the control qubit, and then applying a CNOT gate to one or more target qubits initialized to the state |0>. This process can then be concatenated to propagate entanglement across a network with limited connectivity.

[0059] Stabilized qubits (also referred to as measurement qubits in this disclosure), i.e., qubits within the third and fourth plurality of qubits 403 and 404, and data qubits, i.e., qubits within the first and second plurality of qubits 401 and 402, a CNOT gate is applied between them, and then the measurement qubits, i.e., the qubits within the third and fourth plurality of qubits 403 and 404 are measured, thereby projecting the entire set of data qubits into a Bell-like entangled state. The state of the logical qubit (i.e., the collective state of all data qubits within the first and second plurality of qubits 401 and 402) is then encoded into something similar to a quadratic repetition code. Without noise and without operations on the logical qubit, its state is a steady state. When an error occurs, there are changes in some parity measurements. Through classical post-processing of those changes, advantageously, individual errors can be identified and accordingly the final result of the quantum calculation can be corrected. An example of the error detection process is described in detail in Fowler et al., 2012, Phys. Rev. A 86, 032324.

[0060] FIG. 5A is a diagram of an example gate sequence 500a for measuring the XXXX parity operator. Measuring the XXXX parity operator includes measuring the state of the qubits within the third plurality of qubits 403.

[0061] Figure 5B is a diagram of an example gate sequence 500b for measuring the ZZZZ parity operator. Measuring the ZZZZ parity operator involves measuring the states of the qubits within the fourth plurality of qubits 404. Similarly, the same structure is indicated by the same reference numerals in FIGS. 5A and 5B. In FIGS. 5A and 5B, the control qubits are shown as solid dots and the target qubits are shown as hollow cross dots. Of particular note is the order in which the entanglement operations are performed: in each of gate sequences 500a and 500b, they follow the pattern ABCD or A'B'C'D'. Examples of the pattern ABCD (corresponding to applying a two-qubit gate between qubit 404a and qubits 402c, 401a, 401b, 402d) and A'B'C'D' (responding to applying a two-qubit gate between qubit 403a and qubits 401c, 402a, 402b, 401c) are also shown in FIG. 4. Those skilled in the art will understand that the patterns ABCD and A'B'C'D' shown in FIG. 4 are merely examples, and alternative patterns optimized for different logical qubit layouts and different boundary conditions may be used.

[0062] Gate sequence 500a shows the sequential operations performed as follows: a first measurement X qubit (Mx) within the third plurality of qubits 403, a first data qubit (DA1) within the first plurality of qubits 401, a first data qubit (DB1) within the second plurality of qubits 402, a second data qubit (DB2) within the second plurality of qubits 402, and a second data qubit (DA2) within the first plurality of qubits 401. Gate sequence 500a is an example of the pattern A'B'C'D'.

[0063] Gate sequence 500b shows the sequential operations performed on the following: one measurement Z qubit (Mz) within the fourth plurality of qubits 404, the third data qubit (DB3) within the second plurality of qubits 402, the third data qubit (DA3) within the first plurality of qubits 401, the fourth data qubit (DA4) within the first plurality of qubits 401, and the fourth data qubit (DB4) within the second plurality of qubits. Gate sequence 500b is an example of pattern ABCD.

[0064] Gate sequences 500a and 500b are executed simultaneously or in parallel. Individual data qubits (the qubits within the first and second pluralities of qubits 401 and 402) engage in only one measurement X or measurement Z qubit at any given time. When the data A quantum bot engages in an X parity measurement (e.g., in act 503 described below), the data B qubit engages in a Z parity measurement in a simultaneous step. The roles of the data qubits are then swapped in the next act (e.g., act 504). Ultimately, every data qubit interacts with two measurement X qubits and two measurement Z qubits, but follows a sequence that avoids the conflict between the two types of parity measurements.

[0065] At 501, the parity qubits Mx and Mz are initialized to the ground state |0>. For further details, refer to acts 902a, 902b of method 900 described below.

[0066] At 502, an H gate (Hadamard gate) is applied to Mx.

[0067] In 503, a first two-qubit gate operation (e.g., a CNOT gate) is applied to a first data qubit (DA1) and Mx within a first plurality of qubits 401, where DA1 is used as the target qubit and Mx is used as the control qubit. Similarly, a second two-qubit gate operation (e.g., a CNOT gate) is also applied to a third data qubit (DB3) and Mz within a second plurality of qubits 402, where DB3 is used as the control qubit and Mz is used as the target.

[0068] In 504, a third two-qubit gate operation (e.g., a CNOT gate) is applied to a first data qubit (DB1) and Mx within a second plurality of qubits 402, where DB1 is used as the target qubit and Mx is used as the control qubit. Similarly, a fourth two-qubit gate operation (e.g., a CNOT gate) is also applied to a third data qubit (DA3) and Mz within a first plurality of qubits 401, where DA3 is used as the control qubit and Mz is used as the target.

[0069] In 505, a fifth two-qubit gate operation (e.g., a CNOT gate) is applied to a second data qubit (DB2) and Mx within a second plurality of qubits 402, where DB2 is used as the target qubit and Mx is used as the control qubit. Similarly, a sixth two-qubit gate operation (e.g., a CNOT gate) is also applied to a fourth data qubit (DA4) and Mz within a first plurality of qubits 401, where DA4 is used as the control qubit and Mz is used as the target qubit.

[0070] At 506, a seventh two-qubit gate operation (e.g., a CNOT gate) is applied to a second data qubit (DA2) and Mx within the first plurality of qubits 401, where DA2 is used as the target qubit and Mx is used as the control qubit. Similarly, an eighth two-qubit gate operation (e.g., a CNOT gate) is applied as control to a fourth data qubit (DB4) within the second plurality of qubits 402 and also to Mz, where DB4 is used as the control qubit and Mz is used as the target qubit.

[0071] At 507, an H gate is applied to Mx.

[0072] At 508, the states of Mx and Mz are read out in the Z basis, each resulting in either 0 or 1. Reading the state of Mx leads to the measurement of the XXXX parity operator, while reading the state of Mz leads to the measurement of the ZZZZ parity operator.

[0073] Scalable control Patterns ABCD and A'B'C'D' can be used to control a patch of the 2D surface code using a sparse number of control lines, assuming that the device and control signals can be made sufficiently homogeneous as described with reference to FIGS. 6 and 7.

[0074] FIG. 6 is a schematic diagram of a portion 600 of an example of the quantum processor 400 of FIG. 4, further showing shared qubit control lines.

[0075] The quantum processor 400 includes a first bundle of analog lines 601 that provides control signals to each qubit within a first plurality of qubits 401, a second bundle of analog lines 602 that provides control signals to each qubit within a second plurality of qubits 402, a third bundle of analog lines 603 that provides control signals to each qubit within a third plurality of qubits 403, and a fourth bundle of analog lines 604 that provides control signals to each qubit within a fourth plurality of qubits 404. In this disclosure and the appended claims, the term "bundle" is used to denote one or more lines (e.g., analog lines) that are laid out in a substantially similar manner and provide control signals to the same subset of qubits, couplers, or other devices on the processor. The term "bundle" is used synonymously with "set" or "plurality" in this disclosure and the appended claims.

[0076] Each of the pluralities of qubits 401, 402, 403, and 404 is biased by a respective bundle of analog lines 601, 602, 603, and 604, such that the entire array of qubits of the quantum processor 400 can operate using only four bundles of analog lines.

[0077] Each bundle of analog lines 601, 602, 603, and 604 can transmit two or more analog signal lines. In an example embodiment of a francium qubit, each bundle of analog lines 601, 602, 603, and 604 includes a first VHF control line inductively coupled to each body of each qubit within the first, second, third, and fourth pluralities of qubits 401, 402, 403, and 404 for rotation about an axis in the XY plane of the Bloch sphere, and a second VHF control line inductively coupled to each CJJ of each qubit within the first, second, third, and fourth pluralities of qubits 401, 402, 403, and 404 for rotation about the Z axis of the Bloch sphere. Each bundle of analog lines 601, 602, 603, and 604 may include additional analog bias lines inductively coupled to each CCJJ of each qubit within the first, second, third, and fourth pluralities of qubits 401, 402, 403, and 404.

[0078] FIG. 7 is a schematic diagram of a portion 700 of an example of the quantum processor 400 of FIG. 4 having a shared coupler control line. The coupler control line is addressed according to the ABCD - A'B'C'D' sequence described in FIGS. 5A and 5B. Portion 700 is a smaller portion of the quantum processor 400 of FIG. 4 to reduce visual clutter. One of ordinary skill in the art will understand that the coupler control line is addressed in the same way through the lattice of the quantum processor 400 and other quantum processor architectures having larger lattices.

[0079] The quantum processor 400 includes eight sets of analog lines 701, 702, 703, 704, 705, 706, 707, and 708. Each set of analog lines provides a control signal to a subset of the couplers within a first plurality of couplers 405 or a subset of the couplers within a second plurality of couplers 406 to enable the ABCD - A'B'C'D' sequence described above with respect to FIGS. 5A and 5B.

[0080] The first set of analog lines 701 provides a control signal to the couplers within a first subset of the second plurality of couplers 406 of the portion 700 of the quantum processor 400. The first set of analog lines 701 provides the control signal used in act A of the sequence ABCD.

[0081] The second set of analog lines 702 provides a control signal to the couplers within a second subset of the second plurality of couplers 406 of the portion 700 of the quantum processor 400. The second set of analog lines 702 provides the control signal used in act B of the sequence ABCD.

[0082] The third set of analog lines 703 provides a control signal to the couplers within a third subset of the second plurality of couplers 406 of the portion 700 of the quantum processor 400. The third set of analog lines 703 provides the control signal used in act C of the sequence ABCD.

[0083] The fourth set of analog lines 704 provides control signals to the couplers within a fourth subset of the second plurality of couplers 406 of portion 700 of quantum processor 400. The fourth set of analog lines 704 provides the control signals used in act D of sequence ABCD.

[0084] The fifth set of analog lines 705 provides control signals to the couplers within a first subset of the first plurality of couplers 405 of portion 700 of quantum processor 400. The fifth set of analog lines 705 provides the control signals used in act A’ of sequence A’B’C’D’. The fifth set of analog lines 705 is shown with a darker line for illustrative purposes.

[0085] The sixth set of analog lines 706 provides control signals to the couplers within a second subset of the first plurality of couplers 405 of portion 700 of quantum processor 400. The sixth set of analog lines 706 provides the control signals used in act B’ of sequence A’B’C’D’. The sixth set of analog lines 706 is shown with a darker line for illustrative purposes.

[0086] The seventh set of analog lines 707 provides control signals to the couplers within a third subset of the first plurality of couplers 405 of portion 700 of quantum processor 400. The seventh set of analog lines 707 provides the control signals used in act C’ of sequence A’B’C’D’. The seventh set of analog lines 707 is shown with a darker line for illustrative purposes.

[0087] The eighth set of analog lines 708 provides control signals to the couplers within a fourth subset of the first plurality of couplers 405 of portion 700 of quantum processor 400. The eighth set of analog lines 708 provides the control signals used in act D’ of sequence A’B’C’D’. The eighth set of analog lines 708 is shown with a darker line for illustrative purposes.

[0088] Therefore, there are separate analog control lines for the couplers connected to the qubits (measurement Z qubits, ABCD sequence) in the fourth plurality of qubits 404 and for the couplers connected to the qubits (measurement X qubits, A'B'C'D' sequence) in the third plurality of qubits 403, so that using a relatively small number of analog lines, a two-qubit operation can be applied to the qubits 404 according to the sequence ABCD and, simultaneously (or in parallel), a two-qubit operation can be applied to the qubits 403 according to the sequence A'B'C'D'.

[0089] Each set of analog lines 701, 702, 703, 704, 705, 706, 707, and 708 can include two or more analog signal lines. In one example embodiment, each set of analog lines 701, 702, 703, 704, 705, 706, 707, and 708 includes a first VHF bias line that provides a pulse to the couplers of the first and second plurality of couplers 405 and 406 to oscillate between a high operating level (H) and a low operating level (L), and additional analog bias lines.

[0090] In at least one embodiment using fluxonium qubits, the CNOT gate can be realized by applying a Y π / 2 gate, an X π gate, an H gate, and a Z -π / 2 gate to the data qubits (DB, control qubit) via a second bundle of analog lines 602 and applying an X -π / 2 gate to the qubit Mz (target qubit) via a fourth bundle of analog lines 604. The Z -π / 2 gate applied to the data qubit can provide a Gaussian pulse that toggles the control qubit between a low operating level and a high operating level for a short time. The control pulse having two peaks applied to the couplers of the second plurality of couplers 406 between the qubit Mz and the data qubit DB via the first set of analog lines 701 realizes a

Number

[0091] FIG. 8 is a diagram of an example CNOT waveform sequence 800 that can be executed using the processor 400 of FIG. 4 in some embodiments. The CNOT waveform sequence 800 is divided in FIG. 8, for ease of illustration, into eight uniform time blocks 801, 802, 803, 804, 805, 806, 807, and 808 (along the horizontal axis) that provide an example embodiment corresponding to the acts of the method 900 of FIG. 9.

[0092] FIG. 9 is a flow diagram showing an example surface code implementation method 900 that can be executed on a quantum processor including the qubit control lines and coupler control lines of FIGS. 6 and 7, e.g., the quantum processor 400 of FIG. 4.

[0093] The method 900 can be executed by a classical processor that communicates with the quantum processor, e.g., the digital computer 102 of FIG. 1. The method 900 includes acts 901, 902a, 902b, 903, 904a, 904b, 905a, 905b, 906a, 906b, 907a, 908, 909a, 909b, and 910, where the number of acts is an example, and one of ordinary skill in the art will understand that in some embodiments, certain acts may be omitted, additional acts may be added, and / or the order of the acts may be changed. The method 900 implements the sequences 500a and 500b of FIGS. 5A and 5B, respectively, and implements the CNOT waveform sequence 800 of FIG. 8.

[0094] The method 900 begins at 901, e.g., in response to a call from another routine.

[0095] Acts 902a and 902b are executed in parallel by, or together by, or even simultaneously by the digital computer 102. Acts 902a and 902b correspond to time block 801 of FIG. 8 and act 501 of FIGS. 5A and 5B.

[0096] In 902a, digital computer 102 initializes the qubits (Mx) in the third plurality of qubits 403 to the ground state. In at least one embodiment, digital computer 102 applies a pulse to the CJJ of qubit Mx via the second VHF control line in the third bundle of analog lines 603 to cause a rotation about the Z-axis of the Bloch sphere. In another embodiment, digital computer 102 may apply a large amplitude ramp to the qubit body of qubit Mx via the first VHF control line in the third bundle of analog lines 603.

[0097] In 902b, digital computer 102 initializes the qubits (Mz) in the fourth plurality of qubits 404 to the ground state. In at least one embodiment, digital computer 102 may apply a pulse to the CJJ of qubit Mz via the second VHF control line in the fourth bundle of analog lines 604 to cause a rotation about the Z-axis of the Bloch sphere. In another embodiment, digital computer 102 may apply a large amplitude ramp to the qubit body of qubit Mz via the first VHF control line in the fourth bundle of analog lines 604.

[0098] In 903, digital computer 102 applies a Hadamard gate (H gate) to qubit Mx. In at least one embodiment, digital computer 102 applies a pulse to the body of the qubit via the first VHF control line in the third bundle of analog lines 603 to cause a rotation about the axis in the XY plane. Since qubit Mx is initialized to the ground state |0> of the energy eigenbasis in 902a, qubit Mx then becomes the superposition state |+>. Act 903 corresponds to time block 802 of FIG. 8 and act 502 of FIGS. 5A and 5B.

[0099] Acts 904a and 904b are executed by digital computer 102 either in parallel or together, or even simultaneously. Acts 904a and 904b correspond to time block 803 of FIG. 8 and acts 503 of FIGS. 5A and 5B that respectively perform act A and act A' of sequences ABCD and A'B'C'D'.

[0100] In 904a, digital computer 102 causes a first CNOT gate to be applied to a data qubit (DB) in a second plurality of qubits 402 as a control qubit and to a qubit Mz in a fourth plurality of qubits 404 as a target qubit. This can be archived using the second bundle of analog lines 602, the fourth bundle of analog lines 604, and the first set of analog lines 701 as described above with reference to FIG. 7.

[0101] In 904b, digital computer 102 causes a second CNOT gate to be applied to a data qubit (DA) in a first plurality of qubits 401 as a target qubit and to a qubit Mx in a third plurality of qubits 403 as a control qubit. This can be archived using the first bundle of analog lines 601, the fourth bundle of analog lines 603, and the fifth set of analog lines 705 as described above with reference to FIG. 7.

[0102] Acts 905a and 905b are executed by digital computer 102 either in parallel or together, or even simultaneously. Acts 905a and 905b correspond to time block 804 of FIG. 8 and acts 504 of FIGS. 5A and 5B that respectively perform act B and act B' of sequences ABCD and A'B'C'D'.

[0103] In 905a, digital computer 102 causes a third CNOT gate to be applied to data qubit DA in a first plurality of qubits 401 as a control qubit and to Mz as a target qubit using the first bundle of analog lines 601, the fourth bundle of analog lines 604, and the second set of analog lines 702 as described above with reference to FIG. 7.

[0104] In 905b, as described above with reference to FIG. 7, digital computer 102 uses the second bundle of analog lines 602, the third bundle of analog lines 603, and the sixth set of analog lines 706 to apply a fourth CNOT gate to data qubit DB in the second plurality of qubits 402 as a target qubit and to Mx as a control qubit.

[0105] Acts 906a and 906b are performed by digital computer 102 in parallel or together, or even simultaneously. Acts 906a and 906b correspond to time block 805 in FIG. 8 and to acts 505 in FIGS. 5A and 5B that perform acts C and C' of sequences ABCD and A'B'C'D', respectively.

[0106] In 906a, as described above with reference to FIG. 7, digital computer 102 uses the first bundle of analog lines 601, the fourth bundle of analog lines 604, and the third set of analog lines 703 to apply a fifth CNOT gate to data qubit DA in the first plurality of qubits 401 as a control qubit and to Mz as a target qubit.

[0107] In 906b, as described above with reference to FIG. 7, digital computer 102 uses the second bundle of analog lines 602, the third bundle of analog lines 603, and the seventh set of analog lines 707 to apply a sixth CNOT gate to data qubit DB in the second plurality of qubits 402 as a target qubit and to Mx as a control qubit.

[0108] Acts 907a and 907b are performed by digital computer 102 in parallel or together, or even simultaneously. Acts 907a and 907b correspond to time block 806 in FIG. 8 and to acts 506 in FIGS. 5A and 5B that perform acts D and D' of sequences ABCD and A'B'C'D', respectively.

[0109] At 907a, as described above with reference to FIG. 7, the digital computer 102 uses the second bundle of analog lines 602, the fourth bundle of analog lines 604, and the fourth set of analog lines 704 to apply the seventh CNOT gate to the data qubit DB in the second plurality of qubits 402 as a control qubit and to Mz as a target qubit.

[0110] At 907b, as described above with reference to FIG. 7, the digital computer 102 uses the first bundle of analog lines 601, the third bundle of analog lines 603, and the eighth set of analog lines 708 to apply the eighth CNOT gate to the data qubit DA in the first plurality of qubits 401 as a target qubit and to Mx as a control qubit.

[0111] At 908, the digital computer 102 applies the H gate to the qubit Mx. In at least one embodiment, the digital computer 102 can apply a pulse to the body of the qubit via the first VHF control line in the third bundle of analog lines 603 to cause a rotation about an axis in the XY plane of the Bloch sphere. Act 908 corresponds to time block 807 in FIG. 8 and act 507 in FIGS. 5A and 5B.

[0112] Acts 909a and 909b are executed by the digital computer 102 in parallel or together, or even simultaneously. Acts 909a and 909b correspond to time block 808 in FIG. 8 and act 508 in FIGS. 5A and 5B.

[0113] At 909a, the digital computer 102 causes the state of the qubit Mx to be read out. In some embodiments, the qubit Mx is read out via the readout control system 128. In at least one embodiment, frequency multiplexing resonant readout (FMRR), as described in U.S. Patent No. 10,938,346, is employed.

[0114] In 909b, the digital computer 102 causes the state of the qubit Mz to be read out. By reading out the stabilized qubit, the constraints of the no-cloning theorem that would otherwise clearly measure the data qubit to identify errors can advantageously be avoided. In some embodiments, the qubit Mx is read out via a readout control system 128. In at least one embodiment, frequency multiplexed resonance readout (FMRR) is employed as described in U.S. Patent No. 10,938,346. Further readout techniques that can be employed are described in U.S. Patent Application No. 63 / 448,537.

[0115] In 910, the method 900 ends, for example, until it is called again.

[0116] Device Homogenization and Use of Template Signals Surface code quantum processing units (QPUs) have manufacturing defects, i.e., differences between devices on the same die. Depending on the defect, it may render a few devices within an otherwise functional die unusable. Thus, it can be advantageous to use an on-chip flux DAC to homogenize the properties of the qubits and couplers and to isolate broken devices. In-situ homogenization of the devices can be quite desirable as it can allow for the surface code to extend on the QPU using only a few shared bias lines, as in the embodiments shown in FIGS. 6 and 7.

[0117] Physical Qubit Homogenization The qubits in a quantum processor such as the quantum processor 400 can be controlled to perform rotations about axes in the XY plane and rotations about the Z axis of the Bloch sphere by a modulated AC signal. In the case of fluxonium qubits, these controls correspond to applying magnetic signals to the qubit body and the CJJ respectively. It may be desirable to homogenize the fabrication variations of both the qubits and the qubit-to-qubit couplers using composite - composite Josephson junctions (CCJJs) (Harris et al., 2010, Phys. Rev. B81, 134510). As shown in FIG. 8, it is further desirable to communicate such qubit CCJJs with a static on - chip DAC, communicate an analog pre - bias line with the sub - lobe of the CCJJ to apply signals and improve the junction variations, and communicate a programmable DAC with the main loop of the qubit to homogenize the energy spacing of the qubits at a low (L) operating point. In at least one embodiment, the qubit energy spacing is homogenized using CCJJ control as described above. Considering that small but fast pulses to the target bias are shared among members of the qubit sub - lattice as shown in FIG. 8, the mutual inductance between the global bias and the target loop of each qubit can be beneficially adjusted in - situ, thereby homogenizing the response of the qubits to these signals.

[0118] As will be described later with reference to FIG. 10, the local DAC can flux - bias the adjustable mutual inductance between the global bias and the target loop of each qubit to a point where the response of the qubit is homogenized despite the attenuation and distortion of the control pulse as it travels to the control line and the differences in the qubit - to - qubit field coupling matrix elements between qubits. All time - dependent signals are provided by shared XY control lines and Z control lines, while the adjustable mutual inductance between the global bias and their target loops remains static during the surface code cycle.

[0119] FIG. 10 is a schematic diagram 1000 of a qubit 1001 having homogenized structures 1008 and 1013. The qubit 1001 is a concentrated-element fluxonium qubit having a high kinetic inductance material, similar to the superconducting qubit 300 of FIG. 3. The qubit 1001 includes a plurality of inductances 1002 (only one is shown in FIG. 10 to reduce visual clutter) shunted by a plurality of capacitors 1003 (only one is shown in FIG. 10 to reduce visual clutter). The qubit 1001 further includes an inductance 1004 and a composite - composite Josephson junction (CCJJ) structure 1005. The CCJJ structure 1005 includes a first CJJ 1006a in parallel with a second CJJ 1006b. A first inductance 1007a is in series with the first CJJ 1006a, and a second inductance 1007b is in series with the second CJJ 1006b.

[0120] The first control structure 1008 (CNTL-XY) is communicatively coupled via the inductance 1004 of the qubit 1001 and facilitates rotation about the XY plane of the Bloch sphere by mediating signals from the shared VHF control line 1009 to the inductance 1004. State rotation about an axis in the XY plane of the Bloch sphere is achieved by applying a VHF pulse to the inductance 1004 via the first control structure 1008 (CNTL-XY). The time-dependent control signal applied to the shared VHF control line 1009 can be referred to as a template signal. The control structure 1008 facilitates a per-qubit custom adjustment of the magnitude of the VHF pulse seen by the qubit 1001. If there is some variation in device parameters on the order of a few percent, a custom adjustment of the amplitude of the applied control signal can be sufficient to guarantee high gate fidelity across the qubit sublattice. The custom adjustment can be achieved by setting a static magnetic flux bias using a first DAC 1010 that applies a static magnetic flux bias to the CJJ loop 1011 of the control structure 1008.

[0121] In addition to the control structure 1008, the second DAC 1012 is communicatively coupled to the inductor 1004. The purpose of the second DAC 1012 is to apply a static magnetic flux bias to the body of the qubit 1001 to compensate for the magnetic flux offset within the body of the qubit 1001. The DAC 1012 does not provide control of the first control structure 1008.

[0122] The second control structure 1013 (CNTL-Z) is communicatively coupled to the CCJJ structure 1005 to facilitate rotation about the Z-plane of the Bloch sphere. Rotation about the Z-axis of the Bloch sphere is achieved by applying a VHF pulse to the CCJJ structure 1005 via the second control structure 1013 (CNTL-Z). The time-dependent control signal applied to the shared VHF control line 1014 is referred to as a template signal. The control structure 1013 facilitates a custom qubit-by-qubit adjustment of the magnitude of the VHF pulse as seen by the qubit 1001. If there is some variation in the device parameters on the order of a few percent, a custom adjustment of the amplitude of the applied control signal can be sufficient to guarantee high gate fidelity across the entire qubit sublattice. The custom adjustment can be achieved by setting a static magnetic flux bias using a third DAC 1015 that applies the static magnetic flux bias to the CJJ loop 1016 of the control structure 1013.

[0123] In addition to the control structure 1013, the fourth DAC 1017 is communicatively coupled to the CCJJ structure 1005. The purpose of the fourth DAC 1017 is to apply a static bias to the CCJJ structure 1005 of the qubit 1001 to compensate for the offset within the CCJJ structure 1005. The DAC 1017 does not provide control of the second control structure 1013.

[0124] Homogenization of the qubit-to-qubit coupler The coupler operating point is pulsed during surface code execution to implement entangled gates, and the non - linear flux offset of coupler generation within the qubit is undesirable (Harris et al., 2009, Phys. Rev. B80, 052506). Such a flux offset can be a result of coupler inhomogeneity. The CCJJ control head can be used for the inter - qubit coupler having a static DAC bias in the sub - lobe. Furthermore, the DAC that flux - biases the coupler body can be used to eliminate any static flux offset within the coupler body.

[0125] The control of the time - dependent inter - qubit coupler can be realized by mediating the coupling between the shared analog bias represented by C i (i ∈ [A, B, C, D, A’, B’, C’, D’]) and the CCJJ main loop of the inter - qubit coupler. The mediation is provided by an adjustable inductive coupler. Furthermore, a local DAC can provide a bias signal to the CCJJ main lobe of the inter - qubit coupler. The DAC is used to bias the qubit coupler at its zero - coupling - energy (g = 0) point. The state where the zero signal is present on the analog bias control line C i can be regarded as the low - operating - level of the coupler. C i then biases the coupler to a high - operating - level. Considering that the control of the inter - qubit coupler enables the homogenization of the generated two - qubit gates, some variation in the qubit persistent current is acceptable.

[0126] FIG. 11 shows a schematic diagram 1100 of an inductive coupler 1101 showing a first DAC 1108 and a homogenization structure 1109. The inductive coupler 1101 can be an inter-qubit coupler within the first or second plurality of couplers 405 and 406 of FIG. 4. The inductive coupler 1101 is a lumped element coupler including a plurality of inductances 1102 (only one is shown in FIG. 11 for visual clutter reduction) connected in series and shunted by a plurality of capacitors 1103 (only one is shown in FIG. 11 for visual clutter reduction). The inductive coupler 1101 further includes an inductance 1104 and a CCJJ structure 1105. The CCJJ structure 1105 includes a first CJJ 1106a arranged in parallel with a second CJJ 1106b. A first inductance 1107a is arranged in series with the first CJJ 1106a, and a second inductance 1107b is arranged in series with the second CJJ 1106b.

[0127] The first DAC 1108 is communicatively coupled to the inductance 1104 and is operable to provide a static bias to the loop of the inductive coupler 1101 to compensate for the magnetic flux offset of the coupler 1101.

[0128] The control structure 1109 (CNTL-C) is communicatively coupled to the CCJJ structure 1105, operable to provide an adjustable magnetic flux to the CCJJ structure 1105, and to mediate a DC analog control signal from line 1110 (C i )). The time-dependent control signal applied to the shared VHF control line 1110 is called a template signal. The control structure 1109 facilitates a custom per-quantum-bit adjustment of the magnitude of the VHF pulse seen by the coupler 1101. If there is some variation in the device parameters on the order of a few percent, a custom adjustment of the amplitude of the applied control signal can be sufficient to guarantee high gate fidelity across the entire coupler sublattice. The custom adjustment can be achieved by setting a static magnetic flux bias using a second DAC 1111 that applies a static magnetic flux bias to the CJJ loop 1112 of the control structure 1109.

[0129] In addition to the control structure 1109, a third DAC 1113 is communicatively coupled to the CCJJ structure 1105. The purpose of the third DAC 1113 is to apply a static bias to the CCJJ structure 1105 of the coupler 1101 to compensate for the flux offset within the CCJJ structure 1105.

[0130] Quantum Logic Unit FIG. 12 is a schematic diagram of an example quantum logic unit (QLU) 1200 that can be employed according to the present system, device, and method. The quantum logic unit (QLU) 1200 can be, for example, part of a quantum processor such as the quantum processor 126 of FIG. 1. The QLU 1200 has a plurality of physical qubits and a plurality of couplers, and each coupler provides a controllable coupling between a pair of physical qubits as described with respect to FIG. 4. The QLU 1200 shows qubits and couplers as provided in a portion of the quantum processor 400 in an alternative representation. In FIG. 12, stabilizers are represented by solid squares or rectangles, and the shading of the solid square or rectangle represents the type of parity measurement qubit at the center of the face as shown in the legend 1222. For further consideration of parity stabilizers, see FIGS. 14 and International Application No. PCT / US2021 / 024134. Data qubits are located at the vertices of each square or rectangle. Each edge of the lattice has a color based on the type of logical qubit operator that can be constructed from a sequence of Pauli operators taken along that edge. The arrangement of physical qubits and couplers is similar to that shown in FIG. 4 with both data qubits and error measurement qubits. The QLU 1200 in FIG. 12 has a distance d = 5. In this regard, the distance d is defined as the minimum number of data qubits that must be bit-flipped or phase-flipped simultaneously to implement either a logical X operation or a logical Z operation.

[0131] The QLU1200 includes a logical qubit 1218 that forms a shift register state (only one is mobilized to reduce visual clutter) in a shaded cross region that provides a shift register region 1202 and two local interaction regions (1204, 1206, 1208, 1210). The shift register region 1202 and the two local interaction regions 1204, 1206, 1208, 1210 are composed of one or more logical qubits, and each logical qubit includes a subset of physical qubits among a plurality of physical qubits that are coupled to form a logical qubit, as discussed with respect to FIG. 4. The logical qubits in the interaction regions and the shift register can also be used as memory when not being used for calculations and other interactions so that data can reside in the logical qubits of the shift register or the logical interaction regions. That is, when a particular region is not in use, its logical qubits are available as memory. In some embodiments, a bank of memory registers can also be provided. Region 1204 (delimited by a dashed line) is a YY interaction zone, region 1206 (delimited by a dashed line) is a YZ interaction zone, region 1208 (delimited by a dashed line) is an XZ interaction zone, and region 1210 (delimited by a dashed line) is an XY interaction zone. Each interaction zone is arranged to provide the indicated type of interaction and, in some embodiments, can be hardwired to provide only the indicated type of interaction. The QLU is composed of a plurality of logical qubits including rectangular logical qubits at 1212 and 1214 and square logical qubits at 1218 and 1220. The QLU1200 includes a block of surface codes and forms a logical qubit block, as discussed with respect to FIG. 4. For example, the QLU1200 has logical qubits 1212 and 1214. Each logical qubit block is composed of a plurality of physical qubits among a plurality of physical qubits that are coupled by couplers to form logical qubits, as previously discussed with respect to FIG. 4. Merge blocks, such as merge block 1216, are formed between adjacent logical qubits.The merge block is composed of at least one line of physical data qubits (hereinafter also referred to as "merge block qubits") disposed between two logical qubits. The merge block qubits are controlled independently of the logical qubits. In some embodiments, one or more control lines are directed to the individual control of each merge block. The shift register logical qubits are provided by selectively communicating with at least two interacting logical qubits such as the shift register logical qubit 1218 that communicates with the interacting logical qubit 1214. In some embodiments, the shift register region 1202 is a plurality of logical qubits selectively coupled by a plurality of merge blocks. One or more two-local interaction regions (1204, 1206, 1208, 1210) communicate with the shift register stage and are provided by connecting the shift register stage.

[0132] Each quantum logic block may have one or more independent control lines that provide a possession control bias signal to at least a subset of the physical qubits within each logical qubit. Refer to FIGS. 6 and 7 for considerations of control line arrangement. In some embodiments, one or more independent control lines can be activated to provide a signal to each logical qubit in a group to perform a given action simultaneously. The group can be a particular two-local interaction register such as one of the two-local interaction regions 1204, 1206, 1208, 1210. Each region of the QLU can be hardwired to perform a particular type of interaction, and by activating a dedicated control line, cause that particular interaction to occur.

[0133] FIG. 13 is a schematic diagram of an exemplary embodiment of a quantum logic unit (QLU) 1300 that can be employed by the present system, the present device, and the present method. In particular, FIG. 13 shows the possible directions of data movement within QLU 1300 along with a legend 1316. QLU 1300 is similar to QLU 1200, but FIG. 13 differs from FIG. 12 in that the QLU is annotated to show the direction of data movement during the execution of operations. Region 1308 is a YY interaction zone, region 1310 is a YZ interaction zone, region 1312 is an XZ interaction zone, and region 1314 is an XY interaction zone. Symmetric XX and ZZ interactions are seen in horizontal and vertical movements, respectively. One exception occurs within the XZ interaction zone, where the ZZ interaction occurs obliquely at 1304. As shown by the vertical ZZ movement 1302 (only one is mobilized to reduce noise) and the oblique ZZ movement 1304 in QLU 1300, the data qubits of the target block and the merge block are initialized to the |+> state to move data across adjacent Z edges, the merge operation corresponds to a ZZ measurement, and the data qubits of the source block and the merge block are measured in the X basis. As shown by the horizontal XX movement 1306 (only one is mobilized to reduce noise) in QLU 1300, for movement across adjacent X edges, the data qubits of the target block and the merge block are initialized to the |0> state, the merge operation corresponds to an XX measurement, and the data qubits of the source block and the merge block are measured in the Z basis. Except for the ZZ oblique movement in the XZ zone, the merge operation may correspond to turning on a patch of the standard surface code between the source logical qubit and the target logical qubit. In the case of the above exception, a column of mixed stabilizers is used to perform a transposition in the surface code. XX and ZZ two-local Pauli measurements are available for qubit movement. In addition, XX and ZZ merge blocks can also be used in calculations when both of the neighboring logical qubits contain data.

[0134] FIG. 14 is a schematic diagram of an example quantum logic unit (QLU) 1400 that can be employed by the present system, the present device, and the present method. In particular, FIG. 14 shows an example pattern of stabilizers that change or turn on by activating physical data qubits within XX and ZZ merge blocks, along with a legend 1410. QLU 1400 is similar to QLU 1200 and QLU 1300 and shows the QPU when a particular merge block is activated. The first activated merge block as an example is shown at 1402, the second activated merge block is shown at 1404, the third activated merge block is shown at 1406, and the fourth activated merge block is shown at 1408. It will be understood that the example activated merge blocks 1402, 1404, 1406, 1408 represent merge blocks that can be performed between other similar locations on QLU 1400. Dedicated portions such as the triangular portion of 1402 and the split portion of the fourth activated merge block 1408 can operate using the same schedule as the square stabilizer cells. Merge blocks with mixed-type stabilizers may have a control sequence different from the standard surface code cycle in order to adapt to these dedicated portions.

[0135] FIG. 15 is a schematic diagram of an example quantum logic unit (QLU) 1500 that can be employed by the present system, the present device, and the present method. In particular, FIG. 15 shows examples of merge block stabilizer patterns for XY, XZ, YY, and YZ merges, along with a legend 1518. The QLU 1500 is similar to the QLUs 1200, 1300, and 1400 and shows the activation of different merge blocks from those in FIG. 14. The logical qubit blocks within each region are labeled "1" and "2" (and "3" in the case of the XZ zone) to indicate the pairs of logical qubits [1, 2] (and [2, 3] in the case of the XZ zone) involved in logical interactions. Zone 1502 is a YY zone having a merge block stabilizer pattern 1504 for a YY merge. Zone 1506 is an XZ zone having a merge block stabilizer pattern 1508 for an XZ merge. Zone 1510 is a YZ zone having a merge block stabilizer pattern 1512 for a YZ merge. Zone 1514 is an XY zone having a merge block stabilizer pattern 1516 for an XY merge.

[0136] The YY merge operation involves merging two mirrored hybrid boundaries facing each other. An example of a merge block design is shown as the merge block stabilizer pattern 1504 in FIG. 15. One example embodiment uses two rows of physical data qubits and three rows of stabilizers. On either side of the center of the merge block, it appears like patches of a standard surface code that toggles on / off. However, at the center of the merge block, there is a 6-local parity enforcer. Such local customization of the surface code control waveform may involve introducing one additional time step into the global surface code cycle to keep all operations synchronized across the QLU 1500. The parity of two data qubits along the vertical axis of symmetry in a special stabilizer is measured in the Y basis, which is also a deviation from the standard surface code cycle. Within the example embodiment shown, the YY merge block holds its own template waveform and the Y-basis parity measurement control can be performed only on those two aforementioned physical data qubits.

[0137] The proposed merge block designs for the hybrid two-local Pauli measurements XY and YZ are shown as the merge block stabilizer patterns 1516 and 1512 respectively. Half of the merge block looks like a standard surface code as expected when a pair of X-edges or a pair of Z-edges are merged. In contrast, the other half of the merge zone employs a hybrid stabilizer as shown by the trapezoid and two patterned triangles in FIG. 15. This feature is called a transposed line. At the center of the merge block, there is something that can be called a "twist defect". This feature is a 5-local hybrid parity stabilizer shown touching the edges of the logical qubit "2" in both zones 1510 and 1514. The twist involves the use of Y-basis parity measurements within the 5-local stabilizer since one of the data qubits functions as part of both X-parity and Z-parity measurements. The result is XZ = iY and thus this results in a measurement in the Y basis.

[0138] The proposed data load path and the proposed merge block for the 2-local XZ Pauli measurement are shown in zone 1506 of FIG. 15. In this case, the first task performed by the QLU 1500 is to take data from the shift register and rotate its boundary by π / 2. This is done by moving the data to logical qubit "2" through logical qubits "1" and "special purpose" ZZ merge as shown by the merge block 1408 in FIG. 14. "Special purpose" indicates that the mixed stabilizer inside the merge block 1408 is not used in other ZZ merges, as described herein. Let the second data be loaded into logical qubit "3". The merge block includes transposed lines throughout, as discussed above. The XZ block has a second mode of operation: it can be used to rotate logical qubits. The logical qubit to be rotated is first taken from the shift register and moved to position "2". The logical qubit at position "3" is then initialized to the |0 L > state and then the merge block is turned on between "2" and "3". Finally, the rotated logical qubit is taken from position "3" and returned to the shift register.

[0139] It will be appreciated that the quantum logic units 1200, 1300, 1400, and 1500 may form only a part of the quantum processor. Depending on the quantum processor, two or more quantum logic units may be communicatively coupled. In some embodiments, other types of units may be included, such as units dedicated to template waveform distribution, clock synchronization, DAC programming interface, and readout and error syndrome data compensation / preprocessing. Additionally, an on-chip structure may be provided to perform other operations. In some embodiments, the quantum processor may include a unit that provides at least one error-corrected single-qubit operation block that is not in the Clifford group. The Clifford group defines a set of mathematical transformations that affect the permutations of Pauli operations. In some embodiments, the at least one error-corrected single-qubit operation block may be a magic state distillation module. For example, in some embodiments,

Number

[0140] FIG. 16 is a schematic diagram of an exemplary embodiment of a floor plan of a single-level magic state distillation module 1600 that can be employed by the present system, the present device, and the present method. In particular, FIG. 16 shows the top level together with a legend 1618. In this regard, distillation refers to an act that starts with a plurality of defective copies of a desired state and uses them to extract a copy with a lower defect degree of one of the desired states. When such a distillation procedure functions, the distillation procedures can be concatenated to further reduce the possibility of errors in the final copy. The magic state distillation module 1600 of FIG. 16 has seven logical qubits (1602, 1604, 1606, 1608, 1610, 1612, 1614) and one logical auxiliary qubit 1616.

[0141] FIG. 17 is a schematic diagram of an alternative exemplary embodiment of a floor plan of a single-level magic state distillation module 1700 that can be employed by the present system, the present device, and the present method. In particular, FIG. 17 shows the bottom level together with a legend 1718. The magic state distillation module 1700 of FIG. 17 has seven logical qubits (1702, 1704, 1706, 1708, 1710, 1712, 1714) and one logical auxiliary qubit 1716.

[0142] Each of the seven single logical qubits shown in FIGS. 16 and 17 can be implemented as discussed above and holds a single pair of X edges and a single pair of Z edges. Each of FIGS. 16 and 17 also includes an eighth auxiliary qubit that is a composite object of three logical qubits and has three pairs of X edges and three pairs of Z edges. In FIGS. 16 and 17, the annotations inside each logical qubit indicate an identifier (1-7, A) and the logical state (|0>, |+>, |m0>) in which the qubit should be initialized. The state |m0> indicates a zero-order error-corrected |m> generated via state injection (logical qubits 1604, 1606, 1608, 1610, and 1612 in the magic state distillation module 1600). The output state is a first-order error-corrected |m> indicated as |m1>. The code distance d z and d xrepresents the code distance of the composite auxiliary qubit "A" (logical qubit 1616 or 1716). The code distances d z and d x can be asymmetric in some embodiments. FIG. 17 is laid out similarly to FIG. 16, but the magic state distillation module 1700 in FIG. 17 receives the once-corrected |m1>s. The output state is the twice-error-corrected |m> shown as |m2>. In the illustrated embodiment, the state in which the logical qubit is to be initialized distinguishes the top level and the bottom level. The magic state distillation module 1600 consumes the zero-error-corrected |m>s shown as |m0>, which are generated by state injection (for a detailed description of state injection, see Horsman et al., Surface code quantum computing by lattice surgery, New Journal of Physics, Volume 14, December 2012). The logical qubits 1604, 1606, 1608, 1610, and 1612 are hardwired to perform state injection. For each trial of distillation, the logical qubit 1604 is initialized to |m0> eleven times, while the other logical qubits are initialized only once. The magic state distillation module 1600 generates a single once-error-corrected copy of |m> shown as |m1>. The magic state distillation module 1700 has no basis for state injection and instead consumes the 15 |m1>s generated by a nearby L1 module, which can be another magic state distillation module such as the magic state distillation module 1600 in FIG. 16, to distill one copy of the twice-error-corrected |m> shown as |m2>. In some embodiments, additional layers of distillation can be added to further reduce errors in the final distilled output. The code distances d z and d xcorresponds to the Z-edge and X-edge of the auxiliary qubits 1616 and 1716 respectively. The states of the auxiliary qubits 1616 and 1716 are repeatedly refreshed to |m>, and then consumed during the multi-qubit π / 8 rotation. This is a distillation circuit where the output is verified before use, i.e., if the result is suspected to be defective, the result is not used. Therefore, the lifetimes of the auxiliary qubits 1616 and 1716 do not need to be the same as the lifetime of the entire quantum computation. Thus, the code distances d z and d x may be shorter than those used within the bulk of the surface code QPU. The distance may be shortened, and correspondingly, the success probability of outputting a distilled copy of |m> decreases. Advantageously, this may enable the entire magic state factory to have a smaller footprint and, in some cases, fit within a single die. The final state of the logical qubit 1614 is then transferred to the shift register stage 1804 of FIG. 18, and the final state of the logical qubit 1714 is then transferred to the logical qubit 1808 of FIG. 18.

[0143] FIG. 18 is a schematic diagram of an exemplary embodiment of a floor plan of a magic state factory 1800 that can be employed according to the present system, device, and method. The floor plan of the magic state factory 1800 is shown together with a legend 1814, based on the magic state distillation modules 1600 and 1700 of FIGS. 16 and 17. The shift register stage 1804 (only one is mobilized) moves the primary error-corrected magic state |m1> output by the L1 module 1802 (only one is mobilized) to the input of the L2 module 1806 (only one is mobilized). The secondary error-corrected magic state |m2> is from d z to d QPUIt moves to a dedicated memory register that increases the Hamming distance of the surface code up to. This dedicated memory register acts in the same way as the shift operation. If a viable copy of |m> exists in the long logical qubit 1808, the long logical qubit 1808 merges with a patch of the surface code 1810. The generated logical state occupies the entire patch that forms the logical qubit 1812. Many L1 modules 1802 can be similar to the magic state distillation module 1600 of FIG. 16 and are connected to the shift register state 1804 that supplies inputs to two sides of the L2 module 1806. The number of L1 modules 1802 can be restricted by the projection success rates of the L1 and L2 modules 1802 and 1806. Although it may be beneficial to increase the number of modules, the optimal total number of modules will be restricted by the amount of physical space and the rate at which |m1>s are consumed by the L2 module 1806. The output of the L2 module 1806 is sent to the long logical qubit 1808 of distance d z and the long logical qubit 1808 is coupled to a larger patch 1810 of the surface code of distance d QPU -d z where d QPU is the distance used within the bulk of the surface code QPU as discussed above. With the patch 1810 of the surface code initialized to |0>, when the final two states are merged, a logical qubit 1812 of distance d QPU results. The logical qubit 1812 can interface with the rest of the QPU through the shift register.

[0144] FIG. 19 is a flowchart of an example method 1900 for moving data within a quantum processor that can be employed by the present system, the present device, and the present method. The method 1900 can be used, for example, to move data within a quantum logic unit such as those previously discussed with respect to FIGS. 12-18. In some embodiments, the method 1900 can be executed in a hybrid computing system that includes at least one digital or classical processor and at least one quantum processor. The digital or classical processor can provide control signals or instructions for executing the method to the quantum processor.

[0145] Method 1900 includes acts 1902 - 1908, but the number of acts is an example, and those skilled in the art will understand that in some embodiments, certain acts may be omitted, additional acts may be added, and / or the order of the acts may be changed.

[0146] Method 1900 is initiated, for example, in response to a call or invocation from another routine.

[0147] In 1902, a signal to initialize the target data block is induced on one or more control lines of the target data block. The target data block can include one or more logical qubits of a first set (e.g., logical qubits 1212, 1214, 1218 of FIG. 12), and the target data block can nominally be empty. For movement across an adjacent Z edge, one or more logical qubits of the first set can be initialized to the |+> state. For movement across an adjacent X edge, one or more logical qubits of the first set can be initialized to the |0> state (see the movement direction shown in FIG. 13).

[0148] In 1904, a signal to activate the merge block is induced on one or more merge block control lines (e.g., the activated merge blocks of FIGS. 14 and 15). The merge block can include at least one line of physical qubits, can connect the target data block to a source data block, and the source data block can include one or more logical qubits of a second set and can contain data. For movement across an adjacent Z edge, at least one line of physical qubits can be initialized to the |+> state. For movement across an adjacent X edge, at least one line of physical qubits can be initialized to the |0> state.

[0149] In 1906, multiple surface code cycles are run across target data blocks, merge blocks, and source data blocks. Data moves from the source data block to the target data block through the merge block. In some embodiments, d surface code cycles can be run, where d is the minimum number of data qubits that must be bit-flipped or phase-flipped simultaneously to implement either a logical X operation or a logical Z operation, as discussed above. In some embodiments, the target data block can be a shift register or a two-local interaction register. As discussed above, the two-local interaction register can be one of XX, XY, XZ, YY, YZ, and ZZ interaction registers.

[0150] In 1908, a second set of logical qubits including the source data block and at least one line of physical qubits including the merge block are measured. If some of the target data block is not used, such as when the data is smaller than the entire target data block, the unused logical qubits of the target data block that have not received any data can also be measured. For movement across a Z edge, the second set of logical qubits including the source data block and at least one line of physical qubits including the merge block are measured in the X basis such that the merge operation corresponds to a ZZ measurement. For movement across an X edge, the second set of logical qubits including the source data block and at least one line of physical qubits including the merge block are measured in the Z basis such that the merge operation corresponds to an XX measurement.

[0151] After 1908, method 1900 ends, for example, until it is called again. Method 1900 can be iteratively repeated to move data across the quantum processor, where the target data block of the previous iteration becomes the source data block of the next iteration.

[0152] Robust Quantum Computing Architecture for Implementing 2D Surface Codes Despite the presence of a few defective devices, it is advantageous for a robust integrated circuit implementation of a two-dimensional surface code to function. Typically, such defects correspond to devices in which, for example, due to assembly errors, one or more Josephson junctions are slightly out of specification. Since these devices are still responsive to control signals, they can be excluded from the working graph of the quantum processor so as to minimize their impact on neighboring devices. As used herein, the term "working graph" refers to a set of qubits and couplers available for computation within a quantum processor. It would be advantageous to design a two-dimensional surface code quantum processing unit (QPU) that can function despite such imperfections.

[0153] Depending on the particular QPU, there are parameter considerations that define the acceptable range of device parameters. However, there are also coherence specifications to be met. The presence of strongly coupled two-level systems at inappropriate frequencies can render parametrically accurate qubits incompatible with the multi-control schemes described herein with reference to FIGS. 4-11. Thus, it is beneficial to design a two-dimensional surface code architecture with built-in protection against faulty qubits.

[0154] Nagayama et al. (Nagayama et al., 2017, New J. Phys. 19 023050) describe a stabilizer structure that utilizes SWAP operations when data qubits have defects and redirects parity information to functional stabilizer qubits when stabilizer qubits have defects. However, inserting SWAP operations into surface code cycles at arbitrary locations within a QPU requires resource-intensive customized local control, leading to increased complexity. Therefore, the Nagayama structure is not desirable when implementing scalable control. Auger et al. (Auger et al., 2017, Phys. Rev. A 96, 042316) propose either qubit-disablement or disabling the loop of functional data qubits surrounding a defective stabilizer qubit when a single qubit has a defect or is associated with a defective CNOT operation. The main drawback of this approach is that measurements of the partially disabled Z and X stabilizers must be alternated in successive surface code cycles via local-scale customization of the surface code cycle. This approach requires additional hardware, each contributing to increased complexity. Therefore, the Auger approach may not be desirable when implementing scalable control. Both of the above-cited references assume that the complexity of dealing with defective devices is pushed onto control software that modifies the surface code cycle at a local scale. However, any new local-scale degrees of freedom require an additional layer of hardware to route and apply the required control signals. Ultimately, the added control complexity can be as efficient as providing built-in redundancy.

[0155] Tang and Miao (Tang and Miao, 2016, Phys. Rev. A 93, 032322) proposed an implementation of a non-planar graph that can select a subset of functioning devices to form a fully collapsed patch of a two-dimensional surface code. The approach of Tang and Miao introduces non-planar connections that also increase complexity here without providing full redundancy. To provide a scalable surface code implementation that is robust against defective devices, as shown in FIG. 20, a logical qubit design with full redundancy can be provided. Here, the circuit has tunable couplers (also referred to herein as inter-sheet couplers or inter-layer couplers) between each pair of homogeneous physical qubits, i.e., between one data qubit in one layer and one data qubit in the other layer and between one measurement qubit in one layer and one measurement qubit in the other layer, and consists of two two-dimensional surface code sheets or layers. In the present disclosure and the appended claims, the term "homogeneous" is used to indicate devices (e.g., qubits, couplers) that perform the same role in a two-dimensional surface code, and the devices are in two or more different surface code layers. The inter-sheet couplers are intended to facilitate SWAP operations. Similar to the qubit-to-qubit couplers discussed earlier in FIGS. 4 and 11, these couplers should be designed to be separable from their time-dependent control signals via local programmable flux digital / analog converters (DACs). When the top or main sheet of the two-dimensional surface code is fully collapsed, no inter-sheet couplers need to be activated. Further, it may not be necessary to calibrate the devices in the lower sheet. If there is a defect in a device in one layer, as shown in FIGS. 21A and 21B, the inter-sheet couplers connected to the nearest neighbors of the defective qubit should be activated. Each set of five of the physical qubits is calibrated in the lower sheet for each single defective physical qubit in the top sheet. The addition of a second surface code layer of devices for which only a minimum amount of data should be calibrated adds full redundancy while minimizing the increase in calibration complexity.

[0156] FIG. 20 is a schematic diagram of a portion of an example of a quantum processor 2000 implementing a robust surface code having two surface code layers. The quantum processor 2000 has a first or main surface code layer 2001 and a second or sub-surface code layer 2002. Each of the first and second surface code layers 2001 and 2002 is a portion of a quantum processor arranged to implement a two-dimensional surface code, and may be a part of a larger area of the surface code in, for example, the quantum processor 400 of FIG. 4 and / or the QLU 1200 of FIG. 12. In at least one embodiment, the quantum processor 2000 includes a plurality of fractional quantum bits. In another embodiment, the quantum processor 2000 includes a plurality of fractional quantum bits having high mechanical inductance materials. In yet another embodiment, the quantum processor 2000 includes a plurality of transmon quantum bits.

[0157] The first surface code layer 2001 includes a plurality of four quantum bits arranged in a two-dimensional lattice. The first surface code layer 2001, similar to the quantum processor 400 of FIG. 4, includes a first plurality of quantum bits 2003a (only one is shown in FIG. 20 to reduce visual clutter), a second plurality of quantum bits 2004a (only one is shown in FIG. 20 to reduce visual clutter), a third plurality of quantum bits 2005a (only one is shown in FIG. 20 to reduce visual clutter), and a fourth plurality of quantum bits 20006a (only one is shown in FIG. 20 to reduce visual clutter). The first surface code layer 2001, similar to the quantum processor 400 of FIG. 4, also includes a first plurality of couplers 2007a (only one is shown in FIG. 20 to reduce visual clutter) and a second plurality of couplers 2008a (only one is shown in FIG. 20 to reduce visual clutter) that provide communicable couplings between the qubit pairs of the two-dimensional lattice of the first surface code layer 2001. Although not shown, it should be understood that the first surface code layer 2001 may include qubit control lines similar to those shown in FIG. 6 and coupler control lines similar to those shown in FIG. 7 and may be implemented on one or more layers of a substrate.

[0158] The second surface code layer 2002 includes a plurality of four qubits arranged in a two-dimensional lattice. In the present disclosure and the appended claims, the qubits in the second surface code layer 2002 are also referred to as "replacement qubits". Similar to the quantum processor 400 of FIG. 4, the second surface code layer 2002 includes a first plurality of qubits 2003b (only one is mobilized in FIG. 20 to reduce visual clutter), a second plurality of qubits 2004b (only one is mobilized in FIG. 20 to reduce visual clutter), a third plurality of qubits 2005b (only one is mobilized in FIG. 20 to reduce visual clutter), and a fourth plurality of qubits 2006b (only one is mobilized in FIG. 20 to reduce visual clutter). Similar to the quantum processor 400 of FIG. 4, the second surface code layer 2002 also includes a first plurality of couplers 2007b (only one is shown in FIG. 20 to reduce visual clutter) and a second plurality of couplers 2008b (only one is shown in FIG. 20 to reduce visual clutter) that provide communicable couplings between qubit pairs of the two-dimensional lattice of the second surface code layer 2002. Although not shown, it should be understood that the second surface code layer 2002 may include qubit control lines similar to those shown in FIG. 6 and coupler control lines similar to those shown in FIG. 7 and may be implemented on one or more layers of a substrate.

[0159] The quantum processor 2000 further includes a plurality of interlayer couplers (2009a, 2009b, 2009c, and 2009d are mobilized and collectively referred to as 2009), and provides an adjustable communicable coupling between homogeneous qubit pairs from the first surface code layer 2001 and the second surface code layer 2002. For example, the interlayer coupler 2009a provides a communicable coupling between one qubit from a first plurality of qubits 2003a in the first surface code layer 2001 and one qubit from a plurality of qubits 2003b in the second surface code layer 2002. The interlayer coupler 2009b provides a communicable coupling between one qubit from a second plurality of qubits 2004a in the first surface code layer 2001 and one qubit from a second plurality of qubits 2004b in the second surface code layer 2002. The interlayer coupler 2009c provides a communicable coupling between one qubit from a third plurality of qubits 2005a in the first surface code layer 2001 and one qubit from a third plurality of qubits 2005b in the second surface code layer 2002. The interlayer coupler 2009d provides a communicable coupling between one qubit from a fourth plurality of qubits 2006a in the first surface code layer 2001 and one qubit from a fourth plurality of qubits 2006b in the second surface code layer 2002. The interlayer coupler 2009 is controlled via an interlayer control line, as will be shown later herein in FIGS. 24A-24H.

[0160] FIG. 21A is a schematic diagram of a portion 2100a of an example of the quantum processor 2000 of FIG. 20 in which one defective data A qubit is in the first surface code layer 2001. Those skilled in the art will understand that the portion 2100a of the quantum processor 2000 may have two or more defects or non-operating qubits, as shown in FIG. 21A. In the example of the portion 2100a of the quantum processor 2000 shown in FIG. 21A, the defective qubit is the qubit 2101a within the first plurality of qubits 2003a. The defective qubit 2101a is replaced by a replacement qubit 2101b in the second surface code layer 2002 (only a part of the second surface code layer 2002 is shown in FIG. 21A to reduce visual clutter). The defective qubit 2101a and the replacement qubit 2101b are qubits of the same type or homogeneous qubits, i.e., in this example, data A qubits. When the defective qubit 2101a is required for a parity measurement (e.g., a CNOT operation), the states of the coupled parity qubits (i.e., qubits 2102a, 2103a, 2104a, and 2105a) in the first surface code layer 2001 are exchanged with those of their respective counterparts (i.e., qubits 2102b, 2103b, 2104b, and 2105b) in the second surface code layer 2002 by activating the interlayer couplers 2009 (e.g., coupler 2009_a between qubit 2102a and 2102b, coupler 2009_b between qubit 2103a and 2103b, coupler 2009_c between qubit 2104a and 2104b, and coupler 2009_d between qubit 2105a and 2105b) between qubit pairs. When the CNOT operation is completed (see also FIGS. 22A and 22B), the states of each parity qubit should be exchanged again to the first surface code layer 2001 according to the sequence A'-B'-C'-D as shown in FIG. 21A, similar to the positions of the A-B-C-D and A'-B'-C'-D' sequences described in FIG. 4. For a defective data B qubit, the sequence for exchanging neighboring qubits is A-B'-C'-D. The process of qubit exchange between layers in the presence of a defective data qubit is described in more detail with reference to FIGS. 25A and 25B.

[0161] If there is a defect in a parity qubit (i.e., the qubit in the third or fourth plurality of qubits 2005a or 2006a in FIG. 20), the same procedure can be used, and the nearest-neighbor data qubit states (i.e., the states of the qubits in the first or second plurality of qubits 2003a or 2004a) are exchanged between the first surface code layer 2001 and the second surface code layer 2002, as shown in FIG. 21B.

[0162] FIG. 21B is a schematic diagram of a portion of an example of the quantum processor of FIG. 20 having one defective measurement X qubit per layer. As shown in FIG. 21B, one of ordinary skill in the art would understand that the portion 2100b of the quantum processor 2000 may have two or more defective or non-operating qubits. In an example portion 2100b of the quantum processor 2000 shown in FIG. 21B, the defective qubit is the qubit 2104a within the third plurality of qubits 2005a. The defective qubit 2104a is replaced by a replacement qubit 2104b within the second surface code layer 2002 (only a portion of the second surface code layer 2002 is shown in FIG. 21B to reduce visual clutter). The defective qubit 2104a and the replacement qubit 2104b are of the same type of qubit or homogeneous qubits, i.e., in this example, measurement X qubits. When the defective qubit 2104a is required for a parity measurement (e.g., a CNOT operation), the states of the coupled data qubits in the first surface code layer 2001 (i.e., qubits 2101a, 2106a, 2107a, and 2108a) are exchanged with those of their respective counterparts (i.e., qubits 2101b, 2106b, 2107b, and 2108b) in the second surface code layer 2002 by activating the interlayer couplers 2009 between qubit pairs (e.g., coupler 2009_e between qubits 2101a and 2101b, coupler 2009_f between qubits 2106a and 2106b, coupler 2009_g between qubits 2107a and 2107b, and coupler 2009_h between qubits 2108a and 2108b). When the CNOT operation is complete (see also FIGS. 22A and 22B), the state of each data qubit should be exchanged back to the first surface code layer 2001 according to the sequence A'-B'-C'-D' as shown in FIG. 21B. In the case of a defective measurement Z qubit, the sequence for exchanging neighboring qubits is A-B-C-D. The process of exchanging qubits between layers to perform a parity measurement in the presence of a defective measurement qubit is described in more detail with reference to FIGS. 26A and 26B.

[0163] FIG. 21C is a schematic diagram of a portion of an example of the quantum processor of FIG. 20 having one defective coupler between qubits of one layer. As shown in FIG. 21C, one of ordinary skill in the art will understand that portion 2100c of quantum processor 2000 may have two or more defects or non-functional couplers. For example, if there is a defect in a coupler within a first or second plurality of couplers 2007a or 2008a within the first surface code layer 2001, any of the qubits attached thereto can be removed from the working graph and bypassed by following a variation of the above procedure. In an example portion 2100c of the quantum processor 2000 shown in FIG. 21C, the defective device is coupler 2109a within the first plurality of couplers 2007a in the first surface code layer 2001. Defective coupler 2109a is replaced with replacement coupler 2109b in the second surface code layer 2002 (only a portion of the second surface code layer 2002 is shown in FIG. 21C to reduce visual clutter). The defective coupler 2109a and the replacement coupler 2109b are the same type of coupler, i.e., a homogeneous coupler, i.e., an X coupler in this example.

[0164] If the defective coupler 2109a is required for a parity measurement (i.e., A' of sequence A'B'C'D'), the states of the qubits coupled to the defective coupler 2109a (i.e., qubits 2101a and 2104a) in the first surface code layer 2001 should be exchanged with the states of their respective counterparts (i.e., qubits 2101b and 2104b) in the second surface code layer 2002 by activating the interlayer couplers 2009_c and 2009_e between homogeneous qubit pairs (e.g., interlayer coupler 2009_e between qubits 2101a and 2101b and interlayer coupler 2009_c between qubits 2104a and 2104b). Once the parity measurement operation is complete, the state of each qubit coupled to the defective coupler 2109aa should be swapped back to the first surface code layer 2001. The process of exchanging qubits between layers to perform a parity measurement in the presence of a defective coupler will be described in more detail with reference to FIGS. 27A and 27B.

[0165] The modified surface code cycles are shown in FIGS. 22A and 22B, where time is allocated to the SWAP gates before and after every CNOT operation for each physical qubit. However, note that the SWAP operation is only executed if the interlayer coupler connected to that qubit is active for any given time slot for any particular qubit. The proposed architecture eliminates any need for local-scale changes to the surface code cycle, at the expense of doubling the number of devices and uniformly lengthening the cycle time.

[0166] Measurement of parity operators FIG. 22A is a diagram of a gate sequence 2200a for an example of measuring an XXXX parity operator. In at least one embodiment, measuring the XXXX parity operator includes measuring the states of qubits within a third plurality of qubits 2005a of the quantum processor 2000.

[0167] FIG. 22B is a diagram of a gate sequence 2200b for an example of measuring a ZZZZ parity operator. In at least one embodiment, measuring the ZZZZ parity operator includes measuring the states of qubits within a fourth plurality of qubits 2006a of the quantum processor 2000. Similar or identical structures are indicated by the same reference numerals in FIGS. 22A and 22B.

[0168] The SWAP gate can optionally be applied before and after every CNOT operation to account for defective qubits.

[0169] The gate sequence 2200a shows the sequential operations to be performed on: one measurement X qubit (Mx) within the third plurality of qubits 2005a; the first data qubit (DA1) within the first plurality of qubits 2003a; the first data qubit (DB1) within the second plurality of qubits 2004a; the second data qubit (DB2) within the second plurality of qubits 2004a; and the second data qubit (DA2) within the first plurality of qubits 2003a. The gate sequence 2200a follows the sequence A’B’C’D’.

[0170] The gate sequence 2200b shows the sequential operations to be performed on: one measurement Z qubit (Mz) within the fourth plurality of qubits 2006a; the third data qubit (DB3) within the second plurality of qubits 2004a; the third data qubit (DA3) within the first plurality of qubits 2003a; the fourth data qubit (DA4) within the first plurality of qubits 2003a; and the fourth data qubit (DB4) within the second plurality of qubits 2004a. The gate sequence 2200a follows the sequence ABCD.

[0171] The gate sequences 2200a and 2200b can be executed simultaneously or in parallel. Individual qubits (the qubits within the first and second pluralities of qubits 2003a and 2004a) engage in only one measurement X or measurement Z qubit at any given time.

[0172] In 2201, the parity qubits Mx and Mz are each initialized to the ground state |0> in the gate sequences 2200a and 2200b. Refer to acts 2505a and 2505b of method 2500 for more details below.

[0173] In 2202, an H gate (Hadamard gate) is applied to Mx in the gate sequence 2200a.

[0174] In 2203, optionally, if there is a defect in DA1, a first SWAP gate 2210a (shown as a shaded frame in FIG. 22A) is applied as part of the gate sequence 2200a between the functioning Mx in the first surface code layer 2001 and the corresponding Mx in the second surface code layer 2002. On the other hand, if there is a defect in Mx, an optional first SWAP gate 2210c is applied as part of the gate sequence 2200a between the functioning DA1 in the first surface code layer 2001 and the corresponding DA1 in the second surface code layer 2002. The operation of the first two - qubit gate 2211 (e.g., a CNOT gate) is then applied to the first data qubit (DA1) and Mx. If there are no defects in either DA1 or Mx, the two - qubit gate 2211 is applied as part of the gate sequence 2200b between the qubits within the plurality 2003a and the qubits within the plurality 2005a. If there is a defect in either DA1 or Mx, the two - qubit gate 2211 is applied as part of the gate sequence 2200a between the qubits within the plurality 2003b and the qubits within the plurality 2005b. When an optional first SWAP gate 2210a (or 2210c) is applied, after the two - qubit interaction, a second SWAP gate 2210b (or 2210d) is applied to the same qubits as shown by the second shaded frame in the act 2203 of FIG. 22A. A similar sequence is performed simultaneously in 2203 of FIG. 22B, where in 2203 of FIG. 22B, the two qubits in question are the data qubit DB3 and the measurement Z qubit Mz. If there is a defect in one of these qubits, the gate sequence 2200b includes: transferring the state of the functioning qubit from the first surface code layer 2001 to the second surface code layer 2002 via a SWAP operation 2218a (or 2218c), applying a two - qubit interaction 2219, and then returning the state of the functioning qubit to layer 2001 via a SWAP operation 2218b (or 2218d).

[0175] In 2204, optionally, if there is a defect in DB1, a third SWAP gate 2212a (shown as a shaded frame in FIG. 22A) is applied as part of the gate sequence 2200a between Mx in the first surface code layer 2001 and the corresponding Mx in the second surface code layer 2002. On the other hand, if there is a defect in Mx, an optional SWAP gate 2212c is applied as part of the gate sequence 2200a between the functioning DB1 in the first surface code layer 2001 and the corresponding DB1 in the second surface code layer. The operation of the second two-qubit gate 2213 (e.g., a CNOT gate) is then applied to the first data qubit (DB1) and Mx. If there are no defects in either DB1 or Mx, the application of the two-qubit gate 2213 between qubits within the second plurality of qubits 2004a and qubits within the third plurality of qubits 2005a is included as part of the gate sequence 2200a. If there is a defect in either DB1 or Mx, the two-qubit gate 2213 is applied between qubits within the second plurality of qubits 2004b and qubits within the third plurality of qubits 2005b. If an optional third SWAP gate 2212a (or 2212c) is applied, after the two-qubit interaction, a fourth SWAP gate 2212b (or 2212d) is applied to the same qubits, as shown by the second shaded frame in the action 2204 of FIG. 22A. A similar sequence is performed simultaneously in 2204 of FIG. 22B, where the two qubits in question are the data qubit DA3 and the measurement Z qubit Mz. If there is a defect in one of these qubits, the gate sequence 2200b includes: transferring the state of the functioning qubit from the first surface code layer 2001 to the second surface code layer 2002 via a SWAP operation 2220a (or 2200c), applying a two-qubit interaction 2221, and then returning the state of the functioning qubit to layer 2001 via a SWAP operation 2220b (or 2220d).

[0176] In 2205, optionally, if there is a defect in DB2, a fifth SWAP gate 2214a is applied between the Mx in the first surface code layer 2001 and the corresponding Mx in the second surface code layer 2002 as part of the gate sequence 2200a. On the other hand, if there is a defect in Mx, an optional SWAP gate 2214c is applied between the functioning DB2 in the first surface code layer 2001 and the corresponding DB2 in the second surface code layer as part of the gate sequence 2200a. The operation of a third two-qubit gate 2215 (e.g., a CNOT gate) is then applied to the second data qubit (DB2) and Mx. If there are no defects in either DB2 or Mx, the gate sequence 2200a includes applying the two-qubit gate 2215 between a qubit in the second plurality of qubits 2004a and a qubit in the third plurality of qubits 2005a. If there is a defect in either DB2 or Mx, the two-qubit gate 2215 is applied between a qubit in the second plurality of qubits 2004b and a qubit in the third plurality of qubits 2005b. Optionally, if the SWAP gate 2214a (or 2214c) is applied, a SWAP gate 2214b (or 2214d) is applied to the same qubits as shown by the second shaded box in the act 2205 of FIG. 22A. A similar sequence is performed simultaneously in 2205 of FIG. 22B, where in 2205 of FIG. 22B, the two qubits in question are the data qubit DA4 and the measurement Z qubit Mz. If there is a defect in one of these qubits, the gate sequence 2200b includes: transferring the state of the functioning qubit from the first surface code layer 2001 to the second surface code layer 2002 via a SWAP operation 2222a (or 2222c), applying a two-qubit interaction 2223, and then returning the state of the functioning qubit to layer 2001 via a SWAP operation 2222b (or 2222d).

[0177] In 2206, optionally, if there is a defect in DA2, a seventh SWAP gate 2216a is applied between Mx in the first surface code layer 2001 and the corresponding Mx in the second surface code layer 2002 as part of the gate sequence 2200a. On the other hand, if there is a defect in Mx, an optional SWAP gate 2216c is applied between the functioning DA2 in the first surface code layer 2001 and the corresponding DA2 in the second surface code layer 2002 as part of the gate sequence 2200a. The operation of the fourth two-qubit gate 2217 (e.g., a CNOT gate) is then applied to the second data qubit (DA2) and Mx. If there are no defects in either DA2 or Mx, the two-qubit gate 2217 is applied between the qubits in the plurality 2003a and the qubits in the plurality 2005a. If there is a defect in either DA2 or Mx, the two-qubit gate 2217 is applied between the qubits in the plurality 2003b and the qubits in the plurality 2005b. Optionally, if the SWAP gate 2216a (or 2216c) is applied, a SWAP gate 2216b (or 2216d) is applied to the same qubits as shown by the second shaded box in the act 2206 of FIG. 22A. A similar sequence is performed simultaneously in 2206 of FIG. 22B, where in 2206 of FIG. 22B, the two qubits in question are the data qubit DB4 and the measurement Z qubit Mz. If there is a defect in one of these qubits, the gate sequence 2200b includes: transferring the state of the functioning qubit from the first surface code layer 2001 to the second surface code layer 2002 via a SWAP operation 2224a (or 2224c), applying a two-qubit interaction 2225, and then returning the state of the functioning qubit to layer 2001 via a SWAP operation 2224b (or 2224d).

[0178] In 2207, as part of the gate sequence 2200a, an H gate is applied to Mx.

[0179] At 2208, the states of Mx and Mz are read out in the Z basis as part of gate sequences 2200a and 2200b, each resulting in either 0 or 1. In at least one embodiment, frequency multiplexed resonance readout (FMRR) is employed as described in U.S. Patent No. 10,938,346. Further readout techniques that may be employed are described in U.S. Patent Application No. 63 / 448,537.

[0180] Interlayer Coupler Control It is desirable to perform the SWAP operation pair only on qubits that require the SWAP operation and to apply the SWAP operation only in specific time blocks within the surface code cycle. Additional control signals are involved in the spatial and temporal control of the SWAP operation. A portion of the scalable SWAP control scheme described in this disclosure is shown in FIG. 23.

[0181] FIG. 23 is a schematic diagram of an example circuit 2300 including four time-dependent VHF lines that bias induction coupler 2301. In some embodiments, induction coupler 2301 is an interlayer coupler 2009 that provides a communicable and adjustable coupling between qubits within each of the first and second surface code layers 2001 and 2002 of FIG. 20. Induction coupler 2301 can be a distributed or lumped element circuit including a superconducting loop 2302 and a plurality of inductances 2303 arranged in series and shunted by a plurality of capacitors 2304 (only one is shown in FIG. 23 to reduce visual clutter). Induction coupler 2301 further includes inductor 2305 and CCJJ structure 2306. CCJJ structure 2306 includes a first CJJ 2307 arranged in parallel with a second CJJ 2307b. A first induction transformer 2308a is arranged in series with the first CJJ 2307a, and a second induction transformer 2308b is arranged in series with the second CJJ 2307b.

[0182] The first DAC 2309 is communicably coupled to the induction transformer 2305 and is operable to provide a static bias to the superconducting loop of the induction coupler 2301.

[0183] Four control structures 2310 (CNTL-SWAP-i, only one is shown in FIG. 23 for simplicity) are communicatively coupled to the CCJJ structure 2306, providing an adjustable magnetic flux to the CCJJ structure 2306, and four time-dependent control lines 2311S i (only one is shown in FIG. 23 for simplicity) are operable to mediate an analog control signal from one of them, and in the SWAP coupler associated with the measured Z qubit (the fourth plurality of qubits 2006 in FIG. 20), i ∈ [A, B, C, D]; in the SWAP coupler associated with the measured X qubit (the third plurality of qubits 2005 in FIG. 20), i ∈ [A’, B’, C’, D’]; in the SWAP coupler associated with the data A qubit (the first plurality of qubits 2003 in FIG. 20), i ∈ [A’, B, C, D’]; in the SWAP coupler associated with the data B qubit (the second plurality of qubits 2004 in FIG. 20), i ∈ [A, B’, C’, D]. Each one of the control structures 2310 controls a time-dependent signal that causes a pair of SWAP operations to occur in the acts 2203, 2204, 2205, or 2206 of FIGS. 22A and 22B on the control line S i acts as a static switch that either blocks or transmits one of them.

[0184] The layout of control lines similar to control line 2311 is shown in FIGS. 24A to 24H. In each case, the control lines similar to control line 2311 in FIG. 23 move along a path similar to the qubit - to - qubit coupler control lines (analog lines 701 - 708 shown in FIG. 7). However, unlike the control lines (analog lines 701 - 708), the control lines 2401 - 2408 from FIGS. 24A to 24H converge in four groups on the inter - layer couplers (e.g., inter - layer coupler 2009) associated with each physical qubit on both sides of each qubit - to - qubit coupler. Then, four pairs of SWAP control pulses at appropriate timings arrive at each inter - sheet coupler via the four control lines 2311 (each control line 2311 carries two SWAP pulses), but whether any one of those controls leads to a SWAP gate depends on the state of the four adiabatic quantum flux parametron (aQFP) switches 2312 (only one is shown in FIG. 23 for visual clutter reduction). Examples of QFP can be found, for example, in U.S. Patent Nos. 7,843,209 and 8,169,231. The aQFP switches 2312 apply a magnetic flux bias to the CJJ loop 2313 of the control structure 2310. Since each of the four aQFP switches 2312 can be programmed independently, the control circuit 2300 provides both spatial and temporal control for individual SWAP operations. In addition to the four control structures 2310, a third DAC 2314 is communicatively coupled to the CCJJ structure 2306. The purpose of the third DAC 2314 is to apply a static bias to the CCJJ structure 2306 of the coupler 2301 to compensate for the flux offset in the CCJJ structure 2306.

[0185] The architecture of circuit 2300 and quantum processor 2000 is arranged such that at the expense of doubling the number of devices and introducing eight additional VHF lines (lines 2401, 2402, 2403, 2404, 2405, 2406, 2407, and 2408 in FIGS. 24A, 24B, 24C, 24D, 24E, 24F, 24G, and 24H below) and making the cycle time uniformly longer, local - scale changes to the surface code cycle are not used.

[0186] FIG. 24A is a schematic diagram 2400a including a first interlayer coupler control line 2401 that couples qubits within a first plurality of qubits 2003 and qubits within a third plurality of qubits 2005 between a first and a second surface code layer of a quantum processor implementing the robust architecture described above with reference to FIGS. 20, 21A, 21B, 21C, and 23.

[0187] FIG. 2400a shows a first surface code layer 2001 of qubits of a quantum processor 2000 from FIG. 20 including first, second, third, and fourth pluralities of qubits 2003, 2004, 2005, and 2006 respectively (only one qubit within each of the pluralities of qubits is mobilized in FIG. 24A to reduce visual clutter), and first and second pluralities of couplers 2007 and 2008 respectively (only one coupler within each of the pluralities of couplers is mobilized in FIG. 24A to reduce visual clutter). The first coupler control line 2401 provides an analog signal to interlayer couplers 2009a (only one is mobilized to reduce visual clutter) and 2009c (only one is mobilized to reduce visual clutter). Those skilled in the art will understand that the quantum processor 2000 includes as many interlayer couplers 2009a as there are qubits within the first plurality of qubits 2003 and as many interlayer couplers 2009c as there are qubits within the third plurality of qubits 2005. As described above with reference to FIG. 20, the interlayer coupler 2009a provides a communication coupling between qubits within the first plurality of qubits 2003 in the first surface code layer 2001 and qubits within the first plurality of qubits 2003 in the second surface code layer 2002. The interlayer coupler 2009c provides a communication coupling between qubits within the third plurality of qubits 2005 in the first surface code layer 2001 and qubits within the third plurality of qubits 2005 in the second surface code layer 2002. The first coupler control line 2401 follows the same path as the qubit-to-qubit coupler control line (analog line 705 shown in FIG. 7), but provides the analog signal to the interlayer couplers 2009a and 2009c instead of the qubit-to-qubit coupler.

[0188] FIG. 24B is a schematic diagram 2400b including a second coupler control line 2402 of an interlayer coupler that couples qubits in a second plurality of qubits 2004 and qubits in a third plurality of qubits 2005 between a first and a second surface code layer of a quantum processor implementing the robust architecture described above with reference to FIGS. 20, 21A, 21B, 21C, and 23.

[0189] FIG. 2400b shows a first surface code layer 2001 of qubits of a quantum processor 2000 from FIG. 20, which includes first, second, third, and fourth pluralities of qubits 2003, 2004, 2005, and 2006, respectively (only one qubit within each of the pluralities of qubits is mobilized in FIG. 24B to reduce visual clutter), and first and second pluralities of couplers 2007 and 2008, respectively (only one coupler within each of the pluralities of couplers is mobilized in FIG. 24B to reduce visual clutter). The second coupler control line 2402 provides an analog signal to an interlayer coupler 2009b (only one is mobilized to reduce visual clutter) and an interlayer coupler 2009c (only one is mobilized to reduce visual clutter). Those skilled in the art will understand that the quantum processor 2000 includes as many interlayer couplers 2009b as there are qubits in the second plurality of qubits 2004 and as many interlayer couplers 2009c as there are qubits in the third plurality of qubits 2005. As described above with reference to FIG. 20, the interlayer coupler 2009b provides a communication coupling between qubits in the second plurality of qubits 2004 in the first surface code layer 2001 and qubits in the second plurality of qubits 2004 in the second surface code layer 2002. The interlayer coupler 2009c provides a communication coupling between qubits in the third plurality of qubits 2005 in the first surface code layer 2001 and qubits in the third plurality of qubits 2005 in the second surface code layer 2002. The second coupler control line 2402 follows the same path as the qubit-to-qubit coupler control line (analog line 706 shown in FIG. 7), but provides the analog signal to the interlayer couplers 2009b and 2009c instead of the qubit-to-qubit coupler.

[0190] FIG. 24C is a schematic diagram 2400c including a third coupler control line 2403 of an interlayer coupler that couples qubits in a second plurality of qubits 2004 and qubits in a third plurality of qubits 2005 between a first and a second surface code layer of a quantum processor implementing the robust architecture described above with reference to FIGS. 20, 21A, 21B, 21C, and 23.

[0191] FIG. 2400c shows a first surface code layer 2001 of qubits of a quantum processor 2000 from FIG. 20, including first, second, third, and fourth pluralities of qubits 2003, 2004, 2005, and 2006, respectively (only one qubit within each of the pluralities of qubits is mobilized in FIG. 24C to reduce visual clutter), and first and second pluralities of couplers 2007 and 2008, respectively (only one coupler within each of the pluralities of couplers is mobilized in FIG. 24C to reduce visual clutter). The third coupler control line 2403 provides an analog signal to an interlayer coupler 2009b (only one is mobilized to reduce visual clutter) and an interlayer coupler 2009c (only one is mobilized to reduce visual clutter). One of ordinary skill in the art will understand that the quantum processor 2000 includes as many interlayer couplers 2009b as there are qubits in the second plurality of qubits 2004 and as many interlayer couplers 2009c as there are qubits in the third plurality of qubits 2005. As described above with reference to FIG. 20, the interlayer coupler 2009b provides a communication coupling between qubits in the second plurality of qubits 2004 in the first surface code layer 2001 and qubits in the second plurality of qubits 2004 in the second surface code layer 2002. The interlayer coupler 2009c provides a communication coupling between qubits in the third plurality of qubits 2005 in the first surface code layer 2001 and qubits in the third plurality of qubits 2005 in the second surface code layer 2002. The third coupler control line 2403 follows the same path as the path of the qubit-to-qubit coupler control line (analog line 707 shown in FIG. 7), but provides an analog signal to the interlayer couplers 2009b and 2009c instead of the qubit-to-qubit coupler.

[0192] FIG. 24D is a schematic diagram 2400d including a fourth coupler control line 2404 of an interlayer coupler that couples qubits in a first plurality of qubits 2003 and qubits in a third plurality of qubits 2005 between a first and a second surface code layer of a quantum processor implementing the robust architecture described above with reference to FIGS. 20, 21A, 21B, 21C, and 23.

[0193] FIG. 2400d shows a first surface code layer 2001 of qubits of a quantum processor 2000 from FIG. 20, each including first, second, third, and fourth pluralities of qubits 2003, 2004, 2005, and 2006 (only one qubit within each of the pluralities of qubits is mobilized in FIG. 24D to reduce visual clutter), and first and second pluralities of couplers 2007 and 2008, respectively (only one coupler within each of the pluralities of couplers is mobilized in FIG. 24D to reduce visual clutter). The fourth coupler control line 2404 provides an analog signal to an interlayer coupler 2009a (only one is mobilized to reduce visual clutter) and an interlayer coupler 2009c (only one is mobilized to reduce visual clutter). One of ordinary skill in the art will understand that the quantum processor 2000 includes as many interlayer couplers 2009a as there are qubits in the first plurality of qubits 2003 and as many interlayer couplers 2009c as there are qubits in the third plurality of qubits 2005. As described above with reference to FIG. 20, the interlayer coupler 2009a provides a communication coupling between qubits in the first plurality of qubits 2003 in the first surface code layer 2001 and qubits in the first plurality of qubits 2003 in the second surface code layer 2002. The interlayer coupler 2009c provides a communication coupling between qubits in the third plurality of qubits 2005 in the first surface code layer 2001 and qubits in the third plurality of qubits 2005 in the second surface code layer 2002. The fourth coupler control line 2404 follows the same path as the qubit-to-qubit coupler control line (analog line 708 shown in FIG. 7), but provides the analog signal to the interlayer couplers 2009a and 2009c instead of the qubit-to-qubit coupler.

[0194] FIG. 24E is a schematic diagram 2400e including a fifth coupler control line 2405 of an interlayer coupler that couples qubits in a second plurality of qubits 2004 and qubits in a fourth plurality of qubits 2006 between a first and a second surface code layer of a quantum processor implementing the robust architecture described above with reference to FIGS. 20, 21A, 21B, 21C, and 23.

[0195] FIG. 2400e shows a first surface code layer 2001 of qubits of a quantum processor 2000 from FIG. 20, including first, second, third, and fourth pluralities of qubits 2003, 2004, 2005, and 2006, respectively (only one qubit within each of the pluralities of qubits is mobilized in FIG. 24E to reduce visual clutter), and each of first and second pluralities of couplers 2007 and 2008 (only one coupler within each of the pluralities of couplers is mobilized in FIG. 24E to reduce visual clutter). The fifth coupler control line 2405 provides an analog signal to an interlayer coupler 2009b (only one is mobilized to reduce visual clutter) and an interlayer coupler 2009d (only one is mobilized to reduce visual clutter). Those skilled in the art will understand that the quantum processor 2000 includes as many interlayer couplers 2009b as there are qubits in the second plurality of qubits 2004 and as many interlayer couplers 2009d as there are qubits in the fourth plurality of qubits 2006. As described above with reference to FIG. 20, the interlayer coupler 2009b provides a communication coupling between qubits in the second plurality of qubits 2004 in the first surface code layer 2001 and qubits in the second plurality of qubits 2004 in the second surface code layer 2002. The interlayer coupler 2009d provides a communication coupling between qubits in the fourth plurality of qubits 2006 in the first surface code layer 2001 and qubits in the fourth plurality of qubits 2006 in the second surface code layer 2002. The fifth coupler control line 2405 follows the same path as the path of an inter-qubit coupler control line (analog line 701 shown in FIG. 7), but provides an analog signal to the interlayer couplers 2009b and 2009d instead of an inter-qubit coupler.

[0196] FIG. 24F is a schematic diagram 2400f including a sixth coupler control line 2406 of an interlayer coupler that couples qubits in a first plurality of qubits 2003 and qubits in a fourth plurality of qubits 2006 between a first and a second surface code layer of a quantum processor implementing the robust architecture described above with reference to FIGS. 20, 21A, 21B, 21C, and 23.

[0197] FIG. 2400f shows a first surface code layer 2001 of qubits of a quantum processor 2000 from FIG. 20, which includes first, second, third, and fourth pluralities of qubits 2003, 2004, 2005, and 2006, respectively (only one qubit within each of the pluralities of qubits is mobilized in FIG. 24F to reduce visual clutter), and first and second pluralities of couplers 2007 and 2008, respectively (only one coupler within each of the pluralities of couplers is mobilized in FIG. 24F to reduce visual clutter). The sixth coupler control line 2406 provides an analog signal to an interlayer coupler 2009a (only one is mobilized to reduce visual clutter) and an interlayer coupler 2009d (only one is mobilized to reduce visual clutter). Those skilled in the art will understand that the quantum processor 2000 includes as many interlayer couplers 2009a as the number of qubits in the first plurality of qubits 2003 and as many interlayer couplers 2009d as the number of qubits in the fourth plurality of qubits 2006. As described above with reference to FIG. 20, the interlayer coupler 2009a provides a communication coupling between qubits in the first plurality of qubits 2003 in the first surface code layer 2001 and qubits in the first plurality of qubits 2003 in the second surface code layer 2002. The interlayer coupler 2009d provides a communication coupling between qubits in the fourth plurality of qubits 2006 in the first surface code layer 2001 and qubits in the fourth plurality of qubits 2006 in the second surface code layer 2002. The sixth coupler control line 2406 follows the same path as the path of an inter-qubit coupler control line (the analog line 702 shown in FIG. 7), but provides the analog signal to the interlayer couplers 2009a and 2009d instead of an inter-qubit coupler.

[0198] FIG. 24G is a schematic diagram 2400g including a seventh coupler control line 2407 of an interlayer coupler that couples qubits in a first plurality of qubits 2003 and qubits in a fourth plurality of qubits 2006 between a first and a second surface code layer of a quantum processor implementing the robust architecture described above with reference to FIGS. 20, 21A, 21B, 21C, and 23.

[0199] Figure 2400g shows the first surface code layer 2001 of the qubits of the quantum processor 2000 from FIG. 20, which includes a plurality of first, second, third, and fourth qubits 2003, 2004, 2005, and 2006 respectively (in FIG. 24G, only one qubit within each of the plurality of qubits is mobilized to reduce visual clutter), and each of the first and second plurality of couplers 2007 and 2008 (in FIG. 24G, only one coupler within each of the plurality of couplers is mobilized to reduce visual clutter). The seventh coupler control line 2407 provides an analog signal to the interlayer coupler 2009a (only one is mobilized to reduce visual clutter) and the interlayer coupler 2009d (only one is mobilized to reduce visual clutter). Those skilled in the art will understand that the quantum processor 2000 includes the same number of interlayer couplers 2009a as the number of qubits in the first plurality of qubits 2003 and the same number of interlayer couplers 2009d as the number of qubits in the fourth plurality of qubits 2006. As described above with reference to FIG. 20, the interlayer coupler 2009a provides a communication coupling between the qubits in the first plurality of qubits 2003 in the first surface code layer 2001 and the qubits in the first plurality of qubits 2003 in the second surface code layer 2002. The interlayer coupler 2009d provides a communication coupling between the qubits in the fourth plurality of qubits 2006 in the first surface code layer 2001 and the qubits in the fourth plurality of qubits 2006 in the second surface code layer 2002. The seventh coupler control line 2407 follows the same path as the qubit-to-qubit coupler control line (analog line 703 shown in FIG. 7), but provides the analog signal to the interlayer couplers 2009a and 2009d instead of the qubit-to-qubit coupler.

[0200] FIG. 24H is a schematic diagram 2400h including an eighth coupler control line 2408 of an interlayer coupler that couples the qubits in the second plurality of qubits 2004 and the qubits in the fourth plurality of qubits 2006 between the first and second surface code layers of a quantum processor implementing the robust architecture described above with reference to FIGS. 20, 21A, 21B, 21C, and 23.

[0201] Figure 2400h shows the first surface code layer 2001 of the qubits of the quantum processor 2000 from FIG. 20, which includes a plurality of first, second, third, and fourth qubits 2003, 2004, 2005, and 2006 respectively (in FIG. 24H, only one qubit within each of the plurality of qubits is mobilized to reduce visual clutter), and each of the first and second plurality of couplers 2007 and 2008 (in FIG. 24H, only one coupler within each of the plurality of couplers is mobilized to reduce visual clutter). The eighth coupler control line 2408 provides an analog signal to the interlayer coupler 2009b (only one is mobilized to reduce visual clutter) and the interlayer coupler 2009d (only one is mobilized to reduce visual clutter). Those skilled in the art will understand that the quantum processor 2000 includes as many interlayer couplers 2009b as the number of qubits in the second plurality of qubits 2004 and as many interlayer couplers 2009d as the number of qubits in the fourth plurality of qubits 2006. As described above with reference to FIG. 20, the interlayer coupler 2009b provides a communication coupling between the qubits in the second plurality of qubits 2004 in the first surface code layer 2001 and the qubits in the second plurality of qubits 2004 in the second surface code layer 2002. The interlayer coupler 2009d provides a communication coupling between the qubits in the fourth plurality of qubits 2006 in the first surface code layer 2001 and the qubits in the fourth plurality of qubits 2006 in the second surface code layer 2002. The eighth coupler control line 2408 follows the same path as the path of the qubit - to - qubit coupler control line (the analog line 704 shown in FIG. 7), but provides the analog signal to the interlayer couplers 2009b and 2009d instead of the qubit - to - qubit coupler.

[0202] Figures 25A and 25B are flowcharts showing an example surface code implementation method 2500 in the quantum processor 2000 of FIG. 20. The quantum processor 2000 can have one or more defective qubits as described above with respect to FIG. 21A. FIG. 25A is a flowchart showing the first part 2500a of the method 2500, and FIG. 25B is a flowchart showing the second part 2500b of the method 2500. The control of the method 2500 can move from the first part 2500a to the second part 2500b and can also move in the reverse direction.

[0203] The method 2500 can be executed by a classical computer that communicates with a quantum processor, such as the quantum processor 126 of FIG. 1 and / or the quantum processor 2000 of FIG. 20, such as the digital computer 102 of FIG. 1. The method 2500 includes acts 2501, 2502, 2503, 2504, 2505a, 2505b, 506, 2507, 2508a, 2508b, 2509, 2510, 2511a, 2511b, 2512, 2513, 2514a, 2514b, 2515, 2516, 2517a, 2517b, 2518, 2519, 2520a, 2502b, 2521, but the number of acts is an example, and those skilled in the art will understand that in some embodiments, certain acts may be omitted, additional acts may be added, and / or the order of the acts may be changed. For the method 2500, it is described as having one defective qubit 2101a within the first plurality of qubits 2003a, but those skilled in the art will understand that modifications to the method 2500 are applicable if there are defects in one or more qubits within the second plurality of qubits 2004a, the third plurality of qubits 2005a, and / or the fourth plurality of qubits 2006a. Such modifications are described with reference to the method 2600 of FIGS. 26A and 26B.

[0204] The first part 2500a of the method 2500 starts at 2501, for example, in response to a call from another routine.

[0205] In 2502, the digital computer 102 deactivates four couplers that directly couple a defective qubit (e.g., qubit 2101a) in the first surface code layer 2001 to its neighboring qubits (e.g., qubits 2102a, 2103a, 2104a, and 2105a) within the first surface code layer 2001. The four couplers may belong to the first plurality of couplers 2007a and / or the second plurality of couplers 2008a. The couplers can be deactivated by decoupling from the control lines (analog lines 701 - 707).

[0206] In 2503, the digital computer 102 activates the interlayer couplers (e.g., interlayer couplers 2009_a, 2009_b, 2009_c, and 2009_d) between the neighbors of the defective qubit within the first surface code layer 2001 (e.g., qubits 2102a, 2103a, 2104a, and 2105a) and the homogeneous qubits within the second surface code layer 2002 (e.g., qubits 2102b, 2103b, 2104b, and 2105b). The interlayer couplers 2009 are activated via the coupler control lines 2401 - 2408 and the aQFP switch 2312 as described above with reference to FIGS. 23 and 24A - 24H.

[0207] In 2504, the digital computer 102 activates four couplers that directly connect qubits 2102b, 2103b, 2104b, and 2105b to qubit 2101b in the second surface code layer 2002, where qubit 2101b is the homogeneous qubit in the second surface code layer 2002 corresponding to the defective qubit 2101a in the first surface code layer 2001. The four couplers that directly connect the qubits in the second surface code layer 2002 may belong to the first plurality of couplers 2007a and / or the second plurality of couplers 2008b. Those skilled in the art will understand that the order of acts 2502, 2503, and 2504 is interchangeable, and in some embodiments, acts 2502, 2503, and 2504 can be performed in parallel or together, or even simultaneously.

[0208] Acts 2505a and 2505b are executed by digital computer 102 in parallel, together, or even simultaneously.

[0209] In 2505a, digital computer 102 initializes qubits (Mx) within a third plurality of qubits 2005a to a ground state. Further explanation can be found in act 902a of FIG. 9.

[0210] In 2505b, digital computer 102 initializes qubits (Mz) within a fourth plurality of qubits 2006a to a ground state. Further explanation can be found in act 902b of FIG. 9.

[0211] In 2506, digital computer 102 causes an Hadamard gate (H gate) to be applied to qubit Mx. Further explanation can be found in act 903 of FIG. 9.

[0212] In 2507, digital computer 102 causes a first SWAP gate to be applied between a neighboring qubit 2104a coupled to a defective qubit 2101a in a first surface code layer 2001 and a homogeneous qubit 2104b (Mx) in a second surface code layer 2002.

[0213] Acts 2508a and 2508b are executed by digital computer 102 in parallel, together, or even simultaneously.

[0214] In 2508a, digital computer 102 causes a first CNOT gate to be applied to a data qubit (DB) within a second plurality of qubits 2004a as a control qubit and to a qubit Mz within a fourth plurality of qubits 2006a as a target qubit. Further explanation can be found in act 904a of FIG. 9.

[0215] In 2508b, the digital computer 102 causes a second CNOT gate to be applied to a data qubit (DA) within a first plurality of qubits 2003a as a target qubit and to a qubit Mx within a third plurality of qubits 2005a as a control qubit. Further explanation can be found in act 904b of FIG. 9. Considering that the defective qubit 2101a is within the first plurality of qubits 2003a in the first surface code layer 2001, the second CNOT gate uses the qubit 2101b in the second surface code layer 2002 as the target qubit and the qubit 2104b as the control qubit instead of the qubits 2101a and 2104a.

[0216] In 2509, the digital computer 102 causes a second SWAP gate to be applied between the neighboring qubit 2104b (Mx) coupled to the qubit 2101b in the second surface code layer 2002 and the homogeneous qubit 2104a (Mx) in the first surface code layer 2001.

[0217] In 2510, the digital computer 102 causes a third SWAP gate to be applied between the neighboring qubit 2103a (Mz) coupled to the defective qubit 2101a in the first surface code layer 2001 and the homogeneous qubit 2103b (Mz) in the second surface code layer 2002.

[0218] Acts 2511a and 2511b are executed by the digital computer 102 in parallel or together, or even simultaneously.

[0219] In 2511a, the digital computer 102 applies a third CNOT gate to a data qubit (DA) within a first plurality of qubits 2003a as a control qubit and to qubit Mz as a target qubit. Further explanation can be found in act 905a of FIG. 9. Considering that the defective qubit 2101a is within the first plurality of qubits 2003a in the first surface code layer 2001, the third CNOT gate uses qubit 2101b in the second layer 2002 as a control instead of qubits 2101a and 2103a, and uses qubit 2103b in the second surface code layer 2002 as a target.

[0220] In 2511b, the digital computer 102 applies a fourth CNOT gate to a data qubit DB within a second plurality of qubits 2004a as a target qubit and to qubit Mx as a control qubit. Further explanation can be found in act 905b of FIG. 9.

[0221] In 2512, the digital computer 102 applies a fourth SWAP gate between the neighboring qubit 2103b (Mz) coupled to qubit 2101b in the second surface code layer 2002 and the homogeneous qubit 2103a (Mz) in the first surface code layer 2001. Control of method 2500 then proceeds to the second part 2500b of method 2500 shown in FIG. 25B.

[0222] In 2513, the digital computer 102 applies a fifth SWAP gate between the neighboring qubit 2105a (Mz) coupled to the defective qubit 2101a in the first surface code layer 2001 and the homogeneous qubit 2105b (Mz) in the second surface code layer 2002.

[0223] Acts 2514a and 2514b are executed by the digital computer 102 in parallel or together, or even simultaneously.

[0224] In 2514a, digital computer 102 causes a fifth CNOT gate to be applied to data qubit DA within a first plurality of qubits 2003a as a control qubit and to qubit Mz as a target qubit. Further explanation can be found in act 906a of FIG. 9. Considering that defective qubit 2101a is within the first plurality of qubits 2003a in the first surface code layer 2001, the fifth CNOT gate uses qubit 2101b in the second surface code layer 2002 as a control qubit and qubit 2105b in the second surface code layer 2002 as a target qubit instead of qubits 2101a and 2105a.

[0225] In 2514b, digital computer 102 causes a sixth CNOT gate to be applied to data qubit DB within a second plurality of qubits 2004a as a target qubit and to qubit Mx as a control qubit. Further explanation can be found in act 906b of FIG. 9.

[0226] In 2515, digital computer 102 causes a sixth SWAP gate to be applied between neighboring qubit 2105b (Mz) coupled to qubit 2101b in the second surface code layer 2002 and homogeneous qubit 2105a (Mz) in the first surface code layer 2001.

[0227] In 2516, digital computer 102 causes a seventh SWAP gate to be applied between neighboring qubit 2102a (Mx) coupled to defective qubit 2101a in the first surface code layer 2001 and homogeneous qubit 2102b (Mx) in the second surface code layer 2002.

[0228] Acts 2517a and 2517b are executed by digital computer 102 in parallel or together, or even simultaneously.

[0229] In 2517a, the digital computer 102 causes a seventh CNOT gate to be applied to a data qubit DB in a second plurality of qubits 2004a as a control qubit and to qubit Mz as a target qubit. Further explanation can be found in act 907a of FIG. 9.

[0230] In 2517b, the digital computer 102 causes an eighth CNOT gate to be applied to a data qubit DA in a first plurality of qubits 2003a as a target qubit and to qubit Mx as a control qubit. Further explanation can be found in act 907b of FIG. 9. Considering that the defective qubit 2101a is within a first plurality of qubits 2003a in the first surface code layer 2001, the eighth CNOT gate uses qubit 2101b in the second surface code layer 2002 as the target qubit instead of qubits 2101a and 2102a, and uses qubit 2102b in the second surface code layer 2002 as the control qubit.

[0231] In 2518, the digital computer 102 causes an eighth SWAP gate to be applied between a neighboring qubit 2102a (Mx) coupled to qubit 2101b in the second surface code layer 2002 and a homogeneous qubit 2102a (Mx) in the first surface code layer 2001.

[0232] In 2519, the digital computer 102 applies an H gate to qubit Mx. Further explanation can be found in act 908 of FIG. 9.

[0233] Acts 2520a and 2520b are executed by the digital computer 102 in parallel, or together, or even simultaneously.

[0234] In 2520a, digital computer 102 causes the state of qubit Mx to be read out. Further explanation can be found in act 909a of FIG. 9. In at least one embodiment, frequency multiplexed resonance readout (FMRR) is employed as described in U.S. Patent No. 10,938,346. Further readout techniques that can be employed are described in U.S. Patent Application No. 63 / 448,537.

[0235] In 2520b, digital computer 102 causes the state of qubit Mz to be read out. Further explanation can be found in act 909b of FIG. 9. In at least one embodiment, frequency multiplexed resonance readout (FMRR) is employed as described in U.S. Patent No. 10,938,346. Further readout techniques that can be employed are described in U.S. Patent Application No. 63 / 448,537.

[0236] In 2521, method 2500 ends, for example, until it is called again.

[0237] Method 2500 has been described with one defective qubit 2101a within the first plurality of qubits 2003a, but one of ordinary skill in the art will understand that modifications to method 2500 are applicable if there are defects in one or more qubits within the second plurality of qubits 2004a, the third plurality of qubits 2005a, and / or the fourth plurality of qubits 2006a.

[0238] Figures 26A and 26B are flowcharts showing an example surface code implementation method 2600 in the quantum processor 2000 of FIG. 20, each having the quantum control lines and coupler control lines of FIGS. 3 and 4. The quantum processor 2000 can have one or more defective Mx qubits, as shown in FIG. 21B. FIG. 26A is a flowchart showing the first part 2600a of the method 2600, and FIG. 26B is a flowchart showing the second part 2600b of the method 2600. The control of the method 2600 can move from the first part 2600a to the second part 2600b and vice versa. The method 2600 can be executed by a classical computer, such as the digital computer 102 of FIG. 1, that communicates with a quantum processor, such as the quantum processor 126 of FIG. 1 and / or the quantum processor 2000 of FIG. 20. The method 2600 includes acts 2601, 2602, 2603, 2604, 2605a, 2605b, 2606, 2607, 2608a, 2608b, 2609, 2610, 2611a, 2611b, 2612, 2613, 2614a, 2614b, 2615, 266, 2617a, 2671b, 2618, 2619, 2620a, 2620b, and 2621, but the number of acts is an example, and those skilled in the art will understand that in some embodiments, certain acts may be omitted, additional acts may be added, and / or the order of the acts may be changed. The method 2600 is described as having one defective qubit 2104a (Mx) within a third plurality of qubits 2005a.

[0239] The first part 2600a of the method 2600 begins at 2601, for example, in response to a call from another routine.

[0240] In 2602, the digital computer 102 deactivates four couplers that directly couple a defective qubit (e.g., qubit 2104a) in the first surface code layer 2001 to its neighboring qubits (e.g., qubits 2101a, 2106a, 2107a, and 2106a). The four couplers may belong to the first plurality of couplers 2007a and / or the second plurality of couplers 2008a. The couplers may be deactivated by decoupling from the control lines (analog lines 701 - 707 in FIG. 7).

[0241] In 2603, the digital computer 102 activates the interlayer couplers (e.g., interlayer couplers 2009_e, 2009_f, 2009_g, and 2009_h) between the neighboring qubits (e.g., qubits 2101a, 2106a, 2107a, and 2108a) in the first surface code layer 2001 and the homogeneous qubits (e.g., qubits 2101b, 2106b, 2107b, and 2108b) in the second surface code layer 2002. The interlayer couplers 2009 are activated via the coupler control lines 2401 - 2408 and the aQFP switch 2312 as described above with reference to FIGS. 23 and 24A - 24H.

[0242] In 2604, the digital computer 102 activates four couplers that directly connect qubits 2101b, 2106b, 2107b, and 2108b to qubit 2104b in the second surface code layer 2002, where qubit 2104b is the homogeneous qubit in the second surface code layer 2002 corresponding to the defective qubit 2104b in the first surface code layer 2001. The four couplers may belong to the first plurality of couplers 2007b and / or the second plurality of couplers 2008b. Those skilled in the art will understand that the order of acts 2602, 2603, and 2604 may be mutually interchangeable, and in some embodiments, acts 2602, 2603, and 2604 may be performed in parallel or together, or even simultaneously.

[0243] Acts 2605a and 2605b are executed by digital computer 102 either in parallel or together, or even simultaneously.

[0244] In 2605a, digital computer 102 initializes the qubits (Mx) in the third plurality of qubits 2005a to the ground state. Further explanation can be found in act 902a of FIG. 9. Considering that one qubit in the third layer of qubits 2005a in the first surface code layer 2001 is within the defective qubit 2104a, the homogeneous qubits 2104b in the second surface code layer 2002 are initialized to the ground state.

[0245] In 2605b, digital computer 102 initializes the qubits (Mz) in the fourth plurality of qubits 2006a to the ground state. Further explanation can be found in act 902b of FIG. 9.

[0246] In 2606, digital computer 102 applies a Hadamard gate (H gate) to qubit Mx. Further explanation can be found in act 903 of FIG. 9. Considering that one qubit in the third layer of qubits 2005a in the first surface code layer 2001 is within the defective qubit 2104a, digital computer 102 applies a Hadamard gate (H gate) to the homogeneous qubit 2104b in the second surface code layer 2002.

[0247] In 2607, digital computer 102 applies a first SWAP gate between the neighboring qubit 2101a (DA) coupled to the defective qubit 2104a in the first surface code layer 2001 and the homogeneous qubit 2101b (DA) in the second surface code layer 2002.

[0248] Acts 2608a and 2608b are executed by digital computer 102 either in parallel or together, or even simultaneously.

[0249] In 2608a, the digital computer 102 applies a first CNOT gate to a data qubit (DB) within a second plurality of qubits 2004a as a control qubit and to a qubit Mz within a fourth plurality of qubits 2006a as a target qubit. Further explanation can be found in act 904a of FIG. 9.

[0250] In 2608b, the digital computer 102 applies a second CNOT gate to a data qubit (DA) within a first plurality of qubits 2003a as a target qubit and to a qubit Mx within a third plurality of qubits 2005a as a control qubit. Further explanation can be found in act 904b of FIG. 9. Considering that the defective qubit 2104a is within the third plurality of qubits 2005a in the first surface code layer 2001, the first CNOT gate uses the qubit 2104b in the second surface code layer 2002 as a control instead of qubits 2104a and 2101a, and uses the qubit 2101b in the second surface code layer 2002 as a target.

[0251] In 2609, the digital computer 102 applies a second SWAP gate between a neighboring qubit 2101b (DA) coupled to the qubit 2104b in the second surface code layer 2002 and a homogeneous qubit 2101a (DA) in the first surface code layer 2001.

[0252] In 2610, the digital computer 102 applies a third SWAP gate between a neighboring qubit 2106a (DB) coupled to the defective qubit 2104a in the first surface code layer 2001 and a homogeneous qubit 2106b (DB) in the second surface code layer 2002.

[0253] Acts 2611a and 2611b are executed by the digital computer 102 in parallel, together, or even simultaneously.

[0254] In 2611a, the digital computer 102 applies a third CNOT gate to the data qubit DA in the first plurality of qubits 2003a as the control qubit and to the qubit Mz as the target qubit. Further explanation can be found in act 905a of FIG. 9.

[0255] In 2611b, the digital computer 102 applies a fourth CNOT gate to the data qubit DB in the second plurality of qubits 2004a as the target qubit and to the qubit Mx as the control qubit. Further explanation can be found in act 905b of FIG. 9. Considering that the defective qubit 2104a is within the third plurality of qubits 2005a in the first surface code layer 2001, the fourth CNOT gate uses the qubit 2104b in the second surface code layer 2002 as the control qubit and the qubit 2106b in the second surface code layer 2002 as the target qubit instead of the qubits 2104a and 2106a.

[0256] The control of method 2600 then proceeds to the second part 2600b of method 2600 shown in FIG. 26B.

[0257] In 2612, the digital computer 102 applies a fourth SWAP gate between the neighboring qubit 2106b (DB) coupled to the qubit 2104b in the second surface code layer 2002 and the homogeneous qubit 2106a (DB) in the first surface code layer 2001.

[0258] In 2613, the digital computer 102 applies a fifth SWAP gate between the neighboring qubit 2107a (DB) coupled to the defective qubit 2104a in the first surface code layer 2001 and the homogeneous qubit 2107b (DB) in the second surface code layer 2002.

[0259] Acts 2614a and 2614b are executed by the digital computer 102 in parallel or together, or even simultaneously.

[0260] In 2614a, the digital computer 102 applies a fifth CNOT gate to the data qubit DA in the first plurality of qubits 2003a as the control qubit and to the qubit Mz as the target qubit. Further explanation can be found in act 906a of FIG. 9.

[0261] In 2614b, the digital computer 102 applies a sixth CNOT gate to the data qubit DB in the second plurality of qubits 2004a as the target qubit and to the qubit Mx as the control qubit. Further explanation can be found in act 906b of FIG. 9. Considering that the defective qubit 2104a is within the third plurality of qubits 2005a in the first surface code layer 2001, the sixth CNOT gate uses the qubit 2104b in the second surface code layer 2002 as the control qubit instead of qubits 2104a and 2107a, and uses the qubit 2107b in the second surface code layer 2002 as the target qubit.

[0262] In 2615, the digital computer 102 applies a sixth SWAP gate between the neighboring qubit 2107b (DB) coupled to the qubit 2104b in the second surface code layer 2002 and the homogeneous qubit 2107a (DB) in the first surface code layer 2001.

[0263] In 2616, the digital computer 102 applies a seventh SWAP gate between the neighboring qubit 2108a (DA) coupled to the defective qubit 2104a in the first surface code layer 2001 and the homogeneous qubit 2108b (DA) in the second surface code layer 2002.

[0264] Acts 2617a and 2617b are executed by the digital computer 102 in parallel or together, or even simultaneously.

[0265] In 2617a, the digital computer 102 causes a seventh CNOT gate to be applied to the data qubit DB in the second plurality of qubits 2004a as a control qubit and to the qubit Mz as a target qubit. Further explanation can be found in act 907a of FIG. 9.

[0266] In 2617b, the digital computer 102 causes an eighth CNOT gate to be applied to the data qubit DA in the first plurality of qubits 2003a as a target qubit and to the qubit Mx as a control qubit. Further explanation can be found in act 907b of FIG. 9. Considering that the defective qubit 2104a is within the third plurality of qubits 2005a in the first surface code layer 2001, the eighth CNOT gate uses the qubit 2104b in the second surface code layer 2002 as a control instead of the qubits 2104a and 2108a, and uses the qubit 2108b in the second surface code layer 2002 as a target.

[0267] In 2618, the digital computer 102 causes an eighth SWAP gate to be applied between the neighboring qubit 2108(DA) coupled to the qubit 2104b in the second surface code layer 2002 and the homogeneous qubit 2108a(DA) in the first surface code layer 2001.

[0268] In 2619, the digital computer 102 applies an H gate to the qubit Mx. Further explanation can be found in act 908 of FIG. 9.

[0269] Acts 2620a and 2620b are executed by the digital computer 102 in parallel or together, or even simultaneously.

[0270] In 2620a, digital computer 102 causes the state of qubit Mx to be read out. Further explanation can be found in act 909a of FIG. 9. In at least one embodiment, frequency multiplexed resonance readout (FMRR) is employed as described in U.S. Patent No. 10,938,346. Further readout techniques that may be employed are described in U.S. Patent Application No. 63 / 448,537.

[0271] In 2620b, digital computer 102 causes the state of qubit Mz to be read out. Further explanation can be found in act 909b of FIG. 9. In at least one embodiment, frequency multiplexed resonance readout (FMRR) is employed as described in U.S. Patent No. 10,938,346. Further readout techniques that may be employed are described in U.S. Patent Application No. 63 / 448,537.

[0272] In 2621, method 2600 ends, for example, until it is called again.

[0273] Figures 27A and 27B are flowcharts showing an example of a surface code method 2700 in the quantum processor of FIG. 20, where there is one defective X-coupler in one layer. The quantum processor 2000 may have one or more defective couplers, as shown in FIG. 21C. FIG. 27A is a flowchart showing the first part 2700a of the method 2700, and FIG. 27B is a flowchart showing the second part 2700b of the method 2700. The control of the method 2700 can move from the first part 2700a to the second part 2700b and vice versa. The method 2700 may be executed by a classical computer that communicates with a quantum processor, such as the quantum processor 126 of FIG. 1 and / or the quantum processor 2000 of FIG. 20, for example, the digital computer 102 of FIG. 1. The method 2700 includes acts 2701, 2702, 2703, 2704a, 2704b, 2705, 2706, 2707a, 2707b, 2708, 2709a, 2709b, 2710a, 2710b, 2711a, 2711b, 2712, 2713a, 2713b, and 2714, but the number of acts is an example, and those skilled in the art will understand that in some embodiments, certain acts may be omitted, additional acts may be added, and / or the order of the acts may be changed. The method 2700 is described as having one defective coupler 2109a (X-coupler) within the first plurality of couplers 2007a.

[0274] The first part 2700a of the method 2700 begins at 2701, for example, in response to a call from another routine.

[0275] At 2702, digital computer 102 activates the interlayer couplers (e.g., interlayer couplers 2009_e and 2009_c) between the qubits (e.g., qubits 2101a and 2104a) coupled by a defect coupler (e.g., coupler 2109a) in the first surface code layer 2001 and the homogeneous qubits (e.g., qubits 2101b and 2104b) in the second surface code layer 2002. The interlayer coupler 2009 is activated via coupler control lines 2401 - 2408 and aQFP switch 2312 as described above with reference to FIGS. 23 and 24A - 24H.

[0276] At 2703, digital computer 102 activates coupler 2109b that directly couples qubits 2101b and 2104b in the second surface code layer 2002, and coupler 2109b is the homogeneous coupler in the second surface code layer 2002 of the defect coupler 2109a in the first surface code layer 2001. Those skilled in the art will understand that the order of acts 2702 and 2703 is interchangeable, and in some embodiments, acts 2702 and 2703 can be performed in parallel or together, or even simultaneously.

[0277] Acts 2704a and 2704b are performed in parallel or together, or even simultaneously, by digital computer 102.

[0278] At 2704a, digital computer 102 initializes the qubit (Mx) within the third plurality of qubits 2005a to the ground state. Further explanation can be found in act 902a of FIG. 9.

[0279] At 2704b, digital computer 102 initializes the qubit (Mz) within the fourth plurality of qubits 2006a to the ground state. Further explanation can be found in act 902b of FIG. 9.

[0280] At 2705, digital computer 102 causes an Hadamard gate (H gate) to be applied to qubit Mx. Further explanation can be found in act 903 of FIG. 9.

[0281] At 2706, digital computer 102 causes a first SWAP gate to be applied between neighboring qubits 2101a (DA) and 2104a (Mx) coupled to defect coupler 2109a in the first surface code layer 2001 and homogeneous qubits 2101b (DA) and 2104b (Mx) in the second surface code layer 2002.

[0282] Acts 2707a and 2707b are performed by digital computer 102 in parallel or together, or even simultaneously.

[0283] At 2707a, digital computer 102 causes a first CNOT gate to be applied to a data qubit (DB) in a second plurality of qubits 2004a as a control qubit and to a qubit Mz in a fourth plurality of qubits 2006a as a target qubit. Further explanation can be found in act 904a of FIG. 9.

[0284] At 2707b, digital computer 102 causes a second CNOT gate to be applied to a data qubit (DA) in a first plurality of qubits 2003a as a target qubit and to a qubit Mx in a third plurality of qubits 2005a as a control qubit. Further explanation can be found in act 904b of FIG. 9. Considering that defect coupler 2109a is within the first plurality of couplers 2007a in the first surface code layer 2001, the second CNOT gate uses qubits 2101b in the second surface code layer 2002 as target qubits and qubits 2104b in the second surface code layer 2002 as control qubits instead of qubits 2101a and 2104a.

[0285] At 2708, digital computer 102 applies a second SWAP gate between qubit 2101b(DA) and 2104b(Mx) in the second surface code layer 2002 and homogeneous qubits 2101a(DA) and 2104a(Mx) in the first surface code layer 2002. Control of method 2700 then proceeds to the second part 2700b of method 2700 shown in FIG. 27B.

[0286] Acts 2709a and 2709b are performed by digital computer 102 in parallel or together, or even simultaneously.

[0287] At 2709a, digital computer 102 applies a third CNOT gate to data qubit DA in a first plurality of qubits 2003a as a control qubit and to qubit Mz as a target qubit. Further explanation can be found in act 905a of FIG. 9.

[0288] At 2709b, digital computer 102 applies a fourth CNOT gate to data qubit DB in a second plurality of qubits 2004a as a target qubit and to qubit Mx as a control qubit. Further explanation can be found in act 905b of FIG. 9.

[0289] Acts 2710a and 2710b are performed by digital computer 102 in parallel or together, or even simultaneously.

[0290] At 2710a, digital computer 102 applies a fifth CNOT gate to data qubit DA in a first plurality of qubits 2003a as a control qubit and to qubit Mz as a target qubit. Further explanation can be found in act 906a of FIG. 9.

[0291] In 2710b, digital computer 102 causes a sixth CNOT gate to be applied to data qubit DB in a second plurality of qubits 2004a as a target qubit and to qubit Mx as a control qubit. Further explanation can be found in act 906b of FIG. 9.

[0292] Acts 2711a and 2711b are performed by digital computer 102 in parallel, or together, or even simultaneously.

[0293] In 2711a, digital computer 102 causes a seventh CNOT gate to be applied to data qubit DB in a second plurality of qubits 2004a as a control qubit and to qubit Mz as a target qubit. Further explanation can be found in act 907a of FIG. 9.

[0294] In 2711b, digital computer 102 causes an eighth CNOT gate to be applied to data qubit DA in a first plurality of qubits 2003a as a target qubit and to qubit Mx as a control qubit. Further explanation can be found in act 907b of FIG. 9.

[0295] In 2712, digital computer 102 causes an H gate to be applied to qubit Mx. Further explanation can be found in act 908 of FIG. 9.

[0296] Acts 2713a and 2713b are performed by digital computer 102 in parallel, or together, or even simultaneously.

[0297] In 2713a, digital computer 102 causes the state of qubit Mx to be read out. Further explanation can be found in act 909a of FIG. 9. In at least one embodiment, frequency multiplexed resonance readout (FMRR) is employed as described in U.S. Patent No. 10,938,346. Further readout techniques that may be employed are described in U.S. Patent Application No. 63 / 448,537.

[0298] In 2713b, the digital computer 102 causes the state of the quantum bit Mz to be read out. Further explanation can be found in act 909b of FIG. 9. In at least one embodiment, frequency multiplexed resonance readout (FMRR) is employed as described in U.S. Patent No. 10,938,346. Further readout techniques that may be employed are described in U.S. Patent Application No. 63 / 448,537.

[0299] In 2714, the method 2700 ends until it is called again.

[0300] The methods, processes, or techniques described above can be implemented by a series of processor-readable instructions stored on one or more non-transitory processor-readable media. Some examples of the methods of the methods, processes, or techniques described above are partially executed by a dedicated device such as a quantum processor. Those skilled in the art will understand that the methods, processes, or techniques described above may include various acts, but in alternative examples, certain acts may be omitted and / or additional acts may be added. The order of illustration of the acts is shown for illustrative purposes only and will be recognized by those skilled in the art as being changeable in alternative examples. Some of the illustrative acts or operations of the methods, processes, or techniques described above are repeatedly executed. Some of the acts of the methods, processes, or techniques described above can be executed during each iteration, after a plurality of iterations, or at the end of all iterations.

[0301] The above description of the illustrated embodiments, including what is described in the abstract, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Specific embodiments and examples are described herein for illustrative purposes, but as will be recognized by those skilled in the art, various equivalent changes can be made without departing from the spirit and scope of the present disclosure. The teachings provided herein for the various embodiments may be applicable not necessarily to the exemplary methods of quantum computing outlined above, but to other methods of quantum computing.

[0302] The various embodiments described above can be combined to provide further embodiments. Without limitation, U.S. Patent Application No. 63 / 223,686; U.S. Patent No. 10,938,346; U.S. Patent No. 11,182,230, U.S. Provisional Patent Application No. 63 / 355,663; International Patent Application No. PCT / US2022 / 037457; U.S. Provisional Patent Application No. 63 / 448,414; International Patent Application No. PCT / US2021 / 024134; U.S. Patent No. 7,533,068, U.S. Patent No. 7,843,209, U.S. Patent Application No. 63 / 448,537, U.S. Patent No. 8,174,305, and U.S. Patent No. 8,169,231, all U.S. patent application publications, U.S. patents, foreign patents, and foreign patent applications assigned to the same assignee as the present application and cited herein and / or listed on the application data sheet are hereby incorporated by reference in their entirety.

[0303] These changes and other changes can be made to the embodiments in view of the above detailed description. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed herein and in the claims, but rather the claims should be construed to include all possible embodiments together with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A scalable control system, The first set of multiple qubits, A second set of multiple qubits, A third set of qubits, A fourth plurality of qubits, wherein the first, second, third, and fourth plurality of qubits are arranged in a two-dimensional array, and at least one qubit in the first plurality of qubits and at least one qubit in the second plurality of qubits are each directly and communicably coupled to each of the two qubits in the third plurality of qubits and each of the two qubits in the fourth plurality of qubits, A first set of analog lines, which are communicatively coupled to selectively provide an analog signal to each of the first plurality of qubits, A second set of analog lines, which are communicably coupled to selectively provide an analog signal to each of the qubits in the second plurality of qubits, A third set of analog lines, which are communicably coupled to selectively provide an analog signal to each of the qubits in the third plurality of qubits, A fourth set of analog lines, which are communicably coupled to selectively provide an analog signal to each of the qubits in the fourth plurality of qubits, A system equipped with this feature.

2. A first plurality of couplers, each of the first plurality of couplers directly and communicatively coupling each qubit in the first plurality of qubits to each qubit in the third plurality of qubits, or each qubit in the second plurality of qubits to each qubit in the third plurality of qubits, A second plurality of couplers, each of the second plurality of couplers directly and communicatively coupling each qubit in the first plurality of qubits to each qubit in the fourth plurality of qubits, or each qubit in the second plurality of qubits to each qubit in the fourth plurality of qubits, The system according to claim 1, further comprising the above.

3. The system according to claim 1, wherein each of the first, second, third, and fourth qubits is a fraxonium qubit.

4. The system according to claim 3, wherein each flaxonium qubit includes a mechanical inductor, and the mechanical inductor includes a segment of mechanical inductance material.

5. The system according to claim 1, wherein each of the first, second, third, and fourth qubits is a transmon qubit.

6. The system according to claim 1, wherein each qubit in the first and second plurality of qubits is a data qubit, and each qubit in the third and fourth plurality of qubits is a stabilization qubit, and each stabilization qubit is operable to perform a parity measurement with respect to the nearest qubit.

7. The system according to claim 1, wherein each set of analog lines in the first, second, third, and fourth sets of analog lines includes each of the first very high frequency (VHF) control lines.

8. The system according to claim 7, wherein the first VHF control line in the first set of analog lines is inductively coupled to the qubit body of each qubit in the first plurality of qubits to control the rotation of the Bloch sphere around its axis in the XY plane; the first VHF control line in the second set of analog lines is inductively coupled to the qubit body of each qubit in the second plurality of qubits to control the rotation of the Bloch sphere around its axis in the XY plane; the first VHF control line in the third set of analog lines is inductively coupled to the qubit body of each qubit in the third plurality of qubits to control the rotation of the Bloch sphere around its axis in the XY plane; and the first VHF control line in the fourth set of analog lines is inductively coupled to the qubit body of each qubit in the fourth plurality of qubits to control the rotation of the Bloch sphere around its axis in the XY plane.

9. Each of the first, second, third, and fourth sets of analog lines is: Each of the second VHF control lines, Each analog bias line has at least one, The system according to claim 7, further comprising:

10. The system according to claim 9, wherein each of the second VHF control lines in the first set of analog lines is inductively coupled to a composite Josephson junction (CJJ) of each qubit in the first plurality of qubits to control the rotation of the Bloch sphere around the Z axis; each of the second VHF control lines in the second set of analog lines is inductively coupled to a CJJ of each qubit in the second plurality of qubits to control the rotation of the Bloch sphere around the Z axis; each of the second VHF control lines in the third set of analog lines is inductively coupled to a CJJ of each qubit in the third plurality of qubits to control the rotation of the Bloch sphere around the Z axis; and each of the second VHF control lines in the fourth set of analog lines is inductively coupled to a CJJ of each qubit in the fourth plurality of qubits to control the rotation of the Bloch sphere around the Z axis.

11. The system according to claim 9, wherein each of the at least one analog bias lines in the first, second, third, and fourth sets of analog lines is inductively coupled to each composite Josephson junction (CCJJ) in each of the first, second, third, and fourth sets of qubits.

12. With respect to each qubit in the first, second, third, and fourth plurality of qubits, the system: Each of the first control structures is communicably coupled to each qubit body of each qubit in the first, second, third, and fourth plurality of qubits, and is operable to apply an analog signal from one of the first, second, third, and fourth sets of analog lines to each of the qubits in the first, second, third, and fourth plurality of qubits, Each of the first digital-to-analog converters (DACs) is communicably coupled to each qubit body of each qubit in the first, second, third, and fourth plurality of qubits and is operable to apply a static bias to each of the qubit bodies of each qubit in the first, second, third, and fourth plurality of qubits, Each of the second control structures is communicably coupled to each composite Josephson junction (CCJJ) of each qubit in the first, second, third, and fourth plurality of qubits, and is operable to apply an analog signal from one of the first, second, third, and fourth sets of analog lines to each of the CCJJs of each qubit in the first, second, third, and fourth plurality of qubits, Each of the second DACs is communicably coupled to each CCJJ of each qubit in the first, second, third, and fourth plurality of qubits and is operable to apply a static bias to each of the CCJJs of each qubit in the first, second, third, and fourth plurality of qubits, The system according to claim 1, further comprising the following:

13. A scalable control system, The first set of multiple qubits, A second set of multiple qubits, A third set of qubits, A fourth plurality of qubits, wherein at least one qubit in the first plurality of qubits and at least one qubit in the second plurality of qubits are each directly and communicably coupled to each of the two qubits in the third plurality of qubits and each of the two qubits in the fourth plurality of qubits, A first plurality of couplers, each coupler in the first plurality of couplers directly and communicatively connects each qubit in the first plurality of qubits to each qubit in the third plurality of qubits, or each qubit in the second plurality of qubits to each qubit in the third plurality of qubits, A second plurality of couplers, each coupler in the second plurality of couplers directly and communicatively connects each qubit in the first plurality of qubits to each qubit in the fourth plurality of qubits, or each qubit in the second plurality of qubits to each qubit in the fourth plurality of qubits, A first set of analog coupler wires, wherein each wire in the first set of analog coupler wires is coupled to selectively provide a first analog signal to each coupler in a first subset of the second set of couplers, A second set of analog coupler wires, wherein each wire in the second set of analog coupler wires is coupled to selectively provide a second analog signal to each coupler in a second subset of the second set of couplers, A third set of analog coupler wires, wherein each wire in the third set of analog coupler wires is coupled to selectively provide a third analog signal to each coupler in a third subset of the second set of couplers, A fourth set of analog coupler wires, wherein each wire in the fourth set of analog coupler wires is coupled to selectively provide a fourth analog signal to each coupler in a fourth subset of the second plurality of couplers, A fifth set of analog coupler wires, wherein each wire in the fifth set of analog coupler wires is coupled to selectively provide a fifth analog signal to each coupler in a first subset of the first plurality of couplers, A sixth set of analog coupler wires, each wire in the sixth set of analog coupler wires being coupled to selectively provide a sixth analog signal to each coupler in a second subset of the first plurality of couplers, A seventh set of analog coupler wires, wherein each wire in the seventh set of analog coupler wires is coupled to selectively provide a seventh analog signal to each coupler in a third subset of the first plurality of couplers, An eighth set of analog coupler wires, wherein each wire in the eighth set of analog coupler wires is coupled to selectively provide an eighth analog signal to each coupler in a fourth subset of the first plurality of couplers, A system equipped with this feature.

14. The system according to claim 13, wherein each of the first, second, third, and fourth qubits is a fraxonium qubit.

15. The system according to claim 14, wherein each flaxonium qubit includes a mechanical inductor, and the mechanical inductor includes a segment of mechanical inductance material.

16. The system according to claim 13, wherein each of the first, second, third, and fourth qubits is a transmon qubit.

17. The system according to claim 13, wherein each qubit in the first and second plurality of qubits is a data qubit, and each qubit in the third and fourth plurality of qubits is a stabilization qubit, and each stabilization qubit is operable to perform a parity measurement with respect to the nearest qubit.

18. The system according to claim 13, wherein each analog wire in the first, second, third, fourth, fifth, sixth, seventh, and eighth sets of analog coupler wires includes a first very high frequency (VHF) control wire.

19. The system according to claim 18, wherein each VHF line in the first, second, third, fourth, fifth, sixth, seventh, and eighth sets of analog coupler lines is operable to apply control pulses having low and high operating levels to each coupler in the first and second plurality of couplers.

20. The system according to claim 18, wherein each analog wire in the first, second, third, fourth, fifth, sixth, seventh, and eighth sets of analog coupler wires further comprises at least one additional analog wire.

21. With respect to each coupler in the first and second plurality of couplers, the system Each of the first digital-to-analog converters (DACs) is communicatively coupled to each coupler body of each coupler in the first and second plurality of couplers, and is operable to apply a static bias to each coupler body of each coupler in the first and second plurality of couplers, Each of the control structures is communicatively coupled to each composite Josephson junction (CCJJ) of each coupler in the first and second plurality of couplers, and is operable to apply an analog signal from one of the first, second, third, fourth, fifth, sixth, seventh, and eighth sets of analog lines to each of the CCJJs of each coupler in the first and second plurality of couplers, Each of the first and second plurality of couplers is communicatively coupled to each CCJJ of each coupler, and each of the second DACs is operable to apply a static bias to each CCJJ of each coupler in the first and second plurality of couplers, The system according to claim 13, further comprising the above.

22. A method for operating a quantum processor, the quantum processor comprising: a first plurality of qubits, a second plurality of qubits, a third plurality of qubits, and a fourth plurality of qubits, wherein at least one qubit in the first plurality of qubits and at least one qubit in the second plurality of qubits are communicably directly coupled to each of the two qubits in the third plurality of qubits and each of the two qubits in the fourth plurality of qubits; and a first plurality of couplers, each of the first plurality of couplers is coupled to each of the first plurality of qubits and the third plurality of qubits A first plurality of couplers providing a communicable direct coupling between each of the bits or between each of the second plurality of qubits and each of the third plurality of qubits, and a second plurality of couplers, each of the second plurality of couplers providing a communicable direct coupling between each of the first plurality of qubits and each of the fourth plurality of qubits or between each of the second plurality of qubits and each of the fourth plurality of qubits, wherein the method is performed by a digital processor communicably coupled to the quantum processor, and the method is Applying a pulse signal to the third and fourth plurality of qubits, thereby initializing the qubits within the third and fourth plurality of qubits to their respective ground states; Applying the Hadamard transform to the qubits within the third plurality of qubits, The process involves simultaneously applying a first CNOT gate using the qubits in the second plurality of qubits as a control and the qubits in the fourth plurality of qubits as a target, and applying a second CNOT gate using the qubits in the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control, The process involves simultaneously applying a third CNOT gate using a qubit in the first plurality of qubits as a control and a qubit in the fourth plurality of qubits as a target, and applying a fourth CNOT gate using a qubit in the second plurality of qubits as a target and a qubit in the third plurality of qubits as a control. The process involves simultaneously applying a fifth CNOT gate using a qubit in the first plurality of qubits as a control and a qubit in the fourth plurality of qubits as a target, and applying a sixth CNOT gate using a qubit in the second plurality of qubits as a target and a qubit in the third plurality of qubits as a control. The process involves simultaneously applying a seventh CNOT gate using the qubits in the second plurality of qubits as a control and the qubits in the fourth plurality of qubits as a target, and applying an eighth CNOT gate using the qubits in the first plurality of qubits as a target and the qubits in the third plurality of qubits as a control, Applying the Hadamard transform to the qubits within the third plurality of qubits, Reading out each state of each of the qubits within the third and fourth plurality of qubits, Methods that include...

23. The aforementioned quantum processor A first set of analog lines, which are communicatively coupled to selectively provide a first analog signal to each qubit in the first plurality of qubits, A second set of analog lines, which are communicatively coupled to selectively provide a second analog signal to each qubit in the second plurality of qubits, A third set of analog lines, which are communicatively coupled to selectively provide a third analog signal to each qubit in the third plurality of qubits, A fourth set of analog lines, which are communicably coupled to selectively provide a fourth analog signal to each qubit in the fourth plurality of qubits, A first set of analog coupler wires, wherein each wire in the first set of analog coupler wires is communicatively coupled to selectively provide an analog signal to each coupler in a first subset of the second set of couplers, A second set of analog coupler wires, wherein each wire in the second set of analog coupler wires is communicatively coupled to selectively provide an analog signal to each coupler in a second subset of the second set of couplers, A third set of analog coupler wires, wherein each wire in the third set of analog coupler wires is communicatively coupled to selectively provide an analog signal to each coupler in a third subset of the second set of couplers, A fourth set of analog coupler wires, wherein each wire in the fourth set of analog coupler wires is communicatively coupled to selectively provide an analog signal to each coupler in a fourth subset of the second set of couplers, The system further comprises, wherein each set of analog lines within the first, second, third, and fourth sets of analog lines includes its respective very high frequency (VHF) control line. The aforementioned method, Applying a signal to at least one of the third and fourth plurality of qubits to initialize each of the at least one qubits in the third and fourth plurality of qubits to its respective ground state is The method according to claim 22, further comprising applying a large amplitude slope to the qubit body of each of the at least one qubit in the third and fourth plurality of qubits via each first VHF control line, wherein applying a signal to the at least one qubit in the third plurality of qubits further comprises applying an ultrashort signal to the qubit body of the at least one qubit in the third plurality of qubits via each VHF control line.

24. The aforementioned quantum processor, A fifth set of analog coupler wires, wherein each wire in the fifth set of analog coupler wires is communicatively coupled to selectively provide an analog signal to each coupler in a first subset of the first plurality of couplers, A sixth set of analog coupler wires, each wire in the sixth set of analog coupler wires being communicatively coupled to selectively provide an analog signal to each coupler in a second subset of the first plurality of couplers, A seventh set of analog coupler wires, wherein each wire in the seventh set of analog coupler wires is communicatively coupled to selectively provide an analog signal to each coupler in a third subset of the first plurality of couplers, An eighth set of analog coupler wires, wherein each wire in the eighth set of analog coupler wires is communicatively coupled to selectively provide an analog signal to each coupler in a fourth subset of the first plurality of couplers, The system further includes, where each analog wire in the first to eighth sets of analog coupler wires includes its respective VHF wire. The aforementioned method, The method according to claim 23, further comprising applying a first CNOT gate using the qubit in the second plurality of qubits as a control and the qubit in the fourth plurality of qubits as a target, and simultaneously applying a second CNOT gate using the qubit in the first plurality of qubits as a target and the qubit in the third plurality of qubits as a control, which includes applying a very high frequency signal to the coupler in the first plurality of couplers via the VHF line in the fifth set of analog coupler lines, and applying a very high frequency signal to the coupler in the second plurality of couplers via the VHF line in the first set of analog coupler lines.

25. The method according to claim 24, wherein simultaneously applying a third CNOT gate using the qubit in the first plurality of qubits as a control and the qubit in the fourth plurality of qubits as a target, and applying a fourth CNOT gate using the qubit in the second plurality of qubits as a target and the qubit in the third plurality of qubits as a control, includes applying a very high frequency signal to the coupler in the first plurality of couplers via the VHF line in the sixth set of analog coupler lines, and applying a very high frequency signal to the coupler in the second plurality of couplers via the VHF line in the second set of analog coupler lines.

26. The method according to claim 24, wherein simultaneously applying a fifth CNOT gate using the qubit in the first plurality of qubits as a control and the qubit in the fourth plurality of qubits as a target, and applying a sixth CNOT gate using the qubit in the second plurality of qubits as a target and the qubit in the third plurality of qubits as a control, includes applying a very high frequency signal to the coupler in the first plurality of couplers via the VHF line in the seventh set of analog coupler lines, and applying a very high frequency signal to the coupler in the second plurality of couplers via the VHF line in the third set of analog coupler lines.

27. The method according to claim 24, wherein simultaneously applying a seventh CNOT gate using the qubit in the second plurality of qubits as a control and the qubit in the fourth plurality of qubits as a target, and applying an eighth CNOT gate using the qubit in the first plurality of qubits as a target and the qubit in the third plurality of qubits as a control, includes applying a very high frequency signal to the coupler in the first plurality of couplers via the VHF line in the eighth set of analog coupler lines and applying a very high frequency signal to the coupler in the second plurality of couplers via the VHF line in the fourth set of analog coupler lines.

Images