Integrated Circuit with an Inductor in a Magnetic Package

Abstract

In one example, an integrated circuit (200) includes a substrate (206), a semiconductor die (104), metal interconnects (130, 132, 134, 136), an inductor (202) attached to the substrate, and a magnetic material (208) that encapsulates the semiconductor die, the inductor, and the metal interconnects. The semiconductor die is attached to the substrate via the metal interconnects. The magnetic material includes coated metal particles (510, 512, 514, 520, 522, 524, 526, 528, 530, and 532) that are coated with a first insulating material and a second insulating material (533) in which the coated metal particles are suspended.

Description

Technical Field

[0001] An inductor can store energy in a magnetic field when current flows through it and can provide current by discharging the stored energy. Inductors can have many applications such as proximity sensing, energy storage, starting, power transmission, and filtering. The inductor may be coupled to an integrated circuit or may be part of an integrated circuit, and the integrated circuit can include circuits that operate with the inductor to support these applications. In some examples, the inductor and the circuit can be encapsulated within an integrated circuit package, thereby reducing the footprint of the integrated circuit and shortening the interconnections between the inductor and the circuit.

Summary of the Invention

[0002] An integrated circuit includes a substrate, a semiconductor die, metal interconnects, an inductor, and a magnetic material. The semiconductor die is attached to the substrate via the metal interconnects. The inductor is attached to the substrate. The magnetic material encapsulates the semiconductor die, the inductor, and the metal interconnects, and the magnetic material includes coated metal particles coated with a first insulating material and a second insulating material in which the coated metal particles are suspended.

[0003] A method includes attaching a semiconductor die to a substrate and attaching an inductor to the substrate. The method further includes depositing a magnetic material on the semiconductor die and the inductor, the magnetic material including coated metal particles coated with a first insulating material and a second insulating material in which the coated metal particles are suspended. The method further includes shaping the magnetic material and dicing the magnetic material and the substrate to form integrated circuits each including a respective semiconductor die and inductor.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0015] FIG. 1A and FIG. 1B are schematic diagrams illustrating an exemplary integrated circuit 100. FIG. 1A and FIG. 1B show a perspective view and a side view of the integrated circuit 100, respectively. Referring to FIGS. 1A and 1B, the integrated circuit 100 can include an inductor 102 and a semiconductor die 104 that are attached to a package substrate 106 and encapsulated within an encapsulation package 108. The inductor 102 can include a metal coil surrounding a core. Examples of inductor cores include air cores, ferrite cores, metal particle cores, and the like. Also, the inductor 102 may be a molded inductor, and the coil and core can be encapsulated within a package made of a molding compound such as a magnetic molding compound (MMC) having metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. The encapsulation package 108 can shield the coil and core and increase the magnetic field density, thereby improving the efficiency of the inductor 102 in the conversion between electrical energy and magnetic energy. Also, the encapsulation package 108 can include a molding compound such as an epoxy molding compound (EMC) that can electrically insulate the inductor 102 and the semiconductor die 104 from external electrical signals such as noise signals and electrostatic signals.

[0016] The semiconductor die 104 and the inductor 102 can form a system for supporting specific applications such as proximity detection, energy storage, startup, power transmission, and filtering. For example, the integrated circuit 100 can include a proximity sensor, and the semiconductor die 104 can include an oscillator and a sensing circuit. The oscillator can drive the inductor 102 using an oscillating current signal, and the sensing circuit can sense the frequency of the current signal. When there is a metal object approaching the inductor 102, the inductance of the inductor 102 can change, which can change the frequency of the current signal. The sensing circuit can detect the metal object by detecting this frequency change. As another example, the integrated circuit 100 can include a switched-mode power converter for transmitting power from a power source to a load. In such an example, the inductor 102 can provide energy storage, and the semiconductor die 104 can include switches for charging and discharging the inductor 102 to set the voltage across the load.

[0017] Also, the package substrate 106 can provide mechanical support to the inductor 102 and the semiconductor die 104, and can provide electrical connections between the inductor and the semiconductor die, and between the integrated circuit 100 and an external device. For example, the package substrate 106 can include an electrical insulating material such as a polymer, a MSG build-up film (ABF), or a ceramic material. The package substrate 106 can also include metal pads 110, 112, 114, 116, and 118 that can be copper pads on the surface 120 to which the inductor 102 and the semiconductor die 104 are attached.

[0018] Also, the semiconductor die 104 can include a passivation layer 122 that can be coupled to the metal pads 110, 112, 114, and 116 via respective metal interconnects 130, 132, 134, and 136. Each pad can be coupled to a respective metal interconnect via a solder layer. The passivation layer 122 can insulate circuit elements within the semiconductor die 104 from the metal interconnects 130, 132, 134, and 136. The metal interconnects 130 - 136 can include, for example, copper pillars, solder bumps, and under-bump metallization (UBM) interconnects. Also, the inductor 102 can be coupled to the metal pad 118 via a solder layer. The package substrate 106 can include metal interconnects on or under the surface 120 to provide electrical connections between the inductor 102 and the semiconductor die 104, such as a metal interconnect 140 between the metal pads 116 and 118.

[0019] Package substrate 106 can also include metal pads, such as metal pads 160, 162, and 164, on surface 150 opposite to surface 120. The metal pads can include copper pads or pads made of other metals (e.g., silver or palladium). Package substrate 106 can also include metal interconnects, such as copper interconnects, to provide electrical connections between the metal pads on opposite surfaces. For example, package substrate 106 can include a metal interconnect 170 between metal pads 110 and 160, a metal interconnect 172 between metal pads 112 and 162, and a metal interconnect 174 between metal pads 114 and 164. The metal pads and interconnects on surface 150 can provide electrical connections between an external device and integrated circuit 100. For example, metal pads 160, 162, and 164 can be coupled to a printed circuit board (PCB) 176 via respective solder balls 180, 182, and 184, thereby providing an electrical connection between integrated circuit 100 and an external device (e.g., a power supply) on PCB 176. Package substrate 106 can also include a solder resist layer 190 on surface 150 to shield the metal interconnects (e.g., metal interconnects 170, 172, and 174) within the package substrate from the solder balls.

[0020] FIG. 2A illustrates an example of an integrated circuit 200 that can have a reduced footprint compared to the integrated circuit 100 of FIGS. 1A and 1B. FIG. 2A shows a side view of the integrated circuit 200. Referring to FIG. 2A, the integrated circuit 200 can include an inductor 202 and a semiconductor die 104 that are attached to a package substrate 206. The integrated circuit 200 can also include a magnetic material (e.g., MMC) on the package substrate 206. The magnetic material can encapsulate the inductor 202 and the semiconductor die 104 as an encapsulation package 208. In some examples, the package substrate 206 can include a routable lead frame (RLF). The inductor 202 can include a coil portion 210 that can include various types of cores such as a ferrite core and a metal particle core, and stilt portions 212a and 212b that support the coil portion 210 on the package substrate 206. Also, the semiconductor die 104 can be disposed between the stilt portions 212a and 212b and under the coil portion 210 such that the coil portion 210 and the semiconductor die 104 can form a device stack. In some examples, the coil portion 210 can have a lateral opening (e.g., along the x / y axis) as shown in FIGS. 3A-3C. In some examples, the coil portion 210 can have an opening that faces up / down (e.g., along the z axis) across the semiconductor die 104 as shown in FIGS. 4A-4C.

[0021] The package substrate 206 can include metal pads 220, 222, 224, 226, 228, and 230, which can be copper pads on a surface 232 to which the inductor 202 and the semiconductor die 104 are attached. The integrated circuit 200 can include metal interconnects 130, 132, 134, and 136 of the semiconductor die 104, which can be coupled to respective metal pads 222, 224, 226, and 228 via solder layers. Also, the stilt portions 212a and 212b of the inductor 202 can be coupled to respective metal pads 220 and 230 via solder layers.

[0022] Package substrate 206 can also include metal pads such as metal pads 252, 254, 256, and 258 on surface 250 opposite to surface 232, which can include pads made of copper pads or other metals (e.g., silver and palladium). Metal pads 252, 254, 256, and 258 can be coupled to an external device via solder balls such as solder balls 180 - 184 of PCB 176 and FIG. 1 to provide an electrical connection between integrated circuit 200 and the external device. Package substrate 206 can also include metal interconnects such as copper interconnects that connect metal pads on the same or different surfaces. For example, package substrate 206 can include a metal interconnect 260 coupled between metal pads 220 and 222 (on surface 232) to provide an electrical connection between inductor 202 and semiconductor die 104. Package substrate 206 can also include a metal interconnect 262 coupled between metal pads 224 and 252, a metal interconnect 264 coupled between metal pads 226 and 254, a metal interconnect 266 coupled between metal pads 228 and 256, and a metal interconnect 268 coupled between metal pads 230 and 258 to provide electrical connections between the external device and inductor 202 and / or semiconductor die 104. Package substrate 206 can include an electrical insulation layer 269 such as a polymer, ABF, or ceramic material to provide electrical insulation between the metal interconnect and the metal pad. Also, package substrate 206 can include a solder resist layer 270 under surface 250 to shield the metal interconnects (e.g., metal interconnects 260, 262, 264, 266, and 268) within the package substrate from the solder balls and the external device.

[0023] Also, as described above, the inductor 202 and the semiconductor die 104 can be encapsulated within an encapsulation package 208 on the package substrate 206. The encapsulation package 208 can include a magnetic material such as an MMC. The MMC can have metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. The encapsulation package 208 can shield the inductor 202 and increase the magnetic field density, thereby improving the efficiency of the inductor 202 in the conversion between electrical energy and magnetic energy. The MMC material of the encapsulation package 208 can fill the space within the inductor 202, such as at the center of the coil portion 210 (e.g., when the inductor 202 has an air core) and between the individual coils of the coil portion 210. The MMC material can also fill the space between the coil portion 210 and the semiconductor die 104 and between the metal interconnects 130, 132, 134, and 136.

[0024] FIG. 2B illustrates another example of the integrated circuit 200. Referring to FIG. 2B, the semiconductor die 104 can be disposed outside the inductor 202 and proximate to the inductor 202. The integrated circuit 200 can include another circuit component such as a capacitor 280 disposed beneath the coil portion 210 and the support posts 212a and 212b such that the coil portion 210 and the capacitor 280 can form a device stack. In some examples, the semiconductor die 104 and the capacitor 280 can be disposed beneath the coil portion 210 and the support posts 212a and 212b to form a device stack.

[0025] The package substrate 206 can include metal pads 234 (e.g., copper pads) in addition to the metal pads 220 - 230 on the surface 232 to which the semiconductor die 104 and the capacitor 280 are attached. The integrated circuit 200 can include metal interconnects 130, 132, and 136 (e.g., copper pillars, solder bumps, or UBM interconnects) coupled between the semiconductor die 104 and the respective metal pads 222, 224, and 226 of the package substrate 206. Also, the integrated circuit 200 can include metal interconnects 282 and 284 (e.g., copper pillars, solder bumps, or UBM interconnects) coupled between the capacitor 280 and the respective metal pads 228 and 234. The package substrate 206 can also include metal interconnects coupled between the metal pads on the surface 232 and the metal pads on the surface 250 to provide external access to the semiconductor die 104, the inductor 202, and the capacitor 280. For example, the package substrate 206 can include a metal interconnect 262 coupled between the metal pads 222 and 252, a metal interconnect 264 coupled between the metal pads 224 and 254, a metal interconnect 266 coupled between the metal pads 228 and 256, and a metal interconnect 268 coupled between the metal pads 230 and 258. The package substrate 206 can also include a metal interconnect 260 coupled between the metal pads 220, 226, and 228 to provide internal electrical connections between the semiconductor die 104, the inductor 202, and the capacitor 280.

[0026] By placing the semiconductor die 104 and / or the capacitor 280 beneath the coil portion 210 of the inductor 202, the integrated circuit 200 of FIGS. 2A and 2B can have a reduced footprint (e.g., in the x-y plane), and thereby shorten the metal interconnects between the semiconductor die 104 and the inductor 202 (e.g., the metal interconnect 260) and reduce their parasitic capacitances. The arrangements of FIGS. 2A and 2B also allow the coil portion of the inductor to cover a majority of the footprint of the integrated circuit 200, enabling the integrated circuit 200 to include a larger inductor with an increased inductance. Further, by encapsulating the inductor 202 within the MMC encapsulation package, the magnetic field density within the integrated circuit 200 can be increased, thereby improving the efficiency of the inductor 202 in the conversion between electrical energy and magnetic energy.

[0027] The integrated circuit 200 can be manufactured by attaching a plurality of electronic components (e.g., the semiconductor die 104, the inductor 202, and / or the capacitor 280) to a substrate, depositing an MMC material over the electronic components and the substrate, molding and curing the MMC material to form an encapsulation package, and then dicing the molded and cured MMC material and the substrate into a plurality of integrated circuits 200, such that each integrated circuit 200 can include a set of electronic components (e.g., the semiconductor die 104, the inductor 202, and / or the capacitor 280) attached to the substrate 206 and encapsulated by the MMC encapsulation package 208.

[0028] While the MMC encapsulation package can increase the magnetic field density within the integrated circuit 200, the dicing operation can change the structure of the MMC material on the diced surface and can reduce the electrical breakdown voltage through the MMC material. Since the breakdown voltage is reduced, a relatively small voltage difference between metal interconnects can be sufficient for leakage current to flow between the metal interconnects through the MMC material, thereby increasing the risk of an electrical short circuit. Accordingly, the functionality, reliability, and safety of the integrated circuit 200 can be compromised.

[0029] Figures 5A - 5C are schematic diagrams illustrating an exemplary structure of the MMC material of the encapsulation package 208 of the integrated circuit 200. Figures 5A and 5B illustrate a first view of the MMC encapsulation package 208 and the substrate 206 from the x - axis, where the diced surfaces 502 and 504 are in the x - z plane. Also, Figure 5C shows a second view of the MMC encapsulation package 208 and the substrate 206 from the y - axis of Figure 5A or 5B, including the diced surface 502. The MMC encapsulation package 208 and the substrate 206 can encapsulate the electronic device 506. In the example of Figure 5A, the electronic device 506 can include the semiconductor die 104 of Figure 2A, the inductor 202, and the metal interconnects 130 - 136, and the semiconductor die 104 is disposed under the coil portion 210 between the strut portions 212a and 212b of the inductor 202. In the example of Figure 5B, the electronic device 506 can include the semiconductor die 104 of Figure 2B, the inductor 202, the capacitor 280, and the metal interconnects 132, 134, 282, and 284, the capacitor 280 is disposed under the coil portion 210 between the strut portions 212a and 212b of the inductor 202, and the semiconductor die 104 is disposed adjacent to the inductor 202. In the subsequent Figure 6A, the electronic device 506 is represented by a dotted frame for simplicity.

[0030] Referring to FIGS. 5A-5C, the MMC material of the encapsulation package 208 can include metal particles (e.g., iron particles) such as metal particles 510, 512, 514, 520, 522, 524, 526, 528, 530, and 532 suspended in an epoxy resin 533. In FIG. 5A, the metal particles 510, 512, 514, 520, 522, and 524 are separated by the epoxy resin, whereby electrical leakage through the metal particles can be reduced (and the resistance increased). For example, there may be a leakage current path 535 between metal interconnects 534 and 536 through metal particles 510, 512, and 514, and a leakage current path 542 between metal interconnects 544 and 546 through metal particles 520, 522, and 524. However, since the metal particles are separated by an epoxy resin having a relatively high breakdown voltage (e.g., compared to air), any leakage current paths can have a high resistance, and the leakage current flowing between the metal interconnect through the metal particles and the epoxy resin is negligible.

[0031] However, the dicing operation can remove a portion of the resin on the diced surfaces 502 and 504, thereby exposing the metal particles on the diced surfaces and reducing the resistance of the leakage current paths through those metal particles. For example, metal particles 526 and 528 on the diced surface 502, and metal particles 530 and 532 on the diced surface 504 can be exposed by the removal of the epoxy resin 533. Accordingly, a portion of the metal particles 526 and 528 can be separated by an air gap 550, and a portion of the metal particles 530 and 532 can be separated by an air gap 552. Since air can have a lower breakdown voltage than the epoxy resin, the metal particles exposed on the diced surfaces 502 / 504 can provide leakage current paths having a reduced resistance. For example, referring to FIG. 5C, there is a leakage current path 560 with reduced resistance between metal interconnects 562 and 564 and through the air gaps between metal particles 566, 532, 530, 568, 570, 572, and 574, which can lead to a potential short circuit and compromise the functionality, reliability, and safety of the integrated circuit 200.

[0032] Figures 6A and 6B illustrate an exemplary MMC material that can address at least some of the above-described problems. Referring to FIGS. 6A and 6B, some or all of the metal particles of the MMC material can be coated metal particles coated with an insulating layer 602, and the coated metal particles are suspended within an epoxy resin 533. The insulating layer 602 can include a material having a high breakdown voltage, such as silicon dioxide (e.g., glass) or a metallic phosphate (e.g., iron phosphate). The insulating layer 602 can provide electrical insulation, which can add to the electrical insulation provided by the epoxy resin 533 and increase the breakdown voltage of the MMC material. Also, for metal particles (e.g., metal particles 526, 528, 530, and 532) exposed on the diced surfaces 502 and 504 and separated by an air gap, the insulating layer 602 can also add to the electrical insulation provided by the air gap. Thus, leakage current paths through exposed metal particles, such as the leakage current path 560 between the metal interconnections 562 and 564 in FIG. 6B, can have a high resistance, thereby reducing potential short circuits and improving the functionality, reliability, and safety of the integrated circuit 200.

[0033] Figures 7 and 8 illustrate additional exemplary MMC materials that can reduce leakage along the diced surface. Referring to Figure 7, a portion of the metal particles of the MMC material on the diced surface (e.g., diced surface 504) can be removed to create cavities such as cavities 702, 704, 706, 708, 710, and 712 between the remaining metal particles. The cavities can be filled with an insulating material (e.g., air or epoxy resin) to provide additional electrical insulation between the metal particles, thereby increasing the breakdown voltage and resistance of the current leakage path through the metal particles. For example, cavity 702 may be along leakage current path 560 between metal particles 566 and 530, cavity 704 may be along leakage current path 560 between metal particles 530 and 570, and cavity 706 may be along leakage current path 560 between metal particles 570 and 574. The insulating material within cavities 702, 704, and 706 can increase the resistance of leakage current path 560 and reduce a small amount of leakage current between metal interconnects 562 and 564. Also, as shown in Figure 8, at least a portion of the metal particles remaining on the diced surface, such as metal particles 530, 566, 570, 574, etc., can be coated with an insulating film 602, thereby further increasing the breakdown voltage of the MMC material and reducing potential short circuits.

[0034] Figures 9 and 10 illustrate examples of methods for generating the exemplary MMC materials of Figures 6A and 6B. Figure 9 illustrates a flowchart 900 of an example of a method for creating an MMC material, and Figure 10 is a schematic diagram illustrating some of the operations of the example method of Figure 9.

[0035] Referring to FIG. 9, in operation 902, metal particles (e.g., iron particles) can be mixed with a solvent to form a mixture. Referring to FIG. 10, in sub-operation 902a, the metal particles 1002 can be added to a solvent 1004 such as water or an organic solvent (e.g., alcohol and kerosene), and then in sub-operation 902b, the metal particles 1002 and the solvent 1004 can be mixed and stirred to form a viscous slurry 1006, where the metal particles 1002 can be suspended in the solvent 1004.

[0036] In operation 904, at least a portion of the metal particles can be coated with a layer of a first insulating material (e.g., insulating layer 602). Examples of the first insulating material can include silicon dioxide and phosphate. Referring again to FIG. 10, in sub-operation 904a, a reagent 1008 can be added to the slurry 1007, and subsequently in sub-operation 904b, the reagent 1008 and the slurry 1006 can be heated (e.g., by a heater 1010) and stirred to form an insulating layer.

[0037] In some examples, the reagent 1008 can form X-OH or X-OR bonds to coat the insulating layer on the surface of the metal particles 1002, where X represents Si (silicon) or P (phosphorus), OH represents hydroxide, and R represents an alkyl substituent. Different reagents 1008 can be used to coat different insulating materials on the metal particles 1002. For example, in operation 904, a reagent containing an orthosilicate such as tetraethyl orthosilicate (Si(OC2H5)4) can be used to coat a layer of silicon dioxide on the metal particles 1002. Also, in operation 904, a reagent containing a phosphoric acid such as orthophosphoric acid (H3PO4) can be used to coat a layer of phosphate on the metal particles 1002.

[0038] In operation 906, the metal particles coated with the insulating layer can be separated from the solvent. The separation can be performed, for example, by passing the slurry 1006 through a filter to remove the solvent 1004 and the reagent 1008 while retaining the metal particles, and subsequently washing and drying the metal particles.

[0039] In operation 906, the metal particles coated with the insulating layer can be mixed with a second insulating material to form a magnetic molding compound (MMC) material. The second insulating material can include an epoxy resin. As part of operation 906, a kneading operation of mixing the metal particles with the epoxy resin and then kneading the mixture with an extruder may follow. The kneaded mixture can be shaped into a specific shape (e.g., a sheet) and cooled. The MMC material can then be pulverized into particles, which can be melted and molded to form the encapsulation package 208.

[0040] FIG. 11 and FIGS. 12A - 12G illustrate an example of a method for manufacturing an integrated circuit having an inductor in a magnetic package such as the integrated circuit 200 of FIGS. 2A - 8. FIG. 11 shows a flowchart 1100 of an exemplary method for manufacturing an integrated circuit, and FIGS. 12A - 12C are schematic diagrams illustrating various operations of the exemplary method of FIG. 11.

[0041] In operation 1102, a plurality of semiconductor dies can be attached onto a substrate.

[0042] Referring to FIG. 12A, in sub - operation 1102a, the substrate 1200 can include metal pads 1202, 1204, 1206, 1208, 1210, 1212 on the surface 1216 and metal pads 1222, 1224, 1226, and 1228 on the surface 1230 opposite to the surface 1216. The substrate 1200 can also include metal interconnects 1232, 1234, 1236, and 1238 to provide electrical connections between the metal pads. The substrate 1200 can also include an insulating layer 1240 such as a polymer, ABF, or ceramic material to provide electrical insulation between the metal interconnects and the metal pads. In some examples, the substrate 1200 can include a routable lead frame (RLF).

[0043] Referring to FIG. 12B again, in sub-operation 1102b, solder layers 1242, 1243, 1244, 1245, 1246, and 1247 are deposited on respective metal pads 1202, 1204, 1208, 1210, and 1212.

[0044] Referring to FIG. 12C, in sub-operation 1102c, the semiconductor die 104 can be attached to metal pads 1234 - 1246 of the substrate 1200 via metal interconnects 130 - 136. In some examples, a pick-and-place (PnP) machine can align metal interconnects 130 - 136 with respective solder layers 1243 - 1246 and then place the semiconductor die 104 on the solder layer.

[0045] Referring to FIG. 11 again, in operation 1104, a plurality of inductors can be attached on the substrate.

[0046] Referring to FIG. 12D, in sub-operation 1104a, the support portions 212a and 212b of the inductor 202 can be attached to metal pads 1202 and 1212 of the substrate 1200 via respective solder layers 1242 and 1247, so that the coil portion 210 of the inductor 202 is on / above the semiconductor die 104. In some examples, a PnP machine can align the support portions 212a and 212b of the inductor 202 with respective solder layers 1242 and 1247 and then place the support portions on the solder layer. Referring to FIG. 12E, in sub-operation 1104b, a reflow operation can be performed, and the inductor 202 and the semiconductor die 104 are heated in a furnace 1250 together with the substrate 1200 and the solder layers 1242 - 1247. The solder layers can reflow in a molten state to create a solder joint between the inductor 202, the semiconductor die 104, and the substrate 1200.

[0047] Referring to FIGS. 11 and 12F, in operation 1106, a magnetic material (e.g., MMC) is deposited on the semiconductor die, inductor, and substrate. The magnetic material includes coated metal particles coated with a first insulating material and a second insulating material in which the coated metal particles are suspended. Examples of the magnetic material are illustrated in FIGS. 6A - 8. The magnetic material can include coated metal particles such as metal particles 510, 512, 514, 520, 522, and 524 in FIGS. 6A - 8. Each coated metal particle is coated with an insulating layer 602 such as a silicon dioxide / phosphate layer. The coated metal particles are suspended in an epoxy resin so that leakage on the diced surface where the epoxy resin can be removed and the metal particles are exposed is reduced. Also, the magnetic material can be molded and heated in operation 1108 so that it can be cured to form a sealing package 208 for each semiconductor die 104 and inductor 202.

[0048] Referring to FIG. 12G, in operation 1110, the molded magnetic material and substrate are diced to form an integrated circuit including each semiconductor die and inductor. The dicing can be performed, for example, by a rotating blade 1260.

[0049] In some examples, the dicing can be done to remove a portion of the metal particles from the magnetic material to form a cavity that can be filled with air or another insulating material such as an epoxy resin. The removal of the metal particles can be done by increasing the contact time between the metal particles and the blade during the dicing operation. The contact time can be increased by decreasing the speed at which the blade moves across the dicing surface (e.g., the dicing speed), decreasing the rotational speed of the blade (e.g., the spindle speed), or both, so that the force applied to the metal particles by the blade can overcome the bonding force between the metal particles and the epoxy resin.

[0050] Also, as described above, the cavity can be filled with air or another insulating material such as an epoxy resin. After the dicing operation, a resin coating layer can be applied on the dicing surface to fill the cavity with resin. In some examples, the resin coating layer can be applied by spraying or by a spin coating operation.

[0051] Any of the methods described herein can be implemented, in whole or in part, using a computing system that includes one or more processors configured to perform such steps. Therefore, embodiments can be directed to a computing system configured to perform the steps of any of the methods described herein, and potentially, different components perform respective steps or groups of respective steps. Although shown as numbered steps, the steps of the methods herein may be performed simultaneously or in a different order. Also, some of these steps may be used in conjunction with parts of other steps from other methods. Also, all or part of the steps may be optional. Also, any of the steps of any method can be performed using a module, unit, circuit, or other means for performing these steps.

[0052] As used in this description, the term "coupled" can include a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A provides a signal for controlling device B to perform a certain action, (a) in a first example, device A is directly coupled to device B, or (b) in a second example, when an intervening component C does not substantially change the functional relationship between device A and device B, device A is indirectly coupled to device B through the intervening component C, so that device B is controlled by device A via the control signal provided by device A.

[0053] A device "configured to" perform a certain task or function is configured by the manufacturer during manufacture (e.g., programmed and / or wired) to perform that function, and / or may be configurable (or reconfigurable) by the user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the configuration and / or layout of hardware components, via the interconnection of the device, or via a combination thereof.

[0054] A circuit or device described herein as including particular components may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), which are coupled to those components and adapted to form the described circuit or device. For example, a structure described herein as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more supply sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device, and may be coupled to at least some of the passive elements and / or supply sources, either during or after manufacture, by an end user and / or a third party, etc., and adapted to form the described structure.

[0055] Although specific components may be described herein as being of a particular process technology, these components may be exchanged with components of other process technologies. The circuits described herein are reconfigurable to include the exchanged components in order to provide at least partially similar functions as the functions available prior to component exchange. Components shown as resistors generally represent any one or more elements that are coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown, unless otherwise specified. For example, a resistor or capacitor shown and described herein as a single component may instead be a plurality of resistors or capacitors, respectively, coupled in series or in parallel between the same two nodes as a single resistor or capacitor.

[0056] The use of the phrase "ground voltage potential" herein includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this specification. As used herein, unless otherwise specified, "about", "approximately" or "substantially" preceding a parameter means within + / - 10% of that parameter.

[0057] Within the scope of the claims of the present invention, modifications may be made to the illustrated exemplary embodiments, and other embodiments are possible.

Claims

1. It is an integrated circuit, circuit board and First metal interconnection and A semiconductor die attached to the substrate via the first metal interconnect, An inductor attached to the aforementioned substrate, A magnetic material for sealing the semiconductor die, the inductor, and the first metal interconnect, wherein the magnetic material seals the space within the inductor in order to form the magnetic core of the inductor, An integrated circuit, including

2. The integrated circuit according to claim 1, The aforementioned magnetic material, Metal particles covered with a first insulating material, A second insulating material comprising epoxy resin, wherein the metal particles are suspended from the second insulating material, An integrated circuit, including

3. The integrated circuit according to claim 2, An integrated circuit in which the first insulating material includes a silicon oxide material.

4. The integrated circuit according to claim 2, An integrated circuit in which the first insulating material includes a phosphate material.

5. The integrated circuit according to claim 1, An integrated circuit in which the inductor includes a coil portion and a support portion coupled to the substrate.

6. The integrated circuit according to claim 5, An integrated circuit in which the coil portion is located on the semiconductor die.

7. The integrated circuit according to claim 5, The present invention further includes a capacitor sealed within the magnetic material, An integrated circuit in which the coil portion is located on top of the capacitor.

8. The integrated circuit according to claim 1, The aforementioned substrate, A first metal pad on the first side of the substrate, which is coupled to the first metal interconnect and the inductor, A second metal pad on the second side of the substrate opposite to the first side, An insulating layer between the first side and the second side, A second metal interconnect within the insulating layer, wherein the second metal interconnect is coupled between the first metal pad and the second metal pad, An integrated circuit, including

9. The integrated circuit according to claim 8, The first metal pad and the second metal interconnect include copper metal. The second metal pad comprises at least one of palladium metal and silver metal. An integrated circuit in which the insulating layer comprises at least one of a polymer material, an Ajinomoto build-up film (ABF), and a ceramic material.

10. The integrated circuit according to claim 9, An integrated circuit further comprising a solder resist layer on the second side.

11. The integrated circuit according to claim 5, An integrated circuit in which the magnetic material further fills the gaps between the individual coils of the coil portion.

12. The integrated circuit according to claim 5, An integrated circuit in which the coil portion has an opening that faces laterally in a direction parallel to the substrate.

13. The integrated circuit according to claim 5, An integrated circuit in which the coil portion has an opening that faces the semiconductor die in a direction perpendicular to the substrate.

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