Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, and a circuit pattern layer disposed between the first and second insulating layers, wherein the second insulating layer has a cavity penetrating its upper and lower surfaces, and the circuit pattern layer includes an electrode pattern extending from inside the cavity to outside the cavity.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical / electronic products continues to improve, technologies for mounting more packages on a board with limited size are being proposed and researched.

[0003] A typical semiconductor package has a structure in which multiple chips are arranged. Recently, the size of semiconductor packages has increased due to the high specifications of products to which the semiconductor packages are applied and the adoption of multiple chips such as HBM (High Bandwidth Memory). Therefore, the semiconductor package includes an interposer for connecting multiple chips.

[0004] In addition, semiconductor packages used in products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are required to have high performance and reliability in line with the trend toward higher integration.

[0005] Furthermore, the semiconductor package may have a vertical connection structure between a plurality of substrates, interposers, and semiconductor devices, whereby the semiconductor package may have a vertical thickness that increases depending on the thickness and number of the substrates, interposers, and semiconductor devices.

[0006] Therefore, the semiconductor package has a substrate with a cavity to reduce its vertical thickness. The cavity can be formed by processing the substrate with a laser. To this end, a dummy pattern is provided on the substrate. Then, the cavity is formed by performing a laser process using the dummy pattern as a stopper.

[0007] Therefore, according to the conventional technology, a step of forming the dummy pattern and a step of removing the dummy pattern must be performed, which causes a problem of making the manufacturing process complicated.

[0008] Furthermore, the conventional substrate includes a pad exposed through the cavity. In this case, only the pad exists in the area exposed through the cavity. This is because if an electrode pattern such as a trace exists in the area exposed through the cavity, the dummy pattern may electrically connect the traces to each other, resulting in a short circuit. Therefore, the conventional substrate has a problem of reduced circuit integration.

[0009] (Patent Document 1) KR10-2012-0045639A Summary of the Invention [Problem to be solved by the invention]

[0010] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0011] Furthermore, the embodiments provide a slimmable circuit board and a semiconductor package including the same.

[0012] Furthermore, the embodiments provide a circuit board capable of minimizing the length of a signal line connected to a connecting member, and a semiconductor package including the same.

[0013] Furthermore, the embodiments provide a circuit board that includes a thermosetting resin and that can have an electrode pattern disposed in a cavity region, and a semiconductor package including the same.

[0014] Furthermore, the embodiments provide a circuit board with improved circuit integration and a semiconductor package including the same.

[0015] Furthermore, the present invention provides a circuit board having improved adhesion to a molding member and a semiconductor package including the same.

[0016] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0017] A circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, and a circuit pattern layer disposed between the first and second insulating layers, wherein the second insulating layer has a cavity penetrating its upper and lower surfaces, and the circuit pattern layer includes an electrode pattern extending from inside the cavity to outside the cavity.

[0018] The circuit pattern layer further includes a first pad provided inside the cavity and vertically overlapping the cavity, and a second pad provided outside the cavity and not vertically overlapping the cavity.

[0019] The second insulating layer has a recess recessed in a direction from the lower end of the side wall of the cavity toward the outer surface of the second insulating layer.

[0020] The recessed portion has a first portion that does not overlap the electrode pattern in the vertical direction, and a second portion that overlaps the electrode pattern in the vertical direction.

[0021] The circuit pattern layer is provided to protrude from the first insulating layer, and the first portion of the recess is provided along the frame of the lower end of the side wall of the cavity.

[0022] The first and second portions of the recess have a step.

[0023] Further, each of the first pad, the second pad, and the electrode pattern includes a first metal layer disposed on the first insulating layer and a second metal layer disposed on the first metal layer, and the vertical length of the first recess corresponds to the thickness of the first metal layer.

[0024] Furthermore, the horizontal distance from the lower end of the sidewall of the cavity to the innermost end of the first portion of the recessed portion falls within the range of 5 μm to 17 μm.

[0025] Additionally, the horizontal length of the first portion of the recess is different from the horizontal length of the second portion of the recess.

[0026] Additionally, the thickness of the first pad is different from the thickness of the second pad.

[0027] The vertical length of the first portion of the recess falls within the range of 1.0 μm to 4.0 μm.

[0028] Furthermore, the horizontal length of the first portion of the recess is smaller than the horizontal length of the second portion of the recess.

[0029] The thickness of the first pad is smaller than the thickness of the second pad.

[0030] The electrode pattern also includes a region that overlaps the sidewall of the cavity in the vertical direction and has a thickness that varies along the horizontal direction.

[0031] Furthermore, the first pad, the second pad, and the electrode pattern are embedded in the upper surface of the first insulating layer, and the upper surface of the first region of the first insulating layer is located lower than the upper surface of the second region of the first insulating layer.

[0032] The recess is recessed from the top surface of the first region of the first insulating layer toward the inside of the first insulating layer.

[0033] At least one of the first pad, the second pad, and the electrode pattern has a layer structure different from at least one of the others.

[0034] Furthermore, the first circuit pattern layer includes a first metal layer and a second metal layer, the first pad of the first circuit pattern layer includes the second metal layer excluding the first metal layer, the second pad of the first circuit pattern layer includes both the first metal layer and the second metal layer, and the electrode pattern includes a first portion including only the second metal layer and a second portion including both the first and second metal layers.

[0035] The second insulating layer having the cavity includes a thermosetting resin. [Effects of the Invention]

[0036] The circuit board of the embodiment includes a first insulating layer, a first circuit pattern layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and the first circuit pattern layer. The second insulating layer includes a cavity penetrating its upper and lower surfaces. The first circuit pattern layer includes a first pad disposed in a first region vertically overlapping the cavity, a second pad disposed in a second region not vertically overlapping the cavity, and an electrode pattern disposed in the first region and the second region, connecting the first pad and the second pad.

[0037] That is, in the embodiment, an electrode pattern that directly connects the first pad and the second pad is disposed on the first insulating layer. Through this, the embodiment can reduce the signal transmission distance between the first pad and the second pad. Furthermore, the embodiment can minimize signal transmission loss due to the reduction in the signal transmission distance. As a result, the embodiment can improve the electrical characteristics of a circuit board and a semiconductor package including the same.

[0038] In addition, the embodiment can improve circuit integration by disposing the electrode pattern in an area corresponding to the cavity.

[0039] Meanwhile, the second insulating layer including the cavity includes a thermosetting resin. In the embodiment, the electrode pattern can be arranged while the second insulating layer includes a thermosetting resin. In the embodiment, by forming the insulating layer using a thermosetting resin, the adhesion between the multiple insulating layers can be improved. As a result, the embodiment can improve the physical properties of the circuit board and the semiconductor package including the circuit board.

[0040] Meanwhile, a recess may be formed at a lower end of a sidewall of the cavity along a circumferential direction of a bottom surface of the cavity. The recess may have a closed loop shape along a circumferential direction of the bottom surface of the cavity. In this case, the recess may include a stepped portion in one embodiment, or may not have a stepped portion in another embodiment.

[0041] Therefore, in the embodiment, a connecting member and a molding member that molds the connecting member are disposed in the cavity. The molding member may fill a recess formed in the cavity. In this case, the embodiment may allow a portion of the entire area of the molding member that is disposed in the recess to function as an anchor. Therefore, the embodiment may improve the adhesion between the circuit board and the molding member. As a result, the embodiment may more stably protect the connecting member. Furthermore, the embodiment may further improve the product reliability of the semiconductor package. [Brief explanation of the drawings]

[0042] [Figure 1a] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 1b] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 1c]FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 1d] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 1e] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 1f] FIG. 10 is a cross-sectional view showing a semiconductor package according to a sixth embodiment. [Figure 1g] FIG. 13 is a cross-sectional view showing a semiconductor package according to a seventh embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the circuit board of the first embodiment. [Figure 3] 3 is a plan view showing a first insulating layer and a first circuit pattern layer in the circuit board of FIG. 2. FIG. [Figure 4] 4 is a plan view of the circuit board of FIG. 3 with some components removed. [Figure 5] FIG. 5 is a cross-sectional view taken along the line AA' in FIGS. 3 and 4. [Figure 6] 6 is an optical microscope photograph of the actual product corresponding to FIG. 5. [Figure 7] FIG. 5 is a cross-sectional view taken along the line BB' in FIGS. 3 and 4. [Figure 8] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 9] FIG. 9 is an enlarged view of a portion of the cavity in FIG. 8. [Figure 10] 9 is an enlarged view of another part of the cavity in FIG. 8. FIG. [Figure 11] 1A and 1B are diagrams illustrating a package substrate according to an embodiment. [Figure 12-22] 3A to 3C are diagrams showing a method for manufacturing the circuit board of FIG. 2 according to an embodiment in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0043] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Identical or similar components are designated by the same reference numerals, regardless of their reference numerals, and redundant descriptions will be omitted. The suffixes "module" and "section" used in the following description are used solely for the convenience of drafting the specification and do not have any distinguishing meanings or functions. Furthermore, when describing the embodiments disclosed herein, if a detailed description of related publicly known technology is deemed to obscure the gist of the embodiments disclosed herein, that detailed description will be omitted. Furthermore, the accompanying drawings are intended to facilitate understanding of the embodiments disclosed herein, and the technical concepts disclosed herein should not be limited by the accompanying drawings. It should be understood that the accompanying drawings include all modifications, equivalents, and alternatives within the spirit and scope of the present invention.

[0044] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0045] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that it may be directly coupled or connected to the other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components in between.

[0046] The singular expression includes the plural expression unless the context clearly indicates otherwise.

[0047] In this application, the use of terms such as "comprises" or "having" is intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described herein, and should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0048] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0049] -Electronic Devices-

[0050] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various semiconductor elements may be mounted in the semiconductor package.

[0051] The semiconductor device may include active devices and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0052] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0053] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0054] The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0055] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0056] In one embodiment, the circuit board may be the first board described below.

[0057] In other embodiments, the circuit board may be a second board, as described below.

[0058] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0059] Referring to FIG. 1 a, the semiconductor package of the first embodiment may include a first substrate 1100 , a second substrate 1200 , and a semiconductor device 1300 .

[0060] The first substrate 1100 may refer to a package substrate.

[0061] For example, the first substrate 1100 may provide a space to which at least one external substrate is coupled. The external substrate may refer to the second substrate 1200 coupled on the first substrate 1100. Also, the external substrate may refer to a main board included in an electronic device coupled under the first substrate 1100.

[0062] Although not shown in the drawings, the first substrate 1100 may provide a space in which at least one semiconductor device is mounted. To this end, the first substrate 1100 may include a cavity. At least one semiconductor device may be disposed in the cavity of the first substrate 1100.

[0063] The first substrate 1100 includes at least one insulating layer, an electrode disposed on the at least one insulating layer, and a through-hole penetrating the at least one insulating layer.

[0064] A second substrate 1200 is disposed on the first substrate 1100 .

[0065] The second substrate 1200 may be an interposer. For example, the second substrate 1200 may provide a space in which at least one semiconductor device is mounted. The second substrate 1200 may be connected to the at least one semiconductor device 1300. For example, the second substrate 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are mounted. The second substrate 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320, and may also electrically connect the first and second semiconductor devices 1310 and 1320 to the first substrate 1100. That is, the second substrate 1200 may function as a horizontal connection between a plurality of semiconductor devices and a vertical connection between the semiconductor device and a package substrate.

[0066] 1a illustrates two semiconductor elements 1310 and 1320 disposed on the second substrate 1200, but is not limited thereto. For example, one semiconductor element may be disposed on the second substrate 1200, or alternatively, three or more semiconductor elements may be disposed on the second substrate 1200.

[0067] The second substrate 1200 may be disposed between the semiconductor device 1300 and the first substrate 1100 .

[0068] In one embodiment, the second substrate 1200 may be an active interposer that functions as a semiconductor device. When the second substrate 1200 functions as a semiconductor device, the package of the embodiment may have a vertically stacked structure on the first substrate 1100, with multiple logic chips mounted thereon. A first logic chip among the logic chips that corresponds to the active interposer may perform the function of transmitting signals between the first substrate 1100 and a second logic chip disposed thereon while still functioning as the logic chip.

[0069] According to another embodiment, the second substrate 1200 may be a passive interposer. For example, the second substrate 1200 may perform a signal relay function between the semiconductor device 1300 and the first substrate 1100. That is, the number of terminals in the semiconductor device 1300 is gradually increasing due to factors such as 5G, Internet of Things (IoT), improved image quality, and increased communication speed. That is, as the number of terminals provided on the semiconductor device 1300 increases, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first substrate 1100 is connected to a main board of an electronic device. Therefore, in order for the electrodes provided on the first substrate 1100 to have the width and spacing required to be connected to the semiconductor device 1300 and the main board, respectively, the thickness of the first substrate 1100 increases or the layer structure of the first substrate 1100 becomes complex. Therefore, in the first embodiment, the second substrate 1200 is disposed on the first substrate 1100 and the semiconductor device 1300. The second substrate 1200 may include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor device 1300 .

[0070] The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processing unit (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processing unit (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific integrated circuit (ASIC), or the like, or a chipset including a specific combination of the above. The memory chip may be a stacked memory such as HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0071] Meanwhile, the second substrate 1200 may include at least one cavity, and the semiconductor device 1300 may be disposed in the cavity of the second substrate 1200.

[0072] On the other hand, the semiconductor package of the first embodiment can include a connecting member.

[0073] For example, the semiconductor package includes a first connection member 1410 disposed between a first substrate 1100 and the second substrate 1200. The first connection member 1410 couples the second substrate 1200 to the first substrate 1100 and electrically connects them.

[0074] For example, the semiconductor package may include a second connection member 1420 disposed between the second substrate 1200 and the semiconductor device 1300. The second connection member 1420 may electrically connect the semiconductor device 1300 to the second substrate 1200 while mounting the semiconductor device 1300 on the second substrate 1200.

[0075] The semiconductor package includes a third connection member 1430 disposed on the lower surface of the first substrate 1100. The third connection member 1430 may couple the first substrate 1100 to a main board and electrically connect them.

[0076] In this case, the first connecting member 1410, the second connecting member 1420, and the third connecting member 1430 can electrically connect the multiple components using at least one bonding method of wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connecting member 1410, the second connecting member 1420, and the third connecting member 1430 have the function of electrically connecting the multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as the electrically connected part, not the solder or wire.

[0077] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material including at least one of Sn, Ag, and Cu. The inter-metal direct bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between multiple components without using materials such as solder, wire, or conductive adhesive. The inter-metal direct bonding method may refer to a bonding method using the second connection member 1420. In this case, the second connection member 1420 may refer to a metal layer formed between multiple components through the recrystallization.

[0078] Specifically, the first connecting member 1410, the second connecting member 1420, and the third connecting member 1430 may be bonded to each other using a TC (Terminal Compression) bonding method. The TC bonding method may refer to a method of bonding the first connecting member 1410, the second connecting member 1420, and the third connecting member 1430 by applying heat and pressure to them.

[0079] In this case, a protrusion may be disposed on an electrode on which the first connecting member 1410, the second connecting member 1420, and the third connecting member 1430 are disposed in at least one of the first substrate 1100 and the second substrate 1200. The protrusion may protrude outward from the first substrate 1100 or the second substrate 1200.

[0080] The protrusion may refer to a bump. The protrusion may refer to a post. The protrusion may refer to a pillar. Preferably, the protrusion may refer to an electrode of the second substrate 1200 on which a second connection member 1420 for coupling with the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, short circuits may occur between the second connection members 1420 respectively connected to the terminals of the semiconductor device 1300. Therefore, in this embodiment, a protrusion is included in the electrode of the second substrate 1200 on which the second connection member 1420 is disposed to reduce the volume of the second connection member 1420. The protrusion may improve the alignment between the electrode of the second substrate 1200 and the terminal of the semiconductor device 1300 and prevent the second connection member 1420 from spreading.

[0081] 1b, the semiconductor package of the second embodiment may differ from the semiconductor package of the first embodiment in that a connecting substrate 1210 is disposed on the second substrate 1200. The connecting substrate 1210 may be referred to as a bridge substrate. For example, the connecting substrate 1210 may include a redistribution layer.

[0082] In one embodiment, the connecting substrate 1210 may be a silicon bridge, that is, the connecting substrate 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

[0083] In another embodiment, the connecting substrate 1210 may be an organic bridge. For example, the connecting substrate 1210 may include an organic material. For example, the connecting substrate 1210 may include an organic substrate containing an organic material instead of the silicon substrate.

[0084] The connecting substrate 1210 may be embedded in the second substrate 1200, but is not limited thereto. For example, the connecting substrate 1210 may be disposed on the second substrate 1200 to have a protruding structure.

[0085] Preferably, the second substrate 1200 may include a cavity, and the connecting substrate 1210 may be disposed within the cavity of the second substrate 1200 .

[0086] The connection substrate 1210 may horizontally connect a plurality of semiconductor devices disposed on the second substrate 1200 .

[0087] 1c, the semiconductor package of the third embodiment may include a second substrate 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment may have a structure in which the first substrate 1100 is removed, compared to the semiconductor package of the second embodiment.

[0088] That is, the second substrate 1200 of the third embodiment can function as both an interposer and a package substrate.

[0089] The first connecting member 1410 disposed on the lower surface of the second substrate 1200 can couple the second substrate 1200 to a main board of an electronic device.

[0090] Referring to FIG. 1 d, the semiconductor package of the fourth embodiment includes a first substrate 1100 and a semiconductor device 1300 .

[0091] In this case, the semiconductor package of the fourth embodiment may have a structure in which the second substrate 1200 is removed, compared to the semiconductor package of the second embodiment.

[0092] That is, the first substrate 1100 of the fourth embodiment can function as an interposer connecting the semiconductor device 1300 and a main board while functioning as a package substrate. To this end, the first substrate 1100 can include a connecting substrate 1110 for connecting the plurality of semiconductor devices. The connecting substrate 1110 can be a silicon bridge or an organic bridge for connecting the plurality of semiconductor devices.

[0093] Referring to FIG. 1e, the semiconductor package of the fifth embodiment further includes a third semiconductor element 1330 compared to the semiconductor package of the fourth embodiment.

[0094] For this purpose, a fourth connection member 1440 may be disposed on the lower surface of the first substrate 1100.

[0095] A third semiconductor element 1330 may be disposed on the fourth connecting member 1440. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0096] In this case, the third semiconductor device 1330 may have a structure in which it is disposed on the lower surface of the second substrate 1200 in the semiconductor package of FIG. 1c.

[0097] Referring to FIG. 1f, the semiconductor package of the sixth embodiment may include a first substrate 1100.

[0098] A first semiconductor device 1310 may be disposed on the first substrate 1100. To this end, a first connection member 1410 may be disposed between the first substrate 1100 and the first semiconductor device 1310.

[0099] The first substrate 1100 may also include a conductive coupling part 1450. The conductive coupling part 1450 may further protrude from the first substrate 1100 toward the second semiconductor device 1320. The conductive coupling part 1450 may be referred to as a bump, or alternatively, as a post. The conductive coupling part 1450 may be disposed to have a protruding structure on an electrode disposed on the top side of the first substrate 1100.

[0100] A second semiconductor device 1320 is disposed on the conductive coupling part 1450 of the first substrate 1100. In this case, the second semiconductor device 1320 may be connected to the first substrate 1100 via the conductive coupling part 1450. In addition, a second connection member 1420 may be disposed on the first semiconductor device 1310 and the second semiconductor device 1320.

[0101] Thus, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 via the second connection member 1420 .

[0102] That is, the second semiconductor device 1320 may be connected to the first substrate 1100 through the conductive coupling part 1450 and also connected to the first semiconductor device 1310 through the second connecting member 1420 .

[0103] At this time, the second semiconductor device 1320 may receive a power signal and / or power through the conductive coupling part 1450. In addition, the second semiconductor device 1320 may transmit and receive communication signals to and from the first semiconductor device 1310 through the second connecting member 1420.

[0104] The semiconductor package of the sixth embodiment may be able to supply sufficient power for driving the second semiconductor device 1320 by supplying a power signal to the second semiconductor device 1320 via the conductive coupling part 1450. As a result, the embodiment may improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment may solve the problem of insufficient power supplied to the second semiconductor device 1320. Furthermore, the embodiment may provide the power signal and the communication signal of the second semiconductor device 1320 via different paths via the conductive coupling part 1450 and the second connecting member 1420. As a result, the embodiment may solve the problem of loss of the communication signal due to the power signal. For example, the embodiment may minimize mutual interference between the power signal and the communication signal.

[0105] Meanwhile, in the sixth embodiment, the second semiconductor device 1320 may be disposed on the first substrate 1100 with a POP structure. For example, the second semiconductor device 1320 may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling part 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

[0106] Meanwhile, the semiconductor package according to the sixth embodiment may include a molding member 1460. The molding member 1460 may be disposed between the first substrate 1100 and the second semiconductor element 1320. For example, the molding member 1460 may mold the first connecting member 1410, the second connecting member 1420, the first semiconductor element 1310, and the conductive coupling member 1450.

[0107] Referring to FIG. 1g, the semiconductor package of the seventh embodiment may include a first substrate 1100, a first connecting member 1410, a second connecting member 1420, a semiconductor element 1300, and a third connecting member 1430.

[0108] The semiconductor package of the seventh embodiment may differ from the semiconductor package of the fourth embodiment in that the connecting substrate 1110 is omitted and the first substrate 1100 includes a plurality of substrate layers.

[0109] The first substrate 1100 may include multiple substrate layers, for example, a first substrate layer 1100A corresponding to a package substrate and a second substrate layer 1100B corresponding to a redistribution layer of a connection substrate.

[0110] That is, in this embodiment, the first substrate 1100 can be configured by disposing a second substrate layer 1100B corresponding to the redistribution layer on a first substrate layer 1100A.

[0111] In other words, the semiconductor package of the seventh embodiment may include a first substrate layer 1100A and a second substrate layer 1100B formed integrally. The material of the insulating layer of the second substrate layer 1100B may be different from the material of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second substrate layer 1100B may include a photo-curable material. For example, the second substrate layer 1100B may be a photo-imageable dielectric (PID). Furthermore, the second substrate layer 1100B may include a photo-curable material, thereby enabling miniaturization of electrodes. Therefore, in the seventh embodiment, the second substrate layer 1100B may be formed by sequentially stacking insulating layers of a photo-curable material on the first substrate layer 1100A and forming miniaturized electrodes on the insulating layers of the photo-curable material. In this way, the second substrate 1100B may be a redistribution layer including miniaturized electrodes.

[0112] -Circuit board-

[0113] The circuit board of the embodiment will be described below.

[0114] FIG. 2 is a cross-sectional view showing the circuit board of the first embodiment, FIG. 3 is a plan view showing the first insulating layer and the first circuit pattern layer in the circuit board of FIG. 2, FIG. 4 is a plan view of the circuit board of FIG. 3 with some components removed, FIG. 5 is a cross-sectional view cut along the A-A' direction in FIGS. 3 and 4, FIG. 6 is an optical microscope photograph of the actual product corresponding to FIG. 5, and FIG. 7 is a cross-sectional view cut along the B-B' direction in FIGS. 3 and 4.

[0115] Before describing the circuit board of the embodiment, the circuit board described below may refer to any one of a plurality of boards included in the semiconductor package.

[0116] Preferably, the circuit board in one embodiment described below may be any one of the first substrate 1100 and the second substrate 1200 included in the semiconductor package, and at least one of the first substrate 1100 and the second substrate 1200 may include a cavity described below.

[0117] At this time, a connecting member may be disposed in the cavity.

[0118] When the circuit board is the first board 1100, the connecting member may be any one of a connecting board, a second board, and a semiconductor device.

[0119] Also, when the circuit board is the second board 1200, the connecting member may be one of a semiconductor device and a connecting board.

[0120] 2, the circuit board of the embodiment includes multiple insulating layers, each of which may have a single layer structure, or may be composed of multiple layers.

[0121] Specifically, the circuit board may include a first insulating layer 111 and a second insulating layer 112 .

[0122] In this case, the first insulating layer 111 may have a single layer structure as shown in FIG. 2, or alternatively, may have a multi-layer structure.

[0123] A second insulating layer 112 is disposed on the first insulating layer 111. The second insulating layer 112 may have a single-layer structure, or alternatively, may have a multi-layer structure. The second insulating layer 112 includes a cavity 150. When the second insulating layer 112 has a multi-layer structure, the cavity 150 may penetrate the multi-layer structure.

[0124] However, for the sake of convenience, the following description will be given assuming that the first insulating layer 111 and the second insulating layer 112 each have a single-layer structure.

[0125] In one embodiment, the first insulating layer 111 and the second insulating layer 112 may comprise the same insulating material as each other.

[0126] In another embodiment, the first insulating layer 111 and the second insulating layer 112 may contain different insulating materials. In this case, when the first insulating layer 111 has a multi-layer structure, the first insulating layers may all contain the same insulating material, or may alternatively contain different insulating materials. In addition, when the second insulating layer 112 has a multi-layer structure, the second insulating layers may all contain the same insulating material, or may alternatively contain different insulating materials.

[0127] At least one of the first insulating layer 111 and the second insulating layer 112 may be rigid or flexible. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include glass or plastic. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include reinforced or ductile plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 110 of the substrate 100 may include an optically isotropic film. For example, at least one of the first insulating layer 111 and the second insulating layer 112 may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, at least one of the first insulating layer 111 and the second insulating layer 112 may have a structure in which inorganic filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0128] Specifically, in one embodiment, the first insulating layer 111 may be a core layer containing reinforcing fibers, and the second insulating layer 112 may not contain reinforcing fibers, so the circuit board may be a core board.

[0129] In other embodiments, the circuit board may be a coreless substrate that does not include a core layer.

[0130] In one embodiment, the first insulating layer 111 and the second insulating layer 112 may include an organic material that is easy to process and has excellent rigidity, allowing for slimming of the circuit board and miniaturization of the circuit pattern layer, and does not include a reinforcing material. The reinforcing material may also be referred to as reinforcing fiber or glass fiber.

[0131] For example, the first insulating layer 111 and the second insulating layer 112 may be made of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), BT, or the like.

[0132] In this case, if the first insulating layer 111 and the second insulating layer 112 of the circuit board are made of ABF (Ajinomoto Build-up Film), the warpage characteristics of the circuit board may be reduced.

[0133] Therefore, in another embodiment, the first insulating layer 111 and the second insulating layer 112 are made of ABF (Ajinomoto Build-up Film), and at least one of the ABFs constituting the multiple insulating layers of the circuit board may contain a reinforcing material that can improve warpage characteristics.

[0134] For example, the circuit board may include a layer made of a first ABF and a layer made of a second ABF, which is an ABF that further contains a reinforcing material. In this case, the reinforcing material contained in the second ABF may be glass fiber or may include a GCP (Glass Core Primer) material, but is not limited thereto.

[0135] Meanwhile, in this embodiment, a cavity 150 is provided in the second insulating layer 112, and an electrode pattern such as a trace is disposed in an area exposed through the cavity 150. In this case, if the second insulating layer 112 including the cavity 150 contains a photocurable resin, there may be no significant restrictions on the arrangement of the electrode pattern.

[0136] This is because the photo-curable resin allows the formation of a cavity through an exposure and development process, eliminating the need for a stopper, which is required in the cavity formation process.

[0137] However, if the second insulating layer 112 contains a photocurable resin, the adhesion between the insulating layers of the circuit board may be reduced. Specifically, if all of the insulating layers included in the circuit board are made of a photocurable resin, the rigidity of the circuit board may be reduced, thereby significantly reducing warpage characteristics. Furthermore, if the first insulating layer 111 is made of a thermosetting resin and the second insulating layer 112 is made of a photocurable resin, the adhesion between the thermosetting resin and the photocurable resin may be reduced due to the physical properties of the photocurable resin. That is, the photocurable resin has a higher cure shrinkage rate than a thermosetting resin. Furthermore, the content of ceramic particles such as SiO2 in the photocurable resin is higher than the content of ceramic particles in the thermosetting resin. Due to these differences in physical properties, the adhesion between the thermosetting resin and the photocurable resin may be reduced.

[0138] Furthermore, when the first insulating layer 111 and the second insulating layer 112 both contain a thermosetting resin, it is difficult to arrange an electrode pattern in the area exposed through the cavity 150. That is, a stopper must be included to form the cavity 150. When an electrode pattern is arranged in the area exposed through the cavity 150, a problem of short circuit occurs in which a plurality of electrode patterns are electrically connected by the stopper. Therefore, when a cavity is provided in a thermosetting resin, it has been difficult to arrange an electrode pattern in the area exposed through the cavity in the related art.

[0139] In contrast, in the embodiment, the second insulating layer 112 includes a thermosetting resin, and pads and electrode patterns connected to the pads can be disposed in the area exposed through the cavity 150 of the second insulating layer 112. This will be described in more detail below.

[0140] The first insulating layer 111 and the second insulating layer 112 may each have a thickness in the range of 10 μm to 60 μm. For example, the first insulating layer 111 and the second insulating layer 112 may each have a thickness in the range of 15 μm to 55 μm. For example, the first insulating layer 111 and the second insulating layer 112 may each have a thickness in the range of 20 μm to 50 μm. If the thickness of the first insulating layer 111 and the second insulating layer 112 is less than 10 μm, the circuit pattern layer included in the circuit board may not be stably protected. If the thickness of the first insulating layer 111 and the second insulating layer 112 exceeds 60 μm, the overall thickness of the circuit board may increase. Furthermore, if the thickness of the first insulating layer 111 and the second insulating layer 112 exceeds 60 μm, the thickness of the circuit pattern layer and the through electrode also increases accordingly, which may increase the loss of signals transmitted through the circuit pattern.

[0141] In this case, the thicknesses of the first insulating layer 111 and the second insulating layer 112 can correspond to the distance in the thickness direction between the circuit pattern layers arranged on different layers.

[0142] For example, the thickness of the first insulating layer 111 may refer to the vertical distance between the lower surface of the first circuit pattern layer 121 and the upper surface of the third circuit pattern layer 123. For example, the thickness of the second insulating layer 112 may refer to the vertical linear distance in the thickness direction between the upper surface of the first circuit pattern layer 121 and the lower surface of the second circuit pattern layer 122.

[0143] The second insulating layer 112 may include a cavity 150. The cavity 150 may penetrate the upper and lower surfaces of the second insulating layer 112.

[0144] The cavity 150 may include a bottom surface 150-1 adjacent to the lower surface of the second insulating layer 112. In this case, the cavity 150 penetrates the second insulating layer 112. Therefore, the bottom surface 150-1 of the cavity 150 may be a part of the upper surface of the first insulating layer 111 that vertically overlaps the cavity 150.

[0145] The cavity 150 may include a sidewall 150-2 extending at a slope from the bottom surface 150-1 toward the upper surface of the second insulating layer 112. The sidewall 150-2 may have a slope such that the width of the cavity 150 increases from the lower surface of the second insulating layer 112 toward the upper surface of the second insulating layer 112. However, the embodiment is not limited thereto. For example, the sidewall 150-2 may have a slope such that the width of the cavity 150 decreases from the lower surface of the second insulating layer 112 toward the upper surface of the second insulating layer 112. Furthermore, although the drawings illustrate the sidewall 150-2 as having one slope, the invention is not limited thereto. For example, the sidewall 150-2 may include at least one inflection portion, and the inflection portions may be inclined with different slopes.

[0146] The cavity 150 may include a recess 150-3 extending from a lower end of a sidewall 150-2 connected to the bottom surface 150-1 in a direction away from the cavity 150. For example, the recess 150-3 may be recessed inward from a lower end of the sidewall 150-2 of the second insulating layer 112 constituting the cavity 150 toward the second insulating layer 112. Therefore, the recess 150-3 may also be referred to as an undercut, a cavity extension region, or a depression.

[0147] The recess 150-3 is located adjacent to the frame region of the bottom surface 150-1. The recess 150-3 may be connected to the bottom surface 150-1. Therefore, the region of the top surface of the first insulating layer 111 that vertically overlaps with the recess 150-3 may not be covered with the second insulating layer 112.

[0148] The recess 150-3 may be provided in a peripheral region of the bottom surface 150-1 along a peripheral direction of the bottom surface 150-1. For example, the bottom surface 150-1 may refer to a region of the upper surface of the first insulating layer 111 that vertically overlaps the cavity 150 but does not vertically overlap the first circuit pattern layer 121. The recess 150-3 may be provided entirely along the peripheral direction of the bottom surface 150-1.

[0149] Accordingly, the first insulating layer 111 may be divided into a plurality of regions based on the horizontal direction. For example, the first insulating layer 111 may include a first region R1 that vertically overlaps the cavity 150. In this case, if the cavities 150 have different widths in the thickness direction of the second insulating layer 112, the first region R1 may refer to a region that vertically overlaps a lower region of the cavity 150 corresponding to a lower end of the sidewall 150-2.

[0150] In addition, the first insulating layer 111 may include a second region R2 that does not vertically overlap the cavity 150. The second region R2 may refer to a region of the top surface of the first insulating layer 111 that is covered with the second insulating layer 112.

[0151] The first insulating layer 111 may also include a third region R3 between the first region R1 and the second region R2. The third region R3 may refer to a boundary region between the first region R1 and the second region R2. Preferably, the third region R3 may refer to a region that vertically overlaps the recess 150-3.

[0152] On the other hand, on the surfaces of the first insulating layer 111 and the second insulating layer 112, a circuit pattern layer is disposed.

[0153] For example, a first circuit pattern layer 121 may be disposed between the upper surface of the first insulating layer 111 and the lower surface of the second insulating layer 112. For example, a second circuit pattern layer 122 may be disposed on the upper surface of the second insulating layer 112. For example, a third circuit pattern layer 123 may be disposed on the lower surface of the first insulating layer 111.

[0154] In the first embodiment, the first circuit pattern layer 121 may be disposed on the first insulating layer 111. For example, the first circuit pattern layer 121 may protrude above the top surface of the first insulating layer 111.

[0155] The second circuit pattern layer 122 may protrude above the upper surface of the second insulating layer 112. The second circuit pattern layer 122 may refer to an uppermost circuit pattern layer disposed on the uppermost side of a circuit board.

[0156] The third circuit pattern layer 123 may protrude below the lower surface of the first insulating layer 111. The third circuit pattern layer 123 may refer to a lowermost circuit pattern layer disposed at the bottom of a circuit board.

[0157] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each include pads and traces (or electrode patterns) according to their functions. The pads may be mounting pads on which elements or chips are mounted, or terminal pads connected to an external substrate. The traces may be long signal wiring lines connecting multiple pads. The traces are fine patterns having a width smaller than that of the pads. For example, in an embodiment, the spacing between multiple traces may be in the range of 2 μm to 15 μm, and the line width of each trace may be in the range of 2 μm to 15 μm.

[0158] The circuit pattern layers may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The circuit pattern layers may also be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0159] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 25 μm. For example, the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 23 μm. The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 may each have a thickness in the range of 10 μm to 20 μm.

[0160] If the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is less than 10 μm, the resistance of the circuit pattern increases, which can reduce signal transmission efficiency. For example, if the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is less than 10 μm, signal transmission loss can increase. For example, if the thickness of each of the first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 is more than 25 μm, the line width of the circuit pattern increases, which can increase the overall volume of the circuit board.

[0161] The first circuit pattern layer 121, the second circuit pattern layer 122, and the third circuit pattern layer 123 can be formed using conventional printed circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0162] The first circuit pattern layer 121 may include a plurality of pads and electrode patterns.

[0163] The first circuit pattern layer 121 may include a first pad 121-1 disposed on the first region R1 of the first insulating layer 111. The first pad 121-1 may vertically overlap the cavity 150. Therefore, the first pad 121-1 may not be in contact with the second insulating layer 112.

[0164] The first circuit pattern layer 121 may include a second pad 121-2 disposed on the second region R2 of the first insulating layer 111. The second pad 121-2 may vertically overlap the cavity 150. Therefore, the second pad 121-2 may not be in contact with the second insulating layer 112.

[0165] The first circuit pattern layer 121 may include the electrode pattern 121-3, which may be disposed in the first region R1, the second region R2, and the third region R3 of the first insulating layer 111.

[0166] In this case, the first circuit pattern layer 121 may include a plurality of electrode patterns, and the electrode pattern 121-3 may refer to an electrode pattern directly connected to the first pad 121-1 among the plurality of electrode patterns.

[0167] The electrode pattern 121-3 may directly connect the first pad 121-1 arranged in the first region R1 and the second pad 121-2 arranged in the second region R2. That is, in the embodiment, a cavity 150 is formed in the second insulating layer 112 containing the thermosetting resin, and the electrode pattern 121-3 is arranged on the upper surface of the first insulating layer 111 exposed through the formed cavity 150. As a result, in the embodiment, the first pad 121-1 in the first region R1 and the second pad 121-2 in the second region R2 may be directly connected to each other by the electrode pattern 121-3 on the upper surface of the first insulating layer 111. Therefore, in the embodiment, the first insulating layer 111 and the second insulating layer 112 contain a thermosetting resin, thereby improving adhesion between multiple insulating layers of a circuit board. Furthermore, in the embodiment, the adhesion can be improved and the circuit integration density can be improved. That is, in the conventional case where a cavity is provided in a thermosetting resin, the first pad 121-1 and the second pad 121-2 are connected to each other via at least one through electrode. This increases the signal transmission distance between the first pad 121-1 and the second pad 121-2, resulting in increased signal transmission loss. In contrast, in the embodiment, the first pad 121-1 and the second pad 121-2 are directly connected to each other using the electrode pattern 121-3 without the through electrode. Therefore, the embodiment can reduce the signal transmission distance and minimize the resulting signal transmission loss. As a result, the embodiment can improve the electrical reliability of the circuit board.

[0168] At this time, at least a portion of the electrode pattern 121-3 is connected to the recess 150-3. Here, being connected to the recess 150-3 may mean that the recess 150-3 and the electrode pattern 121-3 overlap with each other in the frame direction. For example, the recess 150-3 vertically overlaps the third region R3 of the first insulating layer 111. The electrode pattern 121-3 includes a portion disposed in the third region R3. At this time, a side surface of the portion of the electrode pattern 121-3 disposed in the third region R3 may be exposed through the recess 150-3. For example, at this time, the side surface of the portion of the electrode pattern 121-3 disposed in the third region R3 may not be covered by the second insulating layer 112 through the recess 150-3.

[0169] Meanwhile, in one embodiment, the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 may have the same thickness.

[0170] In another embodiment, at least one of the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 may have a thickness different from that of the other pads. For example, the thickness of the first pad 121-1 may be different from the thickness of the second pad 121-2. For example, the thickness of the first pad 121-1 may be smaller than the thickness of the second pad 121-2. This may be because the etching amount of the seed layer of the first pad 121-1 is greater than the etching amount of the seed layer of the second pad 121-2. That is, the first pad 121-1 and the second pad 121-2 include seed layers of the same thickness. The thicknesses of the first pad 121-1 and the second pad 121-2 may be reduced during the seed layer etching process. In this case, the seed layer etching process of the first pad 121-1 is performed simultaneously with the etching process of the stopper corresponding to the recess 150-3. In this embodiment, the stopper may be etched with a relatively large etching amount to prevent the stopper from remaining during the stopper etching process, and thus the thickness of the first pad 121-1 may be smaller than the thickness of the second pad 121-2.

[0171] The circuit board according to the embodiment includes a through electrode, which may also be referred to as a "via," and may serve to electrically connect circuit pattern layers disposed on different layers.

[0172] The through electrodes penetrate the first insulating layer 111 and the second insulating layer 112 included in the circuit board, thereby electrically connecting circuit patterns arranged on different layers. In this case, the through electrodes may be formed to penetrate only one insulating layer, or alternatively, may be formed to commonly penetrate at least two or more insulating layers.

[0173] For example, the circuit board includes a first through electrode 131. The first through electrode 131 may be formed to penetrate the first insulating layer 111. The first through electrode 131 may electrically connect the first circuit pattern layer 121 and the third circuit pattern layer 123. For example, an upper surface of the first through electrode 131 may be directly connected to a lower surface of the first circuit pattern layer 121. For example, a lower surface of the first through electrode 131 may be directly connected to the third circuit pattern layer 123.

[0174] Accordingly, the first circuit pattern layer 121 and the third circuit pattern layer 123 are electrically connected to each other through the first through electrodes 131, thereby transmitting signals.

[0175] For example, the circuit board includes a second through-hole electrode 132. The second through-hole electrode 132 may be formed to penetrate the second insulating layer 112. The second through-hole electrode 132 may electrically connect the first circuit pattern layer 121 and the second circuit pattern layer 122. For example, a lower surface of the second through-hole electrode 132 may be directly connected to the first circuit pattern layer 121. For example, an upper surface of the second through-hole electrode 132 may be directly connected to the second circuit pattern layer 122. As a result, the first circuit pattern layer 121 and the second circuit pattern layer 122 may be directly electrically connected to each other through the second through-hole electrode 132, thereby transmitting signals.

[0176] The first through electrode 131 and the second through electrode 132 can be formed by forming through holes that penetrate the first insulating layer 111 and the second insulating layer 112, and filling the inside of the formed through holes with a conductive material.

[0177] The through holes may be formed by any one of mechanical, laser, and chemical processing. When the through holes are formed by mechanical processing, methods such as milling, drilling, and routing may be used. When the through holes are formed by laser processing, methods such as UV or CO2 laser may be used. When the through holes are formed by chemical processing, at least one of the insulating layers may be opened using a chemical containing aminosilane, ketones, etc.

[0178] After the through holes are formed, the insides of the through holes may be filled with a conductive material to form the first through electrodes 131 and the second through electrodes 132. The metal material forming the first through electrodes 131 and the second through electrodes 132 may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductive material may be filled by any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing, and dispensing.

[0179] Meanwhile, the circuit board of the embodiment may include a first protective layer 141 and a second protective layer 142. The first protective layer 141 and the second protective layer 142 may be disposed on the outermost side of the circuit board.

[0180] For example, the first protective layer 141 may be disposed on the first outermost or bottom side of the circuit board, for example, on the lower surface of the first insulating layer 111.

[0181] For example, the second protective layer 142 may be disposed on the second outermost or uppermost side of the circuit board. For example, the second protective layer 142 may be disposed on the top surface of the second insulating layer 112.

[0182] The first protective layer 141 may include at least one opening (not shown). For example, the first protective layer 141 may include an opening that vertically overlaps at least one of the third circuit pattern layers 123. For example, the first protective layer 141 may include an opening that vertically overlaps a terminal pad (not shown) of the third circuit pattern layer 123 on which a conductive coupling portion for connection to an external board is disposed.

[0183] The second protective layer 142 may include at least one opening (not shown). For example, the second protective layer 142 may include an opening that vertically overlaps at least one of the second circuit pattern layers 122. For example, the second protective layer 142 may include an opening that vertically overlaps a terminal pad (not shown) of the second circuit pattern layer 122 on which a conductive coupling portion for connection to a memory substrate or an interposer substrate is disposed. The second protective layer 142 may also include a through-hole (not shown) that vertically overlaps the cavity 121 of the second insulating layer 112.

[0184] The first and second protective layers 141 and 142 may include an insulating material. The first and second protective layers 141 and 142 may include various materials that can be applied and then heated and cured to protect the surfaces of the insulating layer and the circuit pattern layer. The first and second protective layers 141 and 142 may be resist layers. For example, the first and second protective layers 141 and 142 may be solder resist layers including an organic polymer material. For example, the first and second protective layers 141 and 142 may include an epoxy acrylate resin. In particular, the first and second protective layers 141 and 142 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first and second protective layers 141 and 142 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0185] The first protective layer 141 and the second protective layer 142 may have a thickness of 1 μm to 20 μm. The first protective layer 141 and the second protective layer 142 may have a thickness of 1 μm to 15 μm. For example, the first protective layer 141 and the second protective layer 142 may have a thickness of 5 μm to 20 μm. If the thickness of the first protective layer 141 and the second protective layer 142 exceeds 20 μm, the thickness of the circuit board may increase. If the thickness of the first protective layer 141 and the second protective layer 142 is less than 1 μm, the circuit pattern layer included in the circuit board may not be stably protected, which may reduce electrical reliability or physical reliability.

[0186] At this time, although not shown in the drawings, a surface treatment layer (not shown) may be disposed in the openings of the first protective layer 141 and the second protective layer 142 that vertically overlap the second circuit pattern layer 122 and the third circuit pattern layer 123. The surface treatment layer may be formed to improve soldering characteristics while preventing corrosion and oxidation of the surfaces of the third circuit pattern layer 123 that vertically overlaps the openings of the first protective layer 141 and the second circuit pattern layer 122 that vertically overlaps the openings of the second protective layer 142.

[0187] The surface treatment layer may be an organic solderability preservative (OSP) layer. For example, the surface treatment layer may be an organic layer formed of an organic substance such as benzimidazole.

[0188] However, embodiments are not limited thereto. For example, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer.

[0189] The structure of the cavity 150 of the embodiment and the resulting arrangement of the first circuit pattern layer 121 will be described in more detail below.

[0190] 3, a first circuit pattern layer 121 may be disposed on the first insulating layer 111. As described above, the first circuit pattern layer 121 may include a first pad 121-1, a second pad 121-2, and an electrode pattern 121-3.

[0191] The first pad 121-1 may be disposed in a first region R1 that vertically overlaps the cavity 150.

[0192] The second pad 121-2 may be disposed in a second region R2 that does not overlap the cavity 150 vertically.

[0193] Furthermore, the electrode pattern 121-3 may be disposed on the first region R1, the second region R2, and the third region R3. The electrode pattern 121-3 may directly connect the first pad 121-1 and the second pad 121-2 on the first insulating layer 111. For example, one end of the electrode pattern 121-3 may be directly connected to the first pad 121-1, and the other end of the electrode pattern 121-3 may be directly connected to the second pad 121-2.

[0194] Although the drawings show six first pads 121-1, six second pads 121-2, and six electrode patterns 121-3, the number of each may be, but is not limited to, five or fewer or seven or more. The numbers of first pads 121-1, second pads 121-2, and electrode patterns 121-3 may differ from one another. Therefore, at least one of the first pads 121-1 may not be directly connected to the second pad 121-2.

[0195] 4, a second insulating layer 112 may be disposed on the first insulating layer 111. The second insulating layer 112 may include a cavity 150. The cavity 150 may penetrate the second insulating layer 112.

[0196] Therefore, the first pad 121-1 does not have to overlap vertically with the second insulating layer 112. For example, the first pad 121-1 may overlap vertically with the cavity 150.

[0197] Also, the second pad 121-2 may vertically overlap the second insulating layer 112. For example, the second pad 121-2 does not have to vertically overlap the cavity 150.

[0198] Meanwhile, the electrode pattern 121-3 may be divided into a plurality of parts according to its position, where the division into a plurality of parts may mean that one electrode pattern directly connecting one first pad and one second pad is divided into a plurality of parts.

[0199] The electrode pattern 121-3 may include a first portion 121-31 that vertically overlaps the cavity 150 and is connected to the first pad 121-1. The first portion 121-31 of the electrode pattern 121-3 may not vertically overlap the second insulating layer 112. For example, the first portion 121-31 of the electrode pattern 121-3 may not be covered by the second insulating layer 112.

[0200] In addition, the electrode pattern 121-3 may include a second portion 121-32 that vertically overlaps the second insulating layer 112. The second portion 121-32 of the electrode pattern 121-3 does not have to vertically overlap the cavity 150. For example, the second portion 121-32 of the electrode pattern 121-3 may be covered with the second insulating layer 112.

[0201] The electrode pattern 121-3 may further include a third portion 121-33 between the first portion 121-31 and the second portion 121-32.

[0202] The third portion 121-33 of the electrode pattern 121-3 may refer to a portion adjacent to a periphery region of the bottom surface 150-1 of the cavity 150. For example, the third portion 121-33 of the electrode pattern 121-3 may refer to a portion located in a boundary region of the cavity 150. For example, the third portion 121-33 of the electrode pattern 121-3 may refer to a portion located adjacent to the recess 150-3. For example, the third portion 121-33 of the electrode pattern 121-3 may refer to a portion located in a third region R3, which is a boundary region between the first region R1 and the second region R2.

[0203] Meanwhile, the recess 150-3 may be provided in a frame region of the bottom surface 150-1 along a frame direction of the bottom surface 150-1. For example, the recess 150-3 may be recessed inwardly of the second insulating layer 112 at a lower end of the sidewall 150-2 adjacent to the frame region of the bottom surface 150-1. In summary, the lower end of the sidewall 150-2 of the second insulating layer 112 constituting the cavity 150 may be provided with a recess 150-3 recessed inwardly along the frame direction of the bottom surface 150-1.

[0204] In this case, although the drawing shows that the recess 150-3 is not provided in the area of the lower end of the sidewall 150-2 that vertically overlaps with the electrode pattern 121-3, this is not limiting. This will be described as follows.

[0205] Referring to FIGS. 5 to 7, the first circuit pattern layer 121 includes a plurality of metal layers.

[0206] The first circuit pattern layer 121 includes a first metal layer 121a disposed on the first insulating layer 111. The first metal layer 121a may serve as a seed layer for electroplating a second metal layer 121b of the first circuit pattern layer 121.

[0207] For example, the first metal layer 121a may be a chemical copper plating layer, or may be a copper foil layer (Cu foil).

[0208] In an embodiment, the first metal layer 121a may include only one of the chemical copper plating layer and the copper foil layer.

[0209] In another embodiment, the first metal layer 121a may include both the chemical copper plating layer and the copper foil layer.

[0210] The thickness T1 of the first metal layer 121a may be in the range of 1.0 μm to 4.0 μm. Preferably, the thickness T1 of the first metal layer 121a may be in the range of 1.2 μm to 3.5 μm. More preferably, the thickness T1 of the first metal layer 121a may be in the range of 1.5 μm to 3.0 μm.

[0211] If the thickness T1 of the first metal layer 121a is less than 1.0 μm, the first metal layer 121a may not function as a seed layer. If the thickness T1 of the first metal layer 121a is less than 1.0 μm, it may be difficult to form the first metal layer 121a with a uniform thickness on the upper surface of the first insulating layer 111.

[0212] If the thickness T1 of the first metal layer 121a exceeds 4.0 μm, the time required to etch the first metal layer 121a may increase. If the thickness T1 of the first metal layer 121a exceeds 4.0 μm, deformation of the second metal layer 121b may occur during etching of the first metal layer 121a. Deformation of the second metal layer 121b may mean that the side portions of the first metal layer 121a are also etched, increasing the difference between the width of the upper surface and the width of the lower surface of the second metal layer 121b. Furthermore, if the thickness T1 of the first metal layer 121a exceeds 4.0 μm, the reliability of the etching process of the first metal layer 121a, which is used as a stopper in the cavity formation process, may decrease. For example, a portion of the first metal layer 121a is used as a stopper in the cavity formation process. The first metal layer 121a used as the stopper is removed after the formation of the cavity 150 is completed. In this case, if the thickness T1 of the first metal layer 121a exceeds 4.0 μm, a portion of the stopper corresponding to the recess 150-3 may not be removed during the stopper etching process. If a portion of the stopper is not removed, an electrical short circuit problem may occur in which adjacent electrode patterns are connected to each other by the stopper.

[0213] A second metal layer 121b is disposed on the first metal layer 121a. The second metal layer 121b may be an electroplated layer formed by electroplating using the first metal layer 121a as a seed layer.

[0214] The thickness T2 of the second metal layer 121b may correspond to a value obtained by subtracting the thickness of the first metal layer 121a from the total thickness of the first circuit pattern layer 121. The total thickness of the first circuit pattern layer 121 has been described above, so a detailed description thereof will be omitted.

[0215] Meanwhile, the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 of the first circuit pattern layer 121 each include the first metal layer 121a and the second metal layer 121b. In this case, the first pad 121-1, the second pad 121-2, and the electrode pattern 121-3 may refer to a single circuit pattern including the same first metal layer 121a and second metal layer 121b, and may be simply divided according to their positions and functions.

[0216] As described above, the electrode pattern 121-3 includes a first portion 121-31, a second portion 121-32, and a third portion 121-33.

[0217] In this case, the third portion 121-33 of the electrode pattern 121-3 may include a region where the thickness varies. For example, at least a part of the third portion 121-31 of the electrode pattern 121-3 may include a portion having a thickness greater than that of the first portion 121-31. For example, at least a part of the third portion 121-33 of the electrode pattern 121-3 may include a portion having a thickness greater than that of the second portion 121-32.

[0218] For example, at least a part of the upper surface of the third portion 121-33 of the electrode pattern 121-3 may include a portion located higher than the upper surface of the first portion 121-31. For example, at least a part of the upper surface of the third portion 121-33 of the electrode pattern 121-3 may include a portion located higher than the upper surface of the second portion 121-32.

[0219] For example, the third portion 121-32 of the electrode pattern 121-3 may include a protrusion 121-3P whose thickness or height varies from the first portion 121-31 to the second portion 121-32 or from the second portion 121-32 to the first portion 121-31.

[0220] The protrusion 121-3P may include a first part whose height or thickness increases from the first part 121-31 to the second part 121-32, and a second part whose height or thickness decreases from the first part.

[0221] In this embodiment, in the manufacturing process of the circuit board, the first metal layer 121a of the first circuit pattern layer 121 is etched in a plurality of steps.

[0222] That is, in the embodiment, the first metal layer 121a of the first circuit pattern layer 121 arranged in the second region R2 is removed in a first etching process before the cavity 150 of the second insulating layer 112 is formed.

[0223] The first metal layer 121a of the first circuit pattern layer 121 arranged in the first region R1 and the third region R3 is removed in a second etching process after the cavity 150 is formed.

[0224] At this time, the second metal layer of the electrode pattern 121-3 may also be etched in two steps corresponding to the first metal layer. Under ideal conditions, a portion of the second metal layer of the electrode pattern 121-3 may be removed in the first etching process, and the remaining portion may be removed in the second etching process. However, due to process errors of the electrode pattern 121-3, it may be difficult to accurately distinguish between the portion that undergoes the first etching process and the portion that undergoes the second etching process.

[0225] Therefore, a portion of the second metal layer of the electrode pattern 121-3 may not be completely etched in the first and second etching processes. The unetched portion may be provided as the protrusion 121-3P. The protrusion 121-3P may be provided at the boundary between the third region R3 and the second region R2 in the third portion 121-32 of the electrode pattern 121-3.

[0226] Conversely, a portion of the second metal layer of the electrode pattern 121-3 may be completely etched in the first and second etching processes. Under the above conditions, the third portion 121-32 of the electrode pattern 121-3 may have a recess (not shown) instead of the protrusion 121-3P.

[0227] The third portion 121-33 of the electrode pattern 121-3 is a portion adjacent to the recess 150-3.

[0228] In this case, at least a portion of the upper surface of the third portion 121-33 of the electrode pattern 121-3 may be vertically overlapped with the second insulating layer 112 but may not be in contact with the second insulating layer 112.

[0229] For example, a second recess 150-4 may be provided in a region of the lower end of the sidewall 150-2 of the cavity 150 of the second insulating layer 112 that vertically overlaps with the electrode pattern 121-3. As such, the recess 150-3 can be referred to as a first recess. Hereinafter, the recess 150-3 will be referred to as the "first recess."

[0230] The first recess 150-3 and the second recess 150-4 are provided at the lower end of the sidewall 150-2 of the second insulating layer 112 adjacent to the frame region of the bottom surface 150-1.

[0231] In this case, the first recess 150-3 and the second recess 150-4 may have a step. That is, the first recess 150-3 is provided in a region of the lower end of the sidewall 150-2 that does not vertically overlap the electrode pattern 121-3.

[0232] In contrast, the second recess 150-4 is provided in a region of the lower end of the sidewall 150-2 that vertically overlaps the electrode pattern 121-3. Therefore, the first recess 150-3 and the second recess 150-4 may have a step difference equal to the thickness of the electrode pattern 121-3.

[0233] Thus, the first recess 150-3 and the second recess 150-4 may be recessed toward the inside of the second insulating layer 112 along the periphery of the bottom surface 150-1 in the entire area of the lower end of the sidewall 150-2.

[0234] The first recess 150-3 may have a first horizontal distance W1.

[0235] The first horizontal distance W1 may refer to the horizontal distance from the lower end of the sidewall 150-2 adjacent to the first recess 150-3 to the innermost side surface of the first recess 150-3. The first recess 150-3 is a location where the first metal layer used as a stopper in the process of forming the cavity 150 has been removed.

[0236] The first horizontal distance W1 may be in the range of 5 μm to 17 μm. Preferably, the first horizontal distance W1 may be in the range of 7 μm to 15 μm. More preferably, the first horizontal distance W1 may be in the range of 8 μm to 13 μm.

[0237] If the first horizontal distance W1 is less than 5 μm, the cavity 150 may be processed up to an area where no stopper is provided due to a process error in the process of forming the cavity 150. In this case, a portion of the upper surface of the first insulating layer 111 may also be processed in the cavity forming process. In this case, the first insulating layer 111 includes reinforcing fibers. The reinforcing fibers may be exposed by the processing, which may cause problems with physical reliability and electrical reliability.

[0238] Furthermore, if the first horizontal distance W1 exceeds 17 μm, a portion of the stopper may not be removed in a stopper removal process after the cavity 150 is formed. For example, in the embodiment, the stopper is completely removed using an over-etching phenomenon in the stopper removal process. That is, if an etching process for removing the stopper is performed after the cavity 150 is formed, only the portion vertically overlapping the cavity 150 is removed by etching under normal conditions. However, in the embodiment, over-etching conditions are set in the process for removing the stopper, and the stopper is removed according to the set over-etching conditions. When the stopper is removed according to the over-etching conditions, the stopper covered by the second insulating layer 112 in the region adjacent to the cavity 150 is also removed. In this case, if the first horizontal distance W1 exceeds 17 μm, it may mean that the first pad 121-1 may be damaged due to excessive over-etching conditions. Furthermore, if the first horizontal distance W1 exceeds 17 μm, it may mean that a portion of the stopper may not be removed even under over-etching conditions for removing the stopper, and if a portion of the stopper is not removed, problems with electrical reliability such as a short circuit may occur.

[0239] Meanwhile, the first recess 150-3 is a location where the first metal layer 121a has been removed, so that the vertical distance T1 of the first recess 150-3 can correspond to the thickness T1 of the first metal layer 121a.

[0240] The second recess 150-4 may have a second horizontal distance W2. In this case, the second horizontal distance W2 of the second recess 150-4 may be equal to or greater than the first horizontal distance W1 of the first recess 150-3. Preferably, the second horizontal distance W2 of the second recess 150-4 may be greater than the first horizontal distance W1 of the first recess 150-3.

[0241] This means that the first horizontal distance W1 and the second horizontal distance W2 are the same, which may mean that over-etching occurred exactly up to the portion where the stopper was located under over-etching conditions for removing the stopper. In this case, a problem may occur in which a portion of the stopper is not removed. Therefore, in this embodiment, the second horizontal distance W2 is greater than the first horizontal distance W1. Furthermore, the second horizontal distance W2 being greater than the first horizontal distance W1 may mean that over-etching occurred beyond the portion where the stopper was located under over-etching conditions for removing the stopper. This allows the stopper to be completely removed, thereby improving the electrical reliability of the circuit board.

[0242] FIG. 8 is a cross-sectional view showing a circuit board according to the second embodiment, FIG. 9 is an enlarged view of a portion of the cavity in FIG. 8, and FIG. 10 is an enlarged view of another portion of the cavity in FIG. 8.

[0243] 8 to 10, the circuit board of the second embodiment includes a first insulating layer 211, a second insulating layer 212, a first circuit pattern layer 221, a second circuit pattern layer 222, a third circuit pattern layer 223, a first through electrode 231, a second through electrode 232, a first protective layer 241, and a second protective layer 242. The second insulating layer 212 may be provided with a cavity 250 including a bottom surface 250-1 and a sidewall 250-2.

[0244] In this case, the circuit board of the second embodiment may have a structure in which a cavity is provided in the first insulating layer of the first embodiment when the circuit board of the first embodiment is turned upside down.

[0245] Therefore, the circuit boards of the second embodiment may differ from each other in the position of the first recess 250-3 and the layer structure of the first circuit pattern layer 221.

[0246] Specifically, the first recess in the first embodiment is provided in the sidewall of the second insulating layer.

[0247] Alternatively, the first recess 250-3 in the second embodiment may be provided on the top surface of the first insulating layer 211.

[0248] That is, the first circuit pattern layer 221 includes a first metal layer 221a and a second metal layer 221b.

[0249] In this case, in the circuit board of the first embodiment, the second metal layer of the first circuit pattern layer was located closer to the cavity than the first metal layer.

[0250] In contrast, in the circuit board of the second embodiment, the first metal layer 221a of the first circuit pattern layer 221 is positioned closer to the cavity 250 than the second metal layer 221b.

[0251] Therefore, in the circuit board of the second embodiment, the upper surface of the first insulating layer 211 may have a step. For example, the upper surface of a region of the first insulating layer 211 that vertically overlaps the cavity 250 may have a first height. The upper surface of a region of the first insulating layer 211 that does not vertically overlap the cavity 250 may have a second height higher than the first height. In this case, a portion of the upper surface of the first insulating layer 211 that does not vertically overlap the cavity 250 and is adjacent to the cavity 250 may include a first recess 250-3 having the first height. That is, the cavity 250 is formed with the first metal layer 221a of the first circuit pattern layer 221 disposed at a position corresponding to the first recess 250-3. Then, after the cavity 250 is formed, a portion of the first metal layer 221a is removed, so that the upper surface of the first insulating layer 211 may have a step corresponding to the recess 250-3.

[0252] That is, the first recess 250-3 of the second embodiment may be recessed from the lower end of the sidewall 150-2 of the cavity 250 to the inside of the first insulating layer 211.

[0253] In summary, the first and second recesses of the first embodiment are recessed from the lower end of the sidewall of the cavity toward the inside of the second insulating layer, so that the lower surface of the second insulating layer of the first embodiment has steps corresponding to the first and second recesses.

[0254] Alternatively, the first recess 250-3 of the second embodiment may have a structure recessed from the lower end of the sidewall 150-2 of the cavity 250 toward the inside of the first insulating layer 211. Therefore, the upper surface of the first insulating layer 211 may have a step corresponding to the first recess 250-3.

[0255] Meanwhile, the first circuit pattern layer 221 includes a first pad 221-1, a second pad 221-2, and an electrode pattern 221-3, and the electrode pattern 221-3 may include a first portion 221-31, a second portion 221-32, and a third portion 221-33.

[0256] In this case, the first pad 221-1, the second pad 221-2, and the electrode pattern 221-3 may have different thicknesses or different layer structures.

[0257] Preferably, the first circuit pattern layer 221 may include a first metal layer 221a and a second metal layer 221b.

[0258] At this time, the first metal layer of the first pad 221-1 is used as a stopper in the process of forming the cavity 250. Therefore, the first pad 221-1 may include only the second metal layer excluding the first metal layer.

[0259] Alternatively, the second pad 221-2 may include both the first metal layer 221a and the second metal layer 221b.

[0260] Meanwhile, the electrode patterns 221-3 may have different layer structures or thicknesses depending on their positions.

[0261] The first portion 221-31 of the electrode pattern 221-3 may include only the second metal layer 221b because the first metal layer 221a of the first portion 221-31 of the electrode pattern 221-3 is used as a stopper in the process of forming the cavity 250.

[0262] Also, the second portion 221-32 of the electrode pattern 221-3 may include both the first metal layer 221a and the second metal layer 221b.

[0263] Meanwhile, the third portion 221-33 of the electrode pattern 221-3 may include only the second metal layer 221b because over-etching occurs during the process of removing the first metal layer of the first portion 221-31 of the electrode pattern 221-3 by etching, resulting in the removal of the first metal layer 221a of the third portion 221-33 of the electrode pattern 221-3.

[0264] The circuit board of the embodiment includes a first insulating layer, a first circuit pattern layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and the first circuit pattern layer. The second insulating layer includes a cavity penetrating its upper and lower surfaces. The first circuit pattern layer includes a first pad disposed in a first region vertically overlapping the cavity, a second pad disposed in a second region not vertically overlapping the cavity, and an electrode pattern disposed in the first region and the second region, connecting the first pad and the second pad.

[0265] That is, in the embodiment, an electrode pattern that directly connects the first pad and the second pad is disposed on the first insulating layer. Through this, the embodiment can reduce the signal transmission distance between the first pad and the second pad. Furthermore, the embodiment can minimize signal transmission loss due to the reduction in the signal transmission distance. As a result, the embodiment can improve the electrical characteristics of a circuit board and a semiconductor package including the same.

[0266] In addition, the embodiment can improve circuit integration by disposing the electrode pattern in an area corresponding to the cavity.

[0267] Meanwhile, the second insulating layer including the cavity includes a thermosetting resin. In the embodiment, the electrode pattern can be arranged while the second insulating layer includes a thermosetting resin. In the embodiment, by forming the insulating layer using a thermosetting resin, the adhesion between the multiple insulating layers can be improved. As a result, the embodiment can improve the physical properties of the circuit board and the semiconductor package including the circuit board.

[0268] Meanwhile, a recess may be formed at a lower end of a sidewall of the cavity along a circumferential direction of a bottom surface of the cavity. The recess may have a closed loop shape along a circumferential direction of the bottom surface of the cavity. In this case, the recess may include a stepped portion in one embodiment, or may not have a stepped portion in another embodiment.

[0269] Therefore, in the embodiment, a connecting member and a molding member that molds the connecting member are disposed in the cavity. The molding member may fill a recess formed in the cavity. In this case, the embodiment may allow a portion of the entire area of the molding member that is disposed in the recess to function as an anchor. Therefore, the embodiment may improve the adhesion between the circuit board and the molding member. As a result, the embodiment may more stably protect the connecting member. Furthermore, the embodiment may further improve the product reliability of the semiconductor package.

[0270] FIG. 11 is a diagram illustrating a package substrate according to an embodiment.

[0271] Referring to FIG. 11, the package substrate may include a connection member 310 disposed on the first pad 121-1 and a linking member 320 disposed on the connection member 310.

[0272] The connecting member may be any one of the second substrate, the semiconductor device, and the connecting substrate described with reference to FIGS. 1a to 1g.

[0273] Meanwhile, a molding member 330 may be disposed in the cavity 150. The molding member 330 may be disposed in the cavity 150 by molding the connection member 320 therein.

[0274] In this case, at least a portion of the molding member 330 may be disposed by filling the first recess 150-3 and the second recess 150-4 of the cavity 150. The portions of the molding member 330 disposed in the first recess 150-3 and the second recess 150-4 may function as anchors. As a result, this embodiment may further improve the adhesion between the molding member 330 and the circuit board.

[0275] A method for manufacturing a circuit board according to the embodiment will be described below.

[0276] 12 to 22 are diagrams showing the manufacturing method of the circuit board of FIG. 2 according to the embodiment in the order of steps.

[0277] Referring to FIG. 12, an embodiment provides an insulating member based on the manufacture of a circuit board.

[0278] For example, an embodiment includes an insulating member including a first insulating layer 111 and a metal layer on the first insulating layer 111 .

[0279] The metal layer may include a metal layer 121a disposed on the first insulating layer 111 and a metal layer 123a disposed under the first insulating layer 111. The metal layer 121a may be used as a seed layer for forming the first circuit pattern layer 121 by electroplating. The metal layer 123a may be used as a seed layer for forming the third circuit pattern layer 123 by electroplating.

[0280] Next, referring to FIG. 13, in this embodiment, electrolytic plating is performed using the metal layers 121a and 123a as seed layers to form a second metal layer 121b of the first circuit pattern layer 121, a second metal layer 123b of the third circuit pattern layer 123, and a first through electrode 131 that penetrates the first insulating layer 111.

[0281] 13 may include a first region R1, a second region R2, and a third region R3. The first region R1 may be a region corresponding to the size of the actual cavity 150. The second region R2 may be a region where the cavity 150 is not formed. The third region R3 refers to a boundary region between the first region R1 and the second region R2. The third region R3 may be a region that takes into account process errors in the cavity formation process.

[0282] 14, in this embodiment, a dry film DF1 is disposed on the first region R1 and the third region R3 of the first circuit pattern layer 121. The dry film DF1 can prevent the first metal layer 121a, which serves as a stopper in the first etching process, from being removed.

[0283] 15, in an embodiment, a process may be performed to remove the first metal layer 121a of the first circuit pattern layer 121 and the first metal layer 123a of the third circuit pattern layer 123 in the area where the dry film DF1 is not disposed. Through this, in an embodiment, the second pad 121-2 of the first circuit pattern layer 121 and the third circuit pattern layer 123 may be formed.

[0284] 16, the first metal layer 121a disposed in the second region R1 that does not vertically overlap the second metal layer 121b may be entirely removed, thereby forming the second pad 121-2 and a portion (e.g., the second portion 121-32) of the first circuit pattern layer 121. In this case, the first metal layer 121a disposed in the first region R1 and the third region R3 may be used as a first stopper S1 in the process of forming the cavity 150.

[0285] 17, in this embodiment, a second insulating layer 112 may be disposed on a first insulating layer 111. In this case, a first metal layer 122a of the second circuit pattern layer 122, which is a seed layer of the second circuit pattern layer 122, may be disposed on an upper surface of the second insulating layer 112.

[0286] 18, in an embodiment, electrolytic plating may be performed using the first metal layer 122a of the second circuit pattern layer 122 as a seed layer to form the second metal layer 122b of the second circuit pattern layer 122. At this time, a second through electrode 132 penetrating the second insulating layer 112 may be formed together with the second metal layer 122b.

[0287] Next, referring to FIG. 19 , an embodiment may perform a process of removing the first metal layer 122a of the second circuit pattern layer 122 by etching. At this time, in this embodiment, the first metal layer 122a of the second circuit pattern layer 122 is not completely removed, but a portion is left. For example, in this embodiment, the portion of the first metal layer 122a of the second circuit pattern layer 122 located in the first region R1 is completely removed. In this embodiment, the portion of the first metal layer 122a of the second circuit pattern layer 122 located in the third region R3 and the second region R2 adjacent to the third region R3 is not removed. This may be used as a second stopper S2 in the process of forming the cavity 150. At this time, the first stopper S1 and the second stopper S2 may at least partially overlap vertically. For example, the first stopper S1 and the second stopper S2 may vertically overlap in the third region R3. Through this, the embodiment can prevent the size of the cavity 150 from being expanded during the process of forming the cavity 150.

[0288] Next, referring to FIG. 20, in an embodiment, a cavity 150 penetrating the second insulating layer 112 may be formed using the first stopper S1 and the second stopper S2.

[0289] In this case, the cavity 150 at the lower end of the sidewall 150-2 of the cavity 150 does not need to vertically overlap the third region R3.

[0290] 21, in this embodiment, a process of removing the first stopper S1 and the second stopper S2 by etching can be performed. At this time, the second stopper S2 can be easily removed because there is no insulating layer covering it.

[0291] In contrast, a portion of the first stopper S1 corresponding to the third region R3 is covered with the second insulating layer 112. When etching the portion of the first stopper S1 corresponding to the first region R1, over-etching may occur. In this embodiment, the over-etching can be used to easily remove the first stopper S1 in the third region R3. As a result, a first recess 150-3, which is the location where the first stopper S1 is removed, may be formed at the bottom of the sidewall 150-2 of the cavity 150.

[0292] Next, referring to FIG. 22, in this embodiment, a process of forming a first protective layer 141 under the first insulating layer 111 and forming a second protective layer 142 on the second insulating layer 112 may be performed.

[0293] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, the circuit board having the above-described inventive features can maintain stable functionality of IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0294] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0295] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0296] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. a first insulating layer; a second insulating layer disposed on the first insulating layer; a circuit pattern layer disposed between the first and second insulating layers; the second insulating layer has a cavity penetrating the upper surface and the lower surface; The circuit pattern layer includes an electrode pattern extending from inside the cavity to outside the cavity.

2. The circuit pattern layer is a first pad provided inside the cavity and vertically overlapping the cavity; The circuit board according to claim 1 , further comprising: a second pad provided outside the cavity and not vertically overlapping the cavity.

3. The circuit board according to claim 2 , wherein the electrode pattern directly connects the first pad and the second pad.

4. The circuit board according to claim 1 , wherein the second insulating layer has a recess recessed from a lower end of the side wall of the cavity toward an outside of the second insulating layer.

5. The circuit board according to claim 4 , wherein the recessed portion includes a first portion that does not overlap the electrode pattern in the vertical direction, and a second portion that overlaps the electrode pattern in the vertical direction.

6. the circuit pattern layer is provided protruding from the first insulating layer, The circuit board according to claim 3 , wherein the first portion of the recess is provided along a rim of a lower end of a side wall of the cavity.

7. The circuit board according to claim 5 , wherein the first and second portions of the recess have a step.

8. Each of the first pad, the second pad, and the electrode pattern is a first metal layer disposed on the first insulating layer; a second metal layer disposed on the first metal layer; The circuit board according to claim 5 , wherein the vertical length of the first recess corresponds to the thickness of the first metal layer.

9. 6. The circuit board according to claim 5, wherein a horizontal distance from a lower end of the side wall of the cavity to an innermost end of the first portion of the recessed portion falls within a range of 5 μm to 17 μm.

10. The circuit board of claim 5 , wherein a horizontal length of the first portion of the recess is different from a horizontal length of the second portion of the recess.

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