Display panel and display device

Abstract

The present application discloses a display panel and a display device, in which a compensation module in the display panel is used to input a first compensation voltage to a sub-pixel during a blank period of a first display screen and input a second compensation voltage to the sub-pixel during a blank period of a second display screen, the polarity of the first compensation voltage is the same as the polarity of a first data voltage, the polarity of the second compensation voltage is the same as the polarity of the second data voltage, the first compensation voltage is not zero, and the second compensation voltage is not zero.

Description

[Technical Field]

[0001] The present application relates to the field of display technology, and more particularly to display panels and display devices. [Background technology]

[0002] In conventional display panels, the polarity of data voltages input to subpixels is reversed during two consecutive frames. Due to leakage current between the source and drain of the switching transistor, the brightness of the subpixel gradually decreases after the first frame is displayed. When the second frame is displayed, a data voltage of the opposite polarity is input to the subpixel, increasing the voltage difference between the source and drain of the switching transistor. This increases the rate of leakage current between the source and drain, causing the brightness of the subpixel to continue decreasing. After the next scan, the brightness of the pixel increases significantly. This significant change in brightness during the two consecutive frames results in flickering. Summary of the Invention [Problem to be solved by the invention]

[0003] The present application provides a display panel and a display device, which can solve the problem of flicker occurring on the display panel due to a large change in brightness of the display panel between two consecutive frames of the display screen. [Means for solving the problem]

[0004] An embodiment of the present application provides a display panel, the screens displayed by the display panel including a first display screen and a second display screen that are displayed consecutively. The display panel includes a plurality of sub-pixels, a plurality of scan lines, a plurality of data lines, and a compensation module, the plurality of scan lines arranged along a first direction and electrically connected to a plurality of the sub-pixels, the plurality of data lines arranged along a second direction, the first direction intersecting with the second direction, the plurality of data lines electrically connected to a plurality of the sub-pixels, and a first data voltage input to the sub-pixels via the data lines during a display period of the first display screen having a polarity opposite to a second data voltage input to the sub-pixels via the data lines during a display period of the second display screen. The compensation module is electrically connected to one end of the plurality of data lines, and is used to input a first compensation voltage to the sub-pixel during a blank period of the first display screen and a second compensation voltage to the sub-pixel during a blank period of the second display screen, wherein the polarity of the first compensation voltage is the same as the polarity of the first data voltage, the polarity of the second compensation voltage is the same as the polarity of the second data voltage, the first compensation voltage is not zero, and the second compensation voltage is not zero.

[0005] Meanwhile, an embodiment of the present application further provides a display device, the display device including a housing and a display panel, wherein the screens displayed by the display panel include a first display screen and a second display screen that are displayed consecutively. The display panel includes a plurality of sub-pixels, a plurality of scan lines, a plurality of data lines, and a compensation module, wherein the plurality of scan lines are arranged along a first direction and each of the plurality of scan lines is electrically connected to a plurality of the sub-pixels. The plurality of data lines are arranged along a second direction, the first direction intersects with the second direction, and each of the plurality of data lines is electrically connected to a plurality of the sub-pixels, and a polarity of a first data voltage input to the sub-pixels by the data lines during a display period of the first display screen is opposite to a polarity of a second data voltage input to the sub-pixels by the data lines during a display period of the second display screen. The compensation module is electrically connected to one end of the plurality of data lines, and is used to input a first compensation voltage to the sub-pixel during a blank period of the first display screen and a second compensation voltage to the sub-pixel during a blank period of the second display screen, wherein the polarity of the first compensation voltage is the same as the polarity of the first data voltage, the polarity of the second compensation voltage is the same as the polarity of the second data voltage, the first compensation voltage is not zero, and the second compensation voltage is not zero. [Effects of the Invention]

[0006] In the display panel and display device provided by the present application, a compensation module is electrically connected to one end of a plurality of data lines, and is configured to input a first compensation voltage to a subpixel during a blank period of a first display screen and a second compensation voltage to a subpixel during a blank period of a second display screen, thereby reducing the voltage difference between the source electrode and drain electrode of the subpixel during the blank period, stabilizing the potential of the subpixel, and reducing leakage current. This alleviates the problem of a significant drop in the luminance of the subpixel and a significant increase in the luminance of the subpixel after the next scan, which is caused by high leakage current from the end of a subpixel scan to the beginning of the next scan, resulting in a large change in luminance of the display panel during two consecutive frames of display screen, and causing flicker on the display panel, thereby improving the display effect. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic diagram of a display panel according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a first driving timing diagram of a display panel according to an embodiment of the present application. [Figure 3] FIG. 10 is a second driving timing diagram of the display panel according to the embodiment of the present application. [Figure 4] FIG. 10 is a schematic diagram of a display panel according to a second embodiment of the present invention. [Figure 5] FIG. 10 is a third driving timing diagram of the display panel according to the embodiment of the present application. [Figure 6] FIG. 4 is a fourth driving timing diagram of the display panel according to the embodiment of the present application. [Figure 7] FIG. 5 is a fifth driving timing diagram of the display panel according to the embodiment of the present application. [Figure 8] FIG. 10 is a schematic diagram of a display panel according to a third embodiment of the present invention. [Figure 9] FIG. 6 is a sixth driving timing diagram of the display panel according to the embodiment of the present application. [Figure 10] FIG. 7 is a seventh driving timing diagram of the display panel according to the embodiment of the present application. [Figure 11]FIG. 10 is a schematic diagram of a display panel according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] Below, the technical solutions in the embodiments of the present application will be described in conjunction with the drawings in the embodiments of the present application. It should be understood that the described technical solutions are merely for the purpose of explaining the ideas of the present application and are not intended to limit the present application.

[0009] The embodiments provided herein are similar and features in different embodiments can be combined.

[0010] 1 , an embodiment of the present application provides a display panel 100, where an image displayed by the display panel 100 includes a first image and a second image displayed successively. The display panel 100 includes a plurality of sub-pixels 10, a plurality of scan lines 20, a plurality of data lines 30, and a compensation module 40. The plurality of scan lines 20 are arranged along a first direction Y, and each of the plurality of scan lines 20 is electrically connected to a plurality of sub-pixels 10. The plurality of data lines 30 are arranged along a second direction X, and the first direction Y intersects with the second direction X. The plurality of scan lines 20 are electrically connected to a plurality of sub-pixels 10, and the polarity of a first data voltage input to the sub-pixels 10 by the data line 30 during a display period of the first image is opposite to the polarity of a second data voltage input to the sub-pixels 10 by the data line 30 during a display period of the second image.

[0011] The compensation module 40 is electrically connected to one end of the plurality of data lines 30, and is used to input a first compensation voltage to the sub-pixel 10 during the blank period of the first display screen and input a second compensation voltage to the sub-pixel 10 during the blank period of the second display screen, where the polarity of the first compensation voltage is the same as the polarity of the first data voltage, the polarity of the second compensation voltage is the same as the polarity of the second data voltage, the first compensation voltage is not zero, and the second compensation voltage is not zero.

[0012] In this display panel 100, the compensation module 40 is electrically connected to one end of the plurality of data lines 30, and is arranged to input a first compensation voltage to the subpixel 10 during the blank period of the first display screen and a second compensation voltage to the subpixel 10 during the blank period of the second display screen, which are successively displayed. This stabilizes the potential of the subpixel 10. This alleviates the problem of significant drop in luminance of the subpixel 10 and significant increase in luminance of the subpixel 10 after the next scan, which is caused by frequent leakage current from the subpixel 10 after the end of one scan to the next scan, resulting in a large change in luminance of the display panel 100 during two consecutively displayed frames of display screen, and thus causing flicker in the display panel 100, thereby improving the display effect.

[0013] In this embodiment, the compensation module 40 includes a compensation voltage output terminal V0, which is electrically connected to one end of the plurality of data lines 30 and is used to output a first compensation voltage and a second compensation voltage, the absolute value of which is less than or equal to the absolute value of the first data voltage, and the absolute value of which is greater than or equal to the absolute value of the second data voltage.

[0014] Specifically, when the first data voltage is a positive data voltage, for example, when the first data voltage is 2 V, the first compensation voltage is greater than 0 V and less than or equal to 2 V, for example, the first compensation voltage is 1.5 V. When the first data voltage is a negative data voltage, for example, when the first data voltage is −2 V, the first compensation voltage is less than 0 V and greater than or equal to −2 V, for example, the first compensation voltage is −1.5 V.

[0015] Here, the absolute value of the first compensation voltage is equal to the absolute value of the second compensation voltage.

[0016] In the present embodiment, the compensation module 40 includes a plurality of switching transistors T0, the gates of which are electrically connected to the global control signal terminal GAS0, one of the source and drain of each switching transistor T0 is electrically connected to the compensation voltage output terminal V0, and the other of the source and drain of each switching transistor T0 is electrically connected to one end of the data line 30.

[0017] In this embodiment, the display panel further includes a gate driving circuit 50 and a source driving circuit 60. The gate driving circuit 50 is electrically connected to the plurality of scan lines 20 and is used to supply scanning signals to the sub-pixels 10. The source driving circuit 60 is electrically connected to the other ends of the plurality of data lines 30 and is used to supply data voltages to the sub-pixels 10.

[0018] In the present embodiment, during the blank period, the on time of the switching transistor T0 is greater than or equal to the off time.

[0019] 1 and 2, during the display period t01, a low-potential global control signal gas0 is input to the global control signal terminal GAS0. During the blank period t02, a high-potential global control signal gas0 is input to the global control signal terminal GAS0. The switching transistor T0 remains on during the blank period t02.

[0020] As shown in FIGS. 1 and 3, during the display period t01, a low-potential global control signal gas0 is input to the global control signal terminal GAS0. During a portion of the blank period t02, a high-potential global control signal gas0 is input to the global control signal terminal GAS0. The switching transistor T0 is turned on by the control of the high-potential global control signal gas0. Here, the portion of the blank period t02 includes any period within the blank period t02.

[0021] 4, an embodiment of the present application provides a display panel 200, which differs from the display panel 100 in the following respects: the plurality of data lines 30 includes a plurality of first data lines 31 and a plurality of second data lines 32; the compensation module 40 includes a first compensation voltage output terminal V1, a second compensation voltage output terminal V2, a plurality of first switching transistors T1, and a plurality of second switching transistors T2; the first compensation voltage output terminal V1 is electrically connected to the first switching transistor T1 and the first data line 31, and the second compensation voltage output terminal V2 is electrically connected to the second switching transistor T2 and the second data line 32.

[0022] Specifically, the screen displayed by the display panel 200 includes a first display screen and a second display screen that are displayed consecutively. The display panel 200 includes a plurality of sub-pixels 10, a plurality of scan lines 20, a plurality of data lines 30, and a compensation module 40. The plurality of scan lines 20 are arranged along a first direction Y, and each of the plurality of scan lines 20 is electrically connected to a plurality of sub-pixels 10. The plurality of data lines 30 are arranged along a second direction X, and the first direction Y intersects with the second direction X. The plurality of scan lines 20 are electrically connected to a plurality of sub-pixels 10, and the polarity of a first data voltage input to the sub-pixels 10 by the data line 30 during a display period of the first display screen is opposite to the polarity of a second data voltage input to the sub-pixels 10 by the data line 30 during a display period of the second display screen.

[0023] The plurality of data lines 30 includes a plurality of first data lines 31 and a plurality of second data lines 32, and the plurality of first data lines 31 and the plurality of second data lines 32 are alternately arranged along the second direction X. The first data voltage includes a first positive data voltage and a first negative data voltage, and during a display period of a first display screen, the data voltage input to the subpixels 10 by the first data line 31 is the first positive data voltage, and the data voltage input to the subpixels 10 by the second data line 32 is the first negative data voltage. The second data voltage includes a second positive data voltage and a second negative data voltage, and during a display period of a second display screen, the data voltage input to the subpixels 10 by the first data line 31 is the second negative data voltage, and the data voltage input to the subpixels 10 by the second data line 32 is the second positive data voltage.

[0024] In this embodiment, the compensation module 40 includes a first compensation voltage output terminal V1 and a second compensation voltage output terminal V2. The first compensation voltage output terminal V1 is electrically connected to the first data line 31. The first compensation voltage includes a first positive compensation voltage and a first negative compensation voltage. The first positive compensation voltage is less than the first positive data voltage, and the first negative compensation voltage is greater than the first negative data voltage. For example, if the first positive data voltage is 2V, the first positive compensation voltage is greater than 0V and less than 2V, e.g., 1.5V. If the first negative data voltage is −2V, the first negative compensation voltage is less than 0V and greater than −2V, e.g., −1.5V.

[0025] The second compensation voltage output terminal V2 is electrically connected to the second data line 32, and the second compensation voltage includes a second positive compensation voltage and a second negative compensation voltage, where the second positive compensation voltage is less than or equal to the second positive data voltage, and the second negative compensation voltage is greater than or equal to the second negative data voltage.

[0026] For example, when the second positive data voltage is 2 V, the second positive compensation voltage is greater than 0 V and less than or equal to 2 V, e.g., 1 V. When the second negative data voltage is −2 V, the second negative compensation voltage is less than 0 V and greater than or equal to −2 V, e.g., −1 V.

[0027] In the present embodiment, the compensation module 40 includes a plurality of first switching transistors T1 and a plurality of second switching transistors T2, and the gates of the plurality of first switching transistors T1 and the gates of the plurality of second switching transistors T2 are all electrically connected to the global control signal terminal GAS0. One of the source and drain of the first switching transistor T1 is electrically connected to the first compensation voltage output terminal V1, and the other of the source and drain of the first switching transistor T1 is electrically connected to one end of the first data line 31. One of the source and drain of the second switching transistor T2 is electrically connected to the second compensation voltage output terminal V2, and the other of the source and drain of the second switching transistor T2 is electrically connected to one end of the second data line 32.

[0028] In the embodiment of the present application, the first switching transistor T1 and the second switching transistor T2 are turned off during the display period, and the first switching transistor T1 and the second switching transistor T2 are turned on during the blank period.

[0029] 5, a low-potential global control signal gas0 is input to the global control signal terminal GAS0 during the display period t01, turning off the first switching transistor T1 and the second switching transistor T2. The blank period t02 includes a first blank subperiod t001 and a second blank subperiod t002, where the first blank subperiod t001 is adjacent to the second blank subperiod t002 and the duration of the first blank subperiod t001 is equal to the duration of the second blank subperiod t002. A high-potential global control signal gas0 is input to the global control signal terminal GAS0 during the first blank subperiod t001, turning on the first switching transistor T1 and the second switching transistor T2 during the first blank subperiod t001. A low-potential global control signal gas0 is input to the global control signal terminal GAS0 during the second blank subperiod t002, turning off the first switching transistor T1 and the second switching transistor T2 during the second blank subperiod t002.

[0030] 6, a low-potential global control signal gas0 is input to the global control signal terminal GAS0 during the display period t01, turning off the first switching transistor T1 and the second switching transistor T2. The blank period t02 includes a first blank subperiod t001 and a second blank subperiod t002, where the first blank subperiod t001 is adjacent to the second blank subperiod t002 and the duration of the first blank subperiod t001 is equal to the duration of the second blank subperiod t002. A low-potential global control signal gas0 is input to the global control signal terminal GAS0 during the first blank subperiod t001, turning off the first switching transistor T1 and the second switching transistor T2 during the first blank subperiod t001. A high-potential global control signal gas0 is input to the global control signal terminal GAS0 during the second blank subperiod t002, turning on the first switching transistor T1 and the second switching transistor T2 during the second blank subperiod t002.

[0031] 7, during the blank period t02, the on time of the first switching transistor T1 and the second switching transistor T2 is longer than the off time, and the sub-pixel of the data line electrically connected to the first switching transistor T1 receives the compensation voltage for a sufficiently long time, thereby improving the stability of the sub-pixel potential, and the sub-pixel of the data line electrically connected to the second switching transistor T2 receives the compensation voltage for a sufficiently long time, thereby improving the stability of the sub-pixel potential.

[0032] Specifically, the blank period t02 includes a first blank subperiod t001 and a second blank subperiod t002, and the first blank subperiod t001 is adjacent to the second blank subperiod t002, where the duration of the first blank subperiod t001 is greater than the duration of the second blank subperiod t002.

[0033] In the embodiment of the present application, a low-potential global control signal gas0 is input to the global control signal terminal GAS0 during the display period t01, and the first switching transistor T1 and the second switching transistor T2 are turned off. The blank period includes a first blank sub-period t001 and a second blank sub-period t002, and the first blank sub-period t001 is adjacent to the second blank sub-period t002. A high-potential global control signal gas0 is input to the global control signal terminal GAS0 during the first blank sub-period t001, and the first switching transistor T1 and the second switching transistor T2 are turned on during the first blank sub-period t001. A low-potential global control signal gas0 is input to the global control signal terminal GAS0 during the second blank sub-period t002, and the first switching transistor T1 and the second switching transistor T2 are turned off during the second blank sub-period t002.

[0034] Preferably, when the duration of the second blank sub-period t002 is greater than the duration of the first blank sub-period t001, the first switching transistor T1 and the second switching transistor T2 are both turned on in the second blank sub-period t002 and turned off in the first blank sub-period t001.

[0035] 8, an embodiment of the present application provides a display panel 300, which differs from the display panel 200 in the following respects: gates of the plurality of first switching transistors T1 are electrically connected to a first control signal terminal GAS1, and gates of the plurality of second switching transistors T2 are electrically connected to a second control signal terminal GAS2.

[0036] Specifically, the compensation module 40 includes a plurality of first switching transistors T1 and a plurality of second switching transistors T2, where the gates of the plurality of first switching transistors T1 are electrically connected to a first control signal terminal GAS1 and the gates of the plurality of second switching transistors T2 are electrically connected to a second control signal terminal GAS2. One of the source and drain of the first switching transistor T1 is electrically connected to a first compensation voltage output terminal V1, and the other of the source and drain of the first switching transistor T1 is electrically connected to one end of a first data line 31. One of the source and drain of the second switching transistor T2 is electrically connected to a second compensation voltage output terminal V2, and the other of the source and drain of the second switching transistor T2 is electrically connected to one end of a second data line 32.

[0037] The other configurations of the display panel 300 are the same as those of the display panel 200.

[0038] As shown in FIG. 8, the first switching transistor T1 and the second switching transistor T2 are of the same type, and the first switching transistor T1 is an N-type transistor.

[0039] As shown in FIG. 9, the blank period includes a plurality of first blank sub-periods t001 and a plurality of second blank sub-periods t002, the plurality of first blank sub-periods t001 and the plurality of second blank sub-periods t002 alternate, and the first switching transistor T1 is turned on during the plurality of first blank sub-periods t001, and the second switching transistor T2 is turned on during the plurality of second blank sub-periods t002.

[0040] Specifically, a low-potential first control signal gas1 is input to the first control signal terminal GAS1 during the display period, turning off the first switching transistor T1. A low-potential second control signal gas2 is input to the second control signal terminal GAS2 during the display period, turning off the second switching transistor T2. A high-potential first control signal gas1 is input to the first control signal terminal GAS1 during each of the first blank periods t001, turning on the first switching transistor T1 during each of the first blank periods t001. A low-potential first control signal gas1 is input to the first control signal terminal GAS1 during each of the second blank periods t002, turning off the first switching transistor T1 during each of the second blank periods t002. A high-potential second control signal gas2 is input to the second control signal terminal GAS2 during each of the second blank periods t002, turning on the second switching transistor T2 during each of the second blank sub-periods t002. A second control signal gas2 at a low potential is input to the second control signal terminal GAS2 during a plurality of first blank periods t001, and the second switching transistor T2 is turned off during a plurality of first blank periods t001.

[0041] 10, the blank period includes a first blank subperiod t001, a second blank subperiod t002, and a third blank subperiod t003, and the second blank subperiod t002 is located between the first blank subperiod t001 and the third blank subperiod t003. The first switching transistor T1 is turned on during the first blank subperiod t001 and the second blank subperiod t002, and the second switching transistor T2 is turned on during the second blank subperiod t002 and the third blank subperiod t003.

[0042] Specifically, the first control signal terminal GAS1 receives a low-potential first control signal gas1 during the display period, and the second control signal terminal GAS2 receives a low-potential second control signal gas2 during the display period, turning off the first switching transistor T1 and the second switching transistor T2. The first control signal terminal GAS1 receives a high-potential first control signal gas1 during the first blank sub-period t001 and the second blank sub-period t002, turning on the first switching transistor T1. The first control signal terminal GAS1 receives a low-potential first control signal gas1 during the third blank sub-period t003, turning off the first switching transistor T1. The second control signal terminal GAS2 receives a low-potential second control signal gas2 during the first blank sub-period t001, turning off the second switching transistor T2. A high-potential second control signal gas2 is input to the second control signal terminal GAS2 during the second blank sub-period t002 and the third blank sub-period t003, and the second switching transistor T2 is turned on.

[0043] 11 , an embodiment of the present application provides a display panel 400, which differs from the display panel 300 in the following respects: one of the first switching transistor T1 and the second switching transistor T2 is an N-type transistor, and the other of the first switching transistor T1 and the second switching transistor T2 is a P-type transistor. This allows for a variety of circuit layouts in the compensation module 40. For example, the first switching transistor T1 and the second switching transistor T2 may be electrically connected to the first control signal terminal GAS1 and the second control signal terminal GAS2, respectively, or may be electrically connected to the same control signal terminal, thereby reducing the space occupied by the compensation module 40 and the number of signal lines.

[0044] The other configurations of the display panel 400 are the same as those of the display panel 300.

[0045] An embodiment of the present application further provides a display device, which includes a display panel and a housing, the display panel being disposed within the housing.

[0046] The display panel and display device provided by the embodiments of the present application have been described in detail above. However, it should be understood that the description of the above embodiments is merely intended to aid in understanding the core idea of ​​the present application, and the above description is not intended to limit the present application. [Explanation of symbols]

[0047] 10 subpixels 20 scan lines 30 data lines 31 First data line 32 Second data line 40 Compensation Module 50 Gate drive circuit 60 Source driver circuit 100 Display Panel 200 Display Panel 300 Display Panel 400 display panel T1 First switching transistor T2 Second switching transistor

Claims

1. A display panel, wherein a screen displayed by the display panel includes a first display screen and a second display screen that are displayed consecutively, the display panel comprising: a plurality of sub-pixels; a plurality of scanning lines arranged along a first direction, the plurality of scanning lines being electrically connected to a plurality of the sub-pixels, respectively; a plurality of data lines, the plurality of data lines being arranged along a second direction, the first direction intersecting the second direction, the plurality of data lines being electrically connected to a plurality of the sub-pixels, respectively, and the plurality of data lines inputting first data voltages to the sub-pixels during a display period of the first display screen, the polarity of the first data voltages being opposite to the polarity of second data voltages to the sub-pixels during a display period of the second display screen; a compensation module electrically connected to one ends of the plurality of data lines, the compensation module being used to input a first compensation voltage to the sub-pixel during a blank period of the first display screen and a second compensation voltage to the sub-pixel during a blank period of the second display screen, the polarity of the first compensation voltage being the same as the polarity of the first data voltage, and the polarity of the second compensation voltage being the same as the polarity of the second data voltage; wherein the first compensation voltage is non-zero and the second compensation voltage is non-zero; Display panel.

2. the compensation module includes a compensation voltage output terminal, the compensation voltage output terminal is electrically connected to one ends of the plurality of data lines, and the compensation voltage output terminal is used to output the first compensation voltage and the second compensation voltage; an absolute value of the first compensation voltage is equal to or less than an absolute value of the first data voltage, and an absolute value of the second compensation voltage is equal to or greater than an absolute value of the second data voltage; The display panel according to claim 1 .

3. The compensation module includes a plurality of switching transistors, gates of the plurality of switching transistors are electrically connected to a global control signal terminal; one of the source and drain of the switching transistor is electrically connected to the compensation voltage output terminal, and the other of the source and drain of the switching transistor is electrically connected to one end of the data line; The display panel according to claim 2 .

4. During the blank period, the on-time of the switching transistor is equal to or longer than the off-time thereof. The display panel according to claim 3 .

5. the plurality of data lines include a plurality of first data lines and a plurality of second data lines, the plurality of first data lines and the plurality of second data lines being alternately arranged along the second direction; the first data voltages include a first positive data voltage and a first negative data voltage, and during the display period of the first display screen, the data voltage input to the sub-pixel through the first data line is the first positive data voltage, and the data voltage input to the sub-pixel through the second data line is the first negative data voltage; the second data voltages include a second positive data voltage and a second negative data voltage, and during the display period of the second display screen, the data voltage input to the sub-pixel via the first data line is the second negative data voltage, and the data voltage input to the sub-pixel via the second data line is the second positive data voltage. The display panel according to claim 1 .

6. the compensation module includes a first compensation voltage output terminal and a second compensation voltage output terminal, the first compensation voltage output terminal is electrically connected to the first data line, the first compensation voltage includes a first positive compensation voltage and a first negative compensation voltage, the first positive compensation voltage is less than or equal to the first positive data voltage, and the first negative compensation voltage is greater than or equal to the first negative data voltage; the second compensation voltage output terminal is electrically connected to the second data line, the second compensation voltage includes a second positive compensation voltage and a second negative compensation voltage, the second positive compensation voltage is less than the second positive data voltage, and the second negative compensation voltage is greater than the second negative data voltage; The display panel according to claim 5 .

7. the compensation module includes a plurality of first switching transistors and a plurality of second switching transistors, and gates of the plurality of first switching transistors and gates of the plurality of second switching transistors are electrically connected to a global control signal terminal; one of a source and a drain of the first switching transistor is electrically connected to the first compensation voltage output terminal, and the other of the source and the drain of the first switching transistor is electrically connected to one end of the first data line; one of the source and the drain of the second switching transistor is electrically connected to the second compensation voltage output terminal, and the other of the source and the drain of the second switching transistor is electrically connected to one end of the second data line; The display panel according to claim 6 .

8. the first switching transistor and the second switching transistor are turned off during the display period, and the first switching transistor and the second switching transistor are turned on during the blank period; The display panel according to claim 7 .

9. the blank period includes a first blank sub-period and a second blank sub-period, the first blank sub-period being adjacent to the second blank sub-period; wherein the first switching transistor and the second switching transistor are turned on during the first blank sub-period, and the first switching transistor and the second switching transistor are turned off during the second blank sub-period, or the first switching transistor and the second switching transistor are turned on during the second blank sub-period, and the first switching transistor and the second switching transistor are turned off during the first blank sub-period; The display panel according to claim 8 .

10. the compensation module includes a plurality of first switching transistors and a plurality of second switching transistors, gates of the plurality of first switching transistors electrically connected to a first control signal terminal, and gates of the plurality of second switching transistors electrically connected to a second control signal terminal; one of a source and a drain of the first switching transistor is electrically connected to the first compensation voltage output terminal, and the other of the source and the drain of the first switching transistor is electrically connected to one end of the first data line; one of a source and a drain of the second switching transistor is electrically connected to the second compensation voltage output terminal, and the other of the source and the drain of the second switching transistor is electrically connected to one end of the second data line; The display panel according to claim 6 .

11. the blank period includes a first blank sub-period, a second blank sub-period, and a third blank sub-period, and the second blank sub-period is located between the first blank sub-period and the third blank sub-period; the first switching transistor is turned on during the first blank sub-period and the second blank sub-period, the first switching transistor is turned off during the third blank sub-period, the second switching transistor is turned on during the second blank sub-period and the third blank sub-period, and the second switching transistor is turned off during the first blank sub-period; The display panel according to claim 10.

12. the blank period includes a plurality of first blank sub-periods and a plurality of second blank sub-periods, the first blank sub-periods and the second blank sub-periods alternate with each other; wherein the first switching transistor is turned on during a plurality of the first blank sub-periods, the first switching transistor is turned off during a plurality of the second blank sub-periods, the second switching transistor is turned on during a plurality of the second blank sub-periods, and the second switching transistor is turned off during a plurality of the first blank sub-periods. The display panel according to claim 10.

13. during the blank period, an on-time of the first switching transistor and an off-time of the second switching transistor are greater than an off-time of the first switching transistor and the second switching transistor; The display panel according to claim 9 .

14. The display device includes a housing and a display panel, and the screen displayed by the display panel includes a first display screen and a second display screen that are displayed consecutively, and the display panel includes: a plurality of sub-pixels; a plurality of scanning lines arranged along a first direction, the plurality of scanning lines being electrically connected to a plurality of the sub-pixels, respectively; a plurality of data lines, the plurality of data lines being arranged along a second direction, the first direction intersecting the second direction, the plurality of data lines being electrically connected to a plurality of the sub-pixels, respectively, and the plurality of data lines inputting first data voltages to the sub-pixels during a display period of the first display screen, the polarity of the first data voltages being opposite to the polarity of second data voltages to the sub-pixels during a display period of the second display screen; a compensation module electrically connected to one ends of the plurality of data lines, the compensation module being used to input a first compensation voltage to the sub-pixel during a blank period of the first display screen and a second compensation voltage to the sub-pixel during a blank period of the second display screen, the polarity of the first compensation voltage being the same as the polarity of the first data voltage, and the polarity of the second compensation voltage being the same as the polarity of the second data voltage; wherein the first compensation voltage is non-zero and the second compensation voltage is non-zero; Display device.

15. the compensation module includes a compensation voltage output terminal, the compensation voltage output terminal is electrically connected to one ends of the plurality of data lines, and the compensation voltage output terminal is used to output the first compensation voltage and the second compensation voltage; an absolute value of the first compensation voltage is equal to or less than an absolute value of the first data voltage, and an absolute value of the second compensation voltage is equal to or greater than an absolute value of the second data voltage; The display device according to claim 14.

16. The compensation module includes a plurality of switching transistors, gates of the plurality of switching transistors are electrically connected to a global control signal terminal; one of the source and drain of the switching transistor is electrically connected to the compensation voltage output terminal, and the other of the source and drain of the switching transistor is electrically connected to one end of the data line; The display device according to claim 15.

17. During the blank period, the on-time of the switching transistor is equal to or longer than the off-time thereof. The display device according to claim 16.

18. the plurality of data lines include a plurality of first data lines and a plurality of second data lines, the plurality of first data lines and the plurality of second data lines being alternately arranged along the second direction; the first data voltages include a first positive data voltage and a first negative data voltage, and during the display period of the first display screen, the data voltage input to the sub-pixel through the first data line is the first positive data voltage, and the data voltage input to the sub-pixel through the second data line is the first negative data voltage; the second data voltages include a second positive data voltage and a second negative data voltage, and during the display period of the second display screen, the data voltage input to the sub-pixel via the first data line is the second negative data voltage, and the data voltage input to the sub-pixel via the second data line is the second positive data voltage. The display device according to claim 14.

19. the compensation module includes a first compensation voltage output terminal and a second compensation voltage output terminal, the first compensation voltage output terminal is electrically connected to the first data line, the first compensation voltage includes a first positive compensation voltage and a first negative compensation voltage, the first positive compensation voltage is less than or equal to the first positive data voltage, and the first negative compensation voltage is greater than or equal to the first negative data voltage; the second compensation voltage output terminal is electrically connected to the second data line, the second compensation voltage includes a second positive compensation voltage and a second negative compensation voltage, the second positive compensation voltage is less than the second positive data voltage, and the second negative compensation voltage is greater than the second negative data voltage; 19. The display device according to claim 18.

20. the compensation module includes a plurality of first switching transistors and a plurality of second switching transistors, and gates of the plurality of first switching transistors and gates of the plurality of second switching transistors are electrically connected to a global control signal terminal; one of a source and a drain of the first switching transistor is electrically connected to the first compensation voltage output terminal, and the other of the source and the drain of the first switching transistor is electrically connected to one end of the first data line; one of the source and the drain of the second switching transistor is electrically connected to the second compensation voltage output terminal, and the other of the source and the drain of the second switching transistor is electrically connected to one end of the second data line; 20. The display device according to claim 19.

Images