Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising a base and a driving circuit layer disposed on the base, the base including a display area 100 and a non-display area 200, the driving circuit layer including a pixel driving circuit PE located in the display area 100, a gate driving circuit located in the non-display area 200, and at least one initial power supply line, at least a portion of the initial power supply line extending along a first direction D1, the gate driving circuit configured to supply a driving signal to the pixel driving circuit PE, the initial power supply line configured to supply an initial signal to the pixel driving circuit PE, and an orthogonal projection at the base of the at least one initial power supply line at least partially overlapping with an orthogonal projection at the base of the gate driving circuit.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, but is not limited thereto, and more particularly to display substrates and display devices. [Background technology]

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminance, wide viewing angle, high contrast ratio, low power consumption, extremely fast response speed, light weight, flexibility, and low cost. With the continuous development of display technology, flexible displays that use OLEDs or QLEDs as light-emitting devices and thin film transistors (TFTs) for signal control have become the mainstream products in the current display field. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail in the text, which is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, the present disclosure provides a display substrate, comprising: a base; and a driving circuit layer disposed on the base, the base including a display area and a non-display area, the driving circuit layer including a pixel driving circuit located in the display area, a gate driving circuit located in the non-display area, and at least one initial power supply line, at least a portion of the initial power supply line extending along a first direction; the gate drive circuit is configured to supply a drive signal to a pixel drive circuit, and the initial power supply line is configured to supply an initial signal to the pixel drive circuit; An orthogonal projection of at least one of the initial power supply lines at a base and an orthogonal projection of the gate drive circuit at a base at least partially overlap.

[0005] In an exemplary embodiment, the gate drive circuit comprises a plurality of drive circuits arranged along a second direction, the first direction intersecting the second direction; An orthogonal projection of at least one of the initial power supply lines at a base and an orthogonal projection of one of the plurality of drive circuits at a base that is closer to the display area at least partially overlap each other.

[0006] In an exemplary embodiment, the pixel driving circuit comprises an emission transistor and a writing transistor, the plurality of driving circuits comprises an emission driving circuit and a scanning driving circuit, the emission driving circuit is electrically connected to the emission transistor, the scanning driving circuit is electrically connected to the writing transistor, and the scanning driving circuit is located on a side of the emission driving circuit closer to a display area; The orthogonal projection of the at least one initial feed line at its base and the orthogonal projection of the scan drive circuit at its base at least partially overlap.

[0007] In an exemplary embodiment, the pixel drive circuit comprises an emission transistor, a write transistor, and a control transistor, the plurality of drive circuits comprise an emission drive circuit, a scan drive circuit, and a control drive circuit, the emission drive circuit is electrically connected to the emission transistor, the scan drive circuit is electrically connected to the write transistor, and the control drive circuit is electrically connected to the control transistor, the write transistor and the control transistor are of opposite transistor types, and the emission drive circuit and the control drive circuit are located on a side of the scan drive circuit away from a display area; The orthogonal projection of at least one of the initial feed lines at a base and the orthogonal projection of the scan drive circuit at a base at least partially overlap.

[0008] In an exemplary embodiment, the at least one initial power feed line includes a first initial power feed line through an Nth initial power feed line, where N is a positive integer greater than or equal to 1; When N is 2 or more, the N initial feed lines are arranged along the second direction, and the orthogonal projections of the bases of the K adjacent initial feed lines away from the display area and the orthogonal projections of the K adjacent initial feed lines at the bases of the scan drive circuit at least partially overlap, and K is a positive integer less than or equal to N.

[0009] In an exemplary embodiment, the driving circuit layer further includes a first clock signal line, a second clock signal line, a first initial signal line, a first power supply line, and a second power supply line located in a non-display area, wherein at least a portion of the first clock signal line, the second clock signal line, the first initial signal line, the first power supply line, and the second power supply line extends along a first direction; The scanning driving circuits are electrically connected to a first clock signal line, a second clock signal line, a first power supply line, a second power supply line, and a first initial signal line, respectively; The second clock signal line is located on the side of the first clock signal line away from the display area, the second power supply line is located on the side of the first clock signal line closer to the display area, the first initial signal line is located on the side of the second power supply line closer to the display area, the first power supply line is located on the side of the first initial signal line closer to the display area, and the at least one initial power supply line is located on the side of the first power supply line closer to the display area.

[0010] In an exemplary embodiment, the driving circuit layer further includes a second initial signal line located in a non-display area, and at least a portion of the second initial signal line extends along a first direction; The light emitting driving circuit is electrically connected to the second initial signal line, and the second initial signal line is located between the second power line and the first initial signal line.

[0011] In an exemplary embodiment, the driving circuit layer further includes a first output signal line and a second output signal line located in a non-display area, and at least a portion of the first output signal line and the second output signal line extends along a second direction; The first output signal lines are located on a side of the scanning driving circuit close to the display area, and are electrically connected to the scanning driving circuit and the pixel driving circuit, respectively; The second output signal lines pass through the scanning driving circuit and are electrically connected to the pixel driving circuit and one of the light emitting driving circuit and the control driving circuit, respectively.

[0012] In an exemplary embodiment, the driving circuit layer further includes a first output connection line and a second output connection line located in a display region and a non-display region, and at least a portion of the first output connection line and the second output connection line extends along a second direction; the first output connection lines are electrically connected to first output signal lines and pixel driving circuits, respectively; The second output connection lines are electrically connected to second output signal lines and pixel driving circuits, respectively.

[0013] In an exemplary embodiment, when N=2, the driving circuit layer further includes a third output connection line and a fourth output connection line, and at least a portion of the third output connection line and the fourth output connection line extends along the second direction; the third output connection lines are electrically connected to the first initial power supply line and the pixel driving circuit, The fourth output connection lines are electrically connected to the second initial power supply line and the pixel driving circuit, respectively.

[0014] In an exemplary embodiment, the boundary of the display area includes an arc-shaped boundary, and the non-display area located outside the arc-shaped boundary is referred to as a rounded corner area; the scan driving circuit comprises a plurality of scan shift registers and a plurality of dummy scan shift registers, the plurality of scan shift registers being cascade-connected, and the plurality of dummy scan shift registers being interposed between the plurality of scan shift registers; At least some of the dummy scan shift registers are located in the rounded corner areas.

[0015] In an exemplary embodiment, the scan shift register comprises a plurality of transistors and a plurality of capacitors; An orthogonal projection at the base of the initial feed line overlapping the scan drive circuit at least partially overlaps an orthogonal projection at the base of the plurality of capacitors.

[0016] In an exemplary embodiment, the distance between the boundary of the initial power supply line that overlaps the scan drive circuit and the display area is smaller than the distance between the boundary of at least one capacitor of the plurality of capacitors and the display area.

[0017] In an exemplary embodiment, the number of transistors in the dummy scan shift register is less than or equal to the number of transistors in the scan shift register; The width of the dummy scan shift register is equal to or less than the width of the scan shift register.

[0018] In an exemplary embodiment, the distance between the boundary of the second clock signal line located on the dummy scan shift register side away from the display area and the boundary of the at least one initial power supply line that is closest to the display area close to the display area is smaller than the distance between the boundary of the second clock signal line located on the scan shift register side away from the display area and the boundary of the at least one initial power supply line that is closest to the display area close to the display area.

[0019] In an exemplary embodiment, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are stacked in order; the semiconductor layer includes active layers of at least a plurality of transistors; the first conductive layer includes at least control poles of a plurality of transistors and first plates of a plurality of capacitors; the second conductive layer includes at least second plates of a plurality of capacitors, a first output signal line, and a third output signal line; the third conductive layer includes at least a second power supply line, a first electrode and a second electrode of at least one transistor, and a fourth output signal line; The fourth conductive layer includes at least a first initial signal line, a second initial signal line, and a first power line.

[0020] In an exemplary embodiment, the drive circuit layer further includes a fifth conductive layer located away from the base of the fourth conductive layer; The fifth conductive layer includes at least a first output connection line, a second output connection line, a third output connection line and a fourth output connection line.

[0021] In an exemplary embodiment, the initial power supply line has a single-layer structure, and the initial power supply line is located on a fourth conductive layer.

[0022] In an exemplary embodiment, the initial feedline includes a first initial sub-segment and a second initial sub-segment connected to each other, wherein an orthogonal projection of the first initial sub-segment at a base and an orthogonal projection of the second initial sub-segment at a base at least partially overlap; The first initial sub-segment is located on a third conductive layer, and the second initial sub-segment is located on a fourth conductive layer.

[0023] In an exemplary embodiment, the first clock signal line and the second clock signal line have a single-layer structure, and the first clock signal line and the second clock signal line are located on a fourth conductive layer.

[0024] In an exemplary embodiment, a clock signal line includes a first clock sub-segment and a second clock sub-segment connected to each other, the clock signal line including a first clock signal line and a second clock signal line, wherein an orthogonal projection at a base of the first clock sub-segment and an orthogonal projection at a base of the second clock sub-segment at least partially overlap; The first clock sub-segment is located on a third conductive layer, and the second clock sub-segment is located on a fourth conductive layer near the base.

[0025] In an exemplary embodiment, the second output signal line has a single-layer structure, and the second output signal line is located on a second conductive layer.

[0026] In an exemplary embodiment, the drive circuit layer further includes a sixth conductive layer located between the second conductive layer and the third conductive layer; the second output signal line includes a plurality of first output subsegments and a plurality of second output subsegments, wherein adjacent first output subsegments are electrically connected via the second output subsegments, adjacent second output subsegments are electrically connected via the first output subsegments, an orthogonal projection at a base of a second output subsegment at least partially overlaps with an orthogonal projection at a base of the first output subsegment to which it is electrically connected, and an orthogonal projection at a base of a first output subsegment at least partially overlaps with an orthogonal projection at a base of the second output subsegment to which it is electrically connected; The first output sub-segment is located on a second conductive layer, and the second output sub-segment is located on a sixth conductive layer.

[0027] In a second aspect, the present disclosure further provides a display device comprising the above-described display substrate.

[0028] Other aspects will be understood after reading and understanding the drawings and detailed description. [Brief explanation of the drawings]

[0029] The drawings are intended to provide a further understanding of the technical solution of the present disclosure, to be a part of the specification, and to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solution of the present disclosure. The shapes and sizes of each part in the drawings do not reflect actual proportions, and are intended to schematically explain the contents of the present disclosure. [Figure 1A] FIG. 2 is a structural schematic diagram of a display substrate. [Figure 1B] FIG. 2 is a schematic diagram showing the division of a display substrate into regions. [Figure 2] FIG. 10 is a structural schematic diagram of another display substrate. [Figure 3A] FIG. 2 is a schematic diagram of an equivalent circuit of one pixel driving circuit. [Figure 3B] FIG. 3B is an operation timing diagram of the pixel driving circuit according to FIG. 3A. [Figure 4A] FIG. 10 is a schematic equivalent circuit diagram of another pixel driving circuit. [Figure 4B] FIG. 4B is an operation timing diagram of the pixel driving circuit according to FIG. 4A. [Figure 5A] 1 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure; [Figure 5B] FIG. 5B is a partial schematic diagram of the display substrate according to FIG. 5A; [Figure 6A] 2 is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure; [Figure 6B] FIG. 6B is a partial schematic diagram of the display substrate according to FIG. 6A; [Figure 7A] FIG. 2 is an equivalent circuit diagram of a shift register on a display substrate. [Figure 7B] FIG. 7B is a timing diagram of the shift register according to FIG. 7A. [Figure 8A] FIG. 10 is an equivalent circuit diagram of a dummy scanning shift register. [Figure 8B] FIG. 10 is an equivalent circuit diagram of another dummy scanning shift register. [Figure 9A] FIG. 2 is a schematic diagram of one part of a display substrate. [Figure 9B] 9B is a partial schematic diagram of the rounded corner region of the display substrate shown in FIG. 9A. FIG. [Figure 10A] FIG. 2 is another schematic view of a part of the display substrate. [Figure 10B] FIG. 2 is a further partial schematic view of the display substrate. [Figure 11] 10C is a partial schematic view of the rounded corner region of the display substrate shown in FIGS. 10A and 10B. FIG. [Figure 12] FIG. 10 is a partial schematic view of another display substrate. [Figure 13] FIG. 10 is a structural schematic diagram of a second output signal line. [Figure 14] FIG. 9B is a schematic diagram of the semiconductor layer of FIG. 9A after patterning. [Figure 15] FIG. 9B is a schematic diagram of the first conductive layer pattern of FIG. 9A. [Figure 16] FIG. 9B is a schematic diagram of FIG. 9A after the first conductive layer pattern is formed. [Figure 17] FIG. 9B is a schematic diagram of the second conductive layer pattern of FIG. 9A. [Figure 18] 9B is a schematic diagram of FIG. 9A after the second conductive layer pattern is formed. [Figure 19]FIG. 9B is a schematic diagram of FIG. 9A after the third insulating layer pattern is formed. [Figure 20] FIG. 9B is a schematic diagram of the third conductive layer pattern of FIG. 9A. [Figure 21] 9B is a schematic diagram of FIG. 9A after the third conductive layer pattern is formed. [Figure 22] FIG. 9B is a schematic diagram of FIG. 9A after the fourth insulating layer pattern is formed. [Figure 23] FIG. 9B is a schematic diagram of the fourth conductive layer of FIG. 9A. [Figure 24] FIG. 9B is a schematic diagram of FIG. 9A after the fourth conductive layer is formed. [Figure 25] FIG. 10B is a schematic diagram of the semiconductor layer of FIG. 10A after patterning. [Figure 26] FIG. 10B is a schematic diagram of the first conductive layer pattern of FIG. 10A. [Figure 27] FIG. 10B is a schematic diagram of FIG. 10A after the first conductive layer pattern is formed. [Figure 28] FIG. 10B is a schematic diagram of FIG. 10A after the third insulating layer pattern has been formed. [Figure 29] FIG. 10B is a schematic diagram of the third conductive layer pattern of FIG. 10A. [Figure 30] 10B is a schematic diagram of FIG. 10A after the third conductive layer pattern is formed. [Figure 31] FIG. 10B is a schematic diagram of the fourth conductive layer of FIG. 10A. [Figure 32] FIG. 10B is a schematic diagram of FIG. 10A after the fourth conductive layer is formed. [Figure 33] FIG. 10C is a schematic diagram of the semiconductor layer of FIG. 10B after patterning. [Figure 34] FIG. 10C is a schematic diagram of the first conductive layer pattern of FIG. 10B. [Figure 35] FIG. 10C is a schematic diagram of the first conductive layer pattern of FIG. 10B after formation. [Figure 36] FIG. 10C is a schematic diagram of FIG. 10B after the third insulating layer pattern has been formed. [Figure 37] FIG. 10C is a schematic diagram of the third conductive layer pattern of FIG. 10B. [Figure 38] FIG. 10C is a schematic diagram of FIG. 10B after the third conductive layer pattern is formed. [Figure 39] FIG. 10C is a schematic diagram of the fourth conductive layer of FIG. 10B. [Figure 40] FIG. 10C is a schematic diagram of FIG. 10B after the fourth conductive layer is formed. DETAILED DESCRIPTION OF THE INVENTION

[0030] To clarify the objectives, technical solutions, and advantages of the present disclosure, the following detailed description of the embodiments of the present disclosure will be provided with reference to the accompanying drawings. The embodiments may be implemented in many different forms. As those skilled in the art can readily understand, the methods and contents may be embodied in various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the following embodiments. Where there is no conflict, the embodiments and features of the embodiments of the present disclosure may be combined with each other. To maintain clarity and conciseness in the following description of the embodiments of the present disclosure, the present disclosure will omit detailed descriptions of some known functions and components. The drawings of the embodiments of the present disclosure only relate to the structures of the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0031] The proportions in the drawings in this disclosure may be used as a reference for actual processes, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of subpixels in each pixel are also not limited to the numbers shown in the drawings. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0032] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and are not intended to limit the number of components.

[0033] For convenience, the positions of components in this specification are described with reference to the drawings using terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer." However, this is intended to simplify and explain the specification, and is not intended to indicate or suggest that the described devices or elements have a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationships of components may be appropriately changed depending on the direction in which each component is described. Therefore, the terms described in the specification may not be limited and may be appropriately changed as the case may be.

[0034] In this specification, unless otherwise clearly specified and limited, the terms "attach," "couple," and "connect" should be understood in a broad sense. For example, they may be fixedly connected, detachably connected, or integrally connected. They may be mechanically connected or electrically connected. They may be directly connected, indirectly connected via a linker, or internally connected between two elements. Those skilled in the art can understand the specific meanings of the above terms in the present disclosure according to the specific circumstances.

[0035] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, channel region, and source electrode. In this specification, the channel region refers to a region through which a current mainly flows.

[0036] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. The functions of "source electrode" and "drain electrode" may be interchangeable, such as when using transistors with opposite polarity or when the current direction during operation in a circuit changes. Therefore, in this specification, "source electrode" and "drain electrode" may be interchangeable.

[0037] In this specification, "electrically connected" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of "elements having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0038] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and includes a state in which the angle is between -5° and 5°. "Perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and includes a state in which the angle is between 85° and 95°.

[0039] In this specification, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0040] As used herein, "deposited in the same layer" refers to a structure in which two or more types of structures are patterned by the same patterning process, and the materials may be the same or different. For example, the materials forming the precursors of multiple types of structures deposited in the same layer may be the same, and the materials ultimately formed may be the same or different.

[0041] In this disclosure, "about" refers to a case where the boundary is not precisely defined, but rather allows for a numerical value within the tolerances of process and measurement.

[0042] Display substrates have advantages such as high resolution, fast response speed, high brightness, and high aperture ratio, and have the prospect of widespread application. To achieve a better visual experience, narrow frames are the main development direction for displays. Display substrates are equipped with driving circuits that drive pixel driving circuits to emit light, thereby realizing a display. Display substrates cannot achieve narrow frames.

[0043] Fig. 1A is a schematic diagram of the structure of a display substrate, Fig. 1B is a schematic diagram of the division of the display substrate, and Fig. 2 is a schematic diagram of the structure of another display substrate. As shown in Fig. 1A, Fig. 1B and Fig. 2, the display substrate may include at least a display area 100 and a non-display area 200, the boundary of the display area 100 includes at least one arc-shaped boundary C, and the non-display area includes a rounded corner area CR located outside the arc-shaped boundary C.

[0044] In an exemplary embodiment, the shape of the boundary of the display area may be a rounded rectangle, and this disclosure is not limited thereto.

[0045] The display substrate according to the present disclosure can realize large-angle bending of four sides, improve the adhesion wrinkle problem of the module, and increase the yield rate of the product.

[0046] 1A and 2, the display area may include pixel units P arranged in an array, at least one pixel unit including at least three sub-pixels, at least one sub-pixel including a pixel driving circuit and a light-emitting device, and the pixel driving circuit located in the same sub-pixel is electrically connected to the light-emitting device and configured to drive the light-emitting device to emit light.

[0047] In an exemplary embodiment, the pixel unit may include a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel, or may include a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, and the present disclosure is not limited thereto.

[0048] In exemplary embodiments, the shape of the subpixels in a pixel unit may be rectangular, rhombic, pentagonal, or hexagonal. If a pixel unit includes three subpixels, the three subpixels may be arranged in a horizontally parallel, vertically parallel, or square pattern. If a pixel unit includes four subpixels, the four subpixels may be arranged in a horizontally parallel, vertically parallel, or square pattern. The present disclosure is not limited thereto.

[0049] In an exemplary embodiment, the light-emitting device may be an organic light-emitting transistor (OLED) or a quantum dot light-emitting diode (QLED). The OLED may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0050] In an exemplary embodiment, the organic light-emitting layer may include a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL), which are stacked one on top of the other. In exemplary embodiments, the hole injection layers of all subpixels may be connected to a common layer, the electron injection layers of all subpixels may be connected to a common layer, the hole transport layers of all subpixels may be connected to a common layer, the electron transport layers of all subpixels may be connected to a common layer, the hole blocking layers of all subpixels may be connected to a common layer, the emissive layers of adjacent subpixels may overlap slightly or may be separated, and the electron blocking layers of adjacent subpixels may overlap slightly or may be separated.

[0051] In an exemplary embodiment, as shown in FIG. 1A, non-display area 200 may include a binding area located on one side of display area 100 and a frame area located on the other side of display area 100.

[0052] In an exemplary embodiment, the binding region may include a lead region, a fold region, and a composite circuit region arranged in sequence along a direction away from the display region, with the lead region connected to the display region 100, the fold region connected to the lead region, and the composite circuit region connected to the fold region.

[0053] In an exemplary embodiment, a plurality of lead-out lines may be installed in the lead area, with one end of some of the lead-out lines connected to a plurality of data fan-out lines in the display area 100, one end of other of the lead-out lines connected to a plurality of data lines in the display area 100, and the other ends of the lead-out lines connected to integrated circuits in the composite circuit area across the folding area, so that the integrated circuits apply data signals to the data lines via the lead-out lines and the data fan-out lines.

[0054] In an exemplary embodiment, the folding region may be bent with a curvature and the surface of the composite circuit region may be inverted, i.e., the upward-facing surface of the composite circuit region may be converted to a downward-facing surface by bending the folding region. In an exemplary embodiment, when the folding region is folded, the composite circuit region may overlap the display region 100.

[0055] In an exemplary embodiment, the composite circuit area may include an anti-static area, a driver chip area, and a binding pin area, and an integrated circuit (abbreviated as IC) may be binding-connected to the driver chip area, and a flexible printed circuit (abbreviated as FPC) may be binding-connected to the binding pin area.

[0056] In an exemplary embodiment, the integrated circuit can generate drive signals required to drive the sub-pixels and provide the drive signals to the sub-pixels in the display area 100. For example, the drive signals may be data signals that drive the light emission brightness of the sub-pixels. In an exemplary embodiment, the integrated circuit may be binding-connected to the driver chip area by an anisotropic conductive film or other means. In an exemplary embodiment, pads including a plurality of pins (PINs) may be provided in the binding pin area, and the flexible printed circuit board may be binding-connected to the pads.

[0057] In an exemplary embodiment, as shown in Figure 2, the display substrate may include a timing controller, a data driving circuit, a gate driving circuit, and a pixel array. The timing controllers are respectively connected to the data driving circuit and the gate driving circuit, the data driving circuits are respectively connected to the data signal lines Data, and the gate driving circuits are respectively connected to the gate lines. The gate lines may include one or more of the emission signal lines EM, the scanning signal lines Gate, and Scan. The pixel driving circuits may respectively be connected to the gate lines and the data signal lines.

[0058] In an exemplary embodiment, the timing controller may provide gray values ​​and control signals conforming to the specifications of the data driving circuit to the data driving circuit, provide clock signals, start signals, etc. conforming to the specifications of the gate driving circuit to the gate driving circuit, and provide clock signals, stop firing signals, etc. conforming to the specifications of the emission driving circuit to the emission driving circuit. The data driving circuit may generate data voltages to be provided to data signal lines using the gray values ​​and control signals received from the timing controller. For example, the data driving circuit may sample gray values ​​using a clock signal and apply data voltages corresponding to the gray values ​​to the data signal lines in units of pixel rows.

[0059] In an exemplary embodiment, the gate drive circuit can generate a scan signal to be provided to the gate line by receiving a clock signal, a start signal, etc. from a timing controller. For example, the gate drive circuit can sequentially provide a signal having a turn-on level pulse to the gate line. For example, the gate drive circuit can be configured in the form of a shift register, and can generate a scan signal by sequentially transferring a start signal, provided in the form of a turn-on level pulse, to the next stage circuit under the control of a clock signal.

[0060] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.

[0061] 3A is an equivalent circuit diagram of one pixel driving circuit according to an exemplary embodiment. As shown in FIG. 3A, the pixel driving circuit may include seven transistors (first transistor M1 to seventh transistor M7), one capacitor C, and eight signal lines (a data signal line Data, a scanning signal line Gate, a reset signal line Reset, an emission signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a high-level power supply line VDD, and a low-level power supply line VSS).

[0062] As shown in FIG. 3A, the first plate of the capacitor C is connected to the high-level power supply line VDD, and the second plate of the capacitor C is connected to the first node N1. The control electrode of the first transistor M1 is connected to the reset signal line Reset, the first electrode of the first transistor M1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor M1 is connected to the first node N1. The control electrode of the second transistor M2 is connected to the scan signal line Gate, the first electrode of the second transistor M2 is connected to the first node N1, and the second electrode of the second transistor M2 is connected to the second node N2. The control electrode of the third transistor M3 is connected to the first node N1, the first electrode of the third transistor M3 is connected to the second node N2, and the second electrode of the third transistor M3 is connected to the third node N3. The control electrode of the fourth transistor M4 is connected to the scan signal line GATE, the first electrode of the fourth transistor M4 is connected to the data signal line Data, and the second electrode of the fourth transistor M4 is connected to the second node N2. The control electrode of the fifth transistor M5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor M5 is connected to the high-level power supply line VDD, and the second electrode of the fifth transistor M5 is connected to the second node N2. The control electrode of the sixth transistor M6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light-emitting device L. The control electrode of the seventh transistor M7 is connected to the reset signal line Reset or the scanning signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device L, and the second electrode of the light-emitting device L is connected to the low-level power supply line VSS. Figure 3A illustrates the control electrode of the seventh transistor M7 and the reset signal line Reset as an example.

[0063] In an exemplary embodiment, the first transistor M1 may be referred to as a node reset transistor. When an active level signal is input to the reset signal line Reset, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.

[0064] In an exemplary embodiment, the second transistor M2 may be referred to as a compensation transistor. When an active level signal is input to the control signal line SL, the second transistor M2 transmits the signal at the second node N2 to the first node N1 and compensates for the signal at the first node N1.

[0065] In an exemplary embodiment, the third transistor M3 may be referred to as a drive transistor. The third transistor M3 determines the drive current flowing between the high-level power supply line VDD and the low-level power supply line VSS according to the potential difference between the control pole and the first pole.

[0066] In an exemplary embodiment, the fourth transistor M4 may be referred to as a write transistor, etc. When an active level signal is input to the scan signal line Gate, the fourth transistor M4 inputs the data voltage of the data signal line Data to the third node N3.

[0067] In an exemplary embodiment, the fifth transistor M5 and the sixth transistor M6 may be referred to as light-emitting transistors. When an active-level signal is input to the light-emitting signal line EM, the fifth transistor M5 and the sixth transistor M6 form a driving current path between the high-level power supply line VDD and the low-level power supply line VSS, thereby causing the light-emitting device to emit light.

[0068] In an exemplary embodiment, the seventh transistor M7 may be referred to as an anode reset transistor. When an active level signal is input to the reset signal line Reset or the scanning signal line Gate, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light emitting device L to initialize the charge amount of the first electrode of the light emitting device L.

[0069] In an exemplary embodiment, the signal on the high-level power supply line VDD is subsequently supplied as a high-level signal, and the signal on the low-level power supply line VSS is subsequently supplied as a low-level signal.

[0070] According to the characteristics of the transistor, the transistor can be classified as an N-type transistor or a P-type transistor. If the transistor is a P-type transistor, the on-voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltage), and the off-voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltage). If the transistor is an N-type transistor, the on-voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltage), and the off-voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltage).

[0071] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display panel, and improve the yield rate of the product. In some possible embodiments, the first transistor M1 to the seventh transistor M7 may include P-type transistors and N-type transistors.

[0072] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be low-temperature polysilicon film transistors, oxide film transistors, or both low-temperature polysilicon film transistors and oxide film transistors. The active layer of the low-temperature polysilicon film transistor is made of low-temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide film transistor is made of oxide semiconductor (oxide). The low-temperature polysilicon film transistor has advantages such as high mobility and fast charging, while the oxide film transistor has advantages such as low leakage current. By integrating the low-temperature polysilicon film transistors and the oxide film transistors on a single display substrate to form a low-temperature polycrystalline oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized to achieve low-frequency driving, reduce power consumption, and improve display properties.

[0073] In an exemplary embodiment, if the display substrate is an LTPO display substrate, the first transistor T1 and the second transistor T2 may be N-type transistors, and the remaining transistors may be P-type transistors. If the display substrate is an LTPS display substrate, the first transistor M1 to the seventh transistor M7 are P-type transistors.

[0074] In an exemplary embodiment, when the display substrate is an LTPO display substrate, if the first transistor T1 and the second transistor T2 are N-type transistors, the first transistor T1 and the second transistor T2 may also be referred to as control transistors, and similarly, the N-type transistors in the pixel driving circuit may also be referred to as control transistors.

[0075] 3B is an operation timing diagram of the pixel driving circuit according to FIG. 3A, and FIG. 3B illustrates an example in which all the transistors in FIG. 3A are P-type transistors. Hereinafter, an exemplary embodiment of the present disclosure will be described using the operation process of the pixel driving circuit shown in FIG. 3B. In an exemplary embodiment, the operation process of the pixel driving circuit may include the following first stage A1, second stage A2, and third stage A3.

[0076] The first stage A1 is called the reset stage. The signals on the scan signal line Gate and the emission signal line EM are all high-level signals, and the signal on the reset signal line Reset is low-level signal. When the signal on the reset signal line Reset is high, the first transistor M1 is turned on, and the signal on the first initialization signal line INIT1 is supplied to the first node N1, initializing the capacitor C and clearing the original data voltage on the capacitor C. The seventh transistor M7 is turned on, and the initialization voltage on the second initialization signal line INIT2 is supplied to the first terminal of the light-emitting device L, initializing (resetting) the first terminal of the light-emitting device L and clearing the pre-stored voltage therein, completing the initialization. When the signals on the scan signal line Gate and the emission signal line EM are high, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off, and the light-emitting device L does not emit light at this stage.

[0077] The second phase A2 is referred to as a data write phase or threshold compensation phase. The scan signal line Gate is at a low level, the signals on the emission signal line EM and the reset signal line Reset are at high levels, and the data signal line Data outputs a data voltage. In this phase, the first node N1 is at a low level, so the third transistor M3 is turned on. The signal on the scan signal line Gate is at a low level, so the second transistor T2 and the fourth transistor M4 are turned on. With the second transistor M2 and the fourth transistor M4 turned on, the data voltage output from the data signal line Data is provided to the first node N1 via the second node N, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output from the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage at the first node N1 reaches Vd-|Vth|. Vd is the data voltage output from the data signal line Data, and Vth is the threshold voltage of the third transistor M3, which ensures that the light emitting device L does not emit light. The signal on the reset signal line Reset is a high-level signal, so the first transistor M1 is turned off. The signal on the emission signal line EM is a high-level signal, so the fifth transistor M5 and the sixth transistor M6 are turned off.

[0078] The third phase A3 is called the light-emitting phase. The signals on the scan signal line Gate and the reset signal line Reset are high, and the signal on the light-emitting signal line EM is low. When the signal on the light-emitting signal line EM is low, the fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output from the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, causing the light-emitting device L to emit light.

[0079] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is expressed by the following formula: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2 In the formula, I is the driving current flowing through the third transistor M3, i.e., the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the control pole and the first pole of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output from the data signal line Data, and Vdd is the data voltage output from the high-level power supply line VDD.

[0080] 4A is a schematic equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment. As shown in FIG. 4A, the pixel driving circuit may include eight transistors (first transistor M1 to eighth transistor M8), one capacitor C, and nine signal lines (a data signal line Data, a control signal line Scan, a scanning signal line Gate, a reset signal line Reset, an emission signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a high-level power supply line VDD, and a low-level power supply line VSS).

[0081] In an exemplary embodiment, the pixel driving circuit according to FIG. 4A is applied to an LTPO display substrate.

[0082] In an exemplary embodiment, the first plate of the capacitor C is connected to the high-level power supply line VDD, and the second plate of the capacitor C is connected to the first node N1. The control pole of the first transistor M1 is connected to the reset signal line Reset, the first pole of the first transistor M1 is connected to the first initial signal line INIT1, and the second pole of the first transistor M1 is connected to the fourth node N4. The control pole of the second transistor M2 is connected to the scan signal line Gate, the first pole of the second transistor M2 is connected to the fourth node N4, and the second pole of the second transistor M2 is connected to the second node N2. The control pole of the third transistor M3 is connected to the first node N1, the first pole of the third transistor M3 is connected to the second node N2, and the second pole of the third transistor M3 is connected to the third node N3. The control pole of the fourth transistor M4 is connected to the scan signal line Gate, the first pole of the fourth transistor M4 is connected to the data signal line Data, and the second pole of the fourth transistor M4 is connected to the third node N3. The control electrode of the fifth transistor M5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor M5 is connected to the high-level power supply line VDD, and the second electrode of the fifth transistor M5 is connected to the third node N3. The control electrode of the sixth transistor M6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the second node N2, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light-emitting device L. The control electrode of the seventh transistor M7 is connected to the reset signal line Reset, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device L, and the second electrode of the light-emitting device L is connected to the low-level power supply line VSS. The control electrode of the eighth transistor M8 is connected to the control signal line SCAN, the first electrode of the eighth transistor M8 is connected to the first node N1, and the second electrode of the eighth transistor M8 is connected to the fourth node N4.

[0083] In an exemplary embodiment, the control pole of the seventh transistor M7 may further be connected to the scanning signal line Gate, the first pole of the seventh transistor M7 is connected to the second initial signal line INIT2, the second pole of the seventh transistor M7 is connected to the first pole of the light-emitting device L, and the second pole of the light-emitting device L is connected to the low-level power supply line VSS.

[0084] In an exemplary embodiment, the first transistor M1 may be referred to as a node reset transistor. When an active level signal is input to the reset signal line RESET, the first transistor M1 transmits an initialization voltage to the first node N1 to initialize the charge amount of the first node N1.

[0085] In an exemplary embodiment, the eighth transistor M8 may be referred to as a compensation reset transistor. When an active level signal is input to the control signal line Scan, the eighth transistor M8 transmits the signal at the fourth node N4 to the first node N1 to initialize the charge amount at the first node N1 and perform threshold compensation for the third transistor M3.

[0086] In an exemplary embodiment, the second transistor M2 may be referred to as a compensation transistor. When an active level signal is input to the scanning signal line Gate, the second transistor M2 writes the signal at the second node N2 to the fourth node N4.

[0087] In an exemplary embodiment, the third transistor M3 may be referred to as a drive transistor. The third transistor M3 determines the drive current flowing between the high-level power supply terminal VDD and the low-level power supply terminal VSS according to the potential difference between the control pole and the first pole.

[0088] In an exemplary embodiment, the fourth transistor M4 may be referred to as a write transistor. When an active level signal is input to the scan signal line GATE, the fourth transistor M4 inputs the data voltage of the data signal line Data to the pixel driving circuit.

[0089] In an exemplary embodiment, the fifth transistor M5 and the sixth transistor M6 may be referred to as light-emitting transistors. When an active-level signal is input to the light-emitting signal line EM, the fifth transistor M5 and the sixth transistor M6 form a driving current path between the high-level power supply line VDD and the low-level power supply line VSS, thereby causing the light-emitting device to emit light.

[0090] In an exemplary embodiment, the seventh transistor M7 may be referred to as an anode reset transistor. When an active level signal is input to the reset signal line Reset or the scanning signal line Gate, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light emitting device L to initialize the charge amount of the first electrode of the light emitting device L.

[0091] In an exemplary embodiment, the signal on the high-level power supply line VDD is subsequently supplied as a high-level signal, and the signal on the low-level power supply line VSS is subsequently supplied as a low-level signal.

[0092] In an exemplary embodiment, the eighth transistor M8 is a metal oxide transistor and is an N-type transistor, and the first transistor M1 to the seventh transistor M7 are low-temperature polysilicon transistors and are P-type transistors.

[0093] In an exemplary embodiment, the eighth transistor M8 may be referred to as a control transistor.

[0094] In an exemplary embodiment, the eighth transistor M8 is an oxide transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.

[0095] 4B is an operation timing diagram of the pixel driving circuit according to FIG. 4A. Hereinafter, an exemplary embodiment of the present disclosure will be described with reference to the operation process of the pixel driving circuit shown in FIG. 4B. The operation process of the pixel driving circuit may include the following first step A1, second step A2, and third step A3.

[0096] The first stage A1 is referred to as the reset stage. The signals on the control signal line Scan, the light-emitting signal line EM, and the scan signal line Gate are all high-level signals, and the signal on the reset signal line Reset is low-level signal. When the signal on the reset signal line Reset is low-level signal, the first transistor M1 is turned on, and the signal on the first initialization signal line INIT1 is supplied to the fourth node N4. The seventh transistor M7 is turned on, and the initialization voltage on the second initialization signal line INIT2 is supplied to the first terminal of the light-emitting device L, initializing (resetting) the first terminal of the light-emitting device L, e.g., clearing the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting device L does not emit light. When the signal on the control signal line Scan is high-level signal, the eighth transistor M8 is turned on, and the signal on the fourth node N4 is supplied to the first node N1, initializing the capacitor C and clearing the original data voltage on the capacitor C. The signals on the scanning signal line Gate and the light emitting signal line EM are high level signals, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned off, and at this stage the light emitting device L does not emit light.

[0097] The second stage A2 is called a data writing stage or threshold compensation stage. The signal on the scan signal line Gate is low, the signals on the reset signal line Reset, the emission signal line EM, and the control signal line Scan are high, and the data signal line Data outputs a data voltage. In this stage, the first node N1 is low, so the third transistor M3 is turned on. The signal on the scan signal line Gate is low, so the second transistor M2 and the fourth transistor M4 are turned on. The signal on the control signal line Scan is high, so the eighth transistor M8 is turned on. With the second transistor M2, the fourth transistor M4, and the eighth transistor M8 turned on, the data voltage output from the data signal line Data is provided to the first node N1 via the third node N3, the turned-on third transistor M3, the second node N2, the turned-on second transistor M2, the fourth node N4, and the turned-on eighth transistor M8. The difference between the data voltage output from the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 becomes Vd-|Vth|. Vd is the data voltage output from the data signal line Data, and Vth is the threshold voltage of the third transistor M3. The signal on the reset signal line Reset is a low-level signal, turning off the first transistor M1 and the seventh transistor M7. The signal on the emission signal line EM is a high-level signal, turning off the fifth transistor M5 and the sixth transistor M6.

[0098] The third phase A3 is referred to as the light-emitting phase. The signals on the control signal line Scan and the light-emitting signal line EM are both low-level signals, and the signals on the scan signal line Gate and the reset signal line Reset are high-level signals. The signal on the reset signal line Reset is low-level, turning off the first transistor M1 and the seventh transistor M7. The control signal line SCAN is low-level, and the signals on the scan signal line GATE and the reset signal line Reset are high-level signals, turning off the second transistor M2, the fourth transistor M4, and the eighth transistor M8. The signal on the light-emitting signal line EM is low-level, turning on the fifth transistor M5 and the sixth transistor M6. The power supply voltage output from the high-level power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting device L via the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, driving the light-emitting device L to emit light.

[0099] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage at the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is expressed by the following formula: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2 In the formula, I is the driving current flowing through the third transistor M3, i.e., the driving current for driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control pole and the first pole of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output from the data signal line Data, and Vdd is the data voltage output from the high-level power supply terminal VDD.

[0100] FIG. 5A is a structural schematic diagram 1 of a display substrate according to an embodiment of the present disclosure, and FIG. 5B is a partial schematic diagram of the display substrate according to FIG. 5A. FIG. 6A is a structural schematic diagram 2 of a display substrate according to an embodiment of the present disclosure, and FIG. 6B is a partial schematic diagram of the display substrate according to FIG. 6A. As shown in FIGS. 5A, 5B, 6A, and 6B, a display substrate according to an embodiment of the present disclosure may include a base and a driving circuit layer disposed on the base. The base may include a display area 100 and a non-display area 200. The driving circuit layer may include a pixel driving circuit PE located in the display area 100, a gate driving circuit located in the non-display area 200, and at least one initial power supply line. At least a portion of the initial power supply line extends along a first direction D1.

[0101] In an exemplary embodiment, the at least one initial feed line includes a first initial feed line to an Nth initial feed line, where N is a positive integer equal to or greater than 1. When N is equal to or greater than 2, the N initial feed lines are arranged along the second direction D2. 5A, 5B, 6A, and 6B illustrate an example in which two initial feed lines and two initial feed lines are a first initial feed line INITL1 and a second initial feed line INITL2, respectively.

[0102] In an exemplary embodiment, the gate drive circuit is configured to provide a drive signal to the pixel drive circuit P, and the initial supply line is configured to provide an initial signal to the pixel drive circuit.

[0103] In an exemplary embodiment, the orthogonal projection of the base of at least one initial power supply line and the orthogonal projection of the base of the gate drive circuit at least partially overlap. Figures 5A, 5B, 6A, and 6B illustrate an example in which the second initial power supply line INITL2 and the gate drive circuit overlap.

[0104] In exemplary embodiments, the base may be a rigid base or a flexible base. The rigid base may be one or more of, but is not limited to, glass, metal foil sheet, and the flexible base may be one or more of, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0105] In an exemplary embodiment, the display substrate may be an LTPO display substrate or an LTPS display substrate.

[0106] In an exemplary embodiment, the number of driving circuits on the display substrate may be two, three, or more, which is determined by the structure of the display substrate and is not limited thereto in the present disclosure.

[0107] In exemplary embodiments, the light emitting device may be an organic light emitting transistor (OLED) or a quantum dot light emitting diode (QLED).

[0108] In an exemplary embodiment, the display area includes a first side and a second side opposite to each other, and the gate driving circuit may be located on the first side and / or the second side of the display area. Figures 5A and 6A illustrate an example in which the gate driving circuit is located on one side of the display area.

[0109] In an exemplary embodiment, the driving circuit layer may further include at least one initial signal line, at least a portion of which is located in the display area. At least a portion of the initial signal line may extend along the second direction. The at least one initial signal line corresponds one-to-one to the at least one initial power supply line. The initial signal line is electrically connected to the corresponding initial power supply line.

[0110] In an exemplary embodiment, the display substrate may further include a light-emitting structure layer disposed on a side away from the base of the driving circuit layer, and a sealing structure layer disposed on a side away from the base of the light-emitting structure layer. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, and the present disclosure is not limited thereto.

[0111] In an exemplary embodiment, the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode 304. The anode is connected to a pixel driving circuit through a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and the cathode.

[0112] In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers and can prevent external water vapor from penetrating into the light-emitting structure layer.

[0113] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer 44 disposed on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridge electrodes. The second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrode or the second touch electrode may be connected to the bridge electrode through a via.

[0114] In the present disclosure, the orthogonal projection at the base of at least one initial power supply line and the orthogonal projection at the base of the gate driving circuit at least partially overlap, thereby reducing the area occupied by the frame region of the display substrate and realizing a narrow frame.

[0115] In an exemplary embodiment, the gate drive circuit may include a plurality of drive circuits arranged along a second direction, the first direction intersecting the second direction, and an orthogonal projection of a base of the at least one initial power supply line and an orthogonal projection of a base of a drive circuit of the plurality of drive circuits that is closer to the display area at least partially overlap.

[0116] In an exemplary embodiment, the positional relationship between the plurality of driving circuits may be determined according to the structure and function of the display substrate, and the present disclosure does not limit this.

[0117] In an exemplary embodiment, the drive circuit may include multiple cascaded shift registers.

[0118] In an exemplary embodiment, as shown in FIGS. 6A and 6B, the pixel driving circuit includes an emission transistor and a write transistor. The plurality of driving circuits may include an emission driving circuit and a scan driving circuit. The emission driving circuit is electrically connected to the emission transistor, and the scan driving circuit is electrically connected to the write transistor. The scan driving circuit is located on the emission driving circuit closer to the display area 100. In this case, the orthogonal projection at the base of at least one initial feed line and the orthogonal projection at the base of the scan driving circuit at least partially overlap. FIGS. 6A and 6B illustrate an example in which the second initial feed line INITL2 and the scan driving circuit overlap.

[0119] In an exemplary embodiment, the emission drive circuit may include a plurality of cascaded emission shift registers EM-GOA, and the scan drive circuit may include a plurality of scan shift registers Pgate-GOA and a plurality of dummy scan shift registers DPgate-GOA.

[0120] In an exemplary embodiment, the driving circuit layer may further include emission signal lines and scan signal lines, at least a portion of which is located in the display area, wherein the emission shift registers are electrically connected to the pixel driving circuits via the emission signal lines, the scan shift registers are electrically connected to the pixel driving circuits via the scan signal lines, and the dummy scan shift registers are not electrically connected to the scan signal lines.

[0121] In an exemplary embodiment, as shown in Figures 5A and 5B, the pixel drive circuit includes an emission transistor, a write transistor, and a control transistor. The plurality of drive circuits includes an emission drive circuit, a scan drive circuit, and a control drive circuit, where the emission drive circuit is electrically connected to the emission transistor, the scan drive circuit is electrically connected to the write transistor, and the control drive circuit is electrically connected to the control transistor, the write transistor and the control transistor are of opposite transistor types, and the emission drive circuit and the control drive circuit are located on the side of the scan drive circuit away from the display area. The orthogonal projections of the bases of at least one initial feed line and the scan drive circuit at least partially overlap. Figures 6A and 6B illustrate an example in which the second initial feed line INITL2 and the scan drive circuit overlap.

[0122] In an exemplary embodiment, the control transistor may be an N-type transistor in the pixel drive circuit.

[0123] In an exemplary embodiment, the light emitting drive circuit may be located on the side of the control drive circuit closer to the display area, or on the side of the control drive circuit farther from the display area. In Figures 5A and 5B, the light emitting drive circuit is located on the side of the control drive circuit farther from the display area.

[0124] In an exemplary embodiment, as shown in Figure 6B, the emission drive circuit may include a plurality of cascaded emission shift registers EM-GOA, the control drive circuit may include a plurality of cascaded control shift registers Ngate-GOA, and the scan drive circuit may include a plurality of scan shift registers Pgate-GOA and a plurality of dummy scan shift registers DPgate-GOA.

[0125] In an exemplary embodiment, as shown in Figures 5B and 6B, a plurality of scan shift registers Pgate-GOA are cascaded, a plurality of dummy scan shift registers DPgate-GOA are interposed between the plurality of scan shift registers Pgate-GOA, and at least some of the dummy scan shift registers are located in the rounded corner regions.

[0126] In an exemplary embodiment, the orthogonal projections of K adjacent initial feed lines away from the display area at their bases and the orthogonal projections of K adjacent initial feed lines at their bases of the scan drive circuit at least partially overlap, where K is a positive integer less than or equal to N. Illustratively, the orthogonal projections of the first initial feed line and the second initial feed line at their bases may both at least partially overlap with the orthogonal projections of the first initial feed line and the second initial feed line at their bases.

[0127] In an exemplary embodiment, the scan shift register or the dummy scan shift register may include multiple transistors and multiple capacitors, and the circuit structure of the scan shift register or the dummy scan shift register may be 8T2C, which is not limited in the present disclosure.

[0128] Figure 7A is an equivalent circuit diagram of a shift register on a display substrate, and Figure 7B is a timing diagram of the shift register according to Figure 7A. The shift register may be a scan shift register or a dummy scan shift register. As shown in Figure 7A, the shift register includes a first transistor T1 to an eighth transistor T8, a first capacitor C1, and a second capacitor C2.

[0129] In an exemplary embodiment, the control pole of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first pole of the first transistor T1 is electrically connected to the input terminal IN, and the second pole of the first transistor T1 is electrically connected to the first node G1. The control pole of the second transistor T2 is electrically connected to the first node G1, the first pole of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second pole of the second transistor T2 is electrically connected to the second node G2. The control pole of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first pole of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second pole of the third transistor T3 is electrically connected to the second node G2. The control pole of the fourth transistor T4 is electrically connected to the second node G2, the first pole of the fourth transistor T4 is electrically connected to the first power supply terminal V1, and the second pole of the fourth transistor T4 is electrically connected to the output terminal OUT. The control electrode of the fifth transistor T5 is electrically connected to the third node G3, the first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the output terminal OUT. The control electrode of the sixth transistor T6 is electrically connected to the second node G2, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VH, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7. The control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the second electrode of the seventh transistor T7 is electrically connected to the first node G1. The control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected to the first node G1, and the second electrode of the eighth transistor T8 is electrically connected to the third node G3. The first plate C11 of the first capacitor C1 is electrically connected to the first power supply terminal V1, the second plate C12 of the first capacitor C1 is electrically connected to the second node G2, the first plate C21 of the second capacitor C2 is electrically connected to the output terminal OUT, and the second plate C22 of the second capacitor C2 is electrically connected to the third node G3.

[0130] In an exemplary embodiment, the first to eighth transistors T1 to T8 may be P-type transistors or N-type transistors.

[0131] In the exemplary embodiment, the first power supply terminal V1 continues to provide a high level signal and the second power supply terminal V2 continues to provide a low level signal.

[0132] Taking the case where the first to eighth transistors T1 to T8 are P-type transistors as an example, as shown in FIG. 7B, the operation process of the shift register according to the exemplary embodiment includes the following steps.

[0133] In the input stage B1, the signals at the first clock signal terminal CK1 and the input terminal IN are low-level signals, and the signal at the second clock signal terminal CK2 is high-level signals. Because the signal at the first clock signal terminal CK1 is low-level, the first transistor T1 is turned on, and the signal at the input terminal IN is transmitted to the first node G1 via the first transistor T1. The signal at the eighth transistor T8 receives a low-level signal at the second power terminal V2, and the eighth transistor T8 is turned on. The level at the third node G3 may turn on the fifth transistor T5, and the signal at the second clock signal terminal CK2 is transmitted to the output terminal OUT via the fifth transistor T5. That is, in the input stage B1, the signal at the second clock signal terminal CK2 is high-level. Also, because the signal at the first clock signal terminal CK1 is low-level, the third transistor T3 is turned on, and the low-level signal at the second power terminal V2 is transmitted to the second node G2 via the third transistor T3. At this time, the fourth transistor T4 and the sixth transistor T6 are both turned on, and the signal at the second clock signal terminal CK2 is a high level signal, so the seventh transistor T7 is turned off.

[0134] In the output stage B2, the signal at the first clock signal terminal CK1 is high, the signal at the second clock signal terminal CK2 is low, and the signal at the input terminal IN is high. The fifth transistor T5 is turned on, and the signal at the second clock signal terminal CK2 is transmitted to the output terminal OUT via the fifth transistor T5. In the output stage B2, the level of the terminal connected to the output terminal OUT of the second capacitor C2 becomes the signal at the second power supply terminal V2. Due to the bootstrap effect of the second capacitor C2, the eighth transistor T8 is turned off, allowing the fifth transistor T5 to be turned on, and the signal at the output terminal OUT is low. Furthermore, since the signal at the first clock signal terminal CK1 is high, the first transistor T1 and the third transistor T3 are both turned off. The second transistor T2 is turned on, and the high signal at the first clock signal terminal CK1 is transmitted to the second node G2 via the second transistor T2, thereby turning off the fourth transistor T4 and the sixth transistor T6. Since the signal at the second clock signal terminal CK2 is a low level signal, the seventh transistor T7 is turned on.

[0135] In the buffer stage B3, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are both high-level signals, the signal at the input terminal IN is high-level signals, the fifth transistor T5 is turned on, and the second clock signal terminal CK2 becomes the output signal through the fifth transistor T5. Due to the bootstrap effect of the second capacitor C2, the level of the first node G1 becomes V2-Vth. Furthermore, because the signal at the first clock signal terminal CK1 is high-level signals, the first transistor T1 and the third transistor T3 are both turned off, the eighth transistor T8 is turned on, and the second transistor T2 is turned on. The high-level signal at the first clock signal terminal CK1 is transmitted to the second node G2 through the second transistor T2, thereby turning off the fourth transistor T4 and the sixth transistor T6. Because the signal at the second clock signal terminal CK2 is high-level signals, the seventh transistor T7 is turned off.

[0136] In the first sub-stage B41 of the stabilization stage B4, the signal at the first clock signal terminal CK1 is low, and the signals at the second clock signal terminal CK2 and the input terminal IN are high. Because the signal at the first clock signal terminal CK1 is low, the first transistor T1 is turned on, the signal at the input terminal IN is transmitted to the first node G1 through the first transistor T1, and the second transistor T2 is turned off. Because the eighth transistor T8 is on, the fifth transistor T5 is turned off. Because the signal at the first clock signal terminal CK1 is low, the third transistor T3 is turned on, and the fourth transistor T4 and the sixth transistor T6 are all turned on. The high-level signal at the first power terminal V1 is transmitted to the output terminal OUT through the fourth transistor T4, i.e., the signal at the output terminal OUT is high.

[0137] In the second sub-stage B42 of the stabilization stage B4, the signal at the first clock signal terminal CK1 is a high-level signal, the signal at the second clock signal terminal CK2 is a low-level signal, and the signal at the input terminal IN is a high-level signal. The fifth transistor T5 and the second transistor T2 are both turned off. Because the signal at the first clock signal terminal CK1 is a high-level signal, the first transistor T1 and the third transistor T3 are both turned off. Due to the holding effect of the first capacitor C1, the fourth transistor T4 and the sixth transistor T6 are both turned on, and a high-level signal is transmitted to the output terminal OUT through the fourth transistor T4, i.e., the signal at the output terminal OUT is a high-level signal.

[0138] In the second sub-stage B42, since the signal at the second clock signal terminal CK2 is a low level signal, the seventh transistor T7 is turned on, and a high level signal is transmitted to the third node G3 and the first node G1 via the sixth transistor T6 and the seventh transistor T7, maintaining the signals at the third node G3 and the first node G1 as high level signals.

[0139] In the third sub-stage B43, the signals at the first clock signal terminal CK1 and the second clock signal terminal CK2 are both high level signals, and the signal at the input terminal IN is also high level signals. The fifth transistor T5 and the second transistor T2 are turned off. Because the signal at the first clock signal terminal CK1 is high level signals, the first transistor T1 and the third transistor T3 are both turned off, and the fourth transistor T4 and the sixth transistor T6 are both turned on. The high level signal is transmitted to the output terminal OUT via the fourth transistor T4, that is, the signal at the output terminal OUT is high level signals.

[0140] In an exemplary embodiment, the number of transistors in the dummy scan shift register may be less than or equal to the number of transistors in the scan shift register.

[0141] In an exemplary embodiment, the width of the dummy scan shift register may be less than or equal to the width of the scan shift register.

[0142] In an exemplary embodiment, when the number of transistors in the dummy scan shift register is equal to the number of transistors in the scan shift register, the circuit structure of the dummy scan shift register may be the same as the circuit structure of the scan shift register. In this case, the width of the dummy scan shift register may be equal to the width of the scan shift register. The width is the length in a direction perpendicular to the extension direction of the second power line VGL to which the shift register is connected. The shift register includes a dummy scan shift register or a scan shift register.

[0143] In an exemplary embodiment, if the number of transistors in the dummy scan shift register is less than the number of transistors in the scan shift register, the width of the dummy scan shift register may be less than the width of the scan shift register.

[0144] In the exemplary embodiment, in order to ensure the display effect of the rounded corner area, more pixel driving circuits are left close to the rounded corner area. In the present disclosure, the width of the dummy scanning shift register is reduced, which can save space and provide sufficient area for the wiring of the scanning shift register, thereby reducing the area occupied by the rounded corner area and realizing a narrow frame of the display substrate.

[0145] In an exemplary embodiment, Figure 8A is an equivalent circuit diagram of a dummy scan shift register, and Figure 8B is an equivalent circuit diagram of another dummy scan shift register. If the number of transistors in the dummy scan shift register is less than the number of transistors in the scan shift register, the circuit structure of the dummy scan shift register can be the circuit structure of Figure 8A or Figure 8B, and no capacitor is installed in the circuit structures according to Figures 8A and 8B.

[0146] In an exemplary embodiment, as shown in FIG. 8A , the dummy scan shift register may include a first transistor DT1, a second transistor DT2, and a fourth transistor DT4 to an eighth transistor DT8. The control pole, first pole, and second pole of the first transistor DT1 are electrically connected to the second power supply terminal V2. The control pole, first pole, and second pole of the second transistor DT2 are electrically connected to the second power supply terminal V2. The control pole, first pole, and second pole of the fourth transistor DT4 are electrically connected to the second power supply terminal V2. The first pole and second pole of the fifth transistor DT5 are electrically connected to the second power supply terminal V2, and the control pole of the fifth transistor DT5 is electrically connected to the second pole of the eighth transistor DT8. The control pole and first pole of the sixth transistor DT6 are electrically connected to the second power supply terminal V2, and the second pole of the sixth transistor DT6 is electrically connected to the first pole of the seventh transistor DT7. The control pole and second pole of the seventh transistor DT7 are electrically connected to the second power supply terminal V2. The control pole and first pole of the eighth transistor DT8 are electrically connected to the second power supply terminal V2.

[0147] In an exemplary embodiment, as shown in FIG. 8B , the dummy scan shift register may include a first transistor DT1, a second transistor DT2, and sixth to eighth transistors DT6 to DT8. The control pole, first pole, and second pole of the first transistor DT1 are electrically connected to the second power supply terminal V2. The control pole, first pole, and second pole of the second transistor DT2 are electrically connected to the second power supply terminal V2. The control pole and first pole of the sixth transistor DT6 are electrically connected to the second power supply terminal V2, and the second pole of the sixth transistor DT6 is electrically connected to the first pole of the seventh transistor DT7. The control pole and second pole of the seventh transistor DT7 are electrically connected to the second power supply terminal V2. The control pole, first pole, and second pole of the eighth transistor DT8 are electrically connected to the second power supply terminal V2.

[0148] In an exemplary embodiment, the circuit structure of the light emission shift register or the control register may be 13T3C or 10T3C, and this disclosure is not limited thereto.

[0149] In an exemplary embodiment, the display substrate may include other film layers, such as spacer pillars, and the present disclosure is not limited thereto.

[0150] FIG. 9A is a partial schematic view of a display substrate, and FIG. 9B is a partial schematic view of a rounded corner region of the display substrate according to FIG. 9A. FIG. 10A is another partial schematic view of the display substrate, and FIG. 10B is a further partial schematic view of the display substrate. FIG. 11 is a partial schematic view of a rounded corner region of the display substrate according to FIGS. 10A and 10B. As shown in FIGS. 9A to 11, in an exemplary embodiment, the driving circuit layer may further include a first initial signal line GSTV, a first clock signal line GCK1, a second clock signal line GCK2, a first power line VGH, and a second power line VGL located in the non-display area. The scanning driving circuits are electrically connected to the first clock signal line GCK1, the second clock signal line GCK2, the first power line VGH, the second power line VGL, and the first initial signal line GSTV, respectively.

[0151] In an exemplary embodiment, as shown in Figures 9A to 11, the first clock signal line GCK1, the second clock signal line GCK2, the first initial signal line GSTV, the first power supply line VGH, and the second power supply line VGL may at least partially extend along the first direction D1.

[0152] In an exemplary embodiment, the input terminal of the first-stage shift register is electrically connected to a first initial signal line, and the output terminal of the i-th stage shift register is electrically connected to the input terminal of the (i+1)-th stage shift register. The i-th stage shift register has a first clock signal terminal electrically connected to a first clock signal line and a second clock signal terminal electrically connected to a second clock signal line. The i+1-th stage shift register has a first clock signal terminal electrically connected to a second clock signal line and a second clock signal terminal electrically connected to the first clock signal line. The first power supply terminal of the i-th stage shift register is electrically connected to a first power supply line, and the second power supply terminal of the i-th stage shift register is electrically connected to a second power supply line.

[0153] 9A to 11, the second clock signal line GCK2 is located on the side away from the display area of ​​the first clock signal line GCK1, the second power supply line VGL is located on the side closer to the display area of ​​the first clock signal line, the first initial signal line GSTV is located on the side closer to the display area of ​​the second power supply line VGL, the first power supply line VGH is located on the side closer to the display area of ​​the first initial signal line GSTV, and at least one initial feed line is located on the side closer to the display area of ​​the first power supply line VGH. Figures 9A to 11 explain an example of two initial feed lines, i.e., the first initial feed line INITL1 and the second initial feed line INTIL2.

[0154] 9A to 11, the driving circuit layer may further include a second initial signal line ESTV located in the non-display area, and at least a portion of the second initial signal line ESTV extends along the first direction D1. The light-emitting driving circuit is electrically connected to the second initial signal line ESTV, and the second initial signal line ESTV is located between the second power line VGL and the first initial signal line GSTV.

[0155] In an exemplary embodiment, as shown in FIG. 9A, the driving circuit layer may further include a first output signal line OUTL1 and a second output signal line OUTL2 located in the non-display area, and the first output signal line OUTL1 and the second output signal line OUTL2 extend at least partially along the second direction D2.

[0156] In an exemplary embodiment, as shown in FIG. 9A, the first output signal line OUTL1 is located on the side of the scan driving circuit close to the display area, and is electrically connected to the scan driving circuit and the pixel driving circuit respectively.

[0157] In an exemplary embodiment, as shown in FIG. 9A, the second output signal line OUTL2 passes through the scan driving circuit and is electrically connected to the pixel driving circuit and one of the light emitting driving circuit and the control driving circuit, respectively.

[0158] In an exemplary embodiment, as shown in FIG. 9A, the orthogonal projection at the base of the initial power supply line that overlaps the scan drive circuit and the orthogonal projection at the base of the multiple capacitors at least partially overlap, and the orthogonal projection at the base of the second initial signal line INITL2 and the orthogonal projection at the base of the multiple capacitors at least partially overlap.

[0159] In an exemplary embodiment, the distance between the boundary of the initial supply line that overlaps the scan drive circuit and the display area is smaller than the distance between the boundary of at least one of the capacitors and the display area. Using FIG. 8A as an example, the distance between the boundary of the second initial supply line INITL2 and the display area is smaller than the distance between the boundary of at least one of the capacitors and the display area. That is, the second initial supply line INITL2 overlaps the capacitor but not the transistor. This can improve the reliability of the scan shift register.

[0160] In an exemplary embodiment, as shown in Figures 9B, 10A, 10B, and 11, the distance L2 between the boundary of the second clock signal line located on the dummy scan shift register side away from the display area and the boundary of at least one initial power supply line that is closest to the display area close to the display area is smaller than the distance L1 between the boundary of the second clock signal line located on the scan shift register side away from the display area and the boundary of at least one initial power supply line that is closest to the display area close to the display area.

[0161] In an exemplary embodiment, Fig. 12 is a partial schematic diagram of another display substrate. As shown in Fig. 12, the driving circuit layer may further include a first output connection line CL1 and a second output connection line CL2 located in the display area and the non-display area, and at least a portion of the first output connection line CL1 and the second output connection line CL2 extends along the second direction.

[0162] In an exemplary embodiment, the first output connection lines may be electrically connected to the first output signal line OUTL1 and the pixel driving circuit, respectively, and the second output connection lines may be electrically connected to the second output signal line OUTL2 and the pixel driving circuit, respectively.

[0163] In an exemplary embodiment, the first output connecting line is electrically connected to the pixel driving circuit via a scanning signal line. The second output connecting line is electrically connected to the pixel driving circuit via an emission signal line or a control signal line. When the second output signal line to which the second output connecting line is connected is electrically connected to the emission driving circuit, the second output connecting line is electrically connected to the pixel driving circuit via the emission signal line. When the second output signal line to which the second output connecting line is connected is electrically connected to the control driving circuit, the second output connecting line is electrically connected to the pixel driving circuit via the control signal line.

[0164] In an exemplary embodiment, when N=2, the driving circuit layer may further include a third output connecting line CL3 and a fourth output connecting line CL4, at least a portion of which extends along the second direction D2, as shown in Figure 12. The third output connecting line CL3 is electrically connected to the first initial power supply line and the pixel driving circuit, respectively, and the fourth output connecting line CL4 is electrically connected to the second initial power supply line and the pixel driving circuit, respectively.

[0165] In an exemplary embodiment, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are stacked in sequence; the semiconductor layer includes active layers of at least a plurality of transistors; the first conductive layer includes at least control poles of a plurality of transistors and first plates of a plurality of capacitors; the second conductive layer includes at least second plates of the plurality of capacitors, a first output signal line, and a third output signal line; the third conductive layer includes at least a second power supply line, a first electrode and a second electrode of at least one transistor, and a fourth output signal line; The fourth conductive layer includes at least a first initial signal line, a second initial signal line, and a first power line. In an exemplary embodiment, the drive circuit layer further includes a fifth conductive layer located away from the base of the fourth conductive layer; The fifth conductive layer includes at least a first output connection line and a second output connection line.

[0166] In an exemplary embodiment, the first output connecting line and the second output connecting line are located on the fifth conductive layer, which can further reduce the space occupied in the non-display area, and connect from the non-display area to the display area via the first output connecting line, and connect across layers within the display area to the corresponding pixel driving circuit.

[0167] In an exemplary embodiment, a dummy wiring may be provided between the first output connection line and the second output connection line, and the dummy wiring is a signal wiring that does not supply a signal. By providing the dummy wiring between the first output connection line and the second output connection line, the etching uniformity of the fifth conductive layer can be ensured, and the reliability of the display substrate can be ensured.

[0168] In an exemplary embodiment, the initial power supply line may have a single layer structure or a multi-layer structure, and this disclosure is not limited thereto.

[0169] In an exemplary embodiment, the initial feed line has a single layer structure, and the initial feed line is located on the fourth conductive layer.

[0170] In an exemplary embodiment, when the display substrate is an LTPO display substrate, the initial power supply line may be a single layer structure.

[0171] In an exemplary embodiment, the initial feedline includes a first initial subsegment and a second initial subsegment connected to each other, and an orthogonal projection at a base of the first initial subsegment and an orthogonal projection at a base of the second initial subsegment at least partially overlap.

[0172] In an exemplary embodiment, the first initial sub-segment is located on the third conductive layer and the second initial sub-segment is located on the fourth conductive layer.

[0173] In an exemplary embodiment, the stacked design of the initial power supply lines can reduce the load difference of the initial power supply lines, and also meet the jumper rules of the display substrate and avoid the risk of static electricity on the display substrate.

[0174] In an exemplary embodiment, the first clock signal line and the second clock signal line may have a single-layer structure or a multi-layer structure, and the present disclosure is not limited thereto.

[0175] In an exemplary embodiment, the first clock signal line and the second clock signal line have a single-layer structure, and the first clock signal line and the second clock signal line are located on a fourth conductive layer.

[0176] In an exemplary embodiment, the clock signal line may include a first clock sub-segment and a second clock sub-segment connected to each other, the clock signal line including the first clock signal line and the second clock signal line, and an orthogonal projection at the base of the first clock sub-segment and an orthogonal projection at the base of the second clock sub-segment at least partially overlap.

[0177] In an exemplary embodiment, the first clock sub-segment is located on the third conductive layer and the second clock sub-segment is located on the fourth conductive layer closer to the base.

[0178] In an exemplary embodiment, the first clock signal line and the second clock signal line are designed to be stacked, thereby reducing the load difference between the first clock signal line and the second clock signal line, satisfying the jumper rules for the display substrate, and avoiding the risk of static electricity on the display substrate.

[0179] In an exemplary embodiment, the second output signal line may have a single-layer structure or a multi-layer structure, and the present disclosure is not limited thereto.

[0180] In an exemplary embodiment, the second output signal line has a single layer structure, and the second output signal line is located on the second conductive layer.

[0181] In an exemplary embodiment, FIG. 13 is a structural schematic diagram of a second output signal line. As shown in FIG. 13, the driving circuit layer further includes a sixth conductive layer located between the second conductive layer and the third conductive layer. The second output signal line includes a plurality of first output subsegments OUTL2A and a plurality of second output subsegments OUTL2B. Adjacent first output subsegments OUTL2A are electrically connected via the second output subsegments OUTL2B, and adjacent second output subsegments OUTL2B are electrically connected via the first output subsegments OUTL2A. An orthographic projection at the base of the second output subsegment OUTL2B and an orthographic projection at the base of the electrically connected first output subsegment OUTL2A at least partially overlap. An orthographic projection at the base of the first output subsegment OUTL2A and an orthographic projection at the base of the electrically connected second output subsegment OUTL2B at least partially overlap. The first output subsegment OUTL2A is located on the second conductive layer, and the second output subsegment OUTL2B is located on the sixth conductive layer.

[0182] In an exemplary embodiment, the second output signal line includes a first output sub-segment and a second output sub-segment located on different film layers, thereby avoiding the risk of static electricity due to the length of the second output signal line.

[0183] The "patterning process" described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal materials, inorganic materials, or transparent conductive materials, and organic material coating, mask exposure, and development for organic materials. The deposition may be performed by any one or more of sputtering, evaporation coating, and chemical vapor deposition. The coating may be performed by any one or more of spray coating, spin coating, and inkjet printing. The etching may be performed by any one or more of dry etching and wet etching. This disclosure is not limited thereto. A "thin film" refers to a thin film layer fabricated by deposition, coating, or other process on a base material using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, the "thin film" can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern." In the present disclosure, "A and B are disposed on the same layer" means that A and B are formed simultaneously by the same patterning process. The "thickness" of a film layer is the size of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of the present disclosure, "the orthogonal projection of B is located within the range of the orthogonal projection of A" or "the orthogonal projection of A includes the orthogonal projection of B" means that the boundary of the orthogonal projection of B is within the boundary of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.

[0184] The manufacturing process of the display substrate shown in FIG. 9A will be described below as an example, and FIG. 9A illustrates the case where the second output signal line has a single-layer structure.

[0185] (1) Forming a semiconductor layer pattern on a base. In an exemplary embodiment, as shown in Figure 14, forming the semiconductor layer pattern may include depositing a semiconductor thin film on the base and patterning the semiconductor thin film by a patterning process to form a semiconductor layer pattern. Figure 14 is a schematic view of Figure 9A after the semiconductor layer pattern has been formed.

[0186] In an exemplary embodiment, as shown in FIG. 14, the semiconductor layer pattern may include an active layer T11 of the first transistor to an active layer T81 of the eighth transistor.

[0187] In exemplary embodiments, the base may be a rigid base or a flexible base. The rigid base may be one or more of, but is not limited to, glass, metal foil sheet, and the flexible base may be one or more of, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0188] In an exemplary embodiment, the flexible base may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silica (SiOx) to improve the water and oxygen resistance of the base. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking a stacked structure of PI1 / Barrier1 / a-Si / PI2 / Barrier2 as an example, the manufacturing process may include the following steps: First, a layer of polyimide is applied to a glass carrier plate, and then cured and formed into a film to form the first flexible (PI1) layer. Then, one layer of barrier thin film is deposited on the first flexible layer to form a first barrier (Barrier 1) layer covering the first flexible layer. Then, one layer of amorphous silicon thin film is deposited on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer. Then, one layer of polyimide is further applied to the amorphous silicon layer, and after curing and forming a film, a second flexible (PI2) layer is formed. Then, one layer of barrier thin film is deposited on the second flexible layer to form a second barrier (Barrier 2) layer covering the second flexible layer, thereby completing the manufacture of the base.

[0189] In exemplary embodiments, the semiconductor thin film may employ various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc. That is, the present disclosure applies to transistors fabricated based on oxide technology, silicon technology, and organic technology.

[0190] In an exemplary embodiment, as shown in FIG. 14 , the active layer T21 of the second transistor and the active layer T31 of the third transistor may be an integrated structure, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may be an integrated structure, the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor may be an integrated structure, and the active layer T11 of the first transistor and the active layer T81 of the eighth transistor are disposed separately.

[0191] 14 , in the first direction D1, the active layer T81 of the eighth transistor and the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are located on the same side of the active layer T11 of the first transistor. In the second direction D2, the active layer T11 of the first transistor, the active layer T81 of the eighth transistor, the integrated structure of the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor, and the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are located on the same side of the integrated structure of the active layer T21 of the second transistor and the active layer T31 of the third transistor. The integrated structure of the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor and the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are located on the same side of the active layer T81 of the eighth transistor. The active layer T11 of the first transistor of the scan shift register of this stage is located closer to the scan shift register of the previous stage than the active layer T81 of the eighth transistor of the scan shift register of this stage.

[0192] In an exemplary embodiment, the active layer T11 of the first transistor may extend along the second direction D2 and have an elongated structure. The integrated structure of the active layer T21 of the second transistor and the active layer T31 of the third transistor, the integrated structure of the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor, and the active layer T81 of the eighth transistor may have an "I" shape. The integrated structure of the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor may include two "I"-shaped structures, and the two "I" shapes may be arranged along the second direction D2.

[0193] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region T21_2 of the active layer of the second transistor may be the second region T31_2 of the active layer of the third transistor, the second region T41_2 of the active layer of the fourth transistor may be the second region T51_2 of the active layer of the fifth transistor, and the second region T61_2 of the active layer of the sixth transistor may be the first region T71_1 of the active layer of the seventh transistor. The first region T11_1 and the second region T11_2 of the active layer of the first transistor, the first region T21_1 of the active layer of the second transistor, the first region T31_1 of the active layer of the third transistor, the first region T41_1 of the active layer of the fourth transistor, the first region T51_1 of the active layer of the fifth transistor, the first region T61_1 of the active layer of the sixth transistor, the first region T71_2 of the active layer of the seventh transistor, and the first region T81_1 and the second region T81_2 of the active layer of the eighth transistor may be arranged separately.

[0194] (2) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in Figures 15 and 16, forming the first conductive layer pattern may include sequentially depositing a first insulating thin film and a first conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the first conductive thin film through a patterning process to form a first insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the first insulating layer. Figure 15 is a schematic diagram of the first conductive layer pattern of Figure 9A, and Figure 16 is a schematic diagram of Figure 9A after the first conductive layer pattern has been formed.

[0195] In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0196] In an exemplary embodiment, as shown in FIGS. 15 and 16, the first conductive layer pattern may include at least a control pole T12 of the first transistor to a control pole T82 of the eighth transistor, a first electrode plate C11 of the first capacitor, a first electrode plate C21 of the second capacitor, and a first connecting line VL1.

[0197] In an exemplary embodiment, as shown in FIGS. 15 and 16, the first plate C11 of the first capacitor, the control pole T42 of the fourth transistor, and the control pole T62 of the sixth transistor are an integrated structure, and the first plate C21 of the second capacitor and the control pole T52 of the fifth transistor are an integrated structure.

[0198] In an exemplary embodiment, as shown in FIGS. 15 and 16, the first plate C11 of the first capacitor and the first plate C21 of the second capacitor may be arranged along a first direction D1, and the first plate C11 of the first capacitor may be located closer to the scanning shift register one stage before the first plate C21 of the second capacitor.

[0199] In an exemplary embodiment, as shown in FIGS. 15 and 16, the area of ​​the first plate C21 of the second capacitor may be greater than the area of ​​the first plate C11 of the first capacitor.

[0200] 15 and 16, the first plate C11 of the first capacitor may be square in shape and may be located on the side closer to the display area of ​​the control pole T42 of the fourth transistor and the control pole T62 of the sixth transistor. The control pole T42 of the fourth transistor and the control pole T62 of the sixth transistor may have an elongated shape extending along the second direction D2.

[0201] In an exemplary embodiment, as shown in Figures 15 and 16, the first plate C21 of the second capacitor may be square in shape and may be located on the side of the control pole T52 of the fifth transistor closer to the display area. The control pole T52 of the fifth transistor may include a plurality of elongated structures extending along the second direction D2. The integrated structure of the control pole T52 of the fifth transistor and the first plate C21 of the second capacitor may be a comb-like structure. The control pole T52 of the fifth transistor is a comb tooth, and the first plate C21 of the second capacitor is a comb ridge.

[0202] In an exemplary embodiment, the control pole T12 of the first transistor may be located on the side of the first plate C11 of the first capacitor away from the display area, as shown in Figures 15 and 16. The control pole T12 of the first transistor may be shaped like a right-handed rotated "F," with the opening facing the control pole T22 of the second transistor.

[0203] In an exemplary embodiment, as shown in FIGS. 15 and 16, the control pole T22 of the second transistor and the control pole T32 of the third transistor may be elongated structures extending along the second direction D2.

[0204] In an exemplary embodiment, as shown in FIGS. 15 and 16, the control pole T72 of the seventh transistor may be in the shape of a counterclockwise rotated "n", and the lengths of both sides of n are different.

[0205] In the exemplary embodiment, as shown in FIGS. 15 and 16, the control pole T82 of the eighth transistor extends at least partially along the second direction D2 and has a polygonal line shape.

[0206] In an exemplary embodiment, as shown in FIGS. 15 and 16, the first connecting line VL1 may be elongated and extend along the second direction D2, and may be located on the side closer to the shift register one stage before the control pole T42 of the fourth transistor.

[0207] In an exemplary embodiment, as shown in Figures 15 and 16, the control pole T12 of the first transistor spans the active layer of the first transistor, the control pole T22 of the second transistor spans the active layer of the second transistor, the control pole T32 of the third transistor spans the active layer of the third transistor, the control pole T42 of the fourth transistor spans the active layer of the fourth transistor, the control pole T52 of the fifth transistor spans the active layer of the fifth transistor, the control pole T62 of the sixth transistor spans the active layer of the sixth transistor, and the control pole T72 of the seventh transistor spans the active layer of the seventh transistor, and the extension direction of the control pole of at least one transistor and the extension direction of the active layer are perpendicular to each other.

[0208] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer is used as a shielding portion and the semiconductor layer is subjected to a conductive treatment. The semiconductor layer in the region shielded by the first conductive layer forms the channel regions of the first transistor T1 to the seventh transistor T7. The semiconductor layer in the region not shielded by the first conductive layer is made conductive, i.e., the first and second regions of the first transistor T1 to the seventh transistor are both made conductive. The integrated structure of the second region of the active layer of the sixth transistor and the first region of the active layer of the seventh transistor is also used as the second pole T64 of the sixth transistor and the first pole T73 of the seventh transistor.

[0209] (3) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 17 and 18, forming the second conductive layer pattern may include sequentially depositing a second insulating thin film and a second conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the second conductive thin film through a patterning process to form a second insulating layer covering the first conductive layer pattern and a second conductive layer pattern disposed on the second insulating layer. FIG. 17 is a schematic diagram of the second conductive layer pattern of FIG. 9A, and FIG. 18 is a schematic diagram of FIG. 9A after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0210] In an exemplary embodiment, as shown in FIGS. 17 and 18, the second conductive layer pattern may include at least the second plate C12 of the first capacitor, the second plate C22 of the second capacitor, the first output signal line OUTL1, the second output signal line OUTL2, and the third output signal line OUTL3.

[0211] In an exemplary embodiment, as shown in Figures 17 and 18, the second plate C22 of the second capacitor and the first output signal line OUTL1 may be an integrated structure, and the first output signal line OUTL1 is located on the side of the second plate C22 of the second capacitor closer to the display area.

[0212] In an exemplary embodiment, as shown in Figures 17 and 18, the outline of the second plate C12 of the first capacitor may be a sickle shape rotated counterclockwise, and the orthogonal projection at the base of the second plate C12 of the first capacitor and the orthogonal projection at the base of the first plate C11 of the first capacitor at least partially overlap.

[0213] In an exemplary embodiment, as shown in Figures 17 and 18, the outline of the second plate C22 of the second capacitor may be rectangular, and the corners of the rectangle may be chamfered, and the orthogonal projection of the second plate C22 of the second capacitor at the base and the orthogonal projection of the first plate C21 of the second capacitor at the base at least partially overlap.

[0214] In an exemplary embodiment, as shown in Figures 17 and 18, the first output signal line OUTL1, the second output signal line OUTL2, and the third output signal line OUTL3 may have at least a portion extending along the second direction D2 and may be in the form of a broken line.

[0215] In an exemplary embodiment, as shown in Figures 17 and 18, the second output signal line OUTL2 may be located on the side closer to the scanning shift register of the previous stage than the first output signal line OUTL1, and the third output signal line OUTL3 may be located on the side closer to the scanning shift register of the next stage than the first output signal line OUTL1, and the third output signal line OUTL3 is located on the side closer to the display area of ​​the second electrode C12 of the first capacitor.

[0216] (4) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in FIG. 19, forming the third insulating layer pattern may include depositing a third insulating thin film on the base on which the above-mentioned pattern is formed, and patterning the third insulating thin film through a patterning process to form a third insulating layer covering the second conductive layer, and a plurality of via patterns are provided in the third insulating layer. FIG. 19 is a schematic diagram of FIG. 9A after the third insulating layer pattern is formed.

[0217] In an exemplary embodiment, as shown in FIG. 19, the multiple via patterns may include at least a first via H1 to a twenty-second via H22.

[0218] 19, the orthogonal projection of the base of the first via H1 is within the range of the orthogonal projection of the base of the first region of the active layer of the first transistor. The third insulating layer, the second insulating layer, and the first insulating layer in the first via H1 are etched to expose the surface of the first region of the active layer of the first transistor. The first via H1 is configured to connect a first pole of a subsequently formed first transistor T1 to the first region of the active layer of the first transistor through the via.

[0219] 19, the orthogonal projection of the base of the second via H2 is within the range of the orthogonal projection of the base of the second region of the active layer of the first transistor. The third insulating layer, the second insulating layer, and the first insulating layer in the second via H2 are etched to expose the surface of the second region of the active layer of the first transistor. The second via H2 is configured to connect the second pole of the subsequently formed first transistor T1 to the second region of the active layer of the first transistor through the via.

[0220] 19, the orthogonal projection of the base of the third via H3 is within the range of the orthogonal projection of the base of the first region of the active layer of the second transistor. The third insulating layer, the second insulating layer, and the first insulating layer in the third via H3 are etched to expose the surface of the first region of the active layer of the second transistor. The third via H3 is configured to connect the first pole of a subsequently formed second transistor to the first region of the active layer of the second transistor through the via.

[0221] 19, the orthogonal projection of the base of the fourth via H4 is within the range of the orthogonal projection of the base of the second region of the active layer of the second transistor (which is also the second region of the active layer of the third transistor). The third insulating layer, the second insulating layer, and the first insulating layer in the fourth via H4 are etched to expose the surface of the second region of the active layer of the second transistor (which is also the second region of the active layer of the third transistor). The fourth via H4 is configured to connect the second pole of the second transistor (which is also the second pole of the third transistor) to be subsequently formed through the via to the second region of the active layer of the second transistor (which is also the second region of the active layer of the third transistor).

[0222] 19, the orthogonal projection of the base of the fifth via H5 is within the range of the orthogonal projection of the base of the first region of the active layer of the third transistor. The third insulating layer, the second insulating layer, and the first insulating layer within the fifth via H5 are etched to expose the surface of the first region of the active layer of the third transistor. The fifth via H5 is configured to connect the first pole of a subsequently formed third transistor to the first region of the active layer of the third transistor through the via.

[0223] 19, the orthogonal projection of the base of the sixth via H6 is within the range of the orthogonal projection of the base of the first region of the active layer of the fourth transistor. The third insulating layer, the second insulating layer, and the first insulating layer in the sixth via H6 are etched to expose the surface of the first region of the active layer of the fourth transistor. The sixth via H6 is configured to connect the first pole of a subsequently formed fourth transistor to the first region of the active layer of the fourth transistor through the via.

[0224] 19, the orthogonal projection of the base of the seventh via H7 is within the range of the orthogonal projection of the base of the second region of the active layer of the fourth transistor (which is also the second region of the active layer of the fifth transistor). The third insulating layer, the second insulating layer, and the first insulating layer in the seventh via H7 are etched to expose the surface of the second region of the active layer of the fourth transistor (which is also the second region of the active layer of the fifth transistor). The seventh via H7 is configured to connect the second pole of the fourth transistor (which is also the second pole of the fifth transistor) to be subsequently formed through the via to the second region of the active layer of the fourth transistor (which is also the second region of the active layer of the fifth transistor).

[0225] 19, the orthogonal projection of the base of the eighth via H8 is within the range of the orthogonal projection of the base of the first region of the active layer of the fifth transistor. The third insulating layer, the second insulating layer, and the first insulating layer within the eighth via H8 are etched to expose the surface of the first region of the active layer of the fourth transistor. The eighth via H8 is configured to connect the first pole of a subsequently formed fifth transistor to the first region of the active layer of the fifth transistor through the via.

[0226] 19, the orthogonal projection of the base of the ninth via H9 is within the range of the orthogonal projection of the base of the first region of the active layer of the sixth transistor. The third insulating layer, the second insulating layer, and the first insulating layer in the ninth via H9 are etched to expose the surface of the first region of the active layer of the fourth transistor. The ninth via H9 is configured to connect the first pole of a subsequently formed sixth transistor to the first region of the active layer of the sixth transistor through the via.

[0227] 19, the orthogonal projection of the base of the tenth via H10 is within the range of the orthogonal projection of the base of the second region of the active layer of the seventh transistor. The third insulating layer, the second insulating layer, and the first insulating layer in the tenth via H10 are etched to expose the surface of the second region of the active layer of the fourth transistor. The tenth via H10 is configured to connect the second pole of a subsequently formed seventh transistor to the second region of the active layer of the seventh transistor through the via.

[0228] 19, the orthogonal projection of the base of the via H11 is within the range of the orthogonal projection of the base of the first region of the active layer of the eighth transistor. The third insulating layer, the second insulating layer, and the first insulating layer in the via H11 are etched to expose the surface of the first region of the active layer of the fourth transistor. The via H11 is configured to connect the first pole of a subsequently formed eighth transistor to the first region of the active layer of the eighth transistor through the via.

[0229] 19, the orthogonal projection of the base of the twelfth via H12 is within the range of the orthogonal projection of the base of the second region of the active layer of the eighth transistor. The third insulating layer, the second insulating layer, and the first insulating layer in the twelfth via H12 are etched to expose the surface of the first region of the active layer of the fourth transistor. The twelfth via H12 is configured to connect the second pole of a subsequently formed eighth transistor to the second region of the active layer of the eighth transistor through the via.

[0230] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the via H13 is within the range of the orthogonal projection of the base of the control pole of the first transistor. The third insulating layer and the second insulating layer in the via H13 are etched to expose the surface of the control pole of the first transistor. The via H13 is configured to connect the first clock sub-segment of the second clock signal line and the first pole of the second transistor to the control pole of the first transistor, which will be subsequently formed through the via.

[0231] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the fourteenth via H14 is within the range of the orthogonal projection of the base of the control pole of the second transistor. The third insulating layer and the second insulating layer in the fourteenth via H14 are etched to expose the surface of the control pole of the first transistor. The fourteenth via H14 is configured to connect the second pole of the first transistor (which is also the second pole of the seventh transistor and the first pole of the eighth transistor) to the control pole of the first transistor, which will be subsequently formed, through the via.

[0232] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the fifteenth via H15 is within the range of the orthogonal projection of the base of the control pole of the third transistor. The third insulating layer and the second insulating layer in the fifteenth via H15 are etched to expose the surface of the control pole of the second transistor. The fifteenth via H15 is configured to connect the first clock sub-segment of the second clock signal line, which will be subsequently formed, to the control pole of the third transistor through the via.

[0233] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the sixteenth via H16 is within the range of the orthogonal projection of the base of the control pole of the fifth transistor. The third insulating layer and the second insulating layer in the sixteenth via H16 are etched to expose the surface of the control pole of the fifth transistor. The sixteenth via H16 is configured to connect the second pole of a subsequently formed eighth transistor to the control pole of the fifth transistor through the via.

[0234] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the 17th via H17 is within the range of the orthogonal projection of the base of the control pole of the sixth transistor. The third insulating layer and the second insulating layer in the 17th via H17 are etched to expose the surface of the control pole of the sixth transistor. The 17th via H17 is configured to connect the second pole of the second transistor (which is also the second pole of the third transistor) to be subsequently formed through the via to the control pole of the sixth transistor.

[0235] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the via H18 is within the range of the orthogonal projection of the base of the control pole of the seventh transistor. The third insulating layer and the second insulating layer in the via H18 are etched to expose the surface of the control pole of the seventh transistor. The via H18 is configured to connect the first pole of the fifth transistor and the first clock sub-segment of the first clock signal line, which will be subsequently formed, to the control pole of the seventh transistor through the via.

[0236] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the 19th via H19 is within the range of the orthogonal projection of the base of the control pole of the 8th transistor. The third insulating layer and the second insulating layer in the 19th via H19 are etched to expose the surface of the control pole of the 8th transistor. The 19th via H19 is configured to connect the first pole of a subsequently formed third transistor to the control pole of the 8th transistor through the via.

[0237] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the 20th via H20 is within the range of the orthogonal projection of the base of the first connecting line. The third insulating layer and the second insulating layer in the 20th via H20 are etched to expose the surface of the first connecting line. The 20th via H20 is configured to connect the first pole of a subsequently formed first transistor to the first connecting line through the via.

[0238] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the via H21 is within the range of the orthogonal projection of the base of the second plate of the first capacitor. The third insulating layer in the via H21 is etched to expose the surface of the second plate of the first capacitor. The via H21 is configured to connect the first pole of a subsequently formed fourth transistor to the second plate of the first capacitor through the via.

[0239] In an exemplary embodiment, as shown in Figure 19, the orthogonal projection of the base of the via H22 is within the range of the orthogonal projection of the base of the second plate of the second capacitor. The third insulating layer in the via H22 is etched to expose the surface of the second plate of the second capacitor. The via H22 is configured to connect the second pole of a subsequently formed fourth transistor (which is also the second pole of a fifth transistor) to the second plate of the second capacitor through the via.

[0240] In an exemplary embodiment, as shown in Fig. 19, the orthogonal projection of the base of the via H23 is within the range of the orthogonal projection of the base of the third output signal line. The third insulating layer in the via H23 is etched to expose the surface of the third output signal line. The via H23 is configured to connect a first initial sub-segment of a subsequently formed first initial power supply line to the third output signal line through the via.

[0241] (5) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 20 and 21, forming the third conductive layer may include depositing a third conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer disposed on the third insulating layer. FIG. 20 is a schematic diagram of the third conductive layer pattern of FIG. 9A, and FIG. 21 is a schematic diagram of FIG. 9A after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0242] In an exemplary embodiment, as shown in FIGS. 20 and 21 , the third conductive layer pattern may include at least a first clock subsegment GCK1A of the first clock signal line, a first clock subsegment GCK2A of the second clock signal line, a second power supply line VGL, a first initial subsegment INITL1A of the first initial power supply line, a first initial subsegment INITL2A of the second initial power supply line, a fourth output signal line OUTL4, a first pole T13 and a second pole T14 of the first transistor to a first pole T53 and a second pole T54 of the fifth transistor, a first pole T63 of the sixth transistor, a second pole T74 of the seventh transistor, and a first pole T83 and a second pole T84 of the eighth transistor.

[0243] In an exemplary embodiment, as shown in Figures 20 and 21, the shape of the first clock subsegment GCK2A of the second clock signal line may be a line with at least a portion extending along the first direction D1, and the first clock subsegment GCK2A of the second clock signal line is connected to the control pole of the first transistor via the 13th via and connected to the control pole of the third transistor via the 15th via.

[0244] 20 and 21, the first clock subsegment GCK1A of the first clock signal line may have a linear shape with at least a portion extending along the first direction D1, and the first clock subsegment GCK1A of the first clock signal line is located closer to the display area than the first clock subsegment GCK2A of the second clock signal line. The first clock subsegment GCK1A of the first clock signal line is connected to the control pole of the seventh transistor through the eighteenth via.

[0245] In an exemplary embodiment, as shown in Figures 20 and 21, the first clock subsegment GCK2A of the second clock signal line and the first clock subsegment GCK1A of the first clock signal line may have equal or unequal widths, and may be straight or polygonal. This not only facilitates the layout of the scan drive circuit but also reduces parasitic capacitance between signal lines. The present disclosure is not limited thereto.

[0246] 20 and 21, in an exemplary embodiment, the second power supply line VGL and the first pole T33 of the third transistor have an integrated structure. The second power supply line VGL may have a linear shape with at least a portion extending along the first direction D1, and the second power supply line VGL is located on a side of the first clock signal line closer to the display area of ​​the first clock subsegment GCK1A. The first pole T33 of the third transistor is located on a side of the second power supply line VGL closer to the display area, and the first pole T33 of the third transistor is connected to the first region of the active layer of the third transistor through a fifth via and to the control pole of the eighth transistor through a nineteenth via.

[0247] In an exemplary embodiment, the width of the second power supply line VGL may be smaller than the width of the first clock subsegment GCK2A of the second clock signal line or the first clock subsegment GCK1A of the first clock signal line.

[0248] 20 and 21, the first pole T13 of the first transistor may extend along the second direction D2. The first pole T13 of the first transistor is connected to a first region of the active layer of the first transistor through a first via and to a first connection line through a T20 via. The first connection line is connected to the second pole of the fourth transistor (which is also the second pole of the fifth transistor) of the scanning shift register of the previous stage, thereby realizing a cascade connection between the scanning shift register of the current stage and the scanning shift register of the previous stage.

[0249] In an exemplary embodiment, as shown in Figures 20 and 21, the second pole T14 of the first transistor, the second pole T74 of the seventh transistor, and the first pole T83 of the eighth transistor may be an integrated structure, connected to the second region of the active layer of the first transistor through the second via, connected to the control pole of the second transistor through the fourteenth via, connected to the second region of the active layer of the seventh transistor through the tenth via, and connected to the first region of the active layer of the eighth transistor through the eleventh via.

[0250] 20 and 21, the first pole T23 of the second transistor may be linear and extend along the first direction D1. The first pole T23 of the second transistor may be connected to the first region of the active layer of the second transistor through a third via and to the control pole of the first transistor through a thirteenth via.

[0251] 20 and 21, the second pole T24 of the second transistor and the second pole T34 of the third transistor may have an integrated structure and may be a line extending along the second direction D2. The integrated structure of the second pole T24 of the second transistor and the second pole T34 of the third transistor may be connected to the second region of the active layer of the second transistor (which is also the second region of the active layer of the third transistor) through the fourth via and to the control pole of the sixth transistor through the seventeenth via.

[0252] 20 and 21, the second pole T24 of the second transistor and the second pole T34 of the third transistor may have an integrated structure and may be a line extending along the second direction D2. The integrated structure of the second pole T24 of the second transistor and the second pole T34 of the third transistor may be connected to the second region of the active layer of the second transistor (which is also the second region of the active layer of the third transistor) through the fourth via and to the control pole of the sixth transistor through the seventeenth via.

[0253] 20 and 21, the first pole T43 of the fourth transistor and the first pole T63 of the sixth transistor may be an integrated structure, at least a portion of which extends along the second direction D2. The integrated structure of the first pole T43 of the fourth transistor and the first pole T63 of the sixth transistor may be connected to the first region of the active layer of the fourth transistor through a sixth via, connected to the first region of the active layer of the sixth transistor through a ninth via, and connected to the second plate of the first capacitor through a twenty-first via.

[0254] 20 and 21, the second pole T44 of the fourth transistor and the second pole T54 of the fifth transistor may be an integrated structure having a horizontally inverted "F" shape. The integrated structure of the second pole T44 of the fourth transistor and the second pole T54 of the fifth transistor may be connected to the second region of the active layer of the fourth transistor (which is also the second region of the active layer of the fifth transistor) through via 7 and to the second plate of the second capacitor through via 22.

[0255] In an exemplary embodiment, the first pole T53 of the fifth transistor may have an "n" shape that opens to the display area, as shown in Figures 20 and 21. The first pole T53 of the fifth transistor may be connected to the first region of the active layer of the fifth transistor through an eighth via and to the control pole of the seventh transistor through an eighth via.

[0256] 20 and 21, the second pole T84 of the eighth transistor may extend at least partially along the second direction D2. The second pole T84 of the eighth transistor may be connected to the second region of the active layer of the eighth transistor through a 12th via and to the control pole of the fifth transistor through a 16th via.

[0257] In an exemplary embodiment, as shown in Figures 20 and 21, the first initial sub-segment INITL2A of the second initial power supply line and the fourth output signal line OUTL4 have an integrated structure, and the fourth output signal line OUTL4 is located on the side of the first initial sub-segment INITL2A of the second initial power supply line closer to the display area.

[0258] 20 and 21, the first initial subsegment INITL2A of the second initial feed line may have a linear shape extending at least partially along the first direction D1 and may include a plurality of feed electrodes spaced apart. The first initial subsegment INITL2A of the second initial feed line may be located on a side closer to the display area of ​​the integrated structure of the second pole T44 of the fourth transistor and the second pole T54 of the fifth transistor.

[0259] In an exemplary embodiment, as shown in FIGS. 20 and 21, at least a portion of the fourth output signal line OUTL4 may extend along the second direction D2.

[0260] In an exemplary embodiment, as shown in FIGS. 20 and 21, the orthogonal projection at the base of the first initial subsegment INITL2A of the second initial feedline and the orthogonal projection at the base of the second plate of the first capacitor and the second plate of the second capacitor at least partially overlap.

[0261] 20 and 21, the first initial subsegment INITL1A of the first initial feed line may have a linear shape extending at least partially along the first direction D1 and may include a plurality of feed electrodes spaced apart. The first initial subsegment INITL1A of the first initial feed line may be located closer to the display area than the first initial subsegment INITL2A of the second initial feed line.

[0262] In an exemplary embodiment, as shown in Figures 20 and 21, the first initial subsegment INITL1A of the first initial feed line and the first initial subsegment INITL2A of the second initial feed line may have equal or unequal widths, and may be straight or polygonal. This not only facilitates the layout of the scan drive circuit but also reduces parasitic capacitance between signal lines. The present disclosure is not limited thereto.

[0263] (6) Forming a fourth insulating layer pattern. In an exemplary embodiment, as shown in FIG. 22, forming the fourth insulating layer pattern may include depositing a fourth insulating thin film on the base on which the above-mentioned pattern is formed, and patterning the fourth insulating thin film through a patterning process to form a fourth insulating layer covering the third conductive layer, and a plurality of vias are formed in the fourth insulating layer. FIG. 22 is a schematic diagram of FIG. 9A after the fourth insulating layer pattern is formed.

[0264] In the exemplary embodiment, the plurality of vias includes at least the 24th via H24 to the 28th via H28.

[0265] In an exemplary embodiment, as shown in Figure 22, the orthogonal projection of the base of the 24th via H24 is within the range of the orthogonal projection of the base of the first pole of the fourth transistor. The fourth insulating layer of the 24th via H24 is etched to expose the surface of the first pole of the fourth transistor. The 24th via H24 is configured to connect a subsequently formed first power line to the first pole of the fourth transistor through the via.

[0266] In an exemplary embodiment, as shown in Figure 22, the orthogonal projection of the base of the 25th via H25 is within the range of the orthogonal projection of the base of the first clock subsegment of the second clock signal line. The fourth insulating layer of the 24th via H24 is etched to expose the surface of the first clock subsegment of the second clock signal line. The 24th via H24 is configured to connect the second clock subsegment of the second clock signal line to the first clock subsegment of the second clock signal line, which will be subsequently formed, through the via.

[0267] In an exemplary embodiment, as shown in Figure 22, the orthogonal projection of the base of the 26th via H26 is within the range of the orthogonal projection of the base of the first clock subsegment of the first clock signal line. The fourth insulating layer of the 25th via H25 is etched to expose the surface of the first clock subsegment of the first clock signal line. The 25th via H25 is configured to connect a subsequently formed second clock subsegment of the first clock signal line to the first clock subsegment of the first clock signal line through the via.

[0268] In an exemplary embodiment, as shown in Figure 22, the orthogonal projection of the base of the 27th via H27 is within the range of the orthogonal projection of the base of the first initial subsegment of the second initial feed line. The fourth insulating layer of the 27th via H27 is etched to expose the surface of the first initial subsegment of the second initial feed line. The 27th via H27 is configured to connect the second initial subsegment of the second initial feed line, which will be subsequently formed, to the first initial subsegment of the second initial feed line through the via.

[0269] In an exemplary embodiment, as shown in Figure 22, the orthogonal projection of the base of the 28th via H28 is within the range of the orthogonal projection of the base of the first initial subsegment of the first initial feed line. The fourth insulating layer of the 28th via H28 is etched to expose the surface of the first initial subsegment of the first initial feed line. The 28th via H28 is configured to connect a subsequently formed second initial subsegment of the first initial feed line to the first initial subsegment of the first initial feed line through the via.

[0270] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 23 and 24, forming the fourth conductive layer may include depositing a fourth conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the fourth conductive thin film through a patterning process to form a fourth conductive layer disposed on the fourth insulating layer. FIG. 23 is a schematic diagram of the fourth conductive layer in FIG. 9A, and FIG. 24 is a schematic diagram of FIG. 9A after the fourth conductive layer is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0271] In an exemplary embodiment, as shown in FIGS. 23 and 24 , the fourth conductive layer pattern may include at least a second clock subsegment GCK1B of the first clock signal line, a second clock subsegment GCK2B of the second clock signal line, a first power supply line VGH, a second initial subsegment INITL1B of the first initial power supply line, a second initial subsegment INITL2B of the second initial power supply line, a first initial signal line GSTV, and a second initial signal line ESTV.

[0272] 23 and 24, the second clock subsegment GCK2B of the second clock signal line may have a linear shape with at least a portion extending along the first direction D1. The orthogonal projection of the second clock subsegment GCK2B of the second clock signal line at the base and the orthogonal projection of the first clock subsegment of the second clock signal line at the base at least partially overlap and are connected to the first clock subsegment of the second clock signal line via via No. 25, thereby forming the second clock signal line.

[0273] 23 and 24, the second clock subsegment GCK1B of the first clock signal line may have a linear shape with at least a portion extending along the first direction D1. The orthogonal projection of the second clock subsegment GCK1B of the first clock signal line at the base and the orthogonal projection of the first clock subsegment of the first clock signal line at the base at least partially overlap, and are connected to the first clock subsegment of the first clock signal line through via No. 26, thereby forming the first clock signal line.

[0274] In an exemplary embodiment, as shown in Figures 23 and 24, the second initial subsegment GCK2B of the second clock signal line and the second clock subsegment GCK1B of the first clock signal line may have equal or unequal widths, and may be straight or polygonal. This not only facilitates the layout of the scan drive circuit but also reduces parasitic capacitance between signal lines. The present disclosure is not limited thereto.

[0275] In an exemplary embodiment, as shown in Figures 23 and 24, the second initial signal line ESTV is located on a side of the first clock signal line closer to the display area of ​​the second clock subsegment GCK1B, and the orthogonal projection at the base at least partially overlaps with the orthogonal projection at the base of the first pole of the third transistor.

[0276] In an exemplary embodiment, as shown in Figures 23 and 24, the first initial signal line GSTV is located on the side closer to the display area than the second initial signal line ESTV, and the orthogonal projection at the base at least partially overlaps with the orthogonal projection at the base of the control electrode of the eighth transistor.

[0277] In an exemplary embodiment, as shown in Figures 23 and 24, the second initial signal line ESTV and the first initial signal line GSTV may have equal or unequal widths, and may be straight or polygonal. This not only facilitates the layout of the scan drive circuit but also reduces parasitic capacitance between the signal lines. The present disclosure is not limited thereto.

[0278] 23 and 24, the first power supply line VGH may have a linear shape with at least a portion extending along the first direction D1. The orthogonal projection of the base of the first power supply line VGH at least partially overlaps with the orthogonal projections of the second pole of the fourth transistor (which is also the second pole of the fifth transistor) and the first pole of the fourth transistor at the base, and is connected to the first pole of the fourth transistor through via 24.

[0279] 23 and 24, the second initial subsegment INITL2B of the second initial feed line may have a linear shape with at least a portion extending along the first direction D1. The orthogonal projection of the second initial subsegment INITL2B of the second initial feed line at the base and the orthogonal projection of the first initial subsegment of the second initial feed line at the base at least partially overlap and are connected to the first initial subsegment of the second initial feed line through via 27 to form the second initial feed line.

[0280] 23 and 24 , the second initial subsegment INITL1B of the first initial feed line may have a linear shape with at least a portion extending along the first direction D1. The orthogonal projection of the second initial subsegment INITL1B of the first initial feed line at the base and the orthogonal projection of the first initial subsegment of the first initial feed line at the base at least partially overlap and are connected to the first initial subsegment of the first initial feed line through via 28, thereby forming the first initial feed line.

[0281] In an exemplary embodiment, as shown in Figures 23 and 24, the second initial subsegment INITL2B of the second initial feed line and the second initial subsegment INITL1B of the first initial feed line may have equal or unequal widths, and may be straight or polygonal. This not only facilitates the layout of the scan drive circuit but also reduces parasitic capacitance between signal lines. The present disclosure is not limited thereto.

[0282] (8) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include sequentially depositing a fifth insulating thin film and a fifth conductive thin film on the base on which the pattern is formed, and patterning the fifth conductive thin film through a patterning process to form a fourth insulating layer covering the fourth conductive layer pattern and a fifth conductive layer pattern disposed on the fourth insulating layer. In an exemplary embodiment, the fifth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0283] In an exemplary embodiment, the fifth conductive layer pattern may include at least a first output connection line, a second output connection line, a third output connection line, and a fourth output connection line.

[0284] In an exemplary embodiment, the first output connection line is connected to the first output signal line, the second output connection line is connected to the second output signal line, the third output connection line is connected to the third output signal line, and the fourth output connection line is connected to the fourth output signal line.

[0285] Up to this point, the fabrication of the driving circuit layer on the base is completed, and the driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a fifth conductive layer, which are sequentially disposed on the base.

[0286] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. Examples of the metal oxide layer include an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, and an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer. The active layer thin film may employ various materials, such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium-zinc-tin-oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, and the like. That is, the present disclosure applies to transistors fabricated based on oxide technology, silicon technology, and organic technology.

[0287] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer may employ a metal material, such as one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0288] In an exemplary embodiment, the first, second, third, fourth, and fifth insulating layers may employ one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single, multiple, or composite layers. The first and second insulating layers may be referred to as gate insulating (GI) layers, the third and fourth insulating layers may be referred to as interlayer dielectric (ILD) layers, and the fifth insulating layer may be referred to as a photo-transistor (PVX) layer.

[0289] In an exemplary embodiment, when the second output signal line has a two-layer structure, the second conductive layer pattern formed in step (3) includes a first output sub-segment of the second output signal line, and the method may include forming a sixth conductive layer pattern between steps (3) and (4). The formation of the sixth conductive layer pattern may include sequentially depositing a sixth insulating thin film and a sixth conductive thin film on the base on which the aforementioned pattern is formed, and patterning the sixth conductive thin film by a patterning process to form a sixth insulating layer covering the second conductive layer pattern and a sixth conductive layer pattern disposed on the sixth insulating layer.

[0290] In an exemplary embodiment, the sixth conductive layer pattern may include at least a second output sub-segment of the second output signal line.

[0291] In the exemplary embodiment, step (4) forms a fourth insulating layer covering the sixth conductive layer, and subsequent steps are similar to the flow of forming FIG. 9A in the above-described embodiment, and will not be repeated in this disclosure.

[0292] In an exemplary embodiment, the sixth conductive layer may adopt a metal material, such as one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0293] In an exemplary embodiment, the sixth insulating layer may employ one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0294] In an exemplary embodiment, after the fabrication of the driving circuit layer is completed, a light emitting structure layer is fabricated on the driving circuit layer, and the fabrication process of the light emitting structure layer may include the following operations:

[0295] (9) Forming a light-emitting structure layer. In an exemplary embodiment, forming the light-emitting structure layer may include: applying a first planar thin film on the patterned base, patterning the first planar thin film through a patterning process to form a first planar layer; depositing an anode conductive thin film on the patterned base, patterning the anode conductive thin film through a patterning process to form an anode conductive layer disposed on the planar layer, the anode conductive layer including at least a plurality of anode patterns; applying a pixel-defining thin film on the patterned base, and patterning the pixel-defining thin film through a patterning process to form the pixel-defining layer; first forming an organic light-emitting layer on the patterned base by vapor deposition or inkjet printing, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer.

[0296] In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers and can prevent external water vapor from penetrating into the light-emitting structure layer.

[0297] In an exemplary embodiment, the material of the pixel defining layer may include polyimide, acrylic, or polyethylene terephthalate.

[0298] In an exemplary embodiment, the planarization layer may employ an organic material.

[0299] In an exemplary embodiment, the anode thin film may employ indium tin oxide (ITO) or indium zinc oxide (IZO).

[0300] In an exemplary embodiment, the cathode thin film may employ one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy of one or more of the foregoing metals.

[0301] Hereinafter, an exemplary description will be given based on the manufacturing process of Fig. 10A. Fig. 10A shows one dummy scan shift register. The dummy scan shift register includes a first transistor DT1, a second transistor DT2, and a fourth transistor DT4 to an eighth transistor DT8.

[0302] (1) Forming a semiconductor layer pattern on a base. In an exemplary embodiment, as shown in Figure 25, forming the semiconductor layer pattern may include depositing a semiconductor thin film on the base and patterning the semiconductor thin film by a patterning process to form a semiconductor layer pattern. Figure 25 is a schematic view of Figure 10A after the semiconductor layer pattern has been formed.

[0303] In an exemplary embodiment, as shown in FIG. 25, the semiconductor layer pattern may include an active layer DT11 of the first transistor, an active layer DT21 of the second transistor, and an active layer DT41 of the fourth transistor to an active layer DT81 of the eighth transistor.

[0304] In the illustrative embodiment, the active layer DT11 of the first transistor, the active layer DT21 of the second transistor, and the active layer DT61 of the sixth transistor to the active layer DT81 of the eighth transistor in Fig. 25 are positioned and structured the same as the active layer T11 of the first transistor, the active layer T21 of the second transistor, and the active layer T61 of the sixth transistor to the active layer T81 of the eighth transistor in Fig. 14. The difference is that the active layer DT41 of the fourth transistor and the active layer DT51 of the fifth transistor in Fig. 25 may have an integrated structure of "I".

[0305] (2) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 26 and 27, forming the first conductive layer pattern may include sequentially depositing a first insulating thin film and a first conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the first conductive thin film through a patterning process to form a first insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the first insulating layer. FIG. 26 is a schematic diagram of the first conductive layer pattern of FIG. 10A, and FIG. 27 is a schematic diagram of FIG. 10A after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0306] In an exemplary embodiment, as shown in Figures 26 and 27, the first conductive layer pattern may include at least a control pole DT12 of the first transistor, a control pole DT22 of the second transistor, a control pole DT42 of the fourth transistor to a control pole DT82 of the eighth transistor, and a first connecting line VL1.

[0307] In an exemplary embodiment, as shown in Figures 26 and 27, the control pole DT42 of the fourth transistor, the control pole DT62 of the sixth transistor to the control pole DT82 of the eighth transistor may be an integrated structure, and the control pole DT12 of the first transistor, the control pole DT22 of the second transistor, and the control pole DT52 of the fifth transistor may be installed separately.

[0308] In an exemplary embodiment, the shapes of the control pole T12 of the first transistor, the control pole DT22 of the second transistor, and the first connecting line VL1 in FIG. 26 are the same as the shapes of the control pole DT12 of the first transistor, the control pole DT22 of the second transistor, and the first connecting line VL1 in FIG. 15.

[0309] In an exemplary embodiment, as shown in Figures 26 and 27, the control pole DT42 of the fourth transistor may have a comb-like structure with an opening facing the display area, the control poles DT62 of the sixth transistor to the control poles DT82 of the eighth transistor are located on the side of the comb-shaped ridge of the control pole DT42 of the fourth transistor away from the display area, the control pole DT62 of the sixth transistor and the control pole DT72 of the seventh transistor may be linear extending along the second direction D2, and the control pole DT82 of the eighth transistor may be "n" shaped with an opening facing the display area.

[0310] (3) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in FIG. 28, forming the third insulating layer pattern may include depositing a second insulating thin film and a third insulating thin film on the base on which the above-mentioned pattern is formed, and patterning the second insulating thin film and the third insulating thin film through a patterning process to form a second insulating layer and a third insulating layer covering the first conductive layer, and a plurality of via patterns are formed in the third insulating layer. FIG. 28 is a schematic diagram of FIG. 10A after the third insulating layer pattern is formed.

[0311] 28, the multiple via patterns may include at least a first via H1 to a seventeenth via H17. The first via H1 to the eleventh via H11 are opened in the first to third insulating layers, and the twelfth via H12 to the seventeenth via H17 are opened in the second and third insulating layers. The first via H1 exposes a first region of the active layer of the first transistor, the second via H2 exposes a second region of the active layer of the first transistor, the third via H3 exposes a first region of the active layer of the second transistor, the fourth via H4 exposes a second region of the active layer of the second transistor, the fifth via H5 exposes a first region of the active layer of the fourth transistor, the sixth via H6 exposes a second region of the active layer of the fourth transistor (the second region of the active layer of the fifth transistor), the seventh via H7 exposes a first region of the active layer of the fifth transistor, and the eighth via H8 exposes a first region of the active layer of the sixth transistor. The ninth via H9 exposes a second region of the active layer of the seventh transistor, the tenth via H10 exposes a first region of the active layer of the eighth transistor, the eleventh via H11 exposes a second region of the active layer of the eighth transistor, the twelfth via H12 exposes a control electrode of the first transistor, the thirteenth via H13 exposes a control electrode of the second transistor, the fourteenth via H14 exposes a control electrode of the sixth transistor, the fifteenth via H15 exposes a control electrode of the fifth transistor, the sixteenth via H16 exposes a control electrode of the fourth transistor, and the seventeenth via H17 exposes the first connecting line.

[0312] (4) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 29 and 30, forming the third conductive layer may include depositing a third conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer disposed on the third insulating layer. FIG. 29 is a schematic diagram of the third conductive layer pattern of FIG. 10A, and FIG. 30 is a schematic diagram of FIG. 10A after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0313] In an exemplary embodiment, as shown in FIGS. 29 and 30 , the third conductive layer pattern may include at least a first clock subsegment GCK1A of the first clock signal line, a first clock subsegment GCK2A of the second clock signal line, a second power supply line VGL, a first initial subsegment INITL1A of the first initial power supply line, a first initial subsegment INITL2A of the second initial power supply line, a first pole T13 and a second pole T14 of the first transistor, a first pole T23 and a second pole T24 of the second transistor, a first pole T43 and a second pole T44 of the fourth transistor, a first pole T53 and a second pole T54 of the fifth transistor, a first pole T63 of the sixth transistor, a second pole T74 of the seventh transistor, and a first pole T83 and a second pole T84 of the eighth transistor.

[0314] In an exemplary embodiment, the first clock subsegment GCK2A of the second clock signal line, the first clock subsegment GCK1A of the first clock signal line, the second power supply line VGL, the first initial subsegment INITL1A of the first initial power supply line, and the first initial subsegment INITL2A of the second initial power supply line in FIGS. 29 and 30 are the same as the first clock subsegment GCK2A of the second clock signal line, the first clock subsegment GCK1A of the first clock signal line, the second power supply line VGL, the first initial subsegment INITL1A of the first initial power supply line, and the first initial subsegment INITL2A of the second initial power supply line in FIGS. 20 and 21.

[0315] 29 and 30, the second power line VGL, the second pole of the first transistor, the first pole T23 and second pole T24 of the second transistor, the second pole T74 of the seventh transistor, and the first pole T83 of the eighth transistor are integrated into one structure. The second pole of the first transistor, the first pole T23 and second pole T24 of the second transistor, the second pole T74 of the seventh transistor, and the first pole T83 of the eighth transistor are located on the side of the second power line VGL closer to the display area. The integrated structure of the second power supply line VGL, the second pole of the first transistor, the first pole T23 and the second pole T24 of the second transistor, the second pole T74 of the seventh transistor, and the first pole T83 of the eighth transistor is connected to the first region of the active layer of the first transistor through the second via, to the first region of the active layer of the second transistor through the third via, to the second region of the active layer of the second transistor through the fourth via, to the second region of the active layer of the seventh transistor through the ninth via, to the first region of the active layer of the eighth transistor through the tenth via, and to the control pole of the first transistor through the twelfth via.

[0316] In an exemplary embodiment, the first pole T13 of the first transistor shown in FIGS. 29 and 30 is the same as the first pole T13 of the first transistor in FIGS.

[0317] In an exemplary embodiment, as shown in Figures 29 and 30, the first pole T43 and the second pole T44 of the fourth transistor, the first pole T53 and the second pole T54 of the fifth transistor, the first pole T63 of the sixth transistor, and the second pole T84 of the eighth transistor are an integrated structure, and are connected to a first region of the active layer of the fourth transistor through a fifth via, connected to a second region of the active layer of the fourth transistor (the second region of the active layer of the fifth transistor) through a sixth via, connected to a first region of the active layer of the fifth transistor through a seventh via, connected to a first region of the active layer of the sixth transistor through an eighth via, connected to a second region of the active layer of the eighth transistor through an eleventh via, connected to a control pole of the second transistor through a thirteenth via, connected to a control pole of the fifth transistor through a fifteenth via, and connected to a control pole of the fourth transistor through a sixteenth via.

[0318] (5) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 31 and 32, forming the fourth conductive layer may include sequentially depositing a fourth insulating thin film and a fourth conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the fourth insulating thin film and the fourth conductive thin film through a patterning process to form a fourth insulating layer covering the third conductive layer and a fourth conductive layer disposed on the fourth insulating layer. FIG. 31 is a schematic diagram of the fourth conductive layer in FIG. 10A, and FIG. 32 is a schematic diagram of FIG. 10A after the fourth conductive layer has been formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0319] In an exemplary embodiment, as shown in FIGS. 31 and 32 , the fourth conductive layer pattern may include at least a second clock subsegment GCK1B of the first clock signal line, a second clock subsegment GCK2B of the second clock signal line, a first power supply line VGH, a second initial subsegment INITL1B of the first initial power supply line, a second initial subsegment INITL2B of the second initial power supply line, a first initial signal line GSTV, and a second initial signal line ESTV. The second clock subsegment GCK1B of the first clock signal line, the second clock subsegment GCK2B of the second clock signal line, the first power supply line VGH, the second initial subsegment INITL1B of the first initial power supply line, the second initial subsegment INITL2B of the second initial power supply line, the first initial signal line GSTV, and the second initial signal line ESTV in FIGS. 31 and 32 have the same structure as the second clock subsegment GCK1B of the first clock signal line, the second clock subsegment GCK2B of the second clock signal line, the first power supply line VGH, the second initial subsegment INITL1B of the first initial power supply line, the second initial subsegment INITL2B of the second initial power supply line, the first initial signal line GSTV, and the second initial signal line ESTV in FIGS. 23 and 24, and differ only in the spacing between the signal lines.

[0320] In an exemplary embodiment, after the driving circuit layer is fabricated, a light emitting structure layer is fabricated on the driving circuit layer, and the fabrication process of the light emitting structure layer is the same as that of the previous embodiment, and therefore will not be repeated here.

[0321] Hereinafter, an exemplary description will be given using the manufacturing process of Fig. 10B. Fig. 10B shows one dummy scan shift register. The dummy scan shift register includes a first transistor DT1, a second transistor DT2, and sixth to eighth transistors DT6 to DT8.

[0322] (1) Forming a semiconductor layer pattern on a base. In an exemplary embodiment, as shown in Figure 33, forming the semiconductor layer pattern may include depositing a semiconductor thin film on the base and patterning the semiconductor thin film by a patterning process to form a semiconductor layer pattern. Figure 33 is a schematic view of Figure 10B after the semiconductor layer pattern has been formed.

[0323] In an exemplary embodiment, as shown in FIG. 33, the semiconductor layer pattern may include an active layer DT11 of the first transistor, an active layer DT21 of the second transistor, and an active layer DT61 of the sixth transistor to an active layer DT81 of the eighth transistor.

[0324] In an exemplary embodiment, the active layer DT11 of the first transistor, the active layer DT21 of the second transistor, and the active layer DT61 of the sixth transistor to the active layer DT81 of the eighth transistor in Figure 33 are in the same position and structure as the active layer T11 of the first transistor, the active layer T21 of the second transistor, and the active layer T61 of the sixth transistor to the active layer T81 of the eighth transistor in Figure 14.

[0325] (2) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 34 and 35, forming the first conductive layer pattern may include sequentially depositing a first insulating thin film and a first conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the first conductive thin film through a patterning process to form a first insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the first insulating layer. FIG. 34 is a schematic diagram of the first conductive layer pattern of FIG. 10B, and FIG. 35 is a schematic diagram of FIG. 10B after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0326] In an exemplary embodiment, as shown in Figures 34 and 35, the first conductive layer pattern may include at least a control pole DT12 of the first transistor, a control pole DT22 of the second transistor, a control pole DT62 of the sixth transistor to a control pole DT82 of the eighth transistor, a first connecting line VL1, and a second connecting line VL2.

[0327] In an exemplary embodiment, as shown in FIGS. 34 and 35, the control pole T62 of the sixth transistor to the control pole DT82 of the eighth transistor are an integrated structure, and the control pole DT12 of the first transistor and the control pole DT22 of the second transistor are an integrated structure.

[0328] In an exemplary embodiment, the shapes of the control pole T12 of the first transistor, the control pole DT22 of the second transistor, and the first connecting line VL1 in FIG. 34 are the same as the shapes of the control pole DT12 of the first transistor, the control pole DT22 of the second transistor, and the first connecting line VL1 in FIG. 25.

[0329] (3) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in Figure 36, forming the third insulating layer pattern may include depositing a second insulating thin film and a third insulating thin film on the base on which the above-mentioned pattern is formed, and patterning the second insulating thin film and the third insulating thin film by a patterning process to form a second insulating layer and a third insulating layer covering the first conductive layer, and a plurality of via patterns are formed in the third insulating layer. Figure 36 is a schematic diagram of Figure 10B after the third insulating layer pattern is formed.

[0330] 36, the multiple via patterns may include at least a first via H1 to a thirteenth via H13. The first via H1 to the eighth via H8 are opened in the first to third insulating layers, and the ninth via H9 to the thirteenth via H13 are opened in the second and third insulating layers. The first via H1 exposes a first region of the active layer of the first transistor, the second via H2 exposes a second region of the active layer of the first transistor, the third via H3 exposes a first region of the active layer of the second transistor, the fourth via H4 exposes a second region of the active layer of the second transistor, the fifth via H5 exposes a first region of the active layer of the sixth transistor, the sixth via H6 exposes a second region of the active layer of the seventh transistor, and the seventh via H7 exposes a second region of the active layer of the eighth transistor. The via H11 exposes the first region of the active layer, the via H8 exposes the second region of the active layer of the eighth transistor, the via H9 exposes the control pole of the first transistor, the via H10 exposes the control pole of the second transistor, the via H11 exposes the integrated structure of the control pole of the sixth transistor, the control pole of the seventh transistor, and the control pole of the eighth transistor, the via H12 exposes the first connecting line, and the via H13 exposes the second connecting line.

[0331] (4) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 37 and 38, forming the third conductive layer may include depositing a third conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer disposed on the third insulating layer. FIG. 37 is a schematic diagram of the third conductive layer pattern of FIG. 10B, and FIG. 38 is a schematic diagram of FIG. 10B after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0332] In an exemplary embodiment, as shown in Figures 37 and 38, the third conductive layer pattern may include at least a first clock subsegment GCK1A of the first clock signal line, a first clock subsegment GCK2A of the second clock signal line, a second power supply line VGL, a first initial subsegment INITL1A of the first initial power supply line, a first initial subsegment INITL2A of the second initial power supply line, a first pole T13 and a second pole T14 of the first transistor, a first pole T23 and a second pole T24 of the second transistor, a first pole T63 of the sixth transistor, a second pole T74 of the seventh transistor, and a first pole T83 and a second pole T84 of the eighth transistor.

[0333] In an exemplary embodiment, the first clock subsegment GCK2A of the second clock signal line, the first clock subsegment GCK1A of the first clock signal line, the second power supply line VGL, the first initial subsegment INITL1A of the first initial power supply line, and the first initial subsegment INITL2A of the second initial power supply line in FIGS. 37 and 38 are the same as the first clock subsegment GCK2A of the second clock signal line, the first clock subsegment GCK1A of the first clock signal line, the second power supply line VGL, the first initial subsegment INITL1A of the first initial power supply line, and the first initial subsegment INITL2A of the second initial power supply line in FIGS. 20 and 21.

[0334] In an exemplary embodiment, as shown in Figures 37 and 38, the second power supply line VGL and the second pole of the first transistor, the first pole T23 and second pole T24 of the second transistor, the second pole T74 of the seventh transistor, and the first pole T83 of the eighth transistor are integrated into one structure. The integrated structure of the second power supply line VGL, the second pole of the first transistor, the first pole T23 and second pole T24 of the second transistor, the second pole T74 of the seventh transistor, and the first pole T83 of the eighth transistor in Figures 37 and 28 is the same as that of the second power supply line VGL, the second pole of the first transistor, the first pole T23 and second pole T24 of the second transistor, the second pole T74 of the seventh transistor, and the first pole T83 of the eighth transistor in Figures 30 and 31, and is connected to the first region of the active layer of the first transistor through the second via, the first region of the active layer of the second transistor through the third via, the second region of the active layer of the second transistor through the fourth via, the second region of the active layer of the seventh transistor through the sixth via, the first region of the active layer of the eighth transistor through the seventh via, and the control pole of the first transistor through the ninth via.

[0335] In an exemplary embodiment, as shown in Figures 37 and 38, the first pole T13 of the first transistor, the first pole T63 of the sixth transistor, and the second pole T84 of the eighth transistor are an integrated structure, connected to a first region of the active layer of the first transistor through a first via, connected to a first connecting line through a 12 via, connected to a first region of the active layer of the sixth transistor through a 5 via, connected to a second region of the active layer of the eighth transistor through an 8 via, exposing the integrated structure of the control pole of the sixth transistor, the control pole of the seventh transistor, and the control pole of the eighth transistor through an 11 via, and connected to a second connecting line through a 13 via.

[0336] (5) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 39 and 40, forming the fourth conductive layer may include sequentially depositing a fourth insulating thin film and a fourth conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the fourth insulating thin film and the fourth conductive thin film through a patterning process to form a fourth insulating layer covering the third conductive layer and a fourth conductive layer disposed on the fourth insulating layer. FIG. 39 is a schematic diagram of the fourth conductive layer in FIG. 10B, and FIG. 40 is a schematic diagram of FIG. 10B after the fourth conductive layer has been formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0337] In an exemplary embodiment, as shown in FIGS. 39 and 40 , the fourth conductive layer pattern may include at least a second clock subsegment GCK1B of the first clock signal line, a second clock subsegment GCK2B of the second clock signal line, a first power supply line VGH, a second initial subsegment INITL1B of the first initial power supply line, a second initial subsegment INITL2B of the second initial power supply line, a first initial signal line GSTV, and a second initial signal line ESTV. The second clock subsegment GCK1B of the first clock signal line, the second clock subsegment GCK2B of the second clock signal line, the first power supply line VGH, the second initial subsegment INITL1B of the first initial power supply line, the second initial subsegment INITL2B of the second initial power supply line, the first initial signal line GSTV, and the second initial signal line ESTV in Figures 39 and 40 have the same structure as the second clock subsegment GCK1B of the first clock signal line, the second clock subsegment GCK2B of the second clock signal line, the first power supply line VGH, the second initial subsegment INITL1B of the first initial power supply line, the second initial subsegment INITL2B of the second initial power supply line, the first initial signal line GSTV, and the second initial signal line ESTV in Figures 23 and 24, and differ only in the spacing between the signal lines.

[0338] In an exemplary embodiment, after the driving circuit layer is fabricated, a light emitting structure layer is fabricated on the driving circuit layer, and the fabrication process of the light emitting structure layer is the same as that of the previous embodiment, and therefore will not be repeated here.

[0339] The width of the scanning shift register on the display substrate according to the embodiment of the present disclosure may be about 200 microns to 220 microns, and exemplarily, the width of the scanning shift register on the display substrate may be about 210 microns.

[0340] Simulation results show that the load at the same position on the display substrate according to the embodiment of the present disclosure and the reference display substrate are compared, and the difference between the rising edge time and the falling edge time of the data signal is not significant. That is, the display substrate according to the embodiment of the present disclosure reduces the area occupied by the frame region of the display substrate, realizing a narrow frame, without affecting image quality.

[0341] The display substrate according to the embodiments of the present disclosure can be applied to display products with any resolution.

[0342] An embodiment of the present disclosure further provides a display device comprising a display substrate.

[0343] In an exemplary embodiment, the display device may be any product or component having a display function, such as a display, a television, a mobile phone, a tablet, a navigator, a digital photo frame, or a wearable display product.

[0344] The display substrate may be any of the display substrates according to the above embodiments, and the principles and effects of realization are the same, so they will not be described again here.

[0345] The drawings in this disclosure only relate to the structures according to the embodiments of the present disclosure, and other structures may refer to the general design.

[0346] For clarity, the thickness and size of layers or microstructures are exaggerated in the figures illustrating the embodiments of the present disclosure. It will be understood that when an element, such as a layer, film, region, or substrate, is said to be located "on" or "under" another element, the element may be located "directly" "on" or "under" the other element, or intermediate elements may be present.

[0347] The above are the embodiments disclosed in the present disclosure, but the above contents are the embodiments used to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Those skilled in the art can make any modifications and changes to the embodiments and details without departing from the spirit and scope disclosed in the present disclosure, and the patent protection scope of the present disclosure is subject to the scope of the attached claims. [Explanation of symbols]

[0348] 100 display area 200 hidden area

Claims

1. A display substrate, comprising: a base; and a driving circuit layer disposed on the base, the base including a display area and a non-display area, the driving circuit layer including a pixel driving circuit located in the display area, a gate driving circuit located in the non-display area, and at least one initial power supply line, at least a portion of the initial power supply line extending along a first direction; the gate drive circuit is configured to supply a drive signal to a pixel drive circuit, and the initial power supply line is configured to supply an initial signal to the pixel drive circuit; A display substrate, wherein an orthogonal projection of at least one of the initial power supply lines at a base and an orthogonal projection of the gate drive circuit at a base at least partially overlap.

2. the gate drive circuit includes a plurality of drive circuits arranged along a second direction, the first direction intersecting the second direction; 2. The display substrate according to claim 1, wherein an orthogonal projection of at least one of the initial power supply lines at a base thereof and an orthogonal projection of a drive circuit of the plurality of drive circuits that is closest to a display area at a base thereof at least partially overlap each other.

3. the pixel driving circuit includes a light emitting transistor and a writing transistor, the plurality of driving circuits include a light emitting driving circuit and a scanning driving circuit, the light emitting driving circuit is electrically connected to the light emitting transistor, the scanning driving circuit is electrically connected to the writing transistor, and the scanning driving circuit is located on a side of the light emitting driving circuit close to a display area; 3. The display substrate of claim 2, wherein the orthogonal projection at the base of at least one initial feed line and the orthogonal projection at the base of the scan drive circuit at least partially overlap.

4. the pixel driving circuit comprises a light emitting transistor, a write transistor and a control transistor, the plurality of driving circuits comprise a light emitting driving circuit, a scan driving circuit and a control driving circuit, the light emitting driving circuit is electrically connected to the light emitting transistor, the scan driving circuit is electrically connected to the write transistor, the control driving circuit is electrically connected to the control transistor, the write transistor and the control transistor are of opposite transistor types, and the light emitting driving circuit and the control driving circuit are located on a side of the scan driving circuit away from a display area; 3. The display substrate of claim 2, wherein an orthogonal projection at a base of at least one of the initial feed lines and an orthogonal projection at a base of the scan drive circuit at least partially overlap.

5. the at least one initial feed line includes a first initial feed line to an Nth initial feed line, where N is a positive integer equal to or greater than 1; 5. The display substrate according to claim 3, wherein when N is 2 or more, the N initial feed lines are arranged along the second direction, and orthogonal projections of adjacent K initial feed lines away from the display area at their bases and orthogonal projections of the K initial feed lines at their bases of the scan drive circuit at least partially overlap, and K is a positive integer less than or equal to N.

6. the driving circuit layer further includes a first clock signal line, a second clock signal line, a first initial signal line, a first power supply line, and a second power supply line located in a non-display area, at least a portion of the first clock signal line, the second clock signal line, the first initial signal line, the first power supply line, and the second power supply line extending along a first direction; The scanning driving circuits are electrically connected to a first clock signal line, a second clock signal line, a first power supply line, a second power supply line, and a first initial signal line, respectively; 6. The display substrate according to claim 5, wherein the second clock signal line is located on a side of the first clock signal line away from a display area, the second power supply line is located on a side of the first clock signal line closer to the display area, the first initial signal line is located on a side of the second power supply line closer to the display area, the first power supply line is located on a side of the first initial signal line closer to the display area, and the at least one initial power supply line is located on a side of the first power supply line closer to the display area.

7. the driving circuit layer further includes a second initial signal line located in the non-display area, at least a portion of the second initial signal line extending along a first direction; The display substrate according to claim 6 , wherein the light-emitting driving circuit is electrically connected to the second initial signal line, and the second initial signal line is located between the second power line and the first initial signal line.

8. the driving circuit layer further includes a first output signal line and a second output signal line located in a non-display area, at least a portion of the first output signal line and the second output signal line extending along a second direction; The first output signal lines are located on a side of the scanning driving circuit close to the display area, and are electrically connected to the scanning driving circuit and the pixel driving circuit, respectively; 8. The display substrate according to claim 7, wherein the second output signal lines pass through the scanning driving circuit and are electrically connected to a pixel driving circuit and one of a light emitting driving circuit and a control driving circuit.

9. the driving circuit layer further includes a first output connection line and a second output connection line located in a display region and a non-display region, the first output connection line and the second output connection line at least partially extending along a second direction; the first output connection lines are electrically connected to first output signal lines and pixel driving circuits, respectively; The display substrate according to claim 8 , wherein the second output connection lines are electrically connected to second output signal lines and pixel driving circuits, respectively.

10. When N=2, the driving circuit layer further includes a third output connection line and a fourth output connection line, and at least a portion of the third output connection line and the fourth output connection line extends along a second direction; the third output connection lines are electrically connected to the first initial power supply line and the pixel driving circuit, The display substrate according to claim 9 , wherein the fourth output connection lines are electrically connected to a second initial power supply line and a pixel driving circuit, respectively.

11. The boundary of the display area includes an arc-shaped boundary, and the non-display area located outside the arc-shaped boundary is called a rounded corner area; the scan driving circuit comprises a plurality of scan shift registers and a plurality of dummy scan shift registers, the plurality of scan shift registers being cascade-connected, and the plurality of dummy scan shift registers being interposed between the plurality of scan shift registers; 11. The display substrate according to claim 6, wherein at least some of the plurality of dummy scanning shift registers are located in the rounded corner region.

12. the scanning shift register comprises a plurality of transistors and a plurality of capacitors; 12. The display substrate of claim 11, wherein an orthogonal projection at a base of an initial power supply line overlapping a scan drive circuit at least partially overlaps an orthogonal projection at a base of the plurality of capacitors.

13. 13. The display substrate of claim 12, wherein a distance between the display area and a boundary of an initial power supply line overlapping the scanning drive circuit and the display area is smaller than a distance between the display area and a boundary of at least one capacitor of the plurality of capacitors and the display area.

14. the number of transistors in the dummy scan shift register is equal to or less than the number of transistors in the scan shift register; 14. The display substrate according to claim 12, wherein the width of the dummy scan shift register is equal to or less than the width of the scan shift register.

15. 15. The display substrate according to claim 14, wherein a distance between a boundary of the second clock signal line located on the dummy scan shift register side away from the display area and a boundary of the at least one initial power supply line closest to the display area close to the display area is smaller than a distance between a boundary of the second clock signal line located on the scan shift register side away from the display area and a boundary of the at least one initial power supply line closest to the display area close to the display area.

16. the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are stacked in order; the semiconductor layer includes active layers of at least a plurality of transistors; the first conductive layer includes at least control poles of a plurality of transistors and first plates of a plurality of capacitors; the second conductive layer includes at least second plates of a plurality of capacitors, a first output signal line, and a third output signal line; the third conductive layer includes at least a second power supply line, a first pole and a second pole of at least one transistor, and a fourth output signal line; The display substrate of claim 12 , wherein the fourth conductive layer includes at least a first initial signal line, a second initial signal line, and a first power line.

17. the drive circuit layer further includes a fifth conductive layer located on a side away from the base of the fourth conductive layer; 17. The display substrate according to claim 16, wherein the fifth conductive layer includes at least a first output connection line, a second output connection line, a third output connection line, and a fourth output connection line.

18. The display substrate of claim 16 , wherein the initial power supply line has a single-layer structure and is located on a fourth conductive layer.

19. the initial feed line includes a first initial sub-segment and a second initial sub-segment connected to each other, and an orthogonal projection of the first initial sub-segment at a base and an orthogonal projection of the second initial sub-segment at a base at least partially overlap; The display substrate of claim 16, wherein the first initial sub-segment is located on a third conductive layer, and the second initial sub-segment is located on a fourth conductive layer.

20. 17. The display substrate of claim 16, wherein the first clock signal line and the second clock signal line have a single-layer structure, and the first clock signal line and the second clock signal line are located on a fourth conductive layer.

21. a clock signal line including a first clock sub-segment and a second clock sub-segment connected to each other, the clock signal line including a first clock signal line and a second clock signal line, wherein an orthogonal projection of the first clock sub-segment at a base and an orthogonal projection of the second clock sub-segment at a base at least partially overlap; 17. The display substrate of claim 16, wherein the first clock sub-segment is located on a third conductive layer, and the second clock sub-segment is located on a fourth conductive layer closer to the base.

22. The display substrate of claim 16 , wherein the second output signal line has a single-layer structure and is located on a second conductive layer.

23. the driving circuit layer further includes a sixth conductive layer located between the second conductive layer and the third conductive layer; the second output signal line includes a plurality of first output subsegments and a plurality of second output subsegments, wherein adjacent first output subsegments are electrically connected via the second output subsegments, adjacent second output subsegments are electrically connected via the first output subsegments, an orthogonal projection at a base of a second output subsegment at least partially overlaps with an orthogonal projection at a base of the electrically connected first output subsegment, and an orthogonal projection at a base of a first output subsegment at least partially overlaps with an orthogonal projection at a base of the electrically connected second output subsegment; 17. The display substrate of claim 16, wherein the first output sub-segment is located on a second conductive layer, and the second output sub-segment is located on a sixth conductive layer.

24. A display device comprising the display substrate according to any one of claims 1 to 23.

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