Voltage Droop and Overshoot Management Using Nonlinear Slope Detection

Abstract

Voltage Droop and Overshoot Management Using Nonlinear Slope Detection A computer-implemented method for detecting an n-level gradient in voltage levels at a processor, where n is greater than 1, comprising: monitoring a voltage at a processor for a voltage level corresponding to a predefined first edge, and monitoring for a voltage level corresponding to a predefined second edge within a first count limit from detecting the predefined first edge; in response to detecting the predefined second edge within the first count limit, the computer-implemented method comprises monitoring for a voltage level corresponding to a predefined third edge within a second count limit from detecting the predefined second edge; and in response to detecting the predefined third edge within the second count limit, determining whether to adjust power applied to the processor based on the monitored voltage levels.

Description

[Background technology]

[0001] The present invention relates to processor core activity, and more particularly, the present invention relates to managing voltage droop and overshoot through hardware calibrated non-linear slope detection.

[0002] Sudden changes in processor core activity result in large delta currents being drawn from the power supply, causing voltage droop due to induced noise. When multiple cores on a single processor chip change from low to high activity over a short time interval, the voltage droop observed across all cores can become significant. An excessively steep droop is dangerous to system health and needs to be controlled / mitigated. Throttling mechanisms (slowing down processor activity) are used to mitigate dangerous droop.

[0003] In conventional systems, digital droop sensors (DDSs) are placed at various points within the processor to act as voltage droop monitors. However, there is a certain amount of delay (e.g., approximately 40-50 processor clock cycles) between the time an activity change occurs and the time the sensor responds to indicate a voltage droop event. This delay is critical to maintaining system reliability. If the voltage droop is too sharp, the throttling actuator will be late in mitigating the droop. To act early and mitigate sharp droop and / or overshoot, a slope detector has been introduced to detect the rate of change in the processor core voltage.

[0004] However, voltage droop or overshoot due to sudden changes in processor activity impacts system reliability. Unfortunately, detection mechanisms implemented in conventional systems are limited by being based on specific thresholds or slope detection, where voltage droop or overshoot can slip through and disrupt the system. Furthermore, a manual calibration process to find the appropriate settings for each core processor is impractical.

[0005] Currently, limitations exist for sensors to detect voltage droop. Digital detector sensors (DDS) provide a digital "thermometer" of the current voltage level of a processing core. For example, 0 to 16 bins, with each bin in a 10mW range and calibrated at bin 8 = 0.85V. Furthermore, conventional sensors employ the following detection mechanisms: a) threshold-based mechanisms, e.g., throttling if the DDS bin falls below 4, and b) slope-based mechanisms, e.g., throttling if the DDS bin transitions from X to Y in less than Z cycles.

[0006] One drawback of current systems is that there are situations where detection slips through or is detected too late. For example, an overshoot can be followed by a droop, which in turn produces a worse droop. In another example, nonlinear droop can exist. In one such case, the droop can be nonlinear because the circuit is equivalent to an RLC network, which is nonlinear. In another such case, the DDS response behavior can be nonlinear. The DDS response is typically most accurate at its calibration bin, and as the bin moves away from the calibration bin, the mV / bin resolution differs, giving a nonlinear response.

[0007] Another drawback of conventional systems for detecting droop is their impractical calibration process. There are several parameters and gradient settings to set for each core, different processors, different voltage settings, etc. As a result, the current calibration process is conservative. In other words, the current calibration process tends to cover only the worst case scenario while penalizing other cases.

[0008] Key parameters of the dangerously steep droop signature can be provided as parameters for a gradient-based droop management approach. During workload execution, whenever the gradient detector detects a similar signature (e.g., high edge, low edge, width), a throttle signal can be triggered and the core can be throttled until the droop is under control and the throttle is slowly released.

[0009] However, arriving at the correct gradient settings / droop signature has been difficult. Manual evaluation of each chip / core is cumbersome. For example, each chip / core needs to be analyzed, its droop characterized, and then a common gradient setting, e.g., a generic gradient setting, is determined. Appropriate settings are required to effectively mitigate droop and should not be throttled too frequently to impact performance; these settings must be met across all cores / chips. Unfortunately, common settings may not be foolproof, and sometimes dangerous droop slips through, causing the system to enter a checkstop (i.e., failure).

[0010] For example, in zThemis characterization, generic gradient settings are obtained by taking critical path monitor (CPM) traces on selected chips and visually checking the gradients. Manual settings are then derived that are expected to satisfy all chip throttling requirements. However, this solution tends to over-throttle high-speed chips and under-throttle low-speed chips. Therefore, custom gradient settings per core / chip are required.

[0011] In gradient detection, there can be significant differences in the number of cycles required to get from a high CPM bin to a low CPM bin for different individual cores. For example, in the zThemis system, CPM settings could be configured in each core, but the settings were limited by the design infrastructure (VPD). Flexibility in configuring CPM settings for cores / chips is needed.

[0012] Furthermore, when throttle is induced, the throttle pattern affects power management, so a fixed pattern of throttle release technique is not efficient. A configurable throttle pattern is needed. Summary of the Invention

[0013] According to one aspect of the invention, a computer-implemented method is for detecting an n-level gradient in voltage levels at a processor, where n is greater than 1. The method includes monitoring a voltage at the processor for a voltage level corresponding to a predefined first edge and for a voltage level corresponding to a predefined second edge within a first count limit from detecting the predefined first edge. In response to detecting the predefined second edge within the first count limit, the computer-implemented method includes monitoring for a voltage level corresponding to a predefined third edge within a second count limit from detecting the predefined second edge, and in response to detecting the predefined third edge within the second count limit, determining whether to adjust power applied to the processor based on the monitored voltage levels.

[0014] As a solution to the problems described above, the present method provides detection and management of non-linear gradients in processor activity. n-level gradient detection (where n is greater than 1) allows for early detection of changes in processor activity and mitigation of sharp drops and / or overshoots that would otherwise escape detection.

[0015] According to one aspect of the present invention, a computer program product for detecting n-level gradients of voltage levels in a processor, where n is greater than 1, comprises one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media, the program instructions including program instructions for performing the method described above.

[0016] According to one aspect of the invention, a system comprises a processing circuit, the circuit having an n-level slope detector, n being greater than 1, the n-level slope detector including a voltage sensor; and logic integrated with, executable by, or integrated with and executable by the processing circuit, the logic configured to perform the aforementioned method.

[0017] In some approaches, in response to not detecting a predefined second edge within the first count limit, the method is restarted at the beginning of the method by monitoring for a predefined first edge.

[0018] In some approaches, an n-level slope detector, where n is greater than two, monitors for predefined edges, detects nonlinear greater than two level slopes, and adjusts power accordingly. For example, an overshoot and subsequent droop are detected, and power is adjusted specifically according to the nonlinearity of the slope.

[0019] According to one aspect of the present invention, a computer-implemented method for using slope traces based on a processor voltage level includes detecting a plurality of slopes using the slope traces and storing data from the plurality of slopes in a log, the data including minimum and maximum counts for transitions between a predefined high edge and a predefined low edge for each of the detected plurality of slopes. The computer-implemented method also includes selecting a configuration for a slope detector based on a set of data from the plurality of slopes, the selection including a maximum count below a predefined count threshold.

[0020] The gradient-based management approach provides detection of key parameters of dangerously steep droop signatures using gradient tracing methods as described, thereby providing a solution to the problems described above, including failures, to anticipate dangerously steep droop patterns.

[0021] According to one aspect of the present invention, a computer-implemented method for calibrating a slope detector based on a processor having a slope detector includes repeating the following operations for a plurality of power cycles: increasing power on the processor for a predefined duration, recording minimum and maximum counts between high and low edges detected while monitoring voltage levels applied to the processor while increasing the power, and applying a throttle. Data for each of the plurality of power cycles is stored, the data including voltage levels at each high and low edge, respectively, and the maximum count during the transition from each high edge to each low edge. A set of cycles is selected from the plurality of power cycles, the set of cycles having high edge-low edge combinations corresponding to predefined differences in voltage levels. The computer-implemented method includes programming the slope detector on the processor with a configuration corresponding to data from one of the selected set of cycles having the smallest maximum count during the transition between the high and low edges.

[0022] The method for automatic calibration of the gradient detector, as described above, solves the problems of common setup inefficiency and inaccuracy associated with traditional manual evaluation of each chip / core. Moreover, the calibration method as described herein allows for recalibration of the gradient detector using gradient traces.

[0023] Other aspects and techniques of the present invention will become apparent from the following detailed description, taken in conjunction with the drawings, illustrating by way of example the principles of the invention. [Brief explanation of the drawings]

[0024] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0025] [Figure 1] FIG. 1 is a diagram of a computing environment according to one inventive embodiment of the present invention.

[0026] [Figure 2] 1 is a diagram of a tiered data storage system according to one inventive embodiment of the present invention.

[0027] [Figure 3] 1 is a flowchart of a method for detecting an n-level gradient according to one embodiment of the present invention.

[0028] [Figure 4] FIG. 4A is a schematic diagram of an n-level slope detector according to one inventive embodiment of the present invention.

[0029] 4B is a series of diagrams illustrating different slopes detected by an n-level slope detector according to one inventive embodiment of the present invention: portion (a) represents a nonlinear undershoot slope, portion (b) represents a nonlinear overshoot slope, portion (c) represents an overshoot followed by an undershoot, and portion (d) represents an undershoot followed by an overshoot.

[0030] [Figure 5] 1 is a flowchart of a method for generating a gradient trace according to one inventive embodiment of the present invention.

[0031] [Figure 6] FIG. 1 is a schematic diagram of a system that includes generating a gradient trace, according to one inventive embodiment of the present invention.

[0032] [Figure 7] 1 is a flowchart of a method for calibration of a processor-based n-slope detector having n-slope detectors according to one inventive embodiment of the present invention.

[0033] [Figure 8]1 illustrates a set of throttle configurations based on processor type, according to one inventive aspect of the present invention, where part (a) is a configuration with 32 throttle levels and part (b) is a configuration with 16 throttle levels. DETAILED DESCRIPTION OF THE INVENTION

[0034] The following description is made for the purpose of illustrating the general principles of the present invention and is not intended to limit the inventive concepts claimed herein. Moreover, particular features described herein can be used in combination with other described features, in each of the various possible combinations and permutations.

[0035] Unless otherwise specifically defined herein, all terms are to be given their broadest possible interpretation, including the meanings suggested by this specification and those understood by those skilled in the art and / or defined in dictionaries, treatises, etc.

[0036] It should also be noted that, as used in this specification and the appended claims, the singular forms "a," "an," and "the" include the plural forms unless otherwise specified. It will be further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0037] The following description discloses several preferred inventive aspects of systems, methods and computer program products for managing voltage droop and voltage overshoot using non-linear slope detection.

[0038] In one general inventive aspect, a computer-implemented method for detecting an n-level gradient in voltage levels in a processor, where n is greater than 1, includes monitoring a voltage in the processor for a voltage level corresponding to a predefined first edge and for a voltage level corresponding to a predefined second edge within a first count limit from detecting the predefined first edge, in response to detecting the predefined second edge within the first count limit, the computer-implemented method includes monitoring for a voltage level corresponding to a predefined third edge within a second count limit from detecting the predefined second edge, and in response to detecting the predefined third edge within the second count limit, determining whether to adjust power applied to the processor based on the monitored voltage levels.

[0039] In another general inventive aspect, a computer program product for detecting n-level gradients of voltage levels in a processor, where n is greater than 1, comprises one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media, the program instructions including program instructions for performing the method described above.

[0040] In another general inventive aspect, a system comprises a processing circuit, the circuit having an n-level slope detector, n being greater than 1, where the n-level slope detector includes a voltage sensor; and logic integrated with, executable by, or integrated with and executable by the processing circuit, the logic configured to perform the aforementioned method.

[0041] In yet another general inventive aspect, a computer-implemented method for using slope traces based on a processor voltage level includes detecting a plurality of slopes using the slope traces and storing data from the plurality of slopes in a log, the data including minimum and maximum counts for transitions between a predefined high edge and a predefined low edge for each of the detected plurality of slopes. The computer-implemented method also includes selecting a configuration for a slope detector based on a set of data from the plurality of slopes, the selection including a maximum count below a predefined count threshold.

[0042] In another general inventive aspect, a computer-implemented method for calibrating a processor having a slope detector includes repeating the following operations for a plurality of power cycles: increasing power on the processor for a predefined duration, recording minimum and maximum counts between high and low edges detected while monitoring voltage levels applied to the processor while increasing the power, and activating a throttle. Data for each of the plurality of power cycles is stored, the data including voltage levels at each high and low edge, respectively, and the maximum count during the transition from each high edge to each low edge. A set of cycles is selected from the plurality of power cycles, the set of cycles having high edge-low edge combinations corresponding to predefined differences in voltage levels. The computer-implemented method includes programming the slope detector on the processor with a configuration corresponding to data from one of the selected set of cycles having the smallest maximum count during the transition between the high and low edges.

[0043] A list of acronyms used in the description is provided below. ASIC Application Specific Integrated Circuit CD-ROM Compact Disc Read-Only Memory CPP Computer Program Product CPM Critical Path Monitor CPU Central Processing Unit DDS Digital Droop Sensor DVD Digital Versatile Disc EPROM Erasable Programmable Read Only Memory EUD End User Device FPGA Field Programmable Gate Array GPU Graphics Processing Unit HDD Hard Disk Drive IC Integrated Circuit I / O Input / Output IoT Internet of Things LAN Local Area Network NFC Near Field Communication NVM Non-Volatile Memory PME Power Management Engine RAM Random Access Memory ROM Read-Only Memory SAN Storage Area Network SD Secure Digital SDN Software Defined Networking SRAM Static Random Access Memory SSD Solid State Drive UI User Interface USB Universal Serial Bus VCE Virtual Computing Environment WAN Wide Area Network

[0044] Various aspects of the present disclosure are described by text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in inventive aspects of a computer program product (CPP). With respect to any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in successive flowchart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in an at least partially overlapping manner.

[0045] Computer program product inventive aspects (“CPP inventive aspects” or “CPP”) is a term used in this disclosure to describe any set of one or more storage media (also referred to as “media”) collectively contained in a set of one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A “storage device” is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices (such as punch cards or pits / lands formed on the major surface of a disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, is not to be construed as storage in the form of a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals communicated through wires, and / or other transmission media. As will be appreciated by those skilled in the art, data is typically moved at some infrequent time during the normal operation of the storage device, such as during access, defragmentation, or garbage collection, but the above does not qualify a storage device as transitory because the data is not transitory while it is stored.

[0046] Computing environment 100 includes an example environment for the execution of at least a portion of computer code involved in performing the methods of the present invention, such as the n-level slope detector of block 150, where n is greater than 1. In addition to block 150, computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this aspect of the present invention, computer 101 includes a processor set 110 (including processing circuitry 120 and cache 121), a communications fabric 111, volatile memory 112, persistent storage 113 (including an operating system 122 and block 150 as identified above), a peripheral device set 114 (including a user interface (UI) device set 123, storage 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. Remote server 104 includes a remote database 130. The public cloud 105 includes a gateway 140, a cloud orchestration module 141, a set of host physical machines 142, a set of virtual machines 143, and a set of containers 144.

[0047] Computer 101 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 130. As is well understood in the art of computer technology, and depending on the technology, execution of a computer-implemented method may be distributed among multiple computers and / or among multiple locations. While in this presentation of computing environment 100, to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 101. Although computer 101 is not depicted in the cloud of FIG. 1 , it may be located in a cloud. However, computer 101 is not required to reside within a cloud except to any extent that may be expressly indicated.

[0048] Processor set 110 includes one or more computer processors of any type now known or later developed. Processing circuitry 120 may be distributed across multiple packages, e.g., multiple coordinated integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on processor set 110. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all caches for a processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to operate with qubits and perform quantum computing.

[0049] Computer-readable program instructions are typically loaded onto computer 101 to cause processor set 110 of computer 101 to execute a series of operational steps, thereby realizing a computer-implemented method, whereby the instructions so executed instantiate the method specified in the flowcharts and / or descriptions of the computer-implemented method contained herein (collectively referred to as the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by processor set 110 to control and direct the execution of the methods of the present invention. In computing environment 100, at least some of the instructions for executing the methods of the present invention may be stored in block 150 within persistent storage 113.

[0050] Communications fabric 111 is the signal-conducting pathway that allows various components of computer 101 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as those that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways may be used, such as fiber optic and / or wireless communication pathways.

[0051] Volatile memory 112 may be any type of volatile memory now known or later developed. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory 112 is characterized by random access, although this is not required unless expressly indicated. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 101.

[0052] Persistent storage 113 is any form of non-volatile storage for a computer, now known or later developed. The non-volatility of this storage means that stored data remains whether or not power is supplied to computer 101 and / or to persistent storage 113 directly. Persistent storage 113 may be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, data to be deleted, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems employing a kernel. The code contained in block 150 typically includes at least a portion of the computer code involved in performing the methods of the present invention.

[0053] The peripheral device set 114 includes a set of peripheral devices of the computer 101. Data communication connections between the peripheral devices and other components of the computer 101 may be implemented in various ways, such as Bluetooth connections, near field communication (NFC) connections, connections made by cable (such as a universal serial bus (USB)-type cable), insertion-type connections (e.g., a Secure Digital (SD) card), connections made over a local area communication network, and even connections made over a wide area network such as the Internet. In various inventive aspects, the UI device set 123 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. The storage 124 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. The storage 124 may be persistent and / or volatile. In some inventive aspects, the storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In aspects of the invention that require the computer 101 to have a large amount of storage (e.g., the computer 101 stores and manages a large database locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector.

[0054] Network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers over WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some inventive aspects, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other inventive aspects (e.g., inventive aspects utilizing software-defined networking (SDN)), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for implementing the methods of the present invention can be downloaded to computer 101 from an external computer or external storage device, typically through a network adapter card or network interface included in network module 115.

[0055] WAN 102 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances by any technology for communicating computer data, now known or later developed. In some inventive aspects, WAN 102 may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0056] End-user device (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and may take any of the forms discussed above in connection with computer 101. EUD 103 typically receives useful and useful data from the operation of computer 101. For example, in the hypothetical case where computer 101 is designed to provide recommendations to the end user, the recommendations would typically be communicated from network module 115 of computer 101 over WAN 102 to EUD 103. In this manner, EUD 103 can display or otherwise present the recommendations to the end user. In some inventive aspects, EUD 103 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0057] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on historical data, then this historical data may be provided to computer 101 from remote database 130 of remote server 104.

[0058] Public cloud 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer functionality, particularly data storage (cloud storage) and computing power, without direct active management by users. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct active management of public cloud 105's computing resources is performed by computer hardware and / or software in cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments running on various computers that comprise host physical machine set 142, the universe of physical computers in and / or available to public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and / or containers from container set 144. It is understood that these VCEs may be stored as images and can be transferred among and between various physical machine hosts, either as images or after instantiation of the VCEs. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCE, and manages active instantiations of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that enables public cloud 105 to communicate over WAN 102.

[0059] Some further description of a virtualized computing environment (VCE) is now provided. A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from the image. Two well-known types of VCE are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows for the existence of multiple isolated user space instances called containers. These isolated user space instances typically behave as actual computers from the perspective of programs running in them. A computer program running on a normal operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and of the devices assigned to the container; this feature is known as containerization.

[0060] A private cloud 106 is similar to a public cloud 105, except that the computing resources are available only for use by a single enterprise. While the private cloud 106 is shown as communicating with a WAN 102, in other inventive aspects, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often each implemented by a different vendor. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this inventive aspect, both the public cloud 105 and the private cloud 106 are part of a larger hybrid cloud.

[0061] In some aspects, systems according to various inventive aspects may include a processor and logic integrated with and / or executable by the processor, the logic configured to perform one or more of the process steps enumerated herein. The processor may be any configuration as described herein, such as a discrete processor or processing circuitry including numerous components, such as processing hardware, memory, I / O interfaces, etc. By "integrated with," it is intended that the processor has logic embedded as hardware logic, such as an application-specific integrated circuit (ASIC), FPGA, etc. By "executable by a processor," it is intended that the logic may be hardware logic; software logic, such as firmware, a portion of an operating system, a portion of an application program, etc.; or any combination of hardware and software logic that is accessible by the processor and configured to cause the processor to perform some function when executed by the processor. The software logic may be stored on any memory type, local and / or remote, as known in the art. Any processor known in the art may be used, such as a software processor module and / or a hardware processor, e.g., an ASIC, an FPGA, a central processing unit (CPU), an integrated circuit (IC), a graphics processing unit (GPU), etc.

[0062] Referring now to Figure 2, a storage system 201 according to one inventive aspect is shown. Note that some of the elements shown in Figure 2 may be implemented as hardware and / or software in accordance with various inventive aspects. Storage system 201 may include a storage system manager 212 for communicating with multiple media and / or drives on at least one upper storage tier 202 and at least one lower storage tier 206. Upper storage tier 202 may preferably include one or more random-access and / or direct-access media 204, such as hard disks in a hard disk drive (HDD), non-volatile memory (NVM), solid-state memory in a solid-state drive (SSD), flash memory, SSD arrays, flash memory arrays, etc., and / or others described herein or known in the art. Lower storage tier 206 may preferably include one or more lower performance storage media 208, including sequential access media such as magnetic tape in a tape drive and / or optical media, slower access HDDs, slower access SSDs, etc., and / or others described herein or known in the art. One or more additional storage tiers 216 may include any combination of storage memory media as desired by the designer of system 201. Also, any of upper storage tier 202 and / or lower storage tier 206 may include some combination of storage devices and / or storage media.

[0063] Storage system manager 212 may communicate with drives and / or storage media 204, 208 on upper storage hierarchy 202 and lower storage hierarchy 206 through network 210, such as a storage area network (SAN) as shown in FIG. 2, or any other suitable network type. Storage system manager 212 may communicate with one or more host systems (not shown) through host interface 214, which may or may not be part of storage system manager 212. Storage system manager 212 and / or other components of storage system 201 may be implemented in hardware and / or software and may utilize a processor (not shown), such as a central processing unit (CPU), field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc., to execute commands of a type known in the art. Of course, any configuration of storage system may be used, as will be apparent to those skilled in the art upon reading this specification.

[0064] In a further inventive aspect, storage system 201 may include any number of data storage tiers, and each storage tier may include the same or different storage memory media. For example, each data storage tier may include the same type of storage memory media, such as HDDs, SSDs, sequential access media (such as tape in a tape drive or optical disk in an optical disk drive), direct access media (such as CD-ROMs or DVD-ROMs), or any combination of media storage types. In one such configuration, upper storage tier 202 may include a majority of SSD storage media to store data in a higher-performance storage environment, while the remaining storage tiers, including lower storage tier 206 and additional storage tier 216, may include any combination of SSDs, HDDs, tape drives, etc. to store data in a lower-performance storage environment. In this manner, more frequently accessed data, data having a higher priority, data that needs to be accessed more quickly, etc. may be stored in upper storage tier 202, while data that does not have one of these attributes may be stored in additional storage tier 216, which also includes lower storage tier 206. Of course, upon reading this specification, one skilled in the art will be able to devise many other combinations of storage media types for implementing different storage schemes in accordance with the aspects of the present invention presented herein.

[0065] According to some inventive aspects, a storage system (e.g., 201) may include logic configured to receive a request to open a dataset, logic configured to determine whether the requested dataset is stored in a lower storage tier 206 of the tiered data storage system 201 in multiple associated portions, logic configured to move each associated portion of the requested dataset to an upper storage tier 202 of the tiered data storage system 201, and logic configured to assemble the requested dataset on the upper storage tier 202 of the tiered data storage system 201 from the associated portions.

[0066] Of course, this logic may be implemented as a method or computer program product for any device and / or system according to various inventive aspects.

[0067] According to one inventive aspect, a solution for detecting sudden changes in processor activity is a system that operates as a nonlinear slope detector. In one approach, nonlinear droop or overshoot of a processor core may be detected using an n-level slope detector, where n is greater than 1, and a configurable process for adjusting power to the processor.

[0068] Referring now to Figure 3, there is shown a flowchart of a method 300 according to one inventive aspect. Method 300 may be performed in accordance with the present invention in various inventive aspects, particularly in any of the environments shown in Figures 1-8. Of course, more or fewer operations may be included in method 300 than those specifically illustrated in Figure 3, as will be understood by those skilled in the art upon reading this specification.

[0069] Each of the steps of method 300 for detecting n-level gradients of voltage levels in a processor, where n is greater than 1, may be performed by any suitable component of an operating environment. For example, in various inventive aspects, method 300 may be performed partially or entirely by a computer or some other device having one or more processors therein. A processor, e.g., a processing circuit, chip, and / or module, implemented in hardware and / or software and preferably having at least one hardware component, may be utilized in any device to perform one or more steps of method 300. Exemplary processors include, but are not limited to, a central processing unit (CPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or the like, combinations thereof, or any other suitable computing device known in the art.

[0070] As shown in FIG. 3 , method 300 may begin at operation 302, which includes monitoring a voltage at a processor for a voltage level corresponding to a predefined first edge. The monitoring may be performed by an n-level slope detector, where n is an integer greater than 1. The slope detector includes a voltage sensor for monitoring the voltage level. In one approach, the slope detector may have an on-board voltage sensor. In another approach, the monitoring includes receiving readings from voltage sensors located at appropriate locations on the processor chip, such as along power lines, in each core, etc. The readings may be relative voltage values ​​depending on the sensor type configuration. For example, one type of sensor may provide a range of voltage levels from 0 to 24, another type of sensor may provide a range of voltage levels from 0 to 16, etc. In one exemplary approach, the voltage sensor may function as a digital droop sensor (DDS).

[0071] Operation 304 includes monitoring for a voltage level corresponding to a predefined second edge within a first count limit from detecting a predefined first edge. In one approach, the first count may be limited to a predefined number of cycles, clock cycles, or the like. For example, a two-level slope detector is configured with a predefined first edge and a predefined second edge and a first count limit of the maximum number of cycles in a transition between the predefined first edge and the predefined second edge. Each predefined edge and each count limit is configured for an n-level slope detector according to the processor. In one approach, each predefined edge and each count limit may be configured according to the processing behavior of the processor.

[0072] The monitoring of the voltage level may correspond to detecting n levels of nonlinearity. For example, each nonlinear section (e.g., slope) corresponds to a first and second predefined edge and a count limit for the transition between the first and second edges. For example, the n-level slope detector may detect changes in the voltage level including a two-level slope (n=2) that detects two levels of nonlinearity in the voltage change, and therefore the n-level slope detector monitors for three predefined edges: a first edge, a second edge, and a third edge. In another example, the n-level slope detector may detect changes in the voltage level including a three-level slope (n=3) that detects three levels of nonlinearity, and therefore the n-level slope detector monitors for four predefined edges: a first edge, a second edge, a third edge, and a fourth edge. In various approaches, the predefined first edge, predefined second edge, predefined n+1 edge, etc. are configured relative voltage values ​​(e.g., high or low edges) that indicate thresholds of relative values ​​of voltage levels during a change in power with n levels of nonlinearity. The monitored voltage level may be above, below, within, etc. the predefined edges.

[0073] In one example, without intending to be limiting in any way, the voltage level of the chip fluctuates back and forth from 0.9 volts to 1.0 volts, the first edge may be configured to be 0.98, the second edge may be configured to be 0.95, and the first count limit may be configured as 10 (e.g., 10 cycles between the first and second edges). If the voltage changes from 0.98 to 0.95 within 10 cycles, the voltage detector detects voltage droop. A sensor inputting the voltage level provides a digital representation of the voltage, e.g., a bin level. The sensor emits a value equivalent to the voltage level.

[0074] In response to detecting the predefined second edge within the first count limit, operation 306 includes monitoring for a voltage level corresponding to a predefined third edge within the second count limit from the detection of the predefined second edge. Detecting the predefined second edge within the first count limit results in detecting a first slope. Furthermore, detecting the first slope triggers monitoring for a next predefined edge, e.g., a predefined third edge, which, if detected within the second count limit, will determine the second slope. As defined for the first count limit, the second count limit, n-level count limit, etc., may be a predefined number of cycles, e.g., clock cycles, where counting is initiated in response to detecting a voltage level corresponding to each first edge. The first count limit may be different from the second count limit. For example, the first count limit may be 10 cycles, and the second count limit may be 5 cycles.

[0075] In one approach, in response to detecting a predefined second edge, e.g., a first slope, within the first count limit, the method may include adjusting power to the system. For example, a small amount of proactive throttling to the system may be initiated when operation 306 is monitoring for a voltage level corresponding to a predefined third edge within the second count limit.

[0076] One example of method 300 is shown in the schematic diagram of a system 400 for managing processor power in FIG. 4A. FIG. 4A illustrates system 400 according to one inventive aspect. As an option, system 400 may be implemented in conjunction with features from any other inventive aspect enumerated herein, such as those described with reference to other figures. Of course, however, such system 400 and others presented herein may be used in various applications and / or permutations that may or may not be specifically described in the exemplary inventive aspects enumerated herein. Furthermore, system 400 presented herein may be used in any desired environment.

[0077] As shown in FIG. 4A by way of example only, a two-level nonlinear slope detector 402 monitors the relative voltage level of a processor. The system 400 begins by detecting 404 a first slope (e.g., a single level). Using a sensor, a relative voltage level A is monitored corresponding to a first edge. The sensor may be a DDS located on the processor. The first edge is a predefined value (e.g., a configured relative voltage threshold) that indicates a change in voltage across the processor. In one approach, the first edge may be configured as a high edge. In another approach, the first edge may be configured as a low edge.

[0078] The slope detector 402 continues monitoring for a voltage level B corresponding to a predefined second edge within a first count limit (solid arrow). In one approach, the value of the first count limit is configured according to a maximum count (e.g., clock cycles) that may represent voltage droop, overshoot, undershoot, etc. In response to the count of cycles (dashed line) from the monitored voltage level A at the transition to the monitored voltage level B being within the first count limit, a first slope is detected. The detection of the first slope triggers a second slope detection 406, which includes monitoring for a relative voltage level C corresponding to a predefined third edge. The second slope detection 406 corresponds to the count (dashed line) from the monitored voltage level B at the second edge to the monitored voltage level C at the predefined third edge, where the count is within a second count limit (solid arrow). In response to the detection of the second slope, a nonlinear slope is detected.

[0079] 3 , operation 308 includes, in response to detecting a predefined third edge within the second count limit, determining whether to adjust power applied to the processor based on the monitored voltage level to mitigate the effects of voltage changes on the processor. In one approach, the power controller may determine whether to adjust power applied to the processor. In one approach, operation 308 may determine how to adjust power applied to the processor based on the monitored voltage level corresponding to the detected edge to mitigate the effects of voltage changes on the processor.

[0080] In one approach, power may be adjusted by throttling processing activity to reduce power applied to one or more cores of a processor. Power may be adjusted by throttling processing activity to reduce power consumed by one or more cores of a processor. Adjusting power through throttling may be based on the shape of the linearity of the slope detected by the n-level slope detector. For example, a detected nonlinear slope having the shape of a voltage droop may have power adjusted by throttling processing activity to reduce power consumed by one or more processing cores.

[0081] In another example, voltage mitigation may include throttling the code, e.g., suspending instructions executing the code for a short period until the voltage droop is recovered. If voltage throttling is performed too frequently, too many times, etc., the performance of the core will be impaired because instructions are being suspended too frequently. It is desirable for the core to recover from voltage droop without excessive impact on core performance. In a preferred approach, aspects of the invention described herein provide voltage droop management and voltage mitigation for optimal core performance.

[0082] In another approach, power may be regulated by increasing the power applied to the processor. For example, an increase in voltage may be applied to the processor, the frequency may increase, etc. With current technology, with the use of lower nodes and maximum voltage limits for newer processors, an increasingly prevalent problem is stalling, which results in overshoot. Overshoot is similar to voltage droop, but has the opposite effect on the processing core. During periods of very high activity, suddenly there is no activity, e.g., there is no demand for current, so the voltage increases.

[0083] As shown in the exemplary system 400 of FIG. 4A, a two-level gradient detector 402 may be connected to a throttling mechanism 408 for adjusting the power applied to the processor based on the monitored voltage levels in order to mitigate the effects of voltage changes on the processor.

[0084] In one aspect of the invention, a non-linear gradient detector, e.g., an n-level gradient detector where n is greater than 1, enables the detection of any one of a series of results caused by a change in voltage level. In one approach of operation 308 of method 300, after detecting a predefined third edge within a second count limit, the shape of the non-linear gradient is detected, and the non-linear gradient includes the voltage levels detected at a predefined first edge, a predefined second edge, and a predefined third edge, where the power is adjusted based on the detected shape of the non-linear gradient.

[0085] Referring to a two-level gradient detector as shown in FIG. 4A, a series of characteristics can be described according to the monitored voltage values of A, B, and C as follows. The plot shown in FIG. 4B represents the shape of the selected characteristics listed below. 1. There is no rule of A > B > C. Thereby, each monitored voltage level A, B, C is within an operating relative voltage level range, e.g., a DDS bin range; 2. As shown in part (a), when A > B > C, a non-linear undershoot gradient is detected; 3. As shown in part (b), when C > B > A, a non-linear overshoot gradient is detected; 4. As shown in part (c), when A C, an overshoot and a subsequent undershoot are detected; 5. As shown in part (d), when A > B < C, an undershoot and a subsequent overshoot are detected; 6. When A = B or B = C, a normal linear gradient is detected: 7. Slope detection occurs when A→B→C occurs within the count limit; 8. Gradient tracing can be enabled once a gradient is detected; 9. Monitoring is maintained at B and if it times out, the mechanism is reset and the process restarts again at A.

[0086] 3 , in response to not detecting the predefined second edge within the first count limit, the method resumes at operation 302 monitoring for a voltage level corresponding to the predefined first edge. Moreover, in response to not detecting the predefined third edge within the second count limit as described at operation 306, the method resumes at operation 302 monitoring for a voltage level corresponding to the predefined first edge. If, at any time during slope detection or processor execution, a slope is not detected, e.g., a second edge is not detected within the predefined count limit after detecting the first edge, the method resumes by monitoring for the first edge.

[0087] Advantages of the non-linear generalized slope detector include the detection of slopes that represent combinations of changes in voltage levels during processing activity. These combinations include: a) Detection and mitigation of undershoot voltage gradients A>B>C; b) Detection and Mitigation of Overshoot Voltage Gradient Detection A <B<C、 c) Detection and Mitigation of Overshoot and Subsequent Undershoot A C. d) Detection and mitigation of undershoot and subsequent overshoot A>B <C、 e) Linear slope detection when A=B or B=C. This can be either an overshoot or an undershoot.

[0088] According to one inventive aspect, a processor includes gradient tracing logic within the hardware of an apparatus for profiling voltage droop or overshoot. In one approach, a system for detecting nonlinear gradients provides gradient detection for the gradient tracing logic. The gradient tracing logic enables behavior of applications, workloads, etc., running on the processor.

[0089] According to one inventive aspect, the system includes a programmable power management engine (PME), which is a controller associated with the processor. The PME may create a parameter matrix including a combination of values ​​for a predefined first edge (e.g., a high edge bin value), a predefined second edge (e.g., a low edge bin value), and a counter limit (e.g., a minimum count of cycles). The PME may determine, determine, etc., the combination of parameters to be used for slope detection for a particular core. The PME controls slope detection, reads slope traces, calibrates the slope detector, reprograms the slope detector, etc. The PME is programmed to read slope data and store the data in its memory.

[0090] Referring now to Figure 5, there is shown a flowchart of a method 500 for selecting a gradient detector configuration using a gradient trace, according to one inventive aspect. Method 500 may be performed in accordance with the present invention in various inventive aspects, particularly in any of the environments shown in Figures 1-8. Of course, more or fewer operations may be included in method 500 than those specifically illustrated in Figure 5, as will be understood by those skilled in the art upon reading this specification.

[0091] Each of the steps of method 500 for using gradient traces may be performed by any suitable component of an operating environment. For example, in various inventive aspects, method 500 may be performed partially or entirely by a computer or some other device having one or more processors therein. A processor, e.g., a processing circuit, chip, and / or module, implemented in hardware and / or software and preferably having at least one hardware component, may be utilized in any device to perform one or more steps of method 500. Exemplary processors include, but are not limited to, a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like, combinations thereof, or any other suitable computing device known in the art.

[0092] As shown in FIG. 5, method 500 may begin with operation 502, which includes detecting multiple gradients using a gradient trace. Detecting each of the multiple gradients includes logic similar to method 300 (in FIG. 3) for detecting nonlinear gradients during processing activity. In one approach, logic between the gradient tracing process and the gradient detector process may be shared. Detecting each of the multiple gradients includes monitoring for a voltage level corresponding to a predefined high edge, monitoring for a voltage level corresponding to a predefined low edge within a first count limit, and for multiple gradients, and capturing minimum and maximum counts during transitions between the predefined high edge and the predefined low edge. Over a given period of time, minimum and maximum counts between the predefined high edge and the predefined low edge are captured during multiple transitions between the predefined high edge and the predefined low edge.

[0093] Operation 504 includes storing data from the multiple slopes in a log, the data including minimum and maximum counts for transitions between predefined high edges and predefined low edges for each of the detected multiple slopes. For the multiple slopes during a given period, the multiple transitions generate minimum and maximum counts between the predefined high edges and predefined low edges. For example, as counted between relative voltage levels, e.g., from points A / B / C in the detection, the slope tracing logic also captures each minimum count between the high and low edges (e.g., for a 10-cycle count limit, the minimum count may be 5), and the logic captures the maximum count between the high and low edges (e.g., for a 10-cycle count limit, the maximum count may be 12). In addition, the slope tracing logic stores a log (e.g., configured bins) of the minimum and maximum counts detected during the transitions between each edge.

[0094] Additionally, the gradient tracing logic may capture a minimum relative voltage (e.g., DDS min bin). The gradient tracing logic evaluates data for multiple gradients and determines whether the average minimum relative voltage level (e.g., detected DDS bin) of the multiple gradients is associated with a predefined low edge. If the average minimum relative voltage level is different from the low edge, the gradient tracing logic records the average minimum relative voltage level as the next predefined low edge. The predefined low edge may be redefined according to a preprogrammed high-low edge based on the DDS min bin.

[0095] Operation 506 includes selecting a configuration for the slope detector based on a set of data from the plurality of slopes. In a preferred approach, the selection includes a maximum count below a predefined count threshold. In various approaches, the operations of method 500 may be performed by a power management engine associated with the processor.

[0096] 6 shows a schematic diagram of a system 600 including a method 602 for configuring a slope detector 604 using a slope trace according to one embodiment of the present invention. The slope trace counts the number of cycles in a transition between a predefined high edge and a predefined low edge. As shown for the method 602 for using the slope trace, the logic 606 for detecting multiple slopes for the logic may be similar to the logic for detecting slopes (see 404 in FIG. 4A). The logic 606 for detecting multiple slopes may include capturing a count (solid arrow) between the high and low edges of relative voltage levels for each detected slope.

[0097] The gradient tracing method 602 may include instructions for a counter 608 to determine the number of cycles, or cycle count, during a transition from a first edge (e.g., a high edge) to a second edge (e.g., a low edge). The counter 608 may be reset when a voltage level (e.g., a bin) rises above the high edge. The counter 608 may be configured to have a value that reaches a max value. For example, the counter has N bits. If the processor cycles taken from the high edge to the low edge exceed the counter limit, the counter rolls over and saturates to its max value rather than providing false data.

[0098] For example, the set of data may be the worst detections for the last N measurement periods. A profile of the worse detections for the N measurement periods may be stored in the PME. The set of "worst" detections may be based on the prominent type of slope detected. In one approach, the "worst" detections may be the detection of multiple overshoot slopes. In another approach, the "worst" detections may be the detection of multiple voltage droop slopes. The n-level slope detector may be configured according to the type of slope being detected; for example, the sensor may be configured to monitor for predefined edges within a count limit to detect a particular type of slope.

[0099] For example, referring to the slope tracing method 602 of Figure 6, for multiple slopes, the minimum and maximum slope counts 610 and 612 for each of the multiple slopes detected are entered into a log. In one example of creating a slope trace of voltage droop, the slope configuration having the worst case droop number 614 may be selected from the log of maximum counts 612. The worst case droop number 614 may be reset to a zero value on the scom lead.

[0100] In one approach, the worst case droop number 614 may be used by the PME to reprogram the processor's n slope detector 604 (dashed line). The configuration of the worst case droop number 614 may be used to program the count limit of the n slope detector 604, thereby indicating a parameter of the n slope detector for adjusting, e.g., throttling, power. In one approach, the link between determining the worst case droop number 614 of the slope tracing method 602 may be disabled from the n slope detector 604.

[0101] For example, in one approach, during startup and execution of dI / dt (e.g., droop) stress marks and reference workloads, a slope detector (such as a DDS associated with the slope detector logic) may be configured from a very strict to a very relaxed configuration using different throttling patterns. Data is collected for the N worst detections seen at each configuration point. A complete profile may be used to set the appropriate settings according to the sensor measurements. Calibration of counter limit settings allows for refinement for a set of core processors, as the counter limit does not need to be a universal setting for all processors.

[0102] In one approach, the method includes updating the log with the additional slope detected by the slope tracing method. A modified (or next) configuration may be selected based on the updated slope log. In some approaches, when the processor is remote, e.g., for use at a customer location, the PME may remotely manage the slope detector of the processor. Thus, updating the log in a remote processor setting may include the PME receiving from the remote processor the additional slope detected by the slope tracing method. A modified (or next) configuration of the slope detector may be selected based on the updated slope log received from the remote processor.

[0103] In one approach, the slope tracing logic may include machine learning that applies learned values ​​of voltage levels of the processing application, workload, etc. to a method for creating a slope trace. For example, once a slope trace is programmed, the slope tracing logic continues to trace the slope detected by the n slope detectors, such as the maximum number of cycles and minimum number of cycles from one edge to a second edge. The slope tracing logic and the slope detectors operate independently. Each may be configured for the same predefined high / low edges (e.g., used for calibration, slope adjustment by the PME), or each may be configured differently. For example, the slope detectors will detect and operate, and the slope trace will collect data as described herein.

[0104] In the customer environment, the customer executes the workload, and the PME receives the gradient traces continuously generated during the execution of the workload. Thus, in addition to data shared from the remote processor via machine learning, such as temperature, humidity, voltage, etc., additional parameters derived from the gradient trace logic may be included in the machine learning mechanism associated with the processor. In one approach, the processor continuously reads the gradient trace logic of the gradients generated through machine learning from the processor and adjusts the voltage applied to the processor according to the recent gradient trace logic parameters (e.g., increasing the applied voltage in response to processor degradation as indicated by the gradient trace).

[0105] In one example, at a customer setting, a detector may be configured to be appropriate for the field and may collect data on the N worst detections seen during a measurement period. The data may be used to improve "call home data" (e.g., for the next product configuration) or to adjust settings specifically for customer behavior. For example, referring to FIG. 6, the minimum count 610 determined from the gradient trace method 602 may be useful data for logging in the field.

[0106] In one example, in zTelum, dynamic DDS slope counter limit settings may be included with all cores and DDSs. The PME may perform 24x7 data logging of droop information for all DDSs and record the collected data in the call home data.

[0107] According to one inventive aspect, a solution to the conventional manual calibration process associated with conventional gradient detection methods includes an automatic, self-calibrating, configurable power response for effective droop and power management. Using a non-intrusive gradient tracing mechanism that employs feedback as described herein in conjunction with a gradient detector, changes in gradient may be dynamically managed for each core, chip, etc. The non-intrusive, feedback-based gradient tracing mechanism enables automatic calibration of the configuration for gradient setting on the fly without manual intervention.

[0108] According to one inventive aspect, the methodology and mechanism includes self-calibration of the slope detector based on a slope profile of the voltage of the processing core. In one example, the methodology may include POR for zMetis. Referring now to Figure 7, there is shown a flowchart of a method 700 for calibration of n slope detectors based on a processor having n slope detectors, according to one inventive aspect. Method 700 may be performed in accordance with the present invention in various inventive aspects, particularly in any of the environments shown in Figures 1-8. Of course, more or fewer operations than those specifically illustrated in Figure 7 may be included in method 700, as will be understood by those skilled in the art upon reading this specification.

[0109] Each of the steps of method 700 may be performed by any suitable component of an operating environment. For example, in various inventive aspects, method 700 may be performed partially or wholly by a computer or some other device having one or more processors therein. A processor, e.g., a processing circuit, chip, and / or module, implemented in hardware and / or software and preferably having at least one hardware component, may be utilized in any device to perform one or more steps of method 700. Exemplary processors include, but are not limited to, a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like, combinations thereof, or any other suitable computing device known in the art.

[0110] The method 700 begins with operations for worst-case calibration, which may be performed during the startup process. In one example, the operations of the method 700 describe a power management engine (PME) searching for the best slope setting while performing stress marks.

[0111] 7, method 700 may begin with operation 702, which includes repeating the following operations for multiple power cycles: increasing power on the processor for a predefined duration, recording minimum and maximum counts between high and low edges, and activating the throttle. In one example, a power cycle may include switching the dI / dt ON for 1 millisecond (ms) and cooling for 1 second, where this cycle is repeated in approximately 1 minute. During the OFF time, the throttle is gradually damped to capture a droop at the second ON dI / dt, which is unaffected by the throttle response for the first droop. The throttle response will dampen during the cooling period.

[0112] The power cycling process of operation 702 may be repeated for various high-low edges, capturing the minimum / maximum count between the high and low edges at each power cycle. The minimum relative voltage level may be recorded for each cycle. The power cycling parameters are configured to ensure no failures occur during the search.

[0113] Operation 704 includes storing data for each of the multiple power cycles. The data from each of the multiple power cycles includes the voltage levels at each high edge and low edge, and the maximum count during the transition from each high edge to each low edge. In one approach, the high edge may be selected to be less than the voltage level captured when not increasing power. In one approach, the low edge may be selected to be greater than the sensor filter edge of the sensor capturing the respective voltage level. This may be a process of adjusting the filter edge.

[0114] In one example, the data may be stored in a table according to counts of high edges, low edges, and the maximum number of cycles in a programmed high-to-low edge transition.

[0115] Operation 706 includes selecting a set of cycles from the plurality of power cycles, the set of cycles having high edge-low edge combinations that correspond to a predefined difference in voltage levels, which may be configurable.

[0116] Operation 708 includes programming an n-level slope detector on the processor with a configuration corresponding to data from one of the selected set of cycles having a minimum maximum count for a transition between a high edge and a low edge. This configuration is automatically programmed for an n-level slope detector used in a comparable processor. This configuration includes a predefined relative voltage level value for a high edge, a predefined relative voltage level value for a low edge, and a predefined count limit value between the high edge and the low edge corresponding to the minimum maximum count, and these values ​​are based on data from one of the selected set of cycles.

[0117] In one aspect of the calibration method 700, the calibration may include validation of the programmed configuration. In one approach, while executing a reference workload on the processor, the method includes monitoring the throttle response using an n-slope detector with the programmed configuration during calibration of the processor's power management. The monitoring may be performed within a maximum performance penalty threshold to minimize the frequency of throttling of the processor.

[0118] In another aspect of calibration method 700, the processor may be remote from the PME. In one approach, monitoring the calibrated n slope detectors may include receiving recorded data corresponding to processor activity from the processor and recalibrating the configuration of the n slope detectors. In a preferred approach, recalibrating the configuration of the n slope detectors includes restarting a method of calibrating the n slope detectors based on the processor.

[0119] In one example, during customer configuration, the PME may monitor all "call home" recorded data to model customer-specific behavior. If no throttling is observed, no changes to the calibration of the n-slope detector configuration are required. If throttling is occurring during processor activity, the PME may analyze the detector trace data to check whether throttling can be avoided. If a fault is occurring on the processor, the PME may analyze the detector trace data and recalibrate the n-slope detector accordingly.

[0120] FIG. 8 illustrates configurable throttle patterns that may represent a response to detecting an n-level gradient. As shown in section (b), 16 different levels of throttling are represented by separate patterns. Section (a) illustrates a pattern with 32 different levels of throttling as provided by zTelum. The methods described herein enable more efficient use of throttling patterns provided by zTelum and next-generation processors. Configurable throttle patterns allow for more aggressive or less aggressive throttling. In a preferred approach, managing the power applied to the processor allows for improved throttle patterns that mitigate changes in processor performance.

[0121] It will become apparent that the various features of the systems and / or methodologies described above may be combined in any manner and multiple combinations may be made from the description provided above.

[0122] It will be further appreciated that inventive aspects of the present invention may be provided in the form of a service deployed on behalf of a customer to provide the service on demand.

[0123] The description of various inventive aspects of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed inventive aspects. Numerous modifications and variations will be apparent to those skilled in the art without departing from the scope of the inventive aspects described. The terminology used herein has been selected to best explain the principles, practical applications, or technical improvements over the art found in the marketplace of inventive aspects, or to enable others skilled in the art to understand the inventive aspects disclosed herein.

Claims

1. 1. A computer-implemented method for detecting n-level gradients for voltage levels in a processor, where n is greater than 1, the method comprising: monitoring a voltage at the processor for a voltage level corresponding to a predefined first edge; monitoring for a voltage level corresponding to a predefined second edge within a first count limit from detecting the predefined first edge; in response to detecting the predefined second edge within the first count limit, monitoring for a voltage level corresponding to a predefined third edge within a second count limit from detecting the predefined second edge; and determining whether to adjust power applied to the processor based on the monitored voltage level in response to detecting the predefined third edge within the second count limit; A computer-implemented method comprising:

2. The computer-implemented method of claim 1 , comprising restarting the method in response to not detecting a predefined second edge within the first count limit.

3. The computer-implemented method of claim 1 , wherein the first count limit and the second count limit each are a predefined number of cycles.

4. 2. The computer-implemented method of claim 1, wherein the monitoring is by an n-level slope detector, n being an integer greater than 1, the n-level slope detector comprising a voltage sensor for monitoring voltage levels.

5. The computer-implemented method of claim 4 , wherein n is an integer greater than 2.

6. The computer-implemented method of claim 4 , wherein the voltage sensor functions as a digital droop sensor (DDS).

7. 2. The computer-implemented method of claim 1, further comprising detecting a shape of a nonlinear gradient comprising the voltage levels detected at the predefined first edge, the predefined second edge, and the predefined third edge after detecting the predefined third edge within the second count limit, wherein the power is adjusted based on the detected shape of the nonlinear gradient.

8. The computer-implemented method of claim 1 , wherein each predefined edge and each count limit is configured according to a processing behavior of the processor.

9. The computer-implemented method of claim 1 , wherein the method is performed for each core in the processor.

10. 1. A computer program product for detecting n-level gradients of voltage levels in a processor, n being greater than 1, the computer program product comprising a computer-readable storage medium having program instructions embodied thereon, the program instructions causing a computer to: monitoring, with a slope detector, a voltage at the processor for a voltage level corresponding to the predefined first edge; monitoring, by the slope detector, for a voltage level corresponding to a predefined second edge within a first count limit from detecting the predefined first edge; monitoring, by the slope detector, in response to detecting the predefined second edge within the first count limit, for a voltage level corresponding to a predefined third edge within a second count limit from the predefined second detection; and and determining whether to adjust power applied to the processor based on the monitored voltage level in response to detecting the predefined third edge within the second count limit. a computer program product readable and / or executable by said computer to cause said computer to perform

11. 11. The computer program product of claim 10, wherein the program instructions are readable and / or executable by the computer to cause the computer to perform a procedure that restarts the program instructions in response to not detecting a second edge within the first count limit.

12. 1. A system comprising: a processing circuit, wherein the circuit has an n-level slope detector, n being greater than 1, wherein the n-level slope detector includes a voltage sensor; and Logic integrated with, executable by, or integrated with and executable by said processing circuitry, said logic comprising: monitoring, with the slope detector, a voltage level of the processing circuit for a voltage level corresponding to a predefined first edge; monitoring, by the slope detector, for a voltage level corresponding to a predefined second edge within a first count limit from detecting the first edge; monitoring, by the slope detector, in response to detecting the predefined second edge within the first count limit, for a voltage level corresponding to a predefined third edge within a second count limit from detecting the first edge; and determining whether to adjust power applied to the processing circuit based on the monitored voltage level in response to detecting the predefined third edge within the second count limit; configured to: A system comprising:

13. 13. The system of claim 12, wherein the logic is configured to, in response to not detecting a second edge within the first count limit, resume the logic configured to monitor, by the slope detector, for a voltage level corresponding to a predefined first edge.

14. The system of claim 12 , wherein each predefined edge and each count limit is configured according to a processing behavior of the processing circuit.

15. 1. A computer-implemented method for using a gradient trace based on a voltage level of a processor, the method comprising: detecting a plurality of gradients using the gradient trace; storing data from the plurality of gradients in a log, the data including minimum and maximum counts for transitions between a predefined high edge and a predefined low edge for each of the detected plurality of gradients; and selecting a configuration for a slope detector based on a set of data from the plurality of slopes, wherein the selection includes a maximum count below a predefined count threshold; A computer-implemented method comprising:

16. The computer-implemented method of claim 15 , wherein the gradient trace counts the number of cycles in the transition from the predefined high edge to the predefined low edge.

17. updating the log with additional gradients detected by the gradient trace; and selecting a next configuration for the slope detector The computer-implemented method of claim 15 further comprising:

18. The processor is remote from a power management engine that executes the method for using the gradient trace based on the processor, and the updating step comprises: receiving from the processor the additional gradient detected by the gradient trace; and selecting a next slope configuration for the slope detector based on the updated log of slopes received from the processor.

20. The computer-implemented method of claim 17, comprising:

19. 1. A computer-implemented method for calibrating a slope detector based on a processor having the slope detector, the method comprising: For multiple power cycles, the following actions: increasing power on the processor for a predefined duration; recording minimum and maximum counts between high and low edges detected while monitoring the voltage level applied to the processor during said power increase; and Activating the throttle repeating the steps of: storing data for each of the plurality of power cycles, the data including voltage levels at each high edge and low edge, and the maximum count during a transition from each high edge to each low edge; selecting a set of cycles from the plurality of power cycles, the set of cycles having high edge-low edge combinations corresponding to predefined differences in voltage levels; and programming the slope detector on the processor with a configuration corresponding to data from one of the selected set of cycles having a minimum of the maximum counts at the transition between the high edge and the low edge. A computer-implemented method comprising:

20. 20. The computer-implemented method of claim 19, wherein the high edge is selected to be below the voltage level captured when not increasing the power, and the low edge is selected to be above a sensor filter edge of a sensor capturing the respective voltage level.

21. 20. The computer-implemented method of claim 19, wherein the configuration includes a relative voltage level value for a predefined high edge, a relative voltage level value for a predefined low edge, and a count limit value between the predefined high edge and the low edge that corresponds to the minimum value of the maximum count, the values ​​being based on the data for the one of the selected set of cycles.

22. 20. The computer-implemented method of claim 19, further comprising monitoring throttle response using an n-slope detector having the programmed configuration while executing a reference workload on the processor.

23. 20. The computer-implemented method of claim 19, wherein the processor is remote from a power management engine that performs the calibration of the n slope detectors, the method further comprising monitoring the n slope detectors with the programmed configuration.

24. The monitoring step includes: receiving, from the processor, recorded data corresponding to the gradient trace of the processor; and recalibrating the n slope detector configuration; 24. The computer-implemented method of claim 23, comprising:

25. 25. The computer-implemented method of claim 24, wherein recalibrating the configuration of the n slope detectors comprises restarting the method.

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