Information processing apparatus, image forming apparatus, information processing method, program, and network system

Abstract

To achieve an operation corresponding to a factor of a return signal while suppressing power consumption to the minimum even when time is required for noise detection processing.SOLUTION: A first processor that processes an entire operation, a second processor, a third processor, a first memory that records occurrence of a return factor from a power-saving mode to a normal mode and true or false of the return factor, and a second memory that stores a type of the return factor and a processor that detects the true or false of the return factor in association with a recording position of the first memory in which the true or false is recorded; The first processor includes a noise detection unit configured to, when a first return factor occurs, refer to the second memory to determine whether the first return factor is true or false, and record a result of the determination in the first memory, and a return determination unit configured to refer to the first memory to acquire a result of the determination of the first return factor, and determine whether it is necessary to return from the power saving mode in accordance with the result of the determination.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to an information processing apparatus, an image forming apparatus, an information processing method, a program, and a network system. [Background technology]

[0002] Image forming devices, such as MFPs (Multifunction Peripherals), which are multifunction peripherals equipped with multiple functions, are required to reduce power consumption in standby mode. Image forming devices equipped with a power-saving CPU that controls the power states of a main CPU (Central Processing Unit) and a sub-CPU are known. The power-saving CPU stops the operation of the main CPU and the sub-CPU when the image forming device is in an energy-saving mode (hereinafter sometimes referred to as "power-saving mode"), and starts the main CPU and the sub-CPU when it receives a return signal from the power-saving mode. The power-saving CPU prevents unnecessary activation of the main CPU by detecting whether the return signal was generated erroneously due to noise, thereby reducing the power consumption of the image processing device (see, for example, Patent Document 1). Summary of the Invention [Problem to be solved by the invention]

[0003] However, the technology disclosed in Patent Document 1 has a problem in that it does not fully consider how to balance power saving with processing of a return signal for the image forming device when it takes time to detect noise.

[0004] One embodiment of the present invention has been made in consideration of the above problems, and one of its objectives is to realize operation in response to a recovery signal while minimizing power consumption even when noise detection processing takes time. [Means for solving the problem]

[0005] In order to solve the above problem, an information processing device according to one embodiment of the present invention is an information processing device whose internal state switches between a normal mode and a power saving mode, the information processing device comprising: a first processor that processes the overall operation of the information processing device; a second processor that processes auxiliary operations of the information processing device; a third processor that controls the power states of the first processor and the second processor; a first memory that records the occurrence of a cause for returning from the power saving mode to the normal mode and whether the cause for returning has occurred; and a third memory that stores, in association with each other, the type of the cause for returning, the type of processor that detects the truth or falsehood of the cause for returning, and a recording position in the first memory where the truth or falsehood of the cause for returning is recorded. and a second memory, wherein the first processor has a noise detection unit that, when a first return cause occurs, determines whether the first return cause is true or false by referring to the second memory and records the determination result of the true or false of the first return cause in the first memory, and a return determination unit that refers to the first memory to obtain the determination result of the first return cause and determines whether or not to return from the power saving mode in accordance with the determination result of the first return cause, wherein if the determination result of the first return cause is not obtained from the first memory, the return determination unit waits for a predetermined time and then repeatedly refers to the first memory to obtain the determination result of the first return cause. [Effects of the Invention]

[0006] Even if the noise detection process takes time, the process of returning from power saving can be realized while minimizing power consumption. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of a hardware configuration of an image forming apparatus. [Figure 2] FIG. 2 is a diagram illustrating an example of a hardware configuration of an information processing device. [Figure 3] FIG. 3 is a diagram illustrating an example of a hardware configuration of a terminal device. [Figure 4] FIG. 4 is an example of a hardware configuration diagram of an SoC. [Figure 5]FIG. 5 is an example of a functional configuration diagram of an image forming apparatus equipped with an SoC. [Figure 6] FIG. 6 is a diagram showing an example of the return determination table of FIG. [Figure 7A] FIG. 7A is a sequence diagram of a process of returning from the power saving mode to the normal mode by the image forming apparatus equipped with the SoC of FIG. [Figure 7B] FIG. 7B is a sequence diagram following the process of FIG. 7A. [Figure 7C] FIG. 7C is a sequence diagram following the process of FIG. 7B. [Figure 8] FIG. 8 is a flowchart showing the operation of the main CPU. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, an example will be described in which an information processing technology that minimizes power consumption even when noise detection processing requires time and performs processing according to the cause of a return signal is applied to an image forming apparatus or a terminal device. However, the present invention is not limited to this example. The information processing technology of the embodiments can also be applied to other systems and devices that require a power-saving mode. For example, the information processing technology of the embodiments can also be applied to output devices such as PJs (Projectors), IWBs (Interactive Whiteboards: electronic whiteboards with intercommunication capabilities), digital signage, HUDs (Head-Up Display) devices, industrial machinery, imaging devices, sound collection devices, medical equipment, network appliances, automobiles (Connected Cars), notebook PCs (Personal Computers), mobile phones, smartphones, tablet devices, game consoles, PDAs (Personal Digital Assistants), digital cameras, wearable PCs, desktop PCs, servers, scanners, printers, facsimiles, etc.

[0009] 1 is an example of a hardware configuration diagram of an image forming apparatus 10 according to this embodiment. As shown in FIG. 1, the image forming apparatus 10 includes a controller 110, a short-range communication circuit 120, an engine control unit 130, an operation panel 140, and a network I / F (Interface) 150.

[0010] Of these, the controller 110 has a CPU 101, which is the main part of the computer, a system memory (MEM-P) 102, a north bridge (NB) 103, a south bridge (SB) 104, an ASIC (Application Specific Integrated Circuit) 106, a local memory (MEM-C) 107, which is a storage unit, an HDD (Hard Disk Drive) controller 108, and an HD (Hard Disk) 109, which is also a storage unit, and is configured such that the NB 103 and the ASIC 106 are connected by an AGP (Accelerated Graphics Port) bus 121.

[0011] Of these, the CPU 101 is a control unit that performs overall control of the image forming apparatus 10. The NB 103 is a bridge that connects the CPU 101 with the MEM-P 102, the SB 104, and the AGP bus 121, and includes a memory controller that controls reading and writing to the MEM-P 102, a PCI (Peripheral Component Interconnect) master, and an AGP target.

[0012] The MEM-P 102 comprises a ROM (Read Only Memory) 102a, which is memory for storing programs and data that realize the functions of the controller 110, and a RAM (Random Access Memory) 102b, which is used for expanding the programs and data, and as a drawing memory during memory printing. The programs stored in the RAM 102b may be provided by being recorded in an installable or executable file format on a computer-readable recording medium such as a CD (Compact Disc)-ROM, a CD-R (Recordable), or a DVD (Digital Versatile Disc).

[0013] The SB 104 is a bridge for connecting the NB 103 with PCI devices and peripheral devices. The ASIC 106 is an integrated circuit (IC) for image processing applications that has hardware elements for image processing and serves as a bridge connecting the AGP bus 121, PCI bus 122, HDD controller 108, and MEM-C 107. The ASIC 106 includes a PCI target and AGP master, an arbiter (ARB) that forms the core of the ASIC 106, a memory controller that controls the MEM-C 107, multiple direct memory access controllers (DMACs) that perform image data rotation using hardware logic, and a PCI unit that transfers data between the scanner unit 131, printer unit 132, and facsimile unit 133 via the PCI bus 122. A USB (Universal Serial Bus) interface or an IEEE 1394 (Institute of Electrical and Electronics Engineers 1394) interface may be connected to the ASIC 106.

[0014] The MEM-C 107 is a local memory used as an image buffer for copying and a code buffer. The HD 109 is a storage for storing image data, font data used during printing, and forms. The HD 109 controls the reading and writing of data from and to the HD 109 under the control of the CPU 101. The AGP bus 121 is a bus interface for a graphics accelerator card proposed to speed up graphics processing, and by directly accessing the MEM-P 102 at high throughput, the graphics accelerator card can be made faster.

[0015] Further, a short-range communication circuit antenna 120a is provided in the short-range communication circuit 120. The short-range communication circuit 120 is a communication circuit such as NFC (Near Field Communication) or Bluetooth (registered trademark).

[0016] Furthermore, the engine control unit 130 has a scanner unit 131, a printer unit 132, and a facsimile unit 133. The operation panel 140 has a panel display unit 140a such as a touch panel that displays current setting values ​​and selection screens and receives inputs from the operator, and hard keys 140b including a numeric keypad that receives setting values ​​for image formation conditions such as density setting conditions and a start key that receives a copy start command. The controller 110 controls the entire image forming apparatus 10, and controls, for example, drawing, communication, and inputs from the operation panel 140. The scanner unit 131 or the printer unit 132 includes an image processing unit such as error diffusion and gamma conversion.

[0017] The image forming device 10 can sequentially switch among the document box function, copy function, printer function, and facsimile function using the application switching key on the operation panel 140. When the document box function is selected, the image forming device 10 enters the document box mode, when the copy function is selected, the image forming device 10 enters the copy mode, when the printer function is selected, the image forming device 10 enters the printer mode, and when the facsimile mode is selected, the image forming device 10 enters the facsimile mode.

[0018] The network I / F 150 is an interface for performing data communication using a communication network. The short-range communication circuit 120 and the network I / F 150 are electrically connected to the ASIC 106 via a PCI bus 122.

[0019] 2 is an example of a hardware configuration diagram of an information processing device 20 according to this embodiment. The information processing device 20 may be incorporated inside the image forming device 10, or may be connected to the image forming device 10 via a network. The information processing device 20 is constructed by a computer, and includes a CPU 201, a ROM 202, a RAM 203, a HD 204, an HDD controller 205, a display 206, an external device connection I / F 207, a network I / F 208, a bus line 209, a keyboard 210, a pointing device 211, an optical drive 213, and a media I / F 215.

[0020] Of these, the CPU 201 controls the overall operation of the information processing device 20. The ROM 202 stores programs used to drive the CPU 201, such as an IPL (Initial Program Loader). The RAM 203 is used as a work area for the CPU 201. The HD 204 stores various data such as programs. The HDD controller 205 controls the reading and writing of various data from and to the HD 204 under the control of the CPU 201. The display 206 displays various information such as a cursor, menus, windows, characters, or images. The external device connection I / F 207 is an interface for connecting various external devices. In this case, external devices include, for example, a USB (Universal Serial Bus) memory or a printer. The network I / F 208 is an interface for data communication using a communication network. The bus line 209 is an address bus, a data bus, or the like for electrically connecting the components such as the CPU 201 shown in FIG. 2.

[0021] The keyboard 210 is a type of input means having multiple keys for inputting characters, numbers, various instructions, etc. The pointing device 211 is a type of input means for selecting and executing various instructions, selecting a processing target, moving a cursor, etc. The optical drive 213 controls reading and writing of various data from an optical medium 212, which is an example of a removable recording medium. The optical medium 212 may be a CD, DVD, Blu-Ray (registered trademark), etc. The media I / F 215 controls reading and writing (storing) of data from a recording medium 214, such as a flash memory.

[0022] 3 is a diagram illustrating an example of a hardware configuration of a terminal device 30 according to this embodiment. The terminal device 30 may be connected to the image forming device 10 via a network and transmit a packet including an image formation command to the image forming device 10, or the information processing device 20 of FIG. 2 may be applied to the terminal device 30. The terminal device 30 is constructed by a computer and includes a CPU 301, a ROM 302, a RAM 303, an EEP (Electrically Erasable Programmable) ROM 304, a CMOS (Complementary Metal Oxide Semiconductor) sensor 305, an image sensor I / F 306, an acceleration / direction sensor 307, a media I / F 309, and a GPS (Global Positioning System) receiving unit 311. The terminal device 30 according to this embodiment may be, for example, a smartphone.

[0023] Of these, the CPU 301 controls the overall operation of the terminal device 30. The ROM 302 stores programs used to drive the CPU 301, such as the CPU 301 and the IPL. The RAM 303 is used as a work area for the CPU 301. The EEPROM 304 reads and writes various data, such as terminal device programs, under the control of the CPU 301. The CMOS sensor 305 is a type of built-in imaging means that captures an image of a subject (mainly a self-portrait) and obtains image data under the control of the CPU 301. Note that instead of the CMOS sensor 305, an imaging means such as a CCD (Charge Coupled Device) sensor may also be used. The imaging element I / F 306 is a circuit that controls the operation of the CMOS sensor 305. The acceleration / azimuth sensor 307 is a type of sensor, such as an electronic magnetic compass or gyrocompass that detects geomagnetism, or an acceleration sensor. The media I / F 309 controls the reading and writing (storage) of data from and to a recording medium 308, such as a flash memory. The GPS receiver 311 receives GPS signals from GPS satellites.

[0024] The terminal device 30 also includes a long-distance communication circuit 312, a CMOS sensor 313, an image sensor I / F 314, a microphone 315, a speaker 316, an audio input / output I / F 317, a display 318, an external device connection I / F 319, a short-distance communication circuit 320, an antenna 320a, and a touch panel 321.

[0025] Of these, the long-distance communication circuit 312 is a circuit that communicates with other devices via a communication network. The CMOS sensor 313 is a type of built-in imaging means that captures an image of a subject and obtains image data under the control of the CPU 301. The imaging element I / F 314 is a circuit that controls the operation of the CMOS sensor 313. The microphone 315 is a built-in circuit that converts sound into an electrical signal. The speaker 316 is a built-in circuit that converts the electrical signal into physical vibrations to generate sounds such as music and voice. The audio input / output I / F 317 is a circuit that processes the input and output of audio signals between the microphone 315 and the speaker 316 under the control of the CPU 301. The display 318 is a type of display means such as an LCD or organic EL (Electro Luminescence) that displays images of subjects, various icons, etc. The external device connection I / F 319 is an interface for connecting various external devices. The short-distance communication circuit 320 is a communication circuit such as NFC or Bluetooth (registered trademark). The touch panel 321 is a type of input means that allows the user to operate the terminal device 30 by pressing the display 318.

[0026] The terminal device 30 also includes a bus line 310. The bus line 310 is an address bus, a data bus, or the like for electrically connecting the components such as the CPU 301 shown in FIG.

[0027] Fig. 4 is an example of a hardware configuration diagram of an SoC (System on Chip) according to this embodiment. The CPU 101 shown in Fig. 1, the CPU 201 shown in Fig. 2, or the CPU 301 shown in Fig. 3 may be an SoC in which a main CPU 1A, a sub-CPU 1B, and a power-saving CPU 1C are integrated, as shown in Fig. 4. The main CPU 1A is an example of a first processor, the sub-CPU 1B is an example of a second processor, and the power-saving CPU 1C is an example of a third processor.

[0028] The main CPU 1A controls the entire system of the image forming apparatus 10, the information processing apparatus 20, or the terminal device 30. The sub CPU 1B assists the main CPU 1A and controls the sub modules. The assistance of the main CPU 1A performed by the sub CPU 1B may be, for example, an operation to transition the image forming apparatus 10, the information processing apparatus 20, and the terminal device 30 to a power saving mode. The sub module controlled by the sub CPU 1B may be, for example, the facsimile unit 133 in the engine control unit 130 of the image forming apparatus 10. The power saving CPU 1C controls the power states of the main CPU 1A and the sub CPU 1B.

[0029] The main CPU 1A requests the sub CPU 1B and the power-saving CPU 1C to transition to power-saving mode. The main CPU 1A and the sub CPU 1B are powered on and operate in normal mode, and are powered off and stop operating in power-saving mode. The power-saving CPU 1C is powered on and operates regardless of normal mode or power-saving mode. Due to the configuration of the SoC, the power-saving CPU 1C cannot power on only the sub CPU 1B, and always controls the power on and off of the main CPU 1A and the sub CPU 1B. Through this control, the power-saving CPU 1C switches between normal mode and power-saving mode. Hereinafter, transitioning from power-saving mode to normal mode may be called returning.

[0030] Fig. 5 is an example of a functional configuration diagram of an image forming apparatus 10 equipped with the SoC of Fig. 4. The main CPU 1A has a system control unit 1101, a power saving management unit 1102, a recovery cause detection unit 1103, a recovery determination unit 1104, a noise detection unit 1105, a sub-CPU notification unit 1106, and a power saving CPU notification unit 1107. The sub-CPU 1B has a noise detection unit 1201, a sub-module control unit 1202, and a sub-module 1203. The power saving CPU 1C has a sub-CPU control unit 1301, a main CPU control unit 1302, a recovery cause detection unit 1303, and a network packet automatic response unit 1304.

[0031] The system control unit 1101 outputs a power saving transition request for transitioning from normal mode to power saving mode to the power saving management unit 1102. Furthermore, the system control unit 1101 transitions from power saving mode to normal mode based on a system startup request output from the power saving management unit 1102.

[0032] When the power saving management unit 1102 receives a power saving transition request to transition from normal mode to power saving mode, it instructs the sub CPU 1B and the power saving CPU 1C to transition to power saving via the sub CPU notification unit 1106 and the power saving CPU notification unit 1107, respectively. In addition, the power saving management unit 1102 causes the return determination unit 1104 to determine the cause of transition from the power saving mode to the normal mode or return. Hereinafter, the cause of transition from the power saving mode to the normal mode or return may be simply referred to as the return cause.

[0033] When a return cause detection unit 1103 of the main CPU 1A receives a return cause from the source of the return cause, it detects the return cause. A return determination unit 1104 determines the return cause based on an instruction from the power saving management unit 1102. The return determination unit 1104 accesses a return determination table 2001 in the ROM 102a and a shared recording area 2002 in the RAM 102b of the image forming apparatus 10 to acquire the return cause.

[0034] The noise detection unit 1105 of the main CPU 1A and the noise detection unit 1201 of the sub CPU 1B perform a noise check on the return factor. Here, the noise check is a process of determining whether the return factor from the power saving mode to the normal mode has occurred erroneously due to noise. Hereinafter, a return factor that has occurred erroneously due to noise is also referred to as a false return factor.

[0035] The sub CPU notification unit 1106 notifies the sub CPU 1B of an instruction from the power saving management unit 1102 that has received the power saving transition request. The power saving CPU notification unit 1107 notifies the power saving CPU 1C of an instruction from the power saving management unit 1102 that has received the power saving transition request.

[0036] The submodule control unit 1202 outputs a stop instruction to a submodule (such as a facsimile) based on a power saving transition request, causing the submodule to stop. The submodule control unit 1202 outputs a start instruction to a submodule (such as a facsimile) based on a system start request, causing the submodule to start. For example, the facsimile unit 133 of the image forming apparatus 10, which corresponds to a submodule, may be mounted as a submodule 1203 in the subCPU 1B. In other words, the functional unit that is the source of the return cause may be provided in the subCPU 1B.

[0037] The sub CPU control unit 1301 outputs a return request to the sub CPU 1 B. The main CPU control unit 1302 outputs a return request to the main CPU 1 A.

[0038] When the return cause detection unit 1303 of the power-saving CPU 1C receives a return cause from the source of the return cause, the return cause detection unit 1303 of the power-saving CPU 1C detects the return cause and stores information indicating the detected return cause in a return cause storage area of ​​the shared storage area 2002 in the RAM 102b.

[0039] The network packet automatic response unit 1304 automatically responds to packets from the network. When the network packet automatic response unit 1304 receives a packet from the network, if the packet is from a network that has been registered in advance in the image forming apparatus 10, the network packet automatic response unit 1304 does not start the main CPU 1A and the sub-CPU 1B.

[0040] In FIG. 5, RAM 102b of image forming apparatus 10 has a shared recording area 2002 and a normal recording area 2003. The shared recording area 2002 is allocated with an area for storing a noise detection flag and an area for storing a cause of returning from power saving mode. Hereinafter, the area for storing the cause of returning is also referred to as a return cause saving area. The normal recording area 2003 is allocated with an area for storing a noise detection flag. ROM 102a is allocated with an area for storing a return determination table 2001. RAM 102b is an example of a first memory. ROM 102a is an example of a second memory.

[0041] For example, the shared recording area 2002 and the normal recording area 2003 are provided in different chips. The shared recording area 2002 is accessible by the main CPU 1A, the sub-CPU 1B, and the power-saving CPU 1C. The normal recording area 2003 is accessible only by the main CPU 1A. For example, the memory capacity of the shared recording area 2002 is smaller than the memory capacity of the normal recording area 2003.

[0042] Fig. 6 is a diagram showing an example of the return determination table 2001 of Fig. 5. The return determination table 2001 has an area for holding, for each cause of return from the power saving mode, information indicating the CPU that performs the noise check and information indicating the storage address of a noise detection flag that indicates the result of the noise check.

[0043] The power-saving CPU 1C determines factors for returning from the power-saving mode, such as platen detection, which detects that the automatic document feeder of the image forming apparatus 10 has been opened. The power-saving CPU 1C determines factors for returning from the power-saving mode, such as detection of a user's operation on the operation panel 140 and door detection, which detects that the maintenance door of the image forming apparatus 10 has been opened.

[0044] The sub-CPU 1B may determine a cause for returning from the power saving mode such as an incoming facsimile call. The main CPU 1A may determine a cause for returning from the power saving mode such as receiving a packet from a network connected to the image forming apparatus 10. These causes for returning are examples of requests made by the image forming apparatus 10 to the image forming system.

[0045] The power-saving CPU 1C is a CPU that is designed to operate in power-saving mode, so it can use only the minimum resources for noise checks. Therefore, noise checks for simple I / O (Input / Output) such as plate detection and door detection can be performed by the power-saving CPU 1C. On the other hand, noise checks for incoming facsimile calls and packet reception from the network use more resources than simple I / O. Therefore, the sub-CPU 1B or main CPU 1A performs noise checks rather than the power-saving CPU 1C.

[0046] For example, when the sub-CPU 1B detects that the return cause due to an incoming facsimile call is false, it stores a noise detection flag at a predetermined address in the shared recording area 2002 in the RAM 102b of the image forming apparatus 10. For example, when the main CPU 1A detects that the return cause due to receiving a packet from the network is false, it stores a noise detection flag at a predetermined address in the normal recording area 2003 in the RAM 102b of the image forming apparatus 10.

[0047] The noise detection flag may be expressed as a binary value whose value changes depending on whether the main CPU 1A or the sub CPU 1B has detected noise (a false return cause). For example, the noise detection flag may be 1 if the main CPU 1A or the sub CPU 1B has detected noise (a false return cause), and 0 if it has not. The noise detection flag may be expressed by a method other than a binary value whose value changes depending on whether the main CPU 1A or the sub CPU 1B has detected noise (a false return cause).

[0048] The return determination table 2001 is provided in common to the main CPU 1A, the sub CPU 1B, and the power-saving CPU 1C. This allows for centralized management of the correspondence between return factors and the CPUs that perform noise checks, as well as the storage addresses of noise detection flags. Furthermore, for example, when optional hardware that generates a return factor is added to the image forming apparatus 10, it is possible to easily manage information used to control return from the power-saving mode.

[0049] The power-saving CPU 1C has a function of detecting whether the return cause determined by the power-saving CPU 1C is normal or false. If the power-saving CPU 1C detects the occurrence of a false return cause, the power-saving CPU 1C maintains the power-off state without turning on the power to the sub-CPU 1B and the main CPU 1A.

[0050] When the power-saving CPU 1C detects that the return cause determined by the power-saving CPU 1C is false, processing is performed only by the power-saving CPU 1C. Therefore, even if the power-saving CPU 1C detects that the return cause determined by the power-saving CPU 1C is false, the power-saving CPU 1C does not store a noise detection flag in the RAM 102b of the image forming apparatus 10. Therefore, an area for storing the noise detection flag corresponding to the power-saving CPU 1C is not provided in the return determination table 2001.

[0051] The reversion discrimination table 2001 in the specification may be generated by the learning effect of machine learning. Furthermore, by classifying reversion factors and CPUs that perform noise checks using machine learning, it is not necessary to use a correspondence table. Here, machine learning refers to a technology that allows a computer to acquire human-like learning capabilities, and refers to a technology in which a computer autonomously generates algorithms necessary for judgments such as data classification from previously acquired learning data and applies these algorithms to new data to make predictions. The learning method for machine learning may be any of supervised learning, unsupervised learning, semi-supervised learning, reinforcement learning, and deep learning, or may be a combination of these learning methods. The learning method for machine learning is not limited.

[0052] 7A, 7B, and 7C are sequence diagrams of a process for returning from a power saving mode to a normal mode by an image forming apparatus equipped with the SoC shown in Fig. 5. The sequence diagrams shown in Fig. 7A, 7B, and 7C also include a process when a false return factor is detected.

[0053] At the beginning of Fig. 7A, the image forming apparatus 10 is operating in normal mode. For example, because the image forming apparatus 10 has not been operated within a preset timer period, the system control unit 1101 outputs a power-save transition request to the power-save management unit 1102 to transition from normal mode to power-save mode (Fig. 7A(1a)). Upon receiving the power-save transition request, the power-save management unit 1102 instructs the sub-CPU 1B to transition to power-save mode via the sub-CPU notification unit 1106 (Fig. 7A(1b)), and instructs the power-save CPU 1C to transition to power-save mode via the power-save CPU notification unit 1107 (Fig. 7A(1c)).

[0054] Based on the instruction to transition to power saving, the sub-module control unit 1202 of the sub-CPU 1B outputs a stop instruction to the sub-module 1203, causing the sub-module 1203 to stop operating (FIG. 7A(1d)). Having output the stop instruction to the sub-module 1203, the sub-CPU 1B outputs a response to the instruction to transition to power saving to the power saving management unit 1102, and turns off the power (FIG. 7A(1e)).

[0055] Based on the instruction to transition to power saving, the power saving CPU 1C outputs a response to the instruction to transition to power saving to the power saving management unit 1102 (FIG. 7A(1f)). Upon receiving the response to the instruction to transition to power saving, the power saving management unit 1102 turns off the power supply to the main CPU 1A (FIG. 7A(1g)). Then, the operation mode of the image forming apparatus 10 transitions from the normal mode to the power saving mode.

[0056] When a return cause including noise occurs that causes the power-saving mode to return to the normal mode, the power-saving CPU 1C detects the occurrence of the return cause. For example, when the return cause detection unit 1303 of the power-saving CPU 1C receives a return request from the source of the return cause, it detects the return cause (FIG. 7A(2a)). Then, the return cause detection unit 1303 of the power-saving CPU 1C stores information indicating the source of the return cause as the return cause in the return cause storage area of ​​the shared recording area 2002 (FIG. 7A(2b)).

[0057] When a return factor occurs, the power-saving CPU 1C starts detecting packets from the network using the automatic network packet response unit 1304 (FIG. 7A(3a)). When the automatic network packet response unit 1304 receives a packet from the network, if the packet is from a network that has been registered in advance in the image forming apparatus 10 (FIG. 7A(3b)), it automatically responds to the packet from the network (FIG. 7A(3c)). When responding, the main CPU 1A and the sub-CPU 1B do not start up.

[0058] The sub-CPU control unit 1301 of the power-saving CPU 1C outputs a return request to the sub-CPU 1B (FIG. 7A(4a)). Upon receiving the return request, the sub-CPU 1B is powered on and started up. The sub-module control unit 1202 of the started sub-CPU 1B outputs a start-up instruction to the sub-module 1203, causing the sub-module 1203 to start up (FIG. 7A(4b)). Furthermore, the main CPU control unit 1302 of the power-saving CPU 1C outputs a return request to the main CPU 1A (FIG. 7A(2c)). Upon receiving the return request, the main CPU 1A is powered on and started up (FIG. 7A(2d)).

[0059] At this point, the system control unit 1101 of the main CPU 1A does not perform system startup processing. In other words, many of the modules and engines connected to the image forming apparatus 10 do not start. Therefore, the fact that the system control unit 1101 of the main CPU 1A is in a stopped state can be said to lead to a reduction in power consumption.

[0060] The sub CPU 1B accesses the return determination table 2001 in the ROM 120a and acquires information indicating the cause of return from the power saving mode to the normal mode determined by the sub CPU 1B and the storage address of the noise detection flag (FIG. 7A(4c)). Next, the sub CPU 1B accesses the shared recording area 2002 in the RAM 120b and acquires the return cause stored in the return cause storage area by the power saving CPU 1C (FIG. 7A(4d)).

[0061] The sub CPU 1B refers to the information in the acquired recovery determination table 2001 and determines whether or not to perform a noise check for the recovery cause that occurred. For example, if the recovery cause is an incoming facsimile call, the sub CPU 1B determines to perform a noise check and causes the noise detection unit 1201 of the sub CPU 1B to perform the noise check (FIG. 7A (4e)).

[0062] When the noise detection unit 1201 of the sub CPU 1B performs noise detection processing due to a return cause, it refers to the storage address of the noise detection flag shown in the return determination table 2001. Then, it sets a noise detection flag indicating the result of the noise detection processing at that storage address (FIG. 7A (4f)). Note that since the noise detection flag is set to a random initial value, when the noise detection flag is at the initial value, it can be said that the noise detection processing by the noise detection unit 1201 of the sub CPU 1B is incomplete.

[0063] In Fig. 7B, the power saving management unit 1102 of the started main CPU 1A causes the return discrimination unit 1104 to discriminate the cause of return (Fig. 7B(e)). The return discrimination unit 1104 accesses the return discrimination table 2001 in the ROM 120a and acquires information indicating the cause of return from the power saving mode to the normal mode discriminated by the main CPU 1A and the storage address of the noise detection flag (Fig. 7B(2f)). Next, the return discrimination unit 1104 accesses the shared recording area 2002 in the RAM 120b and acquires the return cause stored in the return cause storage area by the power saving CPU 1C (Fig. 7B(2g)).

[0064] The return determination unit 1104 refers to the information in the obtained return determination table 2001 and determines whether or not to perform a noise check on the main CPU 1A for the return cause that occurred. For example, if the return cause is packet reception from the network, the return determination unit 1104 determines to perform a noise check and causes the noise detection unit 1105 of the main CPU 1A to perform the noise check (FIG. 7B(2h)).

[0065] When the noise detection unit 1105 of the main CPU 1A performs noise detection processing due to a return cause, it refers to the storage address of the noise detection flag shown in the return determination table 2001. Then, it sets a noise detection flag indicating the result of the noise detection processing at that storage address (FIG. 7B(2i)). Note that since the noise detection flag is set to a random initial value, when the noise detection flag is at the initial value, it can be said that the noise detection processing by the noise detection unit 1105 of the main CPU 1A is incomplete.

[0066] When the network packet automatic response unit 1304 receives a packet from the network, if the packet is from a network that has not been registered in advance in the image forming device 10 (FIG. 7B(3d)), it stores information indicating the source of the recovery cause (i.e., reception of a packet from the network) as the recovery cause in the recovery cause storage area of ​​the shared recording area 2002 (FIG. 7B(3e)).

[0067] Next, the subsequent processing after the main CPU 1A or sub-CPU 1B performs a noise check on the return cause will be described. In Fig. 7C, the main CPU 1A determines the operation mode according to the return cause. The main CPU 1A accesses the normal recording area 2003 and the shared recording area 2002 of the RAM 120b and acquires the noise detection flags of the normal recording area 2003 and the shared recording area 2002 (Fig. 7C(2j)). Next, the main CPU 1A accesses the shared recording area 2002 of the RAM 120b and acquires the return cause stored in the return cause storage area by the power-saving CPU 1C (Fig. 7C(2k)).

[0068] If another return cause occurs during the determination of the operation mode, the return cause detection unit 1103 of the main CPU 1A detects the other return cause (FIG. 7C(2l)). Furthermore, the return cause detection unit 1103 of the main CPU 1A notifies the return determination unit 1104 of the main CPU 1A of the other return cause that has been detected.

[0069] The main CPU 1A uses the acquired noise detection flag and the acquired or notified return cause to determine whether any of the following five processes is satisfied, and then determines the operation mode according to the return cause.

[0070] (1) When the cause of recovery is noise. (2) When the cause of recovery is not noise. (3) When packets are being received from the network. (4) When the return cause detection unit 1103 of the main CPU 1A detects a return cause other than (3). (5) When the noise detection flag is the initial value.

[0071] In the case of (1), since there is no need to return the system from the power saving mode to the normal mode, the process returns to the power saving mode transition process (i.e., FIG. 7A(1a)) and the process of transitioning to the power saving mode is executed again.

[0072] In the case of (2), since the cause of the return is a normal return cause, it is necessary to return the system from the power saving mode to the normal mode. In the case of (3), since the packet was received from a network that was not registered in advance in the image forming apparatus 10, an automatic response by the network packet automatic response unit 1304 is not possible, so it is necessary to return the system from the power saving mode to the normal mode. In the case of (4), since a cause of the return has occurred, it is necessary to return the system from the power saving mode to the normal mode.

[0073] In (2), (3), and (4), in order to return the system from the power-saving mode to the normal mode, the main CPU 1A requests the automatic network packet response unit 1304 of the power-saving CPU 1C to stop detecting packets from the network (FIG. 7C(2n)). The automatic network packet response unit 1304 receives the request and stops detecting packets from the network (FIG. 7C(2o)). The power-saving management unit 1102 of the main CPU 1A requests the system control unit 1101 of the main CPU 1A to return the system to normal operation (FIG. 7C(2p)), and the system control unit 1101 of the main CPU 1A starts up (FIG. 7C(2q)). Only after these processes are performed will all modules and engines of the image forming apparatus 10 operate.

[0074] In the case of (5), since noise detection processing is in progress, the noise detection processing is put on hold (sleep) for a certain period of time. After that, the noise detection flag and the return cause are acquired (FIG. 7C (2j) and (2k)), and the operation mode determination processing (1) to (5) is performed. This allows the operation mode to be determined appropriately even if the noise detection processing takes a long time, and makes it possible to reduce unnecessary power consumption and return to the power saving mode.

[0075] 8 is a flowchart showing the operation of the main CPU 1A. When a return cause occurs in step S801, a noise check of the return cause is performed in step S802 to determine whether the return cause is due to noise. As mentioned above, depending on the return cause, a CPU other than the main CPU 1A may perform the noise check. A CPU that has completed the noise check stores a noise detection flag in a predetermined shared recording area 2002.

[0076] In step S803, the main CPU 1A acquires a noise detection flag and a return cause. The return cause detection unit 1103 of the main CPU 1A detects any additional return causes and notifies the return determination unit 1104 of the main CPU 1A of the additional return cause. In step S803, if the noise detection flag indicates to the main CPU 1A that the return cause is a false return cause, the main CPU 1A transitions to power-saving mode (step S804). In step S803, if the noise detection flag indicates to the main CPU 1A that the return cause is a normal return cause, or if the additional return cause is the receipt of a packet from the network or something else, the main CPU 1A transitions to normal mode (step S805). In step S803, if the main CPU 1A is informed that the noise detection flag is set to its initial value, the main CPU 1A waits for a certain period of time to wait for the completion of the noise check for the return cause (step S806), and then acquires the noise detection flag and return cause again.

[0077] As described above, according to this embodiment, noise detection processing is possible even when the noise detection processing requires time, and furthermore, the operation of the main CPU according to the cause of the return signal can be minimized.

[0078] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements set forth in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form. The above-described embodiments can be combined with each other.

[0079] Furthermore, each function of the above-described embodiments can be realized by one or more processing circuits. Here, the term "processing circuit" in this specification includes a processor programmed to perform each function by software, such as a processor implemented by an electronic circuit, as well as devices such as an ASIC (Application Specific Integrated Circuit), a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), and conventional circuit modules designed to perform each of the above-described functions.

[0080] For example, aspects of the present invention are as follows.

[0081] <1> In an information processing device whose internal state switches between a normal mode and a power saving mode, a first processor that processes the overall operation of the information processing device; a second processor that processes auxiliary operations of the information processing device; a third processor that controls the power states of the first processor and the second processor; a first memory that records occurrence of a factor that causes the device to return from the power saving mode to the normal mode and whether the factor that caused the return is true or false; a second memory that stores the type of the return factor, the type of processor that detects the truth or falsehood of the return factor, and a recording location in the first memory where the truth or falsehood of the return factor is recorded, in association with each other; The first processor a noise detection unit that, when a first return cause occurs, determines whether the first return cause is true or false by referring to the second memory and records a determination result of the true or false of the first return cause in the first memory; a return determination unit that refers to the first memory to acquire the determination result of the first return cause, and determines whether or not a return from the power saving mode is necessary according to the determination result of the first return cause, when the determination result of the first return cause is not acquired from the first memory, the return determination unit waits for a predetermined time, and then repeatedly acquires the determination result of the first return cause by referring to the first memory. An information processing device characterized by: <2> <1> The information processing device according to When the first processor detects a second return cause before acquiring the determination result of the first return cause, the first processor transitions to the normal mode. An information processing device characterized by: <3> <1> or <2> The information processing device according to the first processor transitions to the normal mode when the determination result of the acquired first return cause is true, and transitions to the power saving mode when the determination result of the acquired first return cause is false; An information processing device characterized by: <4> <1> from <3> The information processing device according to any one of the preceding claims, the first memory has a flag indicating whether the return factor is true or false, the first processor refers to the first memory, and when a first flag of the first return cause is an initial value, it determines that determination of whether the first return cause is true or false is incomplete, and waits for the predetermined time; An information processing device characterized by: <5> <1> from <4> The information processing device according to any one of the preceding claims, when the third processor receives a predetermined packet registered in the information processing device from a network during the time until the first processor acquires the determination result of the first return cause, the third processor automatically responds to the predetermined packet. An information processing device characterized by: <6> <1> from <5> an information processing device according to any one of the preceding claims; an image forming system; The recovery factor includes an operation or a request to the image forming system. <7> An information processing method executed by an information processing device whose internal state switches between a normal mode and a power saving mode, comprising: recording in a first memory the occurrence of a factor causing the device to return from the power saving mode to the normal mode and whether the factor causing the device to return is true or false; a step of storing in a second memory the type of the return factor, the type of processor that detects the truth or falsehood of the return factor, and a recording location in the first memory where the truth or falsehood of the return factor is recorded in association with each other; When a first return cause occurs, determining whether the first return cause is true or false by referring to the second memory, and recording a determination result of whether the first return cause is true or false in the first memory; acquiring the determination result of the first return cause by referring to the first memory, and determining whether or not a return from the power saving mode is necessary according to the determination result of the first return cause; when the determination result of the first return cause is not acquired from the first memory, after waiting for a predetermined time, repeatedly acquiring the determination result of the first return cause by referring to the first memory; An information processing method comprising: <8> An information processing device whose internal state switches between a normal mode and a power saving mode, a process of recording in a first memory the occurrence of a factor for returning from the power saving mode to the normal mode and the truth or falsity of the occurred factor for returning; a process of storing in a second memory the type of the return factor, the type of processor that detects the truth or falsehood of the return factor, and a recording location in a first memory where the truth or falsehood of the return factor is recorded in association with each other; a process of determining whether a first return cause occurs by referring to the second memory and recording a determination result of whether the first return cause occurs in the first memory when a first return cause occurs; a process of obtaining the determination result of the first return cause by referring to the first memory, and determining whether or not to return from the power saving mode according to the determination result of the first return cause; When the determination result of the first return cause is not acquired from the first memory, after waiting for a predetermined time, a process of repeatedly acquiring the determination result of the first return cause by referring to the first memory; A program characterized by causing a program to be executed. <9> <1> an information processing device according to an image forming system; a terminal device connected to the image forming system via a network, the image forming system receives a packet including an operation request for the image forming system from the terminal device via the network; the information processing device processes the reception of the packet as one of the return factors. A network system comprising: [Explanation of symbols]

[0082] 10 Image forming device 1A Main CPU (first processor) 1101 System control unit 1102 Power saving management department 1103 Recovery factor detection unit 1104 Return determination unit 1105 Noise detection unit 1B Sub-CPU (second processor) 1201 Noise detection unit 1203 submodules 1C low-power CPU (third processor) 1303 Recovery factor detection unit 1304 Network Packet Automatic Response Unit 2001 Return Discrimination Table 2002 Shared Recording Area 2003 Normal recording area 102a, 202 ROM (second memory) 102b, 203 RAM (first memory) [Prior art documents] [Patent documents]

[0083] [Patent Document 1] Japanese Patent Application Publication No. 2024-076088

Claims

1. In an information processing device whose internal state switches between a normal mode and a power saving mode, a first processor that processes the overall operation of the information processing device; a second processor that processes auxiliary operations of the information processing device; a third processor that controls the power states of the first processor and the second processor; a first memory for recording occurrence of a factor for returning from the power saving mode to the normal mode and whether the factor for returning has occurred; a second memory that stores the type of the return factor, the type of a processor that detects whether the return factor is true or false, and a recording location in the first memory where the true or false of the return factor is recorded, in association with each other; The first processor a noise detection unit that, when a first return cause occurs, determines whether the first return cause is true or false by referring to the second memory and records a determination result of the truth or falseness of the first return cause in the first memory; a return determination unit that refers to the first memory to acquire the determination result of the first return cause, and determines whether or not a return from the power saving mode is necessary in accordance with the determination result of the first return cause, when the determination result of the first return cause is not acquired from the first memory, the return determination unit waits for a predetermined time, and then repeatedly acquires the determination result of the first return cause by referring to the first memory. An information processing device characterized by:

2. 2. The information processing device according to claim 1, When the first processor detects a second return cause before acquiring the determination result of the first return cause, the first processor transitions to the normal mode. An information processing device characterized by:

3. 2. The information processing device according to claim 1, the first processor transitions to the normal mode when the determination result of the acquired first return cause is true, and transitions to the power saving mode when the determination result of the acquired first return cause is false; An information processing device characterized by:

4. 2. The information processing device according to claim 1, the first memory has a flag indicating whether the return factor is true or false, the first processor refers to the first memory, and when the first flag of the first return cause is an initial value, it considers that determination of the truth or falsehood of the first return cause is incomplete, and waits for the predetermined time; An information processing device characterized by:

5. 3. The information processing device according to claim 2, when the third processor receives a predetermined packet registered in the information processing device from a network during the time until the first processor acquires the determination result of the first return cause, the third processor automatically responds to the predetermined packet. An information processing device characterized by:

6. The information processing device according to any one of claims 1 to 5; an image forming system; the return factor includes an operation or a request to the image forming system; Image forming device.

7. An information processing method executed by an information processing device whose internal state switches between a normal mode and a power saving mode, comprising: recording in a first memory the occurrence of a factor causing the device to return from the power saving mode to the normal mode and whether the factor causing the device to return is true or false; storing in a second memory the type of the return factor, the type of processor that detects the truth or falsehood of the return factor, and a recording location in the first memory where the truth or falsehood of the return factor is recorded in association with each other; When a first return cause occurs, determining whether the first return cause is true or false by referring to the second memory, and recording a determination result of the true or false of the first return cause in the first memory; acquiring the determination result of the first return cause by referring to the first memory, and determining whether or not a return from the power saving mode is necessary according to the determination result of the first return cause; when the determination result of the first return cause is not acquired from the first memory, after waiting for a predetermined time, repeatedly acquiring the determination result of the first return cause by referring to the first memory; An information processing method comprising:

8. An information processing device whose internal state switches between a normal mode and a power saving mode, a process of recording in a first memory the occurrence of a factor for returning from the power saving mode to the normal mode and the truth or falsity of the occurred factor for returning; a process of storing in a second memory the type of the return factor, the type of processor that detects the truth or falsehood of the return factor, and a recording location in a first memory where the truth or falsehood of the return factor is recorded in association with each other; a process of determining whether a first return cause occurs by referring to the second memory and recording a determination result of whether the first return cause occurs in the first memory when a first return cause occurs; a process of obtaining the determination result of the first return cause by referring to the first memory, and determining whether or not a return from the power saving mode is necessary according to the determination result of the first return cause; a process of repeatedly obtaining the determination result of the first return cause by referring to the first memory after waiting for a predetermined time when the determination result of the first return cause is not obtained from the first memory; A program characterized by causing a program to be executed.

9. The information processing device according to claim 1 ; an image forming system; a terminal device connected to the image forming system via a network, the image forming system receives a packet including an operation request for the image forming system from the terminal device via the network; the information processing device processes the reception of the packet as one of the return factors. A network system comprising:

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