Display device and driving method thereof

Abstract

To improve data through with low power consumption.SOLUTION: A display panel including a first pixel in a first pixel row connected to a first data line and a second pixel in a second pixel row adjacent to the first pixel, a data output channel configured to output a first data voltage to the first data line in a first time of a refresh frame and to output a second data voltage to the second data line in a second time subsequent to the first time, a source driver configured to output a first precharge voltage to the first data line in the first time and to output a second precharge voltage to the first data line in the second time; And a MUX switch circuit configured to connect the auxiliary output channel to the second data line, and connect the data output channel to the second data line and the auxiliary output channel to the first data line at the second time.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This disclosure relates to a display device and a driving method thereof. [Background technology]

[0002] The display device includes pixels arranged in a matrix, and realizes a target brightness corresponding to a data voltage through the pixels on a display panel. Each pixel includes a light emitting element, and the target brightness is realized according to the amount of light emitted by the light emitting element.

[0003] The pixel receives the data voltage output from the source driver through the data line. The level of the data voltage supplied through the data line can change over time. The image quality realized by the pixel depends on the data slew of the data voltage. Data slew can be defined as the speed at which the potential of the data line follows the target level of the data voltage.

[0004] To improve the data through, it is possible to consider widening the output range of the data voltage or increasing the length of one horizontal time for driving one pixel row, but this approach is disadvantageous in terms of power consumption. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, the present disclosure provides a display device and a driving method thereof that can improve image quality by improving data through with low power consumption. [Means for solving the problem]

[0006] The display device according to this embodiment includes a display panel including: a first pixel located in a first pixel row and connected to a first data line; and a second pixel located adjacent to the first pixel in a second pixel row and connected to a second data line; a source driver including a data output channel that outputs a first data voltage to be supplied to the first data line during a first time period of a refresh frame and outputs a second data voltage to be supplied to the second data line during a second time period following the first time period in the refresh frame; and an auxiliary output channel that precharges a voltage to be supplied to the data line during the first time period and outputs a second precharge voltage to be supplied to the first data line during the second time period; and a mux switch circuit that connects the data output channel to the first data line and the auxiliary output channel to the second data line during the first time period, and connects the data output channel to the second data line and the auxiliary output channel to the first data line during the second time period.

[0007] The present disclosure has the following advantages.

[0008] The present disclosure provides a method for supplying a precharge voltage to a display panel through a connection configuration of a source driver and a max switch circuit, thereby improving data through with low power consumption and improving image quality.

[0009] In the present disclosure, the generator and supply path of the line stabilization voltage and / or the OBS voltage in addition to the precharge voltage are unified, thereby simplifying the circuitry required for driving and realizing low power consumption.

[0010] The effects of the present disclosure are not limited to the above-mentioned examples, and various other effects are also included within the present disclosure. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating a display device according to an embodiment of the present invention. [Figure 2]1 is a diagram showing a part of a pixel array provided on a screen. [Figure 3] 1 is a diagram illustrating an example of a VRR technique applied to a display device according to an embodiment of the present invention. [Figure 4] 1 is a diagram illustrating a configuration in which a source driver is connected to a pixel array via a max switch circuit. [Figure 5] 10A and 10B are diagrams illustrating a connection configuration and driving timing of a max switch circuit according to a first embodiment for improving data through of a data line for various image patterns. [Figure 6] 10A and 10B are diagrams illustrating a connection configuration and driving timing of a max switch circuit according to a first embodiment for improving data through of a data line for various image patterns. [Figure 7] 10A and 10B are diagrams illustrating a connection configuration and driving timing of a max switch circuit according to a first embodiment for improving data through of a data line for various image patterns. [Figure 8] 10A and 10B are diagrams illustrating a connection configuration and driving timing of a max switch circuit according to a first embodiment for improving data through of a data line for various image patterns. [Figure 9a] 10 is a diagram illustrating an operation state of the max switch circuit implemented in FIG. 6 and FIG. 8 at a first time point. [Figure 9b] 10 is a diagram illustrating an operation state of the max switch circuit implemented at a second time in FIGS. 6 and 8. [Figure 10] 1 is a diagram illustrating a connection configuration of one pixel applied to a display device according to an embodiment of the present invention. [Figure 11] 10 is a diagram showing a driving waveform of one pixel in a refresh frame; [Figure 12] 10 is a diagram showing a driving waveform of one pixel in a skip frame; [Figure 13] 1 is a diagram showing a configuration of a max switch circuit and a portion of a source driver connected thereto according to a first embodiment; [Figure 14]10 is a diagram showing data outputs and auxiliary outputs of a source driver during a refresh frame and a skip frame. [Figure 15a] 10 is a diagram illustrating an operation state of a max switch circuit implemented in a first period of a refresh frame. [Figure 15b] 10 is a diagram illustrating an operation state of a max switch circuit implemented in a second time period of a refresh frame. [Figure 15c] 10 is a diagram illustrating an operation state of a max switch circuit implemented in a skip frame. [Figure 16] 10 is a diagram showing another connection configuration of pixels applied to the display device of the present embodiment; [Figure 17] 10 is a diagram illustrating that a precharge voltage and an on-bias stress voltage are supplied to one data line through one auxiliary output channel at different timings of a refresh frame. [Figure 18] 10 is a diagram showing that a line stabilization voltage and an on-bias stress voltage are supplied to one data line through one auxiliary output channel at different timings of a skip frame. [Figure 19] 10 is a diagram showing an operation state of a max switch circuit for selectively outputting an OBS voltage and a line stabilization voltage in a skip frame. [Figure 20] 10 is a diagram showing a connection configuration of a max switch circuit according to a second embodiment for improving data through of a data line; DETAILED DESCRIPTION OF THE INVENTION

[0012] The advantages and features of the present disclosure, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided so that the disclosure of the present disclosure will be complete and will fully convey the scope of the invention to those skilled in the art. The present disclosure is defined only by the scope of the claims.

[0013] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this disclosure are illustrative only and are not intended to limit the scope of this disclosure. The same reference numerals refer to the same components throughout this disclosure. When words such as "include," "have," and "comprise" are used in this disclosure, other parts may be added unless "only" is used. When a component is expressed in the singular, it also includes the plural unless otherwise explicitly stated.

[0014] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0015] When describing a positional relationship, for example, "above," "upper," "below," or "beside," there may be one or more different parts located between the two parts, unless "immediately" or "directly" is used.

[0016] Although terms such as "first" and "second" may be used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, a first component referred to below may also be a second component within the technical concept of this disclosure.

[0017] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, if it is determined that a detailed description of the notification function or configuration related to the present disclosure unnecessarily obscures the gist of the present disclosure, the detailed description will be omitted.

[0018] 1 is a diagram showing a display device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a part of a pixel array provided on a screen.

[0019] 1 and 2, the display device according to the present embodiment may be, but is not limited to, an organic light emitting display device. The display panel 100 includes a screen AA on which an input image is reproduced. The screen AA includes a pixel array on which pixel data (hereinafter referred to as "video data") of the input image is displayed. The pixel array includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and a plurality of pixels SP.

[0020] The pixels SP may be arranged on the screen AA in the form of a matrix defined by the intersections of the data lines DL and the gate lines GL. Depending on the locations of the pixels SP that emit the same color, the pixels SP may be arranged in various patterns on the screen AA, such as a stripe pattern or a diamond pattern.

[0021] The pixel array includes pixel columns and pixel rows L1 to Ln that intersect with the pixel columns. The pixel columns include pixels SP arranged along the y-axis direction. The pixel rows include pixels SP arranged along the x-axis direction. One vertical period is one frame period required to write one frame's worth of image data DATA to all pixels SP on the screen. One horizontal period is the time obtained by dividing one frame period by the number of pixel rows L1 to Ln. One horizontal period is the time required to write one pixel row's worth of image data DATA that share a gate line GL to the pixels SP of one pixel row.

[0022] The pixel SP may include a first pixel (R in FIG. 2) that generates red (R) light, a second pixel (G in FIG. 2) that generates green (G) light, and a third pixel (B in FIG. 2) that generates blue (B) light for various color combinations. The pixel SP may further include a fourth pixel that generates white (W) light. The first to third pixels or the first to fourth pixels may constitute one unit pixel.

[0023] The R, G, and B pixels may form odd-numbered pixel rows L-Odd and even-numbered pixel rows L-Even. In the odd-numbered pixel rows L-Odd, the R, G, and B pixels may be connected to odd-numbered data lines DL1, 3, 5, 7, 9, and 11, while in the even-numbered pixel rows L-Even, the R, G, and B pixels may be connected to even-numbered data lines DL2, 4, 6, 8, 10, and 12. Two adjacent pixels of the same color that form the same pixel column are connected to different data lines. This connection structure facilitates lower power consumption compared to existing connection structures in which two pixels of the same color are commonly connected to the same data line.

[0024] Each pixel SP may be realized by a pixel circuit connected to a data line DL and a gate line GL. The pixel circuit may include a light-emitting element, a driving transistor, one or more switch transistors, a capacitor, etc. The light-emitting element may be realized by an organic light-emitting diode (OLED). The driving current applied to the light-emitting element may be adjusted according to the gate-source voltage of the driving transistor. The gate-source voltage of the driving transistor may be determined by a data voltage corresponding to image data DATA.

[0025] The pixel circuit samples the threshold voltage of the drive transistor during the pixel programming operation performed within one frame period, and the sampled threshold voltage is reflected in the gate-source voltage (hereinafter referred to as Vgs) of the drive transistor, thereby preventing distortion of the drive current due to changes in the threshold voltage of the drive transistor.

[0026] Pixel circuits may be implemented as a hybrid, in which the semiconductor layers of some transistors are made of low-temperature polycrystalline silicon (LTPS) and the semiconductor layers of the remaining transistors are made of oxide.

[0027] Pixel circuits may be driven according to a variable refresh rate (VRR). VRR technology varies the refresh rate for video data DATA depending on the attributes of the video. With VRR technology, the data refresh cycle becomes longer as the video changes less, which can reduce power consumption.

[0028] To implement the VRR technique, at least one skip frame may be placed between adjacent refresh frames. Data refresh operations are performed in the refresh frames but not in the skip frames. The refresh rate, i.e., frame frequency, may be determined depending on the number of skip frames placed between adjacent refresh frames.

[0029] In the refresh frame, a data refresh operation is performed, including pixel initialization, data programming, etc. During the data refresh operation, the light emitting element is turned off, and at this time, an anode reset operation is performed in which the light emitting element is initialized to an anode reset voltage.

[0030] In a skip frame, the data refresh operation for the pixel SP is omitted (or skipped), and the data refresh conditions (Vgs, drive current) already set in the previous refresh frame are maintained in the skip frame. However, an anode reset operation to turn off the light-emitting element is also performed in the skip frame. Therefore, the length of time the light-emitting element is on may be substantially the same in the skip frame and the refresh frame.

[0031] In each of the refresh frame and the skip frame, an on-bias stress (hereinafter referred to as OBS) operation may be performed on the drive transistor while the anode reset operation is being performed.

[0032] In the hybrid pixel circuit of this embodiment, the OBS operation is intended to prevent poor image quality due to the hysteresis characteristics of the drive transistor. When the grayscale value of the video data DATA changes from black to white, the time required for the hysteresis characteristics of the drive transistor to change can lengthen the grayscale response time in the first frame in which a white image is reproduced, resulting in the DFF (Dim First Frame) phenomenon. In this case, applying an OBS voltage to one electrode of the drive transistor to increase the Vgs of the drive transistor can alleviate the DFF characteristics. This is called the OBS operation.

[0033] A touch sensor may be further disposed on the display panel 100. The touch sensor may be disposed on the screen AA of the display panel 100 as an on-cell type or an add-on type, or may be implemented as an in-cell type touch sensor embedded in the pixel array. Touch input may be sensed only through the pixel SP without a touch sensor, in which case the touch sensor may be omitted.

[0034] The display panel driver includes a source driver 110 and gate drivers 120L and 120R. The display panel driver writes video data DATA to the pixels SP of the display panel 100 under the control of a timing controller .

[0035] The source driver 110 converts the video data DATA received from the timing controller 130 into a gamma compensation voltage using a digital-to-analog converter to generate a data voltage. The source driver 110 supplies the data voltage to a data line DL. The data voltage is supplied to the data line DL and applied to the gate electrode of the drive transistor via the switch transistor of each pixel SP. The source driver 110 may be implemented using multiple source drive integrated circuits.

[0036] In order to reduce RC delay deviation that occurs in the large-area display panel 100, the gate drivers 120L and 120R may be implemented in a double-bank manner. That is, the gate drivers 120L and 120R may be formed in a GIP (Gate Driver In Panel) manner in left and right bezel regions BZ located outside the screen AA of the display panel 100, and may supply gate signals of the same phase to the same gate lines GL on both sides of the display panel 100. The gate drivers 120L and 120R may include a first gate driver 120L located in the left bezel region BZ of the display panel 100 and a second gate driver 120R located in the right bezel region BZ of the display panel 100.

[0037] The gate drivers 120L and 120R on both sides sequentially supply gate signals to the gate lines GL under the control of the timing controller 130. The gate signals select pixel rows L1 to Ln to be charged with a data voltage and simultaneously activate the pixels SP arranged in the corresponding pixel rows L1 to Ln. The gate drivers 120L and 120R output gate signals required for pixel driving and shift the gate signals by pixel row. The gate signals include multiple scan signals that swing between an on level and an off level and a light emission control signal. The gate drivers 120L and 120R on both sides include multiple scan drivers that generate the multiple scan signals and a light emission driver that generates the light emission control signal.

[0038] The timing controller 130 receives video data DATA and timing signals synchronized with the video data DATA from a host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal (Vsync) defines a vertical period. The horizontal synchronization signal (Hsync) defines a horizontal period. The data enable signal DE defines the time during which the video data DATA is transmitted in a vertical period or horizontal period. Since the vertical period and horizontal period can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and horizontal synchronization signal Hsync may be omitted.

[0039] The timing controller 130 generates a source timing control signal DDC for controlling the operation timing of the source driver 110 and a gate timing control signal GDC for controlling the operation timing of the gate drivers 120L and 120R using timing signals Vsync, Hsync, and DE received from the host system.

[0040] The host system may be a television, a set-top box, a navigation system, a personal computer (PC), a home theater, a vehicle display system, a mobile device, or a wearable device. In the mobile device or wearable device, the source driver 110, the timing controller 130, the level shifters 140L and 140R, etc. may be integrated into a single drive integrated circuit.

[0041] The level shifters 140L and 140R convert the voltage of the gate timing control signal GDC output from the timing controller 130 into an ON level voltage and an OFF level voltage, and supply them to the gate drivers 120L and 120R.

[0042] The level shifters 140L and 140R include a first level shifter 140L connected to the first-side gate driver 120L via a first signal wiring, and a second level shifter 140R connected to the second-side gate driver 120R via a second signal wiring.

[0043] FIG. 3 is a diagram showing an example of the VRR technique applied to the display device according to this embodiment.

[0044] Referring to Figure 3, the data refresh cycle performed on the pixels of the display panel may vary depending on the attributes of the input image. The data refresh cycle may be shorter when the amount of change in the image is large, and longer when the amount of change in the image is small. The longer the data refresh cycle, the slower the driving speed, and conversely, the shorter the data refresh cycle, the faster the driving speed.

[0045] The data refresh period is 1 / frame frequency. For example, the data refresh period is 1 second / 120 at 120 Hz, 1 second / 60 at 60 Hz, 1 second / 24 at 24 Hz, and 1 second at 1 Hz.

[0046] The number of skip frames placed between two adjacent refresh frames depends on the frame frequency: for example, the number of skip frames is 0 at 120 Hz, 1 at 60 Hz, 4 at 24 Hz, and 119 at 1 Hz.

[0047] FIG. 4 is a diagram showing a schematic configuration in which a source driver is connected to a pixel array via a max switch circuit.

[0048] Referring to FIG. 4, the display device according to this embodiment electrically connects a pixel array for low power consumption and a source driver 110 for improving data through via a max switch circuit MX-ARY.

[0049] In the pixel array, two adjacent pixels of the same color that form the same pixel column are connected to different data lines. For example, the first and second data lines DL1 and DL2 may be exclusively connected to the R pixels R1 and R2 that are adjacent to each other in the same pixel column, and the third and fourth data lines DL3 and DL4 may be exclusively connected to the G pixels G1 and G2 that are adjacent to each other in the same pixel column, and may be exclusively connected to the fifth and sixth data lines BD2.

[0050] In addition to the data output channels DCH1, DCH2, and DCH3, the source driver 110 further includes an auxiliary output channel ACH for improving data through.

[0051] The data output channels DCH1, DCH2, and DCH3 output a first data voltage to be supplied to the odd-numbered data lines DL-Odd during a first time period of a refresh frame, and a second data voltage to be supplied to the even-numbered data lines DL-Even during a second time period following the first time period of the refresh frame. The first time period of the refresh frame may be a data programming time for the pixels R1, G1, and B1 of the first pixel row, and the second time period of the refresh frame may be a data programming time for the pixels R2, G2, and B2 of the second pixel row.

[0052] The auxiliary output channel ACH outputs a first precharge voltage to be supplied to the even data lines DL-Even during a first time period of a refresh frame, and outputs a second precharge voltage to be supplied to the odd data lines DL-Odd during a second time period of the refresh frame. The first precharge voltage is for increasing the data through of the even data lines DL-Even during the refresh frame and varies over time within a predetermined precharge voltage range. The second precharge voltage is for increasing the data through of the odd data lines DL-Odd during the current refresh frame and varies over time within a predetermined precharge voltage range. Here, the predetermined precharge voltage range is greater than the minimum data voltage and less than the maximum data voltage output from the source driver 110.

[0053] During the first refresh frame, the mux switch circuit MX-ARY connects the data output channels DCH1, DCH2, and DCH3 to the odd-numbered data line DL-Odd and the auxiliary output channel ACH to the even-numbered data line DL-Even according to the mux control signals MX1 and MX2.

[0054] The mux switch circuit MX-ARY connects the data output channels DCH1, DCH2, DCH3 to the even data line DL-Even and connects the auxiliary output channel ACH to the odd data line DL-Odd during the second time of the refresh frame according to the mux control signals MX1, MX2.

[0055] 5 to 8 are diagrams showing the connection configuration and drive timing of the max switch circuit according to the first embodiment for improving data through of the data line for various video patterns.

[0056] 9A is a diagram illustrating the operation state of the MUX switch circuit implemented at the first time in FIGS. 6 and 8. FIG. 9B is a diagram illustrating the operation state of the MUX switch circuit implemented at the second time in FIGS. 6 and 8.

[0057] Referring to FIGS. 5 and 7, the max switch circuit MX-ARY according to the first embodiment may include a first group of switches driving the first and second data lines DL1 and DL2, a second group of switches driving the third and fourth data lines DL3 and DL4, and a third group of switches driving the fifth and sixth data lines DL5 and DL6.

[0058] The first group of switches includes first and second max switches M11 and M12 and first and second auxiliary switches A11 and A12.

[0059] The first mux switch M11 is connected between the first data output channel DCH1 and the first data line DL1 and is turned on or off according to the first mux control signal MX1. The first auxiliary switch A11 is connected between the auxiliary output channel ACH and the second data line DL2 and is turned on or off according to the first mux control signal MX1.

[0060] The second mux switch M12 is connected between the first data output channel DCH1 and the first data line DL2 and is turned on or off according to the second mux control signal MX2. The second auxiliary switch A12 is connected between the auxiliary output channel ACH and the first data line DL1 and is turned on or off according to the second mux control signal MX2.

[0061] The second group of switches includes third and fourth max switches M21 and M22, and third and fourth auxiliary switches A21 and A22.

[0062] The third mux switch M21 is connected between the second data output channel DCH2 and the third data line DL3 and is turned on or off according to the first mux control signal MX1. The third auxiliary switch A21 is connected between the auxiliary output channel ACH and the fourth data line DL4 and is turned on or off according to the first mux control signal MX1.

[0063] The fourth mux switch M22 is connected between the second data output channel DCH2 and the fourth data line DL4 and is turned on or off according to the second mux control signal MX2. The fourth auxiliary switch A22 is connected between the auxiliary output channel ACH and the third data line DL3 and is turned on or off according to the second mux control signal MX2.

[0064] The third group of switches includes fifth and sixth max switches M31 and M32, and fifth and sixth auxiliary switches A31 and A32.

[0065] The fifth mux switch M31 is connected between the third data output channel DCH3 and the fifth data line DL5 and is turned on or off according to the first mux control signal MX1. The fifth auxiliary switch A31 is connected between the auxiliary output channel ACH and the sixth data line DL6 and is turned on or off according to the first mux control signal MX1.

[0066] The sixth mux switch M32 is connected between the third data output channel DCH3 and the sixth data line DL6 and is turned on or off in response to the second mux control signal MX2. The sixth auxiliary switch A32 is connected between the auxiliary output channel ACH and the fifth data line DL5 and is turned on or off in response to the second mux control signal MX2.

[0067] The R1G1B1 pixels connected to odd-numbered data lines DL1, DL3, DL5 may be located in odd-numbered pixel row L-Odd, and the R2G2B2 pixels connected to even-numbered data lines DL2, DL4, DL6 may be located in even-numbered pixel row L-Even.

[0068] First, referring to Figures 5, 6, 9A and 9b, an example of the first image pattern (an image pattern that alternates between black and white gradations in units of one pixel row) in conjunction with the max switch circuit of the first embodiment will be described as follows.

[0069] Referring to Figures 5 and 6, due to the operation of the max switch circuit MX-ARY according to the first embodiment, a black gradation data voltage is charged to the odd-numbered pixel row L-Odd during the first time period X1, and a white gradation data voltage is charged to the even-numbered pixel row L-Even during the second time period X2.

[0070] To this end, during the first time X1, the first data output channel DCH1 outputs a first R data voltage DR1 of black gradation, the second data output channel DCH2 outputs a first G data voltage DG1 of black gradation, and the third data output channel DCH3 outputs a first B data voltage DB1 of black gradation. During the first time X1, the auxiliary output channel ACH outputs a first pre-charge voltage PC1.

[0071] 5, 6, and 9A, during a first time period X1, the first mux control signal MX1 is input at an ON level, and the second mux control signal MX2 is input at an OFF level.

[0072] During the first time X1, the first max control signal MX1 at ON level turns on the first, third, and fifth max switches M11, M21, and M31 of the max switch circuit MX-ARY and the first, third, and fifth auxiliary switches A11, A21, and A31, while the second max control signal MX2 at OFF level turns off the second, fourth, and sixth max switches M12, M22, and M32 of the max switch circuit MX-ARY and the second, fourth, and sixth auxiliary switches A12, A22, and A32.

[0073] During the first time period X1, the first, third, and fifth mux switches M11, M21, and M31 are turned on, so that the first data output channel DCH1 is connected to the first data line DL1, the second data output channel DCH2 is connected to the third data line DL3, and the fifth data output channel DCH3 is connected to the third data line DL5. As a result, the first R data voltage DR1 of the black gradation level BLv is supplied to the first data line DL1, the first G data voltage DG1 of the black gradation level BLv is supplied to the third data line DL3, and the first B data voltage DB1 of the black gradation level BLv is supplied to the fifth data line DL5. The first, third, and fifth data lines DL1, DL3, and DL5 are odd-numbered data lines DL-Odd in FIG. 6.

[0074] During the first time period X1, the first, third, and fifth auxiliary switches A11, A21, and A31 are turned on, connecting the auxiliary output channel ACH to the second, fourth, and sixth data lines DL2, DL4, and DL6, respectively, so that the first precharge voltage PC1 at the precharge level PLv is supplied to the even-numbered data lines DL-Even, that is, the second, fourth, and sixth data lines DL2, DL4, and DL6.

[0075] Meanwhile, during the second time X2, the first data output channel DCH1 outputs the second R data voltage DR2 of white gradation, the second data output channel DCH2 outputs the second G data voltage DG2 of white gradation, and the third data output channel DCH3 outputs the second B data voltage DB2 of white gradation. During the second time X2, the auxiliary output channel ACH outputs the second pre-charge voltage PC2.

[0076] Referring to FIGS. 5, 6 and 9b, during the second time period X2, the first mux control signal MX1 is input at an off level, and the second mux control signal MX2 is input at an on level.

[0077] During the second time X2, the first max control signal MX1 at the off level turns off the first, third, and fifth max switches M11, M21, and M31 of the max switch circuit MX-ARY and the first, third, and fifth auxiliary switches A11, A21, and A31, while the second max control signal MX2 at the on level turns on the second, fourth, and sixth max switches M12, M22, and M32 of the max switch circuit MX-ARY and the second, fourth, and sixth auxiliary switches A12, A22, and A32.

[0078] During the second time period X2, the second, fourth, and sixth mux switches M12, M22, and M32 are turned on, connecting the first data output channel DCH1 to the second data line DL2, the second data output channel DCH2 to the fourth data line DL4, and the third data output channel DCH3 to the sixth data line DL6. As a result, the second R data voltage DR2 of the white gradation level WLv is supplied to the second data line DL2, the second G data voltage DG2 of the white gradation level WLv is supplied to the fourth data line DL4, and the second B data voltage DB2 of the white gradation level WLv is supplied to the sixth data line DL6. The second, fourth, and sixth data lines DL2, DL4, and DL6 are the even-numbered data lines DL-Even in FIG. 6.

[0079] During the second time period X2, the second, fourth, and sixth mux switches M12, M22, and M32 are turned on, connecting the auxiliary output channel ACH to the first, third, and fifth data lines DL1, DL3, and DL5, respectively, so that the second precharge voltage PC2 at the precharge level PLv is supplied to the odd-numbered data lines DL-Odd, that is, the first, third, and fifth data lines DL1, DL3, and DL5.

[0080] Next, referring to Figures 7, 8, 9a and 9b, an example of the second image pattern (an image pattern that alternates between black and white gradations in units of one pixel) in conjunction with the max switch circuit of the first embodiment will be described as follows.

[0081] Referring to Figures 7 and 8, due to the operation of the max switch circuit MX-ARY according to the first embodiment, during the first time period X1, the black data voltage and the white data voltage are alternately charged pixel by pixel from the odd-numbered pixel row L-Odd, and during the second time period X2, the white data voltage and the black data voltage are charged.

[0082] For this purpose, during the first time X1, the first data output channel DCH1 outputs a first R data voltage DR1 of black gradation, the second data output channel DCH2 outputs a first G data voltage DG1 of white gradation, and the third data output channel DCH3 outputs a first B data voltage DB1 of black gradation. During the first time X1, the auxiliary output channel ACH outputs a first pre-charge voltage PC1.

[0083] 7, 8 and 9a, during a first time period X1, the first mux control signal MX1 is input at an ON level, and the second mux control signal MX2 is input at an OFF level.

[0084] During the first time period X1, the first max control signal MX1 at ON level turns on the first, third, and fifth max switches M11, M21, and M31 of the max switch circuit MX-ARY and the first, third, and fifth auxiliary switches A11, A21, and A31. Meanwhile, the second max control signal MX2 at OFF level turns off the second, fourth, and sixth max switches M12, M22, and M32 of the max switch circuit MX-ARY and the second, fourth, and sixth auxiliary switches A12, A22, and A32.

[0085] During the first time period X1, the first, third, and fifth mux switches M11, M21, and M31 are turned on, so that the first data output channel DCH1 is connected to the first data line DL1, the second data output channel DCH2 is connected to the third data line DL3, and the third data output channel DCH3 is connected to the fifth data line DL5. As a result, the first R data voltage DR1 of the black gradation level BLv is supplied to the first data line DL1, the first G data voltage DG1 of the white gradation level WLv is supplied to the third data line DL3, and the first B data voltage DB1 of the black gradation level BLv is supplied to the fifth data line DL5.

[0086] During the first time period X1, the first, third, and fifth auxiliary switches A11, A21, and A31 are turned on, connecting the auxiliary output channel ACH to the second, fourth, and sixth data lines DL2, DL4, and DL6, respectively, so that the first precharge voltage PC1 at the precharge level PLv is supplied to the second, fourth, and sixth data lines DL2, DL4, and DL6.

[0087] Meanwhile, during the second time X2, the first data output channel DCH1 outputs the second R data voltage DR2 of white gradation, the second data output channel DCH2 outputs the second G data voltage DG2 of black gradation, and the third data output channel DCH3 outputs the second B data voltage DB2 of white gradation. During the second time X2, the auxiliary output channel ACH outputs the second pre-charge voltage PC2.

[0088] 7, 8 and 9b, during the second time period X2, the first mux control signal MX1 is input at an off level, and the second mux control signal MX2 is input at an on level.

[0089] During the second time X2, the first max control signal MX1 at the off level turns off the first, third, and fifth max switches M11, M21, and M31 of the max switch circuit MX-ARY and the first, third, and fifth auxiliary switches A11, A21, and A31. Meanwhile, the second max control signal MX2 at the on level turns on the second, fourth, and sixth max switches M12, M22, and M32 of the max switch circuit MX-ARY and the second, fourth, and sixth auxiliary switches A12, A22, and A32.

[0090] During the second time period X2, the second, fourth, and sixth mux switches M12, M22, and M32 are turned on, so that the first data output channel DCH1 is connected to the second data line DL2, the second data output channel DCH2 is connected to the fourth data line DL4, and the third data output channel DCH3 is connected to the sixth data line DL6. As a result, the second R data voltage DR2 of the white gradation level WLv is supplied to the second data line DL2, the second G data voltage DG2 of the black gradation level BLv is supplied to the fourth data line DL4, and the second B data voltage DB2 of the white gradation level WLv is supplied to the sixth data line DL6.

[0091] During the second time period X2, the second, fourth, and sixth mux switches M12, M22, and M32 are turned on, connecting the auxiliary output channel ACH to the first, third, and fifth data lines DL1, DL3, and DL5, respectively, so that the second precharge voltage PC2 at the precharge level PLv is supplied to the odd-numbered data lines DL-Odd, that is, the first, third, and fifth data lines DL1, DL3, and DL5.

[0092] FIG. 10 is a diagram showing one connection configuration of pixels applied to the display device of this embodiment.

[0093] Referring to FIG. 10, one pixel SP(n) arranged in the n-th pixel row Ln may implement a pixel circuit including a light emitting element OLED, a driving transistor DT, a plurality of switch transistors T1 to T7, and a capacitor Cst.

[0094] The driving transistor DT, the switch transistors T1 to T7, and the capacitor Cst may control a driving current flowing through the light-emitting element OLED to drive the light-emitting element OLED. Each of the driving transistor DT and the switch transistors T1 to T7 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0095] The second to sixth switch transistors T2 to T6 and the drive transistor DT may be realized as PMOS types including an LTPS semiconductor layer with good response characteristics, whereas the first and seventh switch transistors T1 and T7, whose gate electrodes are directly connected to the drive transistor DT, may be realized as NMOS types including an oxide semiconductor layer with good off characteristics.

[0096] The on-level voltage of a PMOS transistor may be a gate low voltage and the off-level voltage may be a gate high voltage, whereas the on-level voltage of an NMOS transistor may be a gate high voltage and the off-level voltage may be a gate low voltage.

[0097] The light-emitting element OLED includes an anode electrode (or pixel electrode), a cathode electrode (or common electrode), and an organic compound layer (consisting of a common layer and an emission layer) disposed therebetween. The anode electrode of the light-emitting element OLED may be connected to the fourth node N4, and the cathode electrode of the light-emitting element OLED may be connected to the second power supply voltage ELVSS.

[0098] The driving transistor DT may include a gate electrode connected to a first node N1, a source electrode connected to a second node N2, and a drain electrode connected to a third node N3. The driving transistor DT may generate a driving current based on the voltage of the first node N1 (or the data voltage stored in the capacitor Cst) and apply the driving current to the light emitting element OLED.

[0099] The first switch transistor T1 may include a gate electrode receiving a first scan signal SCAN1 from the first scan line SL1, a drain electrode connected to the third node N3, and a source electrode connected to the first node N1. The first switch transistor T1 is turned on in response to the first scan signal SCAN1 to short the gate electrode and drain electrode of the drive transistor DT. Therefore, the drive transistor DT operates like a diode while the first switch transistor T1 is on.

[0100] The second switch transistor T2 may include a gate electrode receiving a second scan signal SCAN2 from a second scan line SL2, a source electrode connected to the data line (or receiving a data voltage Vdata), and a drain electrode connected to a second node N2. The second switch transistor T2 is turned on in response to the second scan signal SCAN2 to transfer the data voltage Vdata to the second node N2.

[0101] The capacitor Cst is connected between the first node N1 and the input terminal of the first power supply voltage ELVDD, and serves to maintain the voltage of the first node N1.

[0102] The third and fourth switch transistors T3 and T4 may be connected between the first power supply voltage ELVDD and the light emitting element OLED, and may form a current transfer path through which the driving current generated by the driving transistor DT transfers.

[0103] The third switch transistor T3 may include a source electrode connected to the input terminal of the first power supply voltage ELVDD, a drain electrode connected to the second node N2, and a gate electrode receiving the light emitting control signal EM from the light emitting control line EL. The fourth switch transistor T4 may include a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode receiving the light emitting control signal EM from the light emitting control line EL.

[0104] The third and fourth switch transistors T3 and T4 are turned on in response to the light emission control signal EM. While the third and fourth switch transistors T3 and T4 are turned on, the light emitting element OLED receives a driving current from the driving transistor DT and emits light with a corresponding brightness.

[0105] The fifth switch transistor T5 may have a source electrode connected to the input terminal of the OBS voltage Vobs, a second electrode connected to the second node N2, and a gate electrode receiving the third scan signal SCAN3 from the third scan line SL3, and is turned on in response to the third scan signal SCAN3 to apply the OBS voltage Vobs to the second node N2.

[0106] The sixth switch transistor T6 may have a source electrode connected to the input terminal of the anode reset voltage Var, a drain electrode connected to the fourth node N4, and a gate electrode receiving the third scan signal SCAN3 from the third scan line SL3. The sixth switch transistor T6 is turned on in response to the third scan signal SCAN3 to apply the anode reset voltage Var to the fourth node N4.

[0107] The seventh switch transistor T7 may have a source electrode connected to the input terminal of the initialization voltage Vini, a second electrode connected to the first node N1, and a gate electrode receiving a fourth scan signal SCAN4 from the fourth scan line SL4, and is turned on in response to the fourth scan signal SCAN4 to apply the initialization voltage Vini to the first node N1.

[0108] FIG. 11 shows a drive waveform diagram for one pixel SP(n) in a refresh frame.

[0109] Referring to FIG. 11, a first OBS interval Tobs1, an initialization interval Ti, a programming interval Ts, a second OBS interval Tobs2, and a light-emitting interval Te may be arranged in time order within a refresh frame.

[0110] The second scan signal SCAN2 defines a programming period Ts during which the data voltage Vdata is supplied. The programming period Ts is a period during which the second scan signal SCAN2 is at an on level Lon.

[0111] The third scan signal SCAN3 defines a first OBS interval Tobs1 that precedes the programming interval Ts and a second OBS interval Tobs2 that lags the programming interval Ts and precedes the light emission interval Te. The first OBS interval Tobs1 and the second OBS interval Tobs2 are on-level Lon intervals of the third scan signal SCAN3.

[0112] The fourth scan signal SCAN4 defines an initialization period Ti located between the first OBS period Tobs1 and the programming period Ts. The initialization period Ti is an on-level Lon period of the fourth scan signal SCAN4.

[0113] The light emission control signal EM defines a light emission interval Te following the second OBS interval Tobs2. The light emission interval Te is an interval during which the light emission control signal EM is at on level Lon.

[0114] 10 and 11, in the first OBS period Tobs1, the fifth and sixth switch transistors T5 and T6 are turned on in response to the third scan signal SCAN3, and the remaining switch transistors T1 to T4 and T7 are turned off.

[0115] In the first OBS period Tobs1, when the fifth switch transistor T5 is turned on, the OBS voltage Vobs is applied to the second node N2. The OBS voltage Vobs maximizes the source-drain channel of the drive transistor DT, causing the drive transistor DT to maintain a stronger saturation state, which may improve the hysteresis characteristics of the drive transistor DT prior to data programming.

[0116] In the first OBS period Tobs1, the sixth switch transistor T6 is turned on, and thus the anode reset voltage Var is applied to the fourth node N4. The anode reset voltage Var resets the residual charge stored in the parasitic capacitor formed between the anode electrode and the cathode electrode of the light emitting element OLED.

[0117] 10 and 11, during the initialization period Ti, the first and seventh switch transistors T1 and T7 are turned on in response to the first and fourth scan signals SCAN1 and SCAN4, and the remaining switch transistors T2 to T6 are turned off. When the seventh switch transistor T7 is turned on, the first node N1 is initialized to the initialization voltage Vini, and when the first switch transistor T1 is turned on, the drive transistor DT operates like a diode.

[0118] 10 and 11, in the programming period Ts, when the first and second switch transistors T1 and T2 are turned on, a threshold voltage sampling operation and a data programming operation may be performed sequentially or simultaneously.

[0119] During the programming period Ts, the potential of the data line DL changes from the pre-charge voltage Vpc to the data voltage Vdata. Since the voltage difference between the pre-charge voltage Vpc and the data voltage Vdata is small, the data through of the data line DL may be improved.

[0120] During the programming period Ts, the data voltage Vdata charged on the data line DL is applied to the second node N2 via the second switch transistor T2. This data voltage Vdata is applied to the third node N3 via the drive transistor DT, and then to the first node N1 via the first switch transistor T1. Since the drive transistor DT operates like a diode when the first switch transistor T1 is on, the potential of the gate electrode of the drive transistor DT connected to the first node N1 is programmed to Vdata-|Vth|. The potential of the programmed gate electrode of the drive transistor DT reflects the sampled threshold voltage Vth.

[0121] 10 and 11, in the second OBS period Tobs2, the fifth and sixth switch transistors T5 and T6 are turned on in response to the third scan signal SCAN3, and the remaining switch transistors T1 to T4 and T7 are turned off.

[0122] In the second OBS period Tobs2, when the fifth switch transistor T5 is turned on, the OBS voltage Vobs is applied to the second node N2. The OBS voltage Vobs maximizes the source-drain channel of the drive transistor DT, causing the drive transistor DT to maintain a stronger saturated state, which may improve the hysteresis characteristics of the drive transistor DT again prior to light emission.

[0123] In the second OBS period Tobs2, when the sixth switch transistor T6 is turned on, the anode reset voltage Var is applied to the fourth node N4, and the residual charge stored in the parasitic capacitor of the light emitting element OLED is reset again.

[0124] 10 and 11, in the light-emitting period Te, the third and fourth switch transistors T3 and T4 are turned on in response to the light-emitting control signal EM, and the remaining switch transistors T1, T2, T5, T6, and T7 are turned off.

[0125] In the light-emitting period Te, the driving current supplied from the driving transistor DT to the light-emitting element OLED is based on the Vgs of the driving transistor DT set in the programming period Ts. This driving current is related to the data voltage Vdata regardless of the threshold voltage of the driving transistor DT.

[0126] Therefore, since the data line DL in the refresh frame is connected to the auxiliary output channel before being connected to the data output channel of the source driver, the precharge voltage Vpc may be pre-supplied from the auxiliary output channel. The data line DL is line-charged with the precharge voltage Vpc prior to the data voltage Vdata, thereby improving the data through of the data line DL.

[0127] FIG. 12 shows a driving waveform diagram of the pixel SP(n) in the skip frame.

[0128] Referring to FIG. 12, a third OBS interval Tobs3, a fourth OBS interval Tobs4, and a light-emitting interval Te may be arranged in chronological order within a skip frame.

[0129] The light emission control signal EM defines the light emission interval Te of the skip frame. The light emission interval Te is the interval during which the light emission control signal EM is at on level Lon. The interval during which the light emission control signal EM is at on level Lon is substantially equal between the skip frame and the refresh frame.

[0130] The third scan signal SCAN3 further defines a third OBS interval Tobs3 and a fourth OBS interval Tobs4, which are sequentially arranged before the light-emitting interval Te in the skip frame. The third OBS interval Tobs3 and the fourth OBS interval Tobs4 in the skip frame are on-level Lon intervals of the third scan signal SCAN3.

[0131] On the other hand, the initialization section and the programming section are not necessary in the skip frame, and the fourth OBS section Tobs4 in the skip frame can be omitted.

[0132] Referring to FIGS. 10 and 12, the hysteresis characteristics of the driving transistor DT are improved again in the third OBS interval Tobs3 and the fourth OBS interval Tobs4, thereby dramatically reducing the deviation of the hysteresis characteristics between the skip frame and the refresh frame.

[0133] The first and second OBS intervals Tobs1 and Tobs2 of the refresh frame belong to the off level Loff interval of the light emission control signal EM, and similarly, the third and fourth OBS intervals Tobs3 and Tobs4 of the skip frame may also belong to the off level Loff interval of the light emission control signal EM.

[0134] Since the length of the off level Loff section of the emission control signal EM is set equal between the refresh frame and the skip frame, the length of the emission hold time may be equal between the refresh frame and the skip frame.

[0135] On the other hand, in the skip frame, the data line DL is connected to the auxiliary output channel of the source driver, and the auxiliary output channel may further supply a DC level line stabilization voltage Vpark. The line stabilization voltage Vpark fixes the potential of the data line DL during the skip frame, thereby preventing the problem of the voltage charged to the pixel being distorted due to fluctuations in the potential of the data line DL.

[0136] Fig. 13 is a diagram showing a partial configuration of a max switch circuit and a source driver connected thereto according to the first embodiment. Fig. 14 is a diagram showing the data output and auxiliary output of the source driver between a refresh frame and a skip frame.

[0137] 13 and 14, the source driver includes a plurality of digital-to-analog converters (RDAC, GDAC, BDAC, PDAC) and first to fourth output control switches SW1, SW2, SW3, SW4.

[0138] The RDAC generates and outputs first and second R data voltages DR1 and DR2.

[0139] The first output control switch SW1 is connected between the output of the RDAC and the first data output channel DCH1, and is turned on or off according to the first source output control signal SOE1.

[0140] The GDAC generates and outputs first and second G data voltages DG1 and DG2.

[0141] The second output control switch SW2 is connected between the output of the GDAC and the second data output channel DCH2, and is turned on or off according to the first source output control signal SOE1.

[0142] The BDAC generates and outputs first and second B data voltages DB1 and DB2.

[0143] The third output control switch SW3 is connected between the output of the BDAC and the third data output channel DCH3, and is turned on or off according to the first source output control signal SOE1.

[0144] The PDAC generates and outputs first and second precharge voltages PC1 and PC2 and a line stabilization voltage Vpark.

[0145] The first and second precharge voltages PC1 and PC2 are voltages that change over time within a predetermined precharge voltage range. The image gray scale implemented in the same pixel and the target data voltage for representing it change over time. Data slew is defined as the speed at which the potential of the data line follows the target level of the data voltage. Therefore, if the target data voltage changes over time, the first and second precharge voltages PC1 and PC2 may also change over time to follow the target data voltage in order to increase data slew. Here, the precharge voltage range is located between the upper and lower data output limits of the source driver. That is, the precharge voltage range is greater than the minimum data voltage and less than the maximum data voltage.

[0146] The stabilized voltage Vpark is fixed to a voltage within the precharge voltage range. The level of the stabilized voltage Vpark is fixed and does not change over time. The stabilized voltage Vpark has a DC level.

[0147] The fourth output control switch SW4 is connected between the PDAC output and the auxiliary output channel ACH, and is turned on or off according to the second source output control signal SOE2.

[0148] During a refresh frame, the first source output control signal SOE1 and the second source output control signal SOE2 are maintained in an ON state, and the first and second MAX control signals MX1 and MX2 are alternately turned ON and OFF.

[0149] FIG. 15a shows the operation state of the max switch circuit MX-ARY realized at the first time X1 of the refresh frame.

[0150] Referring to FIG. 15a, at a first time X1 of a refresh frame, the first MAX control signal MX1 is turned on and the second MAX control signal MX2 is turned off.

[0151] During the first time X1 of the refresh frame, the first R data voltage DR1 output from the RDAC is supplied to the first data line DL1 via the first output control switch SW1 and the first MUX switch M11.

[0152] During the first time X1 of the refresh frame, the first G data voltage DG1 output from the GDAC is supplied to the third data line DL3 via the second output control switch SW2 and the third MUX switch M21.

[0153] During the first time X1 of the refresh frame, the first B data voltage DB1 output from the BDAC is supplied to the fifth data line DL5 via the third output control switch SW3 and the fifth MUX switch M31.

[0154] During the first time X1 of the refresh frame, the first precharge voltage PC1 output from the PDAC is supplied to the second, fourth, and sixth data lines DL2, DL4, and DL6 via the fourth output control switch SW4 and the first, third, and fifth auxiliary switches A11, A21, and A31.

[0155] FIG. 15b shows the operating state of the max switch circuit MX-ARY realized at the second time X2 of the refresh frame.

[0156] Referring to FIG. 15b, at the second time X2 of the refresh frame, the first MAX control signal MX1 is turned off and the second MAX control signal MX2 is turned on.

[0157] During the second time X2 of the refresh frame, the first R data voltage DR1 output from the RDAC is supplied to the second data line DL2 via the first output control switch SW1 and the second MUX switch M12.

[0158] During the second time X2 of the refresh frame, the first G data voltage DG1 output from the GDAC is supplied to the fourth data line DL4 via the second output control switch SW2 and the fourth MUX switch M22.

[0159] During the second time X2 of the refresh frame, the first B data voltage DB1 output from the BDAC is supplied to the sixth data line DL6 via the third output control switch SW3 and the sixth MUX switch M32.

[0160] During the second time X2 of the refresh frame, the second precharge voltage PC2 output from the PDAC is supplied to the first, third, and fifth data lines DL1, DL3, and DL5 via the fourth output control switch SW4 and the second, fourth, and sixth auxiliary switches A12, A22, and A32.

[0161] FIG. 15c shows the operation state of the max switch circuit MX-ARY realized in the skip frame.

[0162] 15c, during a skip frame, the first source output control signal SOE1 is turned off and the second source output control signal SOE2 is turned on. The off state of the first source output control signal SOE1 causes the data output channels DCH1, DCH2, and DCH3 to be in a floating state (Hi-Z) during the skip frame. The on state of the second source output control signal SOE2 causes the fourth output control switch SW4 to remain on during the skip frame.

[0163] In a skip frame, the PDAC outputs a line stabilization voltage Vpark. The line stabilization voltage Vpark output from the PDAC is supplied to the first to sixth data lines DL1 to DL6 via the fourth output control switch SW4 and the first to sixth auxiliary switches A11 to A32, suppressing potential fluctuations on the data lines depending on the surrounding environment.

[0164] Since the precharge voltages PC1, PC2 and the line stabilization voltage Vpark are generated by the same generator and have the same supply route, the circuit is simplified and power consumption can be easily reduced.

[0165] FIG. 16 is a diagram showing another connection configuration of pixels applied to the display device of this embodiment.

[0166] The pixel circuit in FIG. 16 has the same configuration as the pixel circuit in FIG. 10 except for the connection configuration of the fifth switch transistor T5.

[0167] Referring to FIG. 16, the source electrode of the fifth switch transistor T5 is directly connected to the data line DL, and receives the OBS voltage Vobs from the data line DL.

[0168] The data line DL is connected to the data output channel and auxiliary output channel of the source driver via the above-mentioned max switch circuit MX-ARY.

[0169] As described above, the source driver outputs the data voltage Vdata through the data output channel in the refresh frame and the precharge voltage Vpc through the auxiliary output channel, and also outputs the precharge voltage Vpc through the auxiliary output channel in the skip frame.

[0170] This source driver floats the data output channel during the OBS period of the refresh frame and the skip frame, and outputs the OBS voltage Vobs supplied to the data line DL through the auxiliary output channel.

[0171] The max switch circuit MX-ARY connects the data line DL to the auxiliary output channel during the OBS period, so that the OBS voltage is applied to the second node connected to the source electrode of the drive transistor DT in synchronization with the light emitting element OLED included in the pixel SP(n) being initialized to the anode reset voltage Var during the OBS period.

[0172] In this way, the source driver that drives the pixel circuit of FIG. 16 may further contribute to simplifying the circuit by further outputting the OBS voltage (Vobs) through the auxiliary output channel in refresh frames and skip frames.

[0173] According to this embodiment, as shown in FIG. 17, the precharge voltage Vpc and the OBS voltage Vobs may be charged to one data line via one auxiliary output channel at different timings of a refresh frame.

[0174] According to this embodiment, as shown in FIG. 18, the line stabilizing voltage Vpark and the OBS voltage Vobs may be supplied to one data line through one auxiliary output channel at different timings of the skip frame.

[0175] FIG. 19 shows the operation of the max switch circuit MX-ARY for selectively outputting the line stabilization voltage Vpark and the OBS voltage Vobs in a skip frame.

[0176] 19, in a skip frame, the first source output control signal SOE1 is turned off and the second source output control signal SOE2 is turned on. The off operation of the first source output control signal SOE1 causes the data output channels DCH1, DCH2, and DCH3 to be in a floating state (Hi-Z) in the skip frame. The on operation of the second source output control signal SOE2 causes the fourth output control switch SW4 to maintain an on state in the skip frame.

[0177] During the skip frame, the PDAC alternately outputs the line stabilization voltage Vpark and the OBS voltage Vobs. The line stabilization voltage Vpark output from the PDAC is supplied to the first to sixth data lines DL1 to DL6 via the fourth output control switch SW4 and the first to sixth auxiliary switches A11 to A32, suppressing potential fluctuations on the data lines depending on the surrounding environment.

[0178] The OBS voltage Vobs output from the PDAC is supplied to the first to sixth data lines DL1 to DL6 via the fourth output control switch SW4 and the first to sixth auxiliary switches A11 to A32, and contributes to improving the hysteresis characteristics of the pixels.

[0179] FIG. 20 is a diagram showing a connection configuration of a max switch circuit according to a second embodiment for improving data through of a data line.

[0180] Compared with the max switch circuit MX-ARY according to the first embodiment described above with reference to FIGS. 5 and 7, the max switch circuit MX-ARY in FIG. 20 has the following differences.

[0181] According to the mux switch circuit MX-ARY of FIGS. 5 and 7, the data output channels DCH1, DCH2, and DCH3 are independent for R, G, and B, and the auxiliary output channel ACH is common to R, G, and B.

[0182] According to the max switch circuit MX-ARY of FIG. 20, the data output channels DCH1, DCH2, and DCH3 are independent for R, G, and B, and the auxiliary output channels ACH1, ACH2, and ACH3 are also independent for R, G, and B.

[0183] The first auxiliary output channel ACH1 is selectively connected only to the data lines DL1 and DL2 connected to the R pixels R1 and R2. The output of the first auxiliary output channel ACH1 is supplied to the second data line DL2 via the first auxiliary switch A11 and to the first data line DL1 via the second auxiliary switch A12.

[0184] The second auxiliary output channel ACH2 is selectively connected only to the data lines DL3 and DL4 connected to the G pixels G1 and G2. The output of the second auxiliary output channel ACH2 is supplied to the fourth data line DL4 via the third auxiliary switch A21 and to the third data line DL3 via the fourth auxiliary switch A22.

[0185] The third auxiliary output channel ACH3 is selectively connected only to the data lines DL5 and DL6 connected to the B pixels B1 and B2. The output of the third auxiliary output channel ACH3 is supplied to the sixth data line DL6 via the fifth auxiliary switch A31 and to the fifth data line DL5 via the sixth auxiliary switch A32.

[0186] From the above description, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the disclosure, but should be defined by the claims. [Explanation of symbols]

[0187] 100 Display Panel 110 Source Driver MX-ARY Max Switch Circuit 120 Gate Drivers

Claims

1. a display panel including: first pixels located in a first pixel row and connected to a first data line; and second pixels located in a second pixel row adjacent to the first pixels and connected to a second data line; a data output channel configured to output a first data voltage to be supplied to the first data line during a first time period of a refresh frame and to output a second data voltage to be supplied to the second data line during a second time period following the first time period of the refresh frame; and an auxiliary output channel configured to output a first pre-charge voltage to be supplied to the second data line during the first time period and to output a second pre-charge voltage to be supplied to the first data line during the second time period; a mux switch circuit configured to connect the data output channel to the first data line and the auxiliary output channel to the second data line during the first time, and to connect the data output channel to the second data line and the auxiliary output channel to the first data line during the second time.

2. The max switch circuit a first mux switch connected between the data output channel and the first data line, and turned on or off according to a first mux control signal; a first auxiliary switch connected between the auxiliary output channel and the second data line, and turned on or off according to the first MUX control signal; a second mux switch connected between the data output channel and the second data line, and turned on or off according to a second mux control signal; a second auxiliary switch connected between the auxiliary output channel and the first data line, and turned on or off in response to the second MAX control signal; During the first time period, the first MAX control signal is input at an ON level, and the second MAX control signal is input at an OFF level; 2. The display device of claim 1, wherein the first MAX control signal is input at an off level and the second MAX control signal is input at an on level during the second time period.

3. the first precharge voltage and the second precharge voltage vary over time within a preset precharge voltage range; 2. The display device of claim 1, wherein the precharge voltage range is greater than a minimum data voltage output from the source driver and less than a maximum data voltage output from the source driver.

4. In at least one skip frame following the refresh frame, the source driver floats a data output channel and outputs a line stabilization voltage to be supplied to the first data line and the second data line via the auxiliary output channel; 4. The display device according to claim 3, wherein the mux switch circuit simultaneously connects the first data line and the second data line to the auxiliary output channel.

5. the line stabilization voltage is fixed to a voltage within the precharge voltage range; The display device of claim 4 , wherein the potentials of the first data line and the second data line are maintained at the line stabilization voltage during the at least one skip frame.

6. the source driver floats the data output channel during an on-bias stress (OBS) period different from the first time and the second time in the refresh frame, and outputs an OBS voltage to be commonly supplied to the first data line and the second data line through the auxiliary output channel; the mux switch circuit simultaneously connects the first data line and the second data line to the auxiliary output channel during the OBS period; 2. The display device according to claim 1, wherein during the OBS period, the OBS voltage is applied to the source electrodes of the drive elements included in the first pixel and the second pixel in synchronization with the light-emitting elements included in the first pixel and the second pixel being initialized to an anode reset voltage.

7. In at least one skip frame following the refresh frame, the source driver floats a data output channel and outputs a line stabilization voltage to be supplied to the first data line and the second data line via the auxiliary output channel; 7. The display device of claim 6, wherein the mux switch circuit simultaneously connects the first data line and the second data line to the auxiliary output channel.

8. the line stabilization voltage is fixed to a voltage within a preset precharge voltage range; The display device of claim 7 , wherein the potentials of the first data line and the second data line are maintained at the line stabilizing voltage during the skip frame.

9. The data output channels are provided independently for red (R), green (G), and blue (B), 2. The display device according to claim 1, wherein the auxiliary output channel is provided in common for the R, G, and B colors.

10. The data output channels are provided independently for red (R), green (G), and blue (B), 2. The display device according to claim 1, wherein the auxiliary output channels are also provided independently for each of the R, G, and B colors.

11. A method for driving a display device including a display panel including a first pixel located in a first pixel row and connected to a first data line, and a second pixel located adjacent to the first pixel in a second pixel row and connected to a second data line, comprising: outputting, via a data output channel of the source driver, a first data voltage to be supplied to a first data line during a first time period of a refresh frame, and a second data voltage to be supplied to the second data line during a second time period following the first time period of the refresh frame; outputting a first precharge voltage to be supplied to the second data line during the first time period and a second precharge voltage to be supplied to the first data line during the second time period through an auxiliary output channel of the source driver; operating a mux switch circuit of the display panel to connect the data output channel to the first data line and the auxiliary output channel to the second data line during the first time period; and and operating the mux switch circuit to connect the data output channel to the second data line and the auxiliary output channel to the first data line for the second period of time.

12. the first precharge voltage and the second precharge voltage vary over time within a preset precharge voltage range; 12. The method of claim 11, wherein the precharge voltage range is greater than a minimum data voltage output from the source driver and less than a maximum data voltage output from the source driver.

13. In at least one skip frame following the refresh frame, floating a data output channel of the source driver; outputting a line stabilization voltage to be supplied to the first data line and the second data line via the auxiliary output channel of the source driver; and 13. The method of claim 12, further comprising: operating the mux switch circuit of the display panel to simultaneously connect the first data line and the second data line to the auxiliary output channel.

14. the line stabilization voltage is fixed to a voltage within the precharge voltage range; The method of claim 13 , wherein the potentials of the first data line and the second data line are maintained at the line stabilizing voltage during the at least one skip frame.

15. floating the data output channel of the source driver during an on-bias stress (OBS) period different from a first time and a second time in the refresh frame; outputting an OBS voltage to be commonly supplied to the first data line and the second data line through the auxiliary output channel of the source driver during an OBS period of the refresh frame; further comprising: operating the max switch circuit of the display panel during the OBS period to simultaneously connect the first data line and the second data line to the auxiliary output channel; 12. The display device driving method of claim 11, wherein the OBS voltage is applied to the source electrodes of the drive elements included in the first pixel and the second pixel in synchronization with the light-emitting elements included in the first pixel and the second pixel being initialized to an anode reset voltage during the OBS period.

16. In at least one skip frame following the refresh frame, floating the data output channel of the source driver; outputting a line stabilization voltage to be supplied to the first data line and the second data line via an auxiliary output channel of the source driver; and 16. The method of claim 15, further comprising: operating the mux switch circuit of the display panel to simultaneously connect the first data line and the second data line to the auxiliary output channel.

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