Storage device, disconnection detection method, and drive box

Abstract

Identify breaks in signal lines used to communicate with various specific elements other than the storage drive. [Solution] The controller accesses each of the multiple elements in the drive box through a signal line via each of the first and second expanders in the drive box having multiple storage drives, and determines the location of the break in the signal line if a break has occurred based on the access result pattern consisting of whether or not each of the multiple elements can be accessed via the first and second expanders.

Description

[Technical Field]

[0001] The present invention relates generally to open wire detection. [Background technology]

[0002] As a technique for identifying a disconnection in an electronic device, for example, there is a technique disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-308556 Summary of the Invention [Problem to be solved by the invention]

[0004] A storage device generally has a controller and storage drives, and the controller communicates with various specific elements other than the storage drives (for example, memories and microcontroller units in multiple units in the storage device) via signal lines (for example, a bus) for data collection and control. The signal lines extend to multiple units in the storage device. Since the signal lines are usually duplicated, even if one signal line is broken, communication can continue via another signal line. However, it is desirable to be able to identify the location of the break in the signal line. For example, if the location of the break can be identified, the break can be eliminated by replacing the unit with the break or by other methods.

[0005] According to the electronic device described in Patent Document 1, it is possible to identify a break in any of multiple harnesses, but it is not possible to identify the location of the break in the harness. Therefore, even if the electronic device disclosed in Patent Document 1 is applied to a storage device, it is not possible to identify the location of the break. [Means for solving the problem]

[0006] The controller accesses each of the multiple elements in the drive box through a signal line via each of first and second expanders in the drive box having multiple storage drives, and determines the location of the break in the signal line if a break has occurred based on an access result pattern consisting of whether or not each of the multiple elements can be accessed via the first and second expanders. [Effects of the Invention]

[0007] According to the present invention, it is possible to identify the location of a break in a signal line used for communication with various specific elements other than a storage drive. Problems, configurations, and effects other than those described above will become clear from the description of the following embodiments. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 10 is a block diagram of a drive box according to a comparative example. [Figure 2A] FIG. 2 is a diagram showing a block configuration of a storage device according to an embodiment and points (0a) to (0q) in I2C0. [Figure 2B] 1 is a diagram showing a block configuration of a storage device according to an embodiment and points (1a) to (1q) in an I2C1. [Figure 3A] FIG. 10 is a diagram showing the configuration of a disconnection diagnosis table for points (0a) to (0q) of I2C0. [Figure 3B] FIG. 10 is a diagram showing the configuration of a disconnection diagnosis table for the points (1a) to (1q) of I2C1. [Figure 4A] 10 is a flowchart of a part of a wire break diagnosis process. [Figure 4B] 10 is a flowchart of the remaining steps of the disconnection diagnosis process. [Figure 5] FIG. 1 is a schematic diagram illustrating a configuration of a storage device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] FIG. 5 is a schematic diagram of the configuration of a storage device according to the embodiment.

[0010] The storage device 550 includes a drive box 200 and a controller box 250 .

[0011] The drive box 200 has a housing 500. The height of the housing 500 may be 1U or 2U. A plurality of units excluding a controller and a drive 501 are provided inside the housing 500. The plurality of units includes an interface unit 201, a midplane (circuit board) 202, and a power supply unit 203.

[0012] A plurality of drives 501 are connected to one surface of the midplane 202. The drives 501 are arranged in the width direction. The drives 501 are storage drives (drives having storage media), and are typically hard disk drives (HDDs) or solid state drives (SSDs).

[0013] To the other surface of the midplane 202, duplicated interface units 201 (201A and 201B) and duplicated power supply units 203 (203A and 203B) are connected.

[0014] The controller box 250 has a housing 520. The height of the housing 520 may be 1U or 2U. The controller box 250 has duplicated controllers 251 (251A and 251B). The controllers 251A and 251B are connected to interface units 201A and 201B in the drive box 200, respectively. The controllers 251A and 251B are each supplied with power from the power supply units 203A and / or 203B via (or without) the interface units 201A and / or 201B.

[0015] The various elements in the storage device 550 (in the example shown in Figure 5, the interface unit 201, the power supply unit 203, and the controller 251) are duplicated, so that even if an abnormality occurs in one of the duplicated elements, processing can continue using the other element.

[0016] In the present embodiment, if a break occurs in the drive box 200, the location of the break can be identified. On the other hand, in the comparative example, as shown in FIG. 1, the location of the break in the drive box cannot be identified.

[0017] Specifically, in the comparative example, in a drive box 100, interface units 101A and 101B (ENC8 and ENC9) and power supply units 103A and 103B (PSU8 and PSU9) are connected to a midplane 102. ENC8 has an expander 111A (EXP8), a temperature sensor 112A (TS8), and an EEPROM 113A (ENCMem8). ENC9 has an expander 111B (EXP9), a temperature sensor 112B (TS9), and an EEPROM 113B (ENCMem9). The midplane 102 has EEPROMs 121A and 121B (MIDMem8 and MIDMem9). PSU8 has an EEPROM 131A (PSUMem8) and a microcontroller unit 132A (MCU8). The PSU9 includes an EEPROM 131B (PSUMem9) and a microcontroller unit 132B (MCU9).

[0018] The signal lines include I2C8 and I2C9. Each of I2C8 and I2C9 is a serial bus, and communication conforms to I2C (Inter-Integrated Circuit, or I-squared-C). For example, data (such as a serial number) can be obtained from one of the EEPROMs, or a fan (such as the fan in PSU8 or PSU9) can be controlled by the MCU 132. Each of I2C8 and I2C9 spans multiple units, such as ENC8, ENC9, midplane 102, PSU8, and PSU9. EXP8, EXP9, MIDMem8, PSUMem8, and MCU8 are connected to I2C8. EXP8, EXP9, MIDMem9, PSUMem9, and MCU9 are connected to I2C9. That is, either EXP8 or EXP9 can access MIDMem8, PSUMem8 or MCU8 via I2C8, or MIDMem9, PSUMem9 or MCU9 via I2C9.

[0019] In communication via I2C8 (or I2C9), it may happen that the controller cannot access PSU8 (or PSU9) via EXP8 (or EXP9). This may be caused by either an I2C8 line break (or I2C9 line break) within PSU8 or an I2C8 line break (or I2C9 line break) within the midplane 202. However, even if either is the cause, it is not possible to identify which is the cause (to isolate the location of the break). For example, as shown in FIG. 1, even if the cause is an I2C8 line break within the midplane 202, it is not possible to identify that the I2C8 line break is within the midplane 202.

[0020] This embodiment can solve the problem of the comparative example. In the following description, "EEPROM" is an example of a memory.

[0021] 2A and 2B are block diagrams of a storage device 550 according to an embodiment. (0a) to (0q) in FIG. 2A respectively represent I2C0 locations, and (1a) to (1q) in FIG. 2B respectively represent I2C1 locations. Note that the drive 501 is not shown in FIGS. 2A and 2B. This is because a signal line for communication according to I2C is not connected to the drive 501. In other words, the signal line is a line different from the line (not shown) through which data to be input / output to / from at least one of the multiple drives 501 travels.

[0022] As described above, the storage device 550 includes the drive box 200 and the controller box 250.

[0023] The drive box 200 has interface units 201A and 201B (ENC0 and ENC1), a midplane 202, and power supply units 203A and 203B (PSU0 and PSU1). ENC0 has an expander 211A (EXP0), a temperature sensor 212A (TS0), and an EEPROM 213A (ENCMem0). ENC1 has an expander 211B (EXP1), a temperature sensor 212B (TS1), and an EEPROM 213B (ENCMem1). Each of EXP0 and EXP1 may be a switch circuit. A plurality of drives 501 may be connected to each of EXP0 and EXP1 via data lines (not shown) through which I / O data flows. In response to an I / O request to CTL0 or CTL1, data I / O may be performed by CTL0 or CTL1 to the drive 501 via the data line via EXP0 or EXP1. The midplane 202 has an EEPROM 221A (MIDMem0) and an EEPROM 221B (MIDMem1). The PSU0 has an EEPROM (PSUMem0) and an MCU 232A (MCU0). The PSU1 has an EEPROM (PSUMem1) and an MCU 232B (MCU1).

[0024] The controller box 250 has controllers 251A and 251B (CTL0 and CTL1). CTL0 has a memory 252A (Mem0) and a CPU 253A (CPU0) connected to Mem0. CTL1 has a memory 252B (Mem1) and a CPU 253B (CPU1) connected to Mem1. CPU0 is connected to EXP0, and CPU1 is connected to EXP1. CTL0 (e.g., CPU0) and CTL1 (e.g., CPU1) can communicate with each other in the controller box 250.

[0025] I2C0 and I2C1 extend as duplicated signal lines to multiple units in the drive box 200. EXP0, ENCMem0, MIDMem0, PSUMem0, MCU0, EXP1, ENCMem1, MIDMem1, PSUMem1, and MCU1 are connected to I2C0 and I2C1, respectively. By executing a program stored in Mem0, CPU0 can access a desired specific element among multiple specific elements such as ENCMem0, MIDMem0, PSUMem0, MCU0, ENCMem1, MIDMem1, PSUMem1, and MCU1 via I2C0 or I2C1 via EXP0, and can perform a wire break diagnosis process, which will be described later. By executing the program stored in Mem1, CPU1 can access a desired specific element among multiple specific elements such as ENCMem0, MIDMem0, PSUMem0, MCU0, ENCMem1, MIDMem1, PSUMem1, and MCU1 via EXP1 through I2C0 or I2C1, and can perform the open circuit diagnosis process described below.

[0026] For example, CPU0 (or CPU1) receives data representing the temperature detected by TS0 (or TS1) via EXP0 (or EXP1), and transmits a control command for controlling a fan (not shown) in PSU0 (or PSU1) according to the temperature represented by the data to MCU0 (or MCU1) via EXP0 (or EXP1) and through I2C0 (or I2C1).

[0027] In this embodiment, multiple locations are defined for each of I2C0 and I2C1. Specifically, locations (0a) to (0q) are defined for I2C0 as shown in Fig. 2A, and locations (1a) to (1q) are defined for I2C1 as shown in Fig. 2B.

[0028] From another perspective, in order to be able to identify the location of a disconnection when a disconnection occurs in each of I2C0 and I2C1, each of I2C0 and I2C1 is connected to EXP0 or EXP1, each memory (MIDMem0 and MIDMem1) in the midplane 202, and each memory (ENCMem0, ENCMem1, PSUMem0 and PSUMem1) in ENC0, ENC1, PSU0 and PSU1 connected to the midplane 202. Each of CTL0 and CTL1 accesses each memory in ENC0, ENC1, midplane 202, PSU0 and PSU1 via I2C0 and I2C1 via EXP0 or EXP1, and from the access result pattern, which is a combination of the access results (accessibility) for each memory, it is determined whether a break has occurred in one or both of I2C0 and I2C1, and if a break has occurred, which part of I2C0 and / or I2C1 has the break. The part of the break that can be identified in this determination is either one of (0a) to (0q) or one of (1a) to (1q) based on the connection configuration of I2C0 and I2C1. (0a) to (0q) and (1a) to (1q) are as follows. (0a) is within ENC0 and between EXP0 and the branch to ENCMem0. (0b) is within ENC0 and between the branch to ENCMem0 and ENCMem0. (0c) is within ENC0 and between the branch to ENCMem0 and the boundary between ENC0 and the midplane 202. (0d) is within the midplane 202 and between the boundary between ENC0 and the midplane 202 and the branch to MIDMem0. (0e) is within the midplane 202 and between the branch to MIDMem0 and MIDMem0. (0f) is within the midplane 202 and between the branch to MIDMem0 and the branch to PSU0. ·(0g) is within the midplane 202 and between the branch to PSU0 and the boundary between the midplane 202 and PSU0. ·(0h) is within the midplane 202 and between the branch to PSU0 and the branch to PSU1. ·(0i) is within the midplane 202 and between the branch to PSU1 and the boundary between the midplane 202 and PSU1. ·(0j) is within the midplane 202 and between the branch to PSU1 and the branch to MIDMem1. ·(0k) is within the midplane 202 and between the branch to MIDMem1 and MIDMem1. ·(01) is within the midplane 202 and between the branch to MIDMem1 and the boundary between ENC1 and the midplane 202. ·(0m) is within ENC1 and between the branch to ENCMem1 and the boundary between ENC1 and midplane 202. (0n) is within ENC1 and between the branch to ENCMem1 and ENCMem1. ·(0o) is within ENC1 and between EXP1 and the branch to ENCMem1. ·(0p) is within PSU0 and between the boundary between the midplane 202 and PSU0 and PSUMem0. ·(0q) is within PSU1 and between the boundary between the midplane 202 and PSU1 and PSUMem1. (1a) is within ENC0 and between EXP0 and the branch to ENCMem0. (1b) is within ENC0 and between the branch to ENCMem0 and ENCMem0. (1c) is within ENC0 and between the branch to ENCMem0 and the boundary between ENC0 and the midplane 202. (1d) is within the midplane 202 and between the boundary between ENC0 and the midplane 202 and the branch to MIDMem0. (1e) is within the midplane 202 and between the branch to MIDMem0 and MIDMem0. (1f) is within the midplane 202 and between the branch to MIDMem0 and the branch to PSU0. (1g) is within the midplane 202 and between the branch to PSU0 and the boundary between the midplane 202 and PSU0. (1h) is within the midplane 202 and between the branch to PSU0 and the branch to ENC1. (1i) is within the midplane 202 and between the branch to MIDMem1 and the boundary between the midplane 202 and PSU1. (1j) is within the midplane 202 and between the branch to ENC1 and the branch to MIDMem1. ·(1k) is within the midplane 202 and between the branch to MIDMem1 and MIDMem1. (1l) is within the midplane 202 and between the branch to ENC1 and the boundary between ENC1 and the midplane 202. ·(1m) is within ENC1 and between the branch to ENCMem1 and the boundary between ENC1 and midplane 202. (1n) is within ENC1 and between the branch to ENCMem1 and ENCMem1. (1o) is within ENC1 and between EXP1 and the branch to ENCMem1. (1q) is within PSU0 and between the boundary between the midplane 202 and PSU0 and PSUMem0. ·(1q) is within PSU1 and between the boundary between the midplane 202 and PSU1 and PSUMem1.

[0029] For each of I2C0 and I2C1, another location may be defined instead of or in addition to at least one of the above-mentioned locations. For example, a location within PSU0 between the boundary between the midplane 202 and PSU0 and MCU0 may be newly defined for I2C0, and similarly, a location within PSU1 between the boundary between the midplane 202 and PSU1 and MCU1 may be newly defined for I2C1. In this way, a location may be defined for each of I2C0 and I2C1 depending on the element to which the signal line is connected.

[0030] To determine whether a break has occurred at any point, break diagnosis tables 350A and 350B shown in FIGS. 3A and 3B are stored in Mem0 and Mem1, respectively.

[0031] Disconnection diagnosis table 350A shows the access result pattern for each of points (0a) to (0q) in I2C0 when that point is the disconnection point. Disconnection diagnosis table 350B shows the access result pattern for each of points (1a) to (1q) in I2C1 when that point is the disconnection point. In both disconnection diagnosis tables 350A and 350B, the column "From EXP0" shows the results of access to ENCMem0, ENCMem1, MIDMem0, MIDMem1, PSUMem0, and PSUMem1 via EXP0, through I2C0 and I2C1, respectively. The column "From EXP1" shows the results of access to ENCMem0, ENCMem1, MIDMem0, MIDMem1, PSUMem0, and PSUMem1 via EXP1, through I2C0 and I2C1, respectively. For example, according to the access result pattern when (0q) is the disconnection location, access to PSUMem1 from CPU0 via EXP0 and I2C0 and access to PSUMem1 from CPU1 via EXP1 and I2C0 are both impossible, but other accesses are possible. Similarly, according to the access result pattern when (1q) is the disconnection location, access to PSUMem1 from CPU0 via EXP0 and I2C1 and access to PSUMem1 from CPU1 via EXP1 and I2C1 are both impossible, but other accesses are possible.

[0032] According to each of the disconnection diagnosis tables 350A and 350B, the replaceable parts are ENC0, ENC1, midplane 202, PSU0, and PSU1. That is, ENC0, ENC1, midplane 202, PSU0, and PSU1 are each replaceable units. By replacing the unit with the disconnection, it is possible to recover from the disconnection.

[0033] 4A and 4B are flowcharts of the wire break diagnosis process. The wire break diagnosis process may be performed when PSU0 or PSU1 is powered on, when the fan in PSU0 or PSU1 is controlled, or periodically.

[0034] CPU0 (CPU1) accesses each of ENCMem0, ENCMem1, MIDMem0, MIDMem1, PSUMem0, and PSUMem1 via EXP0 (EXP1) and I2C0 and I2C1 (S401), receives the access result (accessibility) for each access destination, and records it in Mem0 (Mem1) (S402). As a result, data indicating the access result via EXP0 is recorded in Mem0, and data indicating the access result via EXP1 is recorded in Mem1.

[0035] CPU0 and CPU1 share the access results via EXP0 and the access results via EXP1, and CPU0 (and / or CPU1) determines the access result pattern that matches the access results via EXP0 and the access results via EXP1 from the disconnection diagnosis tables 350A and 350B in Mem0 (Mem1) (S403).

[0036] If there is no matching access result pattern, that is, if all access results are accessible, there is no disconnection, so the process ends (S404A: No, S408: No, S412: No, S416: No).

[0037] If there are multiple matching access result patterns and the multiple access result patterns are disconnection points in different units (S404A: Yes), that is, the disconnection point cannot be uniquely identified and separated. Specifically, for example, there are the following cases. The access result patterns of points (0c) and (0d) are the same (see FIG. 3A). That is, points (0c) and (0d) span ENC0 and the midplane 202, so if point (0c) or point (0d) is the break point, it is not possible to determine whether the break point is in ENC0 or in the midplane 202. The same is true for points (1c) and (1d). That is, the access result patterns of points (1c) and (1d) are the same (see FIG. 3b). The access result patterns of points (0m) and (0l) are the same (see FIG. 3A). That is, points (0m) and (0l) span both ENC1 and the midplane 202, so if point (0m) or point (0l) is the disconnection point, it is not possible to determine whether the disconnection is in ENC1 or in the midplane 202. The same is true for points (1m) and (1l). That is, the access result patterns of points (1m) and (1l) are the same (see FIG. 3b). The access result patterns of points (0g) and (0p) are the same (see FIG. 3A). That is, points (0g) and (0p) span the midplane 202 and PSU0, so if point (0g) or point (0p) is the disconnection point, it is not possible to determine whether the disconnection is in the midplane 202 or in PSU0. The same is true for points (1g) and (1p). That is, the access result patterns of points (1g) and (1p) are the same (see FIG. 3b). The access result patterns of points (0i) and (0q) are the same (see FIG. 3A). That is, points (0i) and (0q) span the midplane 202 and PSU1, so if point (0i) or point (0q) is the disconnection point, it is not possible to determine whether the disconnection is in the midplane 202 or in the PSU1. The same is true for points (1i) and (1q). That is, the access result patterns of points (1i) and (1q) are the same (see FIG. 3b).

[0038] If the location of the break cannot be uniquely identified and isolated (S404A: Yes), CPU0 (and / or CPU1) determines whether it is the ENC or the midplane 202 that cannot be isolated, and specifically, whether the break location (access pattern) identified in S403 and corresponding to S404A: Yes is related to the ENC or the midplane 202 (S404B).

[0039] If the determination result of S404B is true (S404B: Yes), CPU0 (and / or CPU1) determines whether or not there is a break in both I2C0 and I2C1 (S405). If the determination result of S405 is true (S405: Yes), CPU0 (and / or CPU1) lights up the red LED (Light Emitting Diode) of each of the enclosure 500 and ENC0 (and / or ENC1) (S406). On the other hand, if the determination result of S405 is false (S405: No), there is no break in one of the signal lines and use of that signal line can continue, so CPU0 (and / or CPU1) blinks the red LED of each of the enclosure 500 and ENC0 (and / or ENC1) as an example of a weaker warning than the case of S405: Yes (S407). The red LEDs on both the housing 500 and the ENC lit or flashing are an example of a notification that the location of the disconnection could not be isolated (uniquely identified), in other words, an example of a method of suggesting that both units (for example, both ENC0 or 1 and the midplane) should be replaced because the location of the disconnection cannot be isolated. Also, flashing is an example of a method of notifying that it is preferable to replace both I2C0 and I2C1 as a preventative measure to prevent disconnection.

[0040] If the determination result of S404B is false (S404B: No), CPU0 (and / or CPU1) determines whether or not there is a break in both I2C0 and I2C1 (S404C). If the determination result of S404C is true (S404C: Yes), CPU0 (and / or CPU1) turns on the red LEDs of the midplane 202 and PSU0 (and / or PSU1) (S404D). On the other hand, if the determination result of S404C is false (S404C: No), there is no break in one of the signal lines and that signal line can continue to be used, so CPU0 (and / or CPU1) blinks the red LEDs of the midplane 202 and PSU0 (and / or PSU1) (S404E).

[0041] If the disconnection location corresponding to the matching access result pattern is ENC0 (and / or ENC1) (S408: Yes), CPU0 (and / or CPU1) determines whether the disconnection location is in both I2C0 and I2C1 (S409). If the determination result in S409 is true (S409: Yes), CPU0 (and / or CPU1) turns on the red LED of ENC0 (and / or ENC1) that has the disconnection location, that is, the replacement part (S410). If the determination result in S409 is false (S409: No), CPU0 (and / or CPU1) blinks the red LED of ENC0 (and / or ENC1) that has the disconnection location (S411).

[0042] If the disconnection location corresponding to the matching access result pattern is in the midplane 202 (S412: Yes), CPU0 (and / or CPU1) determines whether the disconnection location is in both I2C0 and I2C1 (S413). If the determination result in S413 is true (S413: Yes), CPU0 (and / or CPU1) turns on the red LED of the midplane 202 that has the disconnection location (S414). If the determination result in S413 is false (S413: No), CPU0 (and / or CPU1) blinks the red LED of the midplane 202 that has the disconnection location (S415).

[0043] If the disconnection location corresponding to the matching access result pattern is PSU0 (and / or PSU1) (S416: Yes), CPU0 (and / or CPU1) determines whether the disconnection location is in both I2C0 and I2C1 (S417). If the determination result of S417 is true (S417: Yes), CPU0 (and / or CPU1) turns on the red LED of PSU0 (and / or PSU1) that has the disconnection location (S418). If the determination result of S417 is false (S417: No), CPU0 (and / or CPU1) blinks the red LED of PSU0 (and / or PSU1) that has the disconnection location (S419).

[0044] According to this embodiment, each of CPU0 and CPU1 accesses each of ENCMem0, ENCMem1, MIDMem0, MIDMem1, PSUMem0, and PSUMem1 (an example of a plurality of elements) via EXP0 and EXP1 and through I2C0 and I2C1, respectively (for example, by sending a signal for disconnection diagnosis or by sending a dummy signal), and based on the access result pattern consisting of whether each access is possible or not, if there is a disconnection in at least one of I2C0 and I2C1, it is determined whether there is a disconnection in any of a plurality of predefined locations. Specifically, in this embodiment, CTL0 (and / or CTL1) stores disconnection diagnosis tables 350A and 350B (an example of disconnection diagnosis data) that represent access result patterns for each of multiple predefined locations for I2C0 or I2C1 when the location is a disconnection location. If an access result pattern in the disconnection diagnosis table 350A or 350B matches an access result pattern consisting of whether or not access is possible to ENCMem0, ENCMem1, MIDMem0, MIDMem1, PSUMem0, and PSUMem1 via EXP0 and EXP1, CTL0 (and / or CTL1) determines the location corresponding to the matching access result pattern as the disconnection location. In this way, it is possible to identify the disconnection location in a signal line used for communication with various specific elements other than the drive 501. Since the disconnection location is isolated and does not span multiple units, it is possible to replace only the unit with the disconnection location. Note that signal lines do not necessarily need to be duplicated, as in the case of I2C0 and I2C1. Furthermore, instead of or in addition to I2C0 and I2C1, the signal lines may be signal lines for communication conforming to a standard other than I2C.

[0045] According to this embodiment, CTL0 (and / or CTL1) indicates the unit that has the determined broken location, for example, by lighting or blinking the LED of that unit, or by displaying information representing that unit on a display device (e.g., an information processing terminal). This makes it possible to identify which of multiple units needs to be replaced to restore I2C0 or I2C1. Furthermore, the manner in which the unit with the broken location is indicated differs depending on whether the broken location is in one or both of I2C0 and I2C1 (e.g., lighting an LED or blinking an LED). This allows the user to decide when to replace the unit depending on the manner in which the indication is given.

[0046] Furthermore, according to this embodiment, in the disconnection diagnosis tables 350A and 350B (an example of disconnection diagnosis data), for each of one or more sets of locations among the multiple locations, the access result pattern of two locations (an example of two or more locations) belonging to the location set is the same, and the location set spans the midplane 202 and ENC0 or ENC1, or the midplane 202 and PSU0 or PSU1. If the access result pattern matching the access result in S403 (the access result via EXP0 and the access result via EXP1) is the access result pattern of a location belonging to one of the location sets, CTL0 (and / or CTL1) indicates the two units spanned by the location set (for example, by lighting or blinking an LED for each of the two units). The method of indicating the units may be any method; for example, instead of or in addition to lighting or blinking an LED for the unit, information indicating the two units spanned by the location set may be displayed on the display of a computer (for example, a personal computer) that can communicate with the storage device. In this way, according to this embodiment, it is possible to identify that it is not possible to isolate the broken part, and output according to the determination result that it is not possible to isolate the broken part can be given to, for example, a maintenance worker, etc., thereby enabling appropriate replacement to be carried out quickly.

[0047] In this embodiment, the multiple location sets include a first location set spanning the midplane 202 and ENC0 or ENC1, and a second location set spanning the midplane 202 and PSU0 or PSU1. If the matching access result pattern is an access result pattern of a location belonging to one of the location sets (e.g., S404A: Yes), CTL0 (and / or CTL1) determines whether the location set is the first location set or the second location set (e.g., S404B), and notifies the two units spanned by the determined location set.

[0048] As described above, the present invention is not limited to the above-described embodiment, and includes various modifications and equivalent configurations within the spirit and scope of the appended claims. The above-described embodiment has been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to one having all of the described configurations.

[0049] For example, instead of or in addition to the red LEDs that each of the chassis 500, ENC0, ENC1, midplane 202, PSU0 and PSU1 has, LEDs of other colors may be installed and turned on or blink, and instead of or in addition to turning on and / or blinking LEDs, CPU0 (and / or CPU1) may display information indicating the location of the broken wire on an information processing terminal (e.g., a personal computer) not shown that is connected to the storage device 550.

[0050] Furthermore, for example, a CPU that integrates CPU0 and CPU1 can be used instead of CPU0 and CPU1. Specifically, the controllers do not necessarily have to be duplicated as in CTL0 and CTL1; a single controller 251 may be used instead of CTL0 and CTL1. That is, a single controller 251 may be provided in the controller box 250. EXP0 and EXP1 are connected to the controller 251, and the controller 251 may access ENCMem0, ENCMem1, MIDMem0, MIDMem1, PSUMem0, and PSUMem1 via I2C0 and I2C1, respectively, via EXP0 and EXP1. Also, the controller box 250 may not be necessary. In that case, the controller 251 (CTL0 and CTL1) may be housed in the housing 500 of the drive box 200, and the drive box 200 may be provided as a storage device 550. Furthermore, the controller, which is an example of a computer, may be a remote computer. [Explanation of symbols]

[0051] 550: storage device, 200: drive box, 201: interface unit, 203: power supply unit, 251: controller

Claims

1. A controller and a drive box are provided, the drive box includes a plurality of storage drives, a plurality of units, and a signal line; The plurality of units include: a midplane, which is a circuit board to which the plurality of storage drives are connected; a first interface unit and a second interface unit that are duplicated interface units connected to the midplane; first and second power supply units that are duplicated power supply units connected to the midplane; Including, the first interface unit has a first expander connected to the controller; the second interface unit includes a second expander connected to the controller; the signal line is a line different from a line through which data to be input / output to at least one of the plurality of storage drives is routed, one end of the signal line is connected to the first expander, the other end of the signal line is connected to the second expander, the signal lines are connected to a plurality of elements within the first and second interface units, the midplane, and the first and second units; The controller accessing each of the plurality of elements through the signal lines via each of the first and second expanders; determining a location of a disconnection in the signal line, if any, based on an access result pattern consisting of whether or not access is possible to each of the plurality of elements via the first and second expanders; Storage device.

2. The controller stores wire break diagnosis data, the disconnection diagnosis data represents, for each of a plurality of predetermined locations on the signal line, an access result pattern when the location is a disconnection location; When an access result pattern matching an access result pattern consisting of whether or not access is possible to each of the plurality of elements via the first and second expanders is found in the disconnection diagnosis data, the controller determines that a location corresponding to the matching access result pattern is a disconnection location. The storage device according to claim 1 .

3. the controller notifies the unit having the determined disconnection location among the plurality of units; The storage device according to claim 1 .

4. the signal lines are first and second signal lines that are duplicated signal lines, The controller accessing each of the plurality of elements through each of the first and second signal lines via each of the first and second expanders; determining the location of a disconnection in the first and second signal lines, if any, based on a combination of whether or not the first signal line is accessible to each of the plurality of elements via the first and second expanders and whether or not the second signal line is accessible to each of the plurality of elements via the first and second expanders; The storage device according to claim 1 .

5. the controller changes the manner in which it notifies the unit having the disconnection depending on whether the disconnection is in both or one of the first and second signal lines in the unit where the disconnection is determined to be present; The storage device according to claim 4.

6. In the disconnection diagnosis data, for one or each of a plurality of sets of locations among the plurality of locations, The access result patterns of two or more locations belonging to the location set are the same, the location set straddling the midplane and the first or second interface unit, or straddling the midplane and the first or second power supply unit, When the matching access result pattern is an access result pattern of a location belonging to any one of the location sets, the controller notifies the two units that the location set spans. The storage device according to claim 1 .

7. In the disconnection diagnosis data, the plurality of sets of locations include a first set of locations that spans the midplane and the first or second interface unit, and a second set of locations that spans the midplane and the first or second power supply unit, When the matching access result pattern is an access result pattern of a location belonging to any of the location sets, the controller determines whether the location set is the first location set or the second location set, and notifies the two units that the determined location set spans. The storage device according to claim 6.

8. accessing each of a plurality of elements in a drive box having a plurality of storage drives through a signal line via each of first and second expanders in the drive box; determining a location of a disconnection in the signal line, if any, based on an access result pattern consisting of whether or not access is possible to each of the plurality of elements via the first and second expanders; This is done by computer, the drive box includes a plurality of units in addition to the signal line and the plurality of storage drives; The plurality of units include: a midplane, which is a circuit board to which the plurality of storage drives are connected; a first interface unit and a second interface unit that are duplicated interface units connected to the midplane; first and second power supply units that are duplicated power supply units connected to the midplane; Including, the first interface unit includes a first expander connected to the computer; the second interface unit includes a second expander connected to the computer; the signal line is a line different from a line through which data to be input / output to at least one of the plurality of storage drives is routed, one end of the signal line is connected to the first expander, the other end of the signal line is connected to the second expander, the signal lines are connected to the elements in the first and second interface units, in the midplane, and in the first and second units; Disconnection diagnosis method.

9. Multiple storage drives and Multiple units and Signal line and Including, The plurality of units include: a midplane, which is a circuit board to which the plurality of storage drives are connected; a first interface unit and a second interface unit that are duplicated interface units connected to the midplane; first and second power supply units that are duplicated power supply units connected to the midplane; Including, the first interface unit includes a first expander; the second interface unit includes a second expander; the signal line is a line different from a line through which data to be input / output to at least one of the plurality of storage drives is routed, one end of the signal line is connected to the first expander, the other end of the signal line is connected to the second expander, the signal lines are connected to a plurality of elements within the first and second interface units, the midplane, and the first and second units; Drive box.

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