Photoelectric assembly, light source pool, photoelectric switching device, and control method for photoelectric assembly

Abstract

The present invention provides an optoelectric assembly for improving efficiency, a control method thereof, a light source pool, and an optoelectric switching device. [Solution] The photoelectric assembly includes a voltage conversion circuit, a photoelectric semiconductor device, a photoelectric detection circuit, and a controller. The voltage conversion circuit provides a bias voltage to the photoelectric semiconductor device and adjusts the output optical power output by the photoelectric semiconductor device by changing the bias voltage. Within the range of target optical power, the differential resistance Rdiff of the photoelectric semiconductor device satisfies 0.1Ω ≤ Rdiff ≤ 50Ω, where the differential resistance is the ratio of the voltage fluctuation to the current fluctuation corresponding to the voltage fluctuation. The photoelectric detection circuit detects the output optical power output by the photoelectric semiconductor device and outputs a detection signal to the controller. The controller determines a control signal based on the detection signal and outputs a control signal to the voltage conversion circuit that is used to adjust the bias voltage.

Description

Technical Field

[0001] This application relates to the field of optical communications, and more particularly, to optoelectronic assemblies, light source pools, optoelectronic switching devices, and control methods for optoelectronic assemblies.

Background Art

[0002] The optical power output by an optoelectronic semiconductor device may be too large or too small. For example, the output optical power may decrease due to aging of the device or an increase in ambient temperature. In order to stabilize the optical power output by the optoelectronic semiconductor device within a preset range, a drive circuit may be added to the optoelectronic semiconductor device to form an optoelectronic assembly, so that the optoelectronic assembly can adjust the optical power output by the optoelectronic semiconductor device to complete an automatic power control (APC) function.

[0003] However, current optoelectronic assemblies adjust the optical power output by an optoelectronic semiconductor device by using an adjustable current source, resulting in low efficiency.

Summary of the Invention

[0004] Embodiments of this application provide an optoelectronic assembly, a light source pool, an optoelectronic switching device, and a control method for an optoelectronic assembly to improve the efficiency of the optoelectronic assembly.

[0005] To achieve the above object, the following technical solutions are used in embodiments of this application.

[0006] According to a first embodiment, an optoelectronic assembly is provided, comprising a voltage conversion circuit, an optoelectronic semiconductor device, a photoelectric detection circuit, and a controller. The voltage conversion circuit is configured to supply a bias voltage to the optoelectronic semiconductor device and to adjust the output optical power output by the optoelectronic semiconductor device by changing the bias voltage, where the differential resistance Rdiff of the optoelectronic semiconductor device within a target optical power range satisfies 0.1Ω ≤ Rdiff ≤ 50Ω, and the differential resistance is the ratio of the voltage fluctuation to the current fluctuation corresponding to the voltage fluctuation. The photoelectric detection circuit is configured to detect the output optical power output by the optoelectronic semiconductor device and to output a detection signal to the controller. The controller is configured to determine a control signal based on the detection signal and to output the control signal to the voltage conversion circuit, where the control signal is used to adjust the bias voltage. The target optical power is typically determined based on the optical power budget range of the optical links in the system in which the optoelectronic assembly, light source pool, or optoelectronic switching device is located, to ensure that the system can be in a normal operating state where the bit error rate is smaller than a certain index. In this application, the optoelectronic assembly includes a load link and a feedback link. The load link acts as the load for the voltage conversion circuit and includes the voltage conversion circuit and optoelectronic semiconductor devices. The feedback link includes a photoelectric detection circuit and a controller. The controller does not need to receive current sampling information from the load link. The bias voltage can be adjusted based on the output signal of the photoelectric detection circuit.

[0007] In the photoelectric assembly provided in this embodiment of the present application, a voltage conversion circuit provides a bias voltage to a photoelectric semiconductor device to adjust the output optical power output by the photoelectric semiconductor device. A photoelectric detection circuit receives light output by the photoelectric semiconductor device, detects the output optical power output by the photoelectric semiconductor device, and outputs a detection signal to a controller. Based on the detection signal, the controller may determine a control signal to be used to adjust the bias voltage and send the control signal to the voltage conversion circuit. There is no need for another detection circuit to be coupled between the voltage conversion circuit and the photoelectric semiconductor device, and no additional power output by the voltage conversion circuit is consumed; most of the power output by the voltage conversion circuit is converted into output optical power output by the photoelectric semiconductor device. Thus, this can improve the efficiency of the photoelectric assembly.

[0008] The differential resistance Rdiff of an optoelectronic semiconductor device within the target optical power range satisfies the requirement of 0.1Ω ≤ Rdiff ≤ 50Ω, mainly for the following reasons:

[0009] When the differential resistance Rdiff of an optoelectronic semiconductor device is excessively large within the target optical power range, the optoelectronic semiconductor device needs to be able to accept large bias voltage fluctuations to generate small current fluctuations in its equivalent current. In other words, when the bias voltage input to the optoelectronic semiconductor device has large fluctuations, the fluctuations in the equivalent current flowing through the optoelectronic semiconductor device are small, and correspondingly, the fluctuations in carrier concentration are small, which is insufficient to effectively change the output optical power output by the optoelectronic semiconductor device. For example, suppose the differential resistance Rdiff = 100Ω. A voltage fluctuation of 100mV is required to generate a current fluctuation of 1mA, which usually corresponds to a state before the turn-on threshold of the optoelectronic semiconductor device is reached and is not suitable for normal operation of the automatic power control (APC) loop. Even if the optoelectronic semiconductor device is in a good lathing state above the turn-on threshold at this time, a voltage fluctuation of 1V is required to achieve a current fluctuation of 10mA for such an optoelectronic semiconductor device. In practical applications, it is difficult to implement due to limitations in the voltage output capability and voltage conversion efficiency of the voltage conversion circuit.

[0010] When the differential resistance Rdiff of an optoelectronic semiconductor device within the target optical power range is excessively small, small bias voltage fluctuations input to the optoelectronic semiconductor device can cause large current fluctuations in the optoelectronic semiconductor device, and correspondingly, carrier concentration fluctuations become excessively large. The output optical power output by the optoelectronic semiconductor device changes significantly, and the optical power may fall into an excessively large or excessively small range, or it may fall within the roll-off operation of the optoelectronic semiconductor device (i.e., the output optical power decreases with increasing injection current). Therefore, it is difficult to apply to APC. For example, assume that the differential resistance of the optoelectronic semiconductor device within the target optical power range is 0.01Ω. When the input voltage fluctuation is 1mV, the current fluctuation of the current flowing through the optoelectronic semiconductor device is 100mA. This is unacceptable for feedback adjustment of the APC loop.

[0011] The optoelectronic semiconductor device in the embodiments of this application is a light-emitting device made from a semiconductor material, and includes, for example, a light source (e.g., a laser diode (LD), a laser, or a lidar) or a semiconductor optical amplifier (SOA).

[0012] The bias adjustment circuit in this embodiment of the present application is an adjustable voltage source or an adjustable current source configured to adjust the bias voltage or bias current of a circuit, for example, an optoelectronic semiconductor device.

[0013] In this embodiment of the present application, the voltage conversion circuit replaces the adjustable current source to provide a bias voltage to the optoelectronic semiconductor device and controls the bias voltage output by the voltage conversion circuit by collecting only the output optical power output by the optoelectronic assembly as feedback, rather than collecting the current of the load link. Thus, linear control is implemented and the control logic is simple. Compared with conventional techniques in which an adjustable current source provides the drive current to the optoelectronic semiconductor device, in this technique the voltage conversion circuit provides the bias voltage to the optoelectronic semiconductor device. This can improve conversion efficiency. This is because the solution provided in this embodiment of the present application can be applied to application scenarios involving high power and high drive current. For example, the optoelectronic assembly can be used as an externally modulated light source (i.e., a light source isolated from an optical modulator) or as an optical amplifier. The optoelectronic assembly, light source pool, or optoelectronic switching device needs to output light to multiple silicon photonic links, has high output optical power up to about 100 mW, requires high carrier density, i.e., requires high drive current injection. However, a tunable current source provides the drive current to the optoelectronic semiconductor device. As a result, a larger drive current leads to a larger additional voltage drop generated by the current sampling circuit and a lower conversion efficiency for the entire optoelectronic assembly. A voltage conversion circuit (e.g., a direct current-to-direct current (DC-DC) converter) provides the bias voltage to the optoelectronic semiconductor device. Essentially, voltage conversion is implemented through the charging and discharging of high-frequency switches, inductors, capacitors, transformers, etc. Therefore, no large additional voltage drop occurs, and the conversion efficiency can reach 90% or even 93%. In addition, based on a tunable current source, there is no operational amplifier required in the optoelectronic assembly. Therefore, this can reduce the cost of the optoelectronic assembly, improve integration, and facilitate miniaturization.

[0014] In possible implementations, the photoelectric assembly may be an externally modulated light source (i.e., a light source isolated from the optical modulator) or an optical amplifier. The photoelectric assembly can be used as a device requiring high power and high drive current, such as an externally modulated light source or an optical amplifier.

[0015] In a possible implementation, the optoelectronic semiconductor device is the light source, and the resistance of the light source is less than or equal to 60Ω within the range of the target optical power.

[0016] In a possible implementation, the optoelectronic semiconductor device is an optical amplifier, and the resistance of the optical amplifier is less than or equal to 60Ω within the range of the target optical power.

[0017] When the resistance of a photoelectronic semiconductor device is low, it indicates that the device has turned on well and entered a good lathing state. In this case, the current-voltage relationship curve of the photoelectronic semiconductor device changes smoothly and has clear linear characteristics, the differential resistance of the photoelectronic semiconductor device is also moderate, and a change in the bias voltage of the photoelectronic semiconductor device can cause a linear change in the corresponding current of the photoelectronic semiconductor device, and subsequently a linear change in the carrier concentration of the photoelectronic semiconductor device. This makes it possible to change the output optical power output by the photoelectronic semiconductor device linearly and effectively. Conversely, when the resistance of a photoelectronic semiconductor device is high, it indicates that the photoelectronic semiconductor device is close to a threshold state. In this case, a change in the bias voltage of the photoelectronic semiconductor device can cause a nonlinear change in the corresponding current of the photoelectronic semiconductor device, and subsequently a nonlinear change in the carrier concentration of the photoelectronic semiconductor device. It is difficult to change the output optical power output by the photoelectronic semiconductor device linearly and effectively.

[0018] In possible implementations, the voltage conversion circuit is the sole bias adjustment circuit for the optoelectronic semiconductor device. Specifically, the output optical power of the optoelectronic semiconductor device is controlled solely by the bias voltage output by the voltage conversion circuit, and no adjustable current source or similar is required to provide the drive current.

[0019] In possible implementations, the bit width of the digital signal processed by the controller is greater than or equal to 6 bits. The controller can be a micro-control unit (MCU), a field-programmable gate array (FPGA), or similar.

[0020] In this application, the bit width of the digital signal processed by the controller is required to be at least 6 bits, and the voltage fluctuation corresponding to the minimum weight bit satisfies the requirement for fine-tuning the bias voltage output by the voltage conversion circuit, thereby enabling precise control of the bias voltage output by the voltage conversion circuit. If the digital signal processed by the controller has only 4 bits, for example, if the controller's internal reference voltage of 2.5V corresponds to the maximum value of a 4-bit binary number, the voltage fluctuation corresponding to the minimum weight bit of the control signal Z output by the controller is 2.5V / 2^4 ≈ 156mV. This voltage adjustment accuracy is unacceptable. If the bit width of the digital signal processed by the controller is 6 bits, for example, if the controller's internal reference voltage of 2.5V corresponds to the maximum value of a 6-bit binary number, the voltage fluctuation corresponding to the minimum weight bit of the control signal Z output by the controller is 2.5V / 2^6 ≈ 39mV. Even if the accuracy of the bias voltage output by the voltage conversion circuit is the same as the voltage fluctuation of 39mV corresponding to the minimum weight bit of the control signal Z, if the differential resistance Rdiff of the optoelectronic semiconductor device within the target optical power range is 10Ω and the bias voltage fluctuation output by the voltage conversion circuit is 39mV, the current fluctuation of the current flowing through the optoelectronic semiconductor device is 3.9mA. This may be considered a case where the equivalent adjustment current step is large in APC loop control, but this is also acceptable. Furthermore, if the bit width of the digital signal processed by the controller is 8 bits, for example, if the controller's internal reference voltage of 2.5V corresponds to the maximum value of an 8-bit binary number, the voltage fluctuation corresponding to the minimum weight bit of the control signal Z output by the controller is 2.5V / 2^8 ≈ 9.8mV. Even if the accuracy of the bias voltage output by the voltage conversion circuit is the same as the voltage fluctuation of 9.8mV corresponding to the minimum weight bit of the control signal Z, if the differential resistance Rdiff of the optoelectronic semiconductor device within the target optical power range is 10Ω and the bias voltage fluctuation output by the voltage conversion circuit is 9.8mV, the current fluctuation of the current flowing through the optoelectronic semiconductor device is 0.98mA.This can be considered acceptable when the equivalent adjustment current step is small in APC loop control.

[0021] In possible implementations, the controller is further configured to enable or disable the voltage conversion circuit.

[0022] When the controller is initialized, the voltage converter circuit is initially disabled, and then, after the controller outputs a control signal to the voltage converter circuit, the voltage converter circuit is enabled. Alternatively, during the controller initialization process, the voltage converter circuit may be disabled based on a fixed high / low level as an input, or through another logic gate circuit. Alternatively, during the controller initialization process, the voltage converter circuit may be enabled through a soft-start circuit to turn on the optoelectronic semiconductor device. In this way, it is possible to prevent the optoelectronic semiconductor device from burning out due to unstable control signals during the initialization process and excessively high bias voltages output by the voltage converter circuit. Otherwise, if the voltage converter circuit is enabled before the controller outputs a control signal, the bias voltage output by the voltage converter circuit is uncontrolled and therefore can become excessively high. As a result, the optoelectronic semiconductor device in the load link will burn out. In addition, these methods can be combined.

[0023] In possible implementations, the controller is configured to acquire load link information and determine a control signal based on the load link information and the detection signal, where the load link information includes the value of the bias voltage.

[0024] If the load link information indicates the actual value of the bias voltage, the deviation between the theoretical and actual values ​​of the bias voltage caused by device parameter deviations and fluctuations in the feedback network can be eliminated, providing the controller with a more accurate input for obtaining the control signal Z. For example, the controller may calculate the control signal Z according to the formula Z = A*X + B*Y + C, or obtain the control signal Z through a table lookup, where A is the tuning rule corresponding to the load link information X, B is the tuning rule corresponding to the backlight sampling voltage Y, and C is a fitting constant. The values ​​of A, B, and C can be obtained by looking up a pre-calibrated or pre-fitted table in the controller, or through real-time calculation. Furthermore, A, B, and C in the pre-calibrated or pre-fitted table in the controller can be corrected based on the actual accurate input.

[0025] In possible implementations, the optoelectronic assembly further includes a temperature control drive circuit and a temperature control circuit. The temperature control drive circuit is configured to supply power to the temperature control circuit, and the temperature control circuit is configured to perform temperature control on the optoelectronic semiconductor device.

[0026] Temperature control may include, for example, cooling or heating, so that the photoelectric semiconductor device operates at a preset operating temperature to increase the output optical power of the photoelectric semiconductor device or extend its service life. For example, the temperature control circuit may be a thermoelectric cooler (TEC).

[0027] In possible implementations, the power supply voltage input to the temperature-controlled drive circuit ranges from 2V to 18V.

[0028] The value of the power supply voltage is optimized and set based on the voltage, current, cooling capacity, heating capacity, cooling power consumption, heating power consumption, etc. of the temperature control drive circuit and the temperature control circuit, and the power energy efficiency of the temperature control circuit can be improved. For example, the power supply voltage may be 3.3V, 5V, 12V, etc., and the deviation accuracy of the power supply voltage may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 10%. Still further, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0029] In a possible implementation, the power supply voltage input by voltage conversion circuit ranges from 1.8V to 18V.

[0030] The value of the power supply voltage is optimized and set based on the input-output voltage change efficiency curve of the voltage conversion circuit, and the voltage conversion efficiency of the voltage conversion circuit can be improved as much as possible. For example, the power supply voltage may be 3.3V, 5V, 12V, etc., and the deviation accuracy of the power supply voltage may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 10%. Still further, the deviation accuracy of the power supply voltage may be less than or equal to5%.

[0031] In a possible implementation, the power supply voltage input by the controller ranges from 1.5V to 6V. The value of the power supply voltage is optimized and set based on the voltage, current, and power consumption of devices such as the controller, analog-to-digital converter, and digital-to-analog converter, etc., which can guarantee the normal operation of the devices and improve the system stability. For example, the power supply voltage may range from 1.8V to 3.6V. Furthermore, the power supply voltage may be 3.3V, and the deviation accuracy of the power supply voltage may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage may be less than or equal to 10%. Still further, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0032] The power supply voltages connected to the voltage conversion circuit, temperature control drive circuit, and controller are determined based on the load characteristics of the coupled devices. This can improve power energy efficiency, reduce power consumption, and improve system stability.

[0033] In a possible implementation, if the detection signal is less than a first threshold, the control signal indicates that the bias voltage should be increased. The detection signal corresponds to the output optical power output by the optoelectronic semiconductor device. A detection signal less than the first threshold indicates that the output optical power output by the optoelectronic semiconductor device is excessively low. Therefore, the control signal indicates that the voltage conversion circuit should increase the bias voltage to increase the output optical power output by the optoelectronic semiconductor device.

[0034] In possible implementations, if the detection signal is greater than a second threshold, the control signal indicates that the bias voltage should be reduced. The detection signal corresponds to the output optical power output by the optoelectronic semiconductor device. A detection signal greater than the second threshold indicates an excessively high output optical power output by the optoelectronic semiconductor device. Therefore, the control signal indicates that the voltage conversion circuit should reduce the bias voltage to reduce the output optical power output by the optoelectronic semiconductor device. decrease To make someone do it.

[0035] In possible implementations, the voltage conversion circuit includes a first voltage conversion circuit and a second voltage conversion circuit. The optoelectronic semiconductor device includes a first optoelectronic semiconductor device and a second optoelectronic semiconductor device. The photoelectric detection circuit includes a first photoelectric detection circuit and a second photoelectric detection circuit. The first photoelectric detection circuit is configured to detect the output optical power output by the first optoelectronic semiconductor device and to output a first detection signal to the controller. The second photoelectric detection circuit is configured to detect the output optical power output by the second optoelectronic semiconductor device and to output a second detection signal to the controller. The controller is configured to determine a first control signal based on the first detection signal and send the first control signal to the first voltage conversion circuit, the first control signal being used to adjust the bias voltage supplied to the first optoelectronic semiconductor device, and to determine a second control signal based on the second detection signal and send the second control signal to the second voltage conversion circuit, the second control signal being used to adjust the bias voltage supplied to the second optoelectronic semiconductor device.

[0036] The photoelectric assembly provided in this embodiment of the present application is not limited to supporting two photoelectric semiconductor devices for outputting light, but may further include more photoelectric semiconductor devices to output multiple paths of light.

[0037] In possible implementations, the optoelectronic assembly further includes a digital-to-analog converter. The controller is configured to sequentially send a first control signal and a second control signal to the digital-to-analog converter. The digital-to-analog converter is configured to perform a digital-to-analog conversion with respect to the first control signal and output the signal obtained through the digital-to-analog conversion to a first voltage conversion circuit, and to perform a digital-to-analog conversion with respect to the second control signal and output the signal obtained through the digital-to-analog conversion to a second voltage conversion circuit.

[0038] This implementation can improve the design flexibility of the optoelectronic assembly, further reduce resource requirements for the controller's digital-to-analog conversion interface, reduce the number of digital-to-analog converters, lower the cost of the optoelectronic assembly, improve integration, and facilitate miniaturization. For example, when a digital-to-analog converter converts two digital signals to one analog signal, it is possible to reduce the number of digital-to-analog converters by 50%. When a digital-to-analog converter can convert more digital signals to one analog signal, it is possible to reduce the number of digital-to-analog converters by even more.

[0039] In possible implementations, the bit width of the digital-to-analog converter is greater than or equal to 6 bits. For example, the bit width of the digital-to-analog converter matches the bit width of the digital signal processed by the controller.

[0040] In a possible implementation, the optoelectronic semiconductor device includes a first optoelectronic semiconductor device and a second optoelectronic semiconductor device. The photoelectric detection circuit also includes a first photoelectric detection circuit and a second photoelectric detection circuit. The first photoelectric detection circuit is configured to detect the output optical power output by the first optoelectronic semiconductor device and to output a first detection signal to a controller. The second photoelectric detection circuit is configured to detect the output optical power output by the second optoelectronic semiconductor device and to output a second detection signal to a controller. The controller is configured to determine a control signal based on the first and second detection signals and to send the control signal to a voltage conversion circuit, which is used to adjust the bias voltage supplied to the first optoelectronic semiconductor device and the bias voltage supplied to the second optoelectronic semiconductor device.

[0041] In a possible implementation, if the first detection signal is smaller than the second detection signal, and the first detection signal is smaller than a first threshold, the control signal indicates that the bias voltage should be increased.

[0042] In a possible implementation, if the first detection signal is smaller than the second detection signal, and the second detection signal is larger than the second threshold, the control signal indicates that the bias voltage should be reduced.

[0043] In possible implementations, the optoelectronic assembly further includes an analog-to-digital converter. The analog-to-digital converter performs an analog-to-digital conversion on a first detection signal and an analog-to-digital conversion on a second detection signal, and the first detection signal and the second obtained through the analog-to-digital conversion. 2 The detection signal is configured to be continuously output to the controller.

[0044] This implementation can improve the design flexibility of optoelectronic assemblies, further reduce resource requirements for analog-to-digital conversion interfaces, reduce the number of analog-to-digital converters, lower the cost of optoelectronic assemblies, improve integration, and facilitate miniaturization. For example, when an analog-to-digital converter converts two analog signals to one digital signal, it is possible to reduce the size of the analog-to-digital converter by 50%. When an analog-to-digital converter can convert more analog signals to one digital signal, it is possible to reduce the size of the analog-to-digital converter by more.

[0045] In possible implementations, the bit width of the analog-to-digital converter is greater than or equal to 6 bits. For example, the bit width of the analog-to-digital converter matches the bit width of the digital signal processed by the controller.

[0046] In possible implementations, the optoelectronic assembly further includes a feedback network. The feedback network is configured to increase or decrease the voltage range of the control signal.

[0047] A feedback network can further improve the accuracy of control signals, and thus the accuracy of the bias voltage output by the voltage conversion circuit, which in turn can improve the resolution of the analog-to-digital conversion interface in the DAC or controller.

[0048] In a possible implementation, the feedback network includes a first resistor, a second resistor, and a third resistor. The second terminal of the first resistor is grounded. The first terminal of the first resistor, the second terminal of the second resistor, and the first terminal of the third resistor are coupled to the feedback terminal of the voltage conversion circuit. The first terminal of the second resistor is coupled to the output terminal of the voltage conversion circuit. The second terminal of the third resistor is coupled to the output terminal of the controller. The output terminal of the controller is configured to output a control signal. The feedback terminal of the voltage conversion circuit is configured to receive a control signal that increases or decreases its voltage range.

[0049] A feedback network based on a resistor-voltage divider network implements linear increase or decrease of a control signal based on a feedback control signal, meeting the requirements for the range of signals input by the voltage conversion circuit and improving the accuracy of the control signal. In addition, the feedback network is simple in design and compact in structure. This facilitates miniaturization of the entire optoelectronic assembly.

[0050] In possible implementations, the voltage conversion circuit is a DC-DC conversion circuit.

[0051] In this application, voltage conversion is implemented in a DC-DC conversion circuit through the charging and discharging of high-frequency switches, inductors, capacitors, transformers, etc. Therefore, no large additional voltage drop occurs, and the conversion efficiency can reach 90% or even 93%.

[0052] According to a second embodiment, a light source pool is provided, which includes at least one photoelectric assembly in either the first embodiment or an implementation of the first embodiment.

[0053] The solution provided in this embodiment of the present application can be applied to application scenarios involving high power and high drive current. The light source pool needs to output light to multiple silicon photonic links, has a high output optical power of up to about 100 mW, requires a high carrier density, i.e., requires a high drive current to be injected. In the case of a 10 W light source pool, power consumption of approximately 3 W can be reduced by using the optoelectronic assembly in this application. This can greatly improve the thermal design, reliability, and external power supply pressure of the product, greatly extend the product's lifespan, miniaturize the product, and further improve the overall competitiveness of the product.

[0054] According to a third aspect, an optoelectric switching device is provided, comprising at least one of a photoelectric assembly in either the first aspect or an implementation of the first aspect, or a light source pool in the second aspect, an optical modulator, and a switching chip. The photoelectric assembly or light source pool is configured to output light. The switching chip is configured to control the optical modulator to modulate the light output by the photoelectric assembly or light source pool.

[0055] The solution provided in this embodiment of the present application can be applied to application scenarios involving high power and high drive current. The optoelectronic switching device requires at least one of a photoelectric assembly or a light source pool to output light to multiple silicon photonic links of the optical modulator in the optoelectronic switching device, has a high output optical power of up to about 100 mW, requires a high carrier density, i.e., requires a high drive current to be injected. This can implement miniaturization of the optoelectronic switching device, improve drive efficiency, and reduce the overall power consumption of the optoelectronic switching device.

[0056] In possible implementations, the photoelectric switching device further includes a first controller which determines a board control signal based on whether the value of the optical power output by the photoelectric switching device meets a requirement, and outputs the board control signal to the controller of the photoelectric assembly to request adjustment of the output optical power output by the photoelectric assembly or the light source pool, or outputs the board control signal to the controller of the light source pool to request adjustment of the output optical power output by the light source pool, thereby increasing or decreasing the optical power output by the photoelectric switching device, or decreasing the output optical power to zero.

[0057] According to a fourth aspect, a control method for a photoelectric assembly is provided. The method may be applied to a photoelectric assembly in either the first aspect or an implementation of the first aspect. The method includes the steps of: receiving a detection signal from a photoelectric detection circuit in the photoelectric assembly, the detection signal indicating the output optical power output by a photoelectric semiconductor device in the photoelectric assembly; determining a control signal based on the detection signal and sending the control signal to a voltage conversion circuit in the photoelectric assembly, the control signal being used to adjust the bias voltage.

[0058] In possible implementations, the method further includes the steps of disabling the voltage converter circuit and enabling it by outputting a pre-set control signal to the voltage converter circuit.

[0059] In possible implementations, if the detection signal is less than a first threshold, the control signal indicates that the bias voltage should be increased.

[0060] In possible implementations, if the detection signal is greater than a second threshold, the control signal indicates that the bias voltage should be reduced.

[0061] In a possible implementation, the method further includes the step of obtaining load link information, where the load link information includes a bias voltage value. The step of determining a control signal based on a detection signal includes the step of determining a control signal based on the load link information and the detection signal.

[0062] In a possible implementation, the method further includes the step of sequentially sending a first control signal and a second control signal to a digital-to-analog converter in an optoelectronic assembly, wherein the first control signal is used to adjust the bias voltage supplied to a first optoelectronic semiconductor device, and the second control signal is used to adjust the bias voltage supplied to a second optoelectronic semiconductor device.

[0063] In a possible implementation, the method further includes the steps of determining a control signal based on a first detection signal and a second detection signal, and sending the control signal to a voltage conversion circuit, wherein the control signal is used to adjust the bias voltage supplied to a first optoelectronic semiconductor device and the bias voltage supplied to a second optoelectronic semiconductor device, the first detection signal indicating the output optical power output by the first optoelectronic semiconductor device, and the second detection signal indicating the output optical power output by the second optoelectronic semiconductor device.

[0064] In a possible implementation, if the first detection signal is smaller than the second detection signal, and the first detection signal is smaller than a first threshold, the control signal indicates that the bias voltage should be increased.

[0065] In a possible implementation, if the first detection signal is smaller than the second detection signal, and the second detection signal is larger than the second threshold, the control signal indicates that the bias voltage should be reduced.

[0066] For the technical effects of the second to fourth embodiments, please refer to the technical effects of the first embodiment or any one of the implementations of the first embodiment. [Brief explanation of the drawing]

[0067] [Figure 1] This is a schematic diagram of the structure of an optoelectronic switching device according to one embodiment of this application. [Figure 2] Figure 1 is a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 3] Figure 2 is a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 4] Figure 3 is a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 5] Figure 4 shows a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 6] Figure 5 shows a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 7A] This is a schematic diagram of a coupling configuration between a power supply, a voltage conversion circuit, and an optoelectronic semiconductor device according to one embodiment of this application. [Figure 7B] This is a schematic diagram of a coupling configuration between a power supply, a voltage conversion circuit, and an optoelectronic semiconductor device according to one embodiment of this application. [Figure 7C] This is a schematic diagram of a coupling configuration between a power supply, a voltage conversion circuit, and an optoelectronic semiconductor device according to one embodiment of this application. [Figure 7D] This is a schematic diagram of a coupling configuration between a power supply, a voltage conversion circuit, and an optoelectronic semiconductor device according to one embodiment of this application. [Figure 7E] This is a schematic diagram of a coupling configuration between a power supply, a voltage conversion circuit, and an optoelectronic semiconductor device according to one embodiment of this application. [Figure 7F] This is a schematic diagram of a coupling configuration between a power supply, a voltage conversion circuit, and an optoelectronic semiconductor device according to one embodiment of this application. [Figure 8A] This is a schematic diagram of a coupling configuration between an ADC and a controller according to one embodiment of the present application. [Figure 8B] This is a schematic diagram of a coupling configuration between an ADC and a controller according to one embodiment of the present application. [Figure 8C]This is a schematic diagram of a coupling configuration between an ADC and a controller according to one embodiment of the present application. [Figure 8D] This is a schematic diagram of a coupling configuration between an ADC and a controller according to one embodiment of the present application. [Figure 9A] This is a schematic diagram of a coupling configuration between a DAC and a controller according to one embodiment of the present application. [Figure 9B] This is a schematic diagram of a coupling configuration between a DAC and a controller according to one embodiment of the present application. [Figure 9C] This is a schematic diagram of a coupling configuration between a DAC and a controller according to one embodiment of the present application. [Figure 9D] This is a schematic diagram of a coupling configuration between a DAC and a controller according to one embodiment of the present application. [Figure 10] Figure 6 shows a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 11] Figure 7 shows a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 12] Figure 8 shows a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 13] Figure 9 shows a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 14] Figure 10 shows a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 15] Figure 11 shows a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 16] Figure 12 shows a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 17] This is a schematic diagram of a coupling configuration between a power supply, a voltage conversion circuit, a temperature control drive circuit, and a controller according to one embodiment of this application. [Figure 18] Figure 13 is a schematic diagram of the structure of an optoelectronic assembly according to one embodiment of this application. [Figure 19] This is a schematic flowchart of a control method for an optoelectronic assembly according to one embodiment of the present application. [Figure 20] This is a schematic flowchart of another control method for an optoelectric assembly according to one embodiment of the present application. [Modes for carrying out the invention]

[0068] With the rapid development of technologies such as cloud computing, big data, 5th generation (5G) communications, and autonomous driving, higher requirements such as miniaturization, high bandwidth, and low power consumption have also been proposed for optoelectronic modules or optoelectronic components used in optical communication networks. However, high bandwidth requires increased optical power, increased drive current, and increased power consumption for optoelectronic semiconductor devices used in optoelectronic modules or optoelectronic components. For example, Table 1 shows the drive current and power consumption of optoelectronic semiconductor devices in different application scenarios. This has adverse effects on designs that require miniaturization and low power consumption, and presents an unprecedented challenge to the design of drive circuits for optoelectronic semiconductor devices.

[0069] [Table 1]

[0070] The optoelectronic semiconductor devices in the embodiments of this application are light-emitting devices made from semiconductor materials, and include, for example, laser diodes (LDs), lasers, semiconductor optical amplifiers (SOAs), lidar, or other devices.

[0071] Existing optoelectronic assemblies adjust the optical power output by optoelectronic semiconductor devices by using a drive current (sometimes called a bias current) output by a tunable current source. This solution has the following drawbacks:

[0072] 1. Low driving efficiency. The optoelectronic assembly has to convert the input voltage and then output the converted voltage to an adjustable current source, which reduces its conversion efficiency. The driving current output by the adjustable current source needs to be detected by a current sampling circuit. This generates unnecessary voltage drops, further reducing the conversion efficiency. Therefore, the overall conversion efficiency of the optoelectronic assembly is approximately 66.5%.

[0073] 2. There are multiple feedback loops, multiple input parameters for adjustment, and complex rules. When adjusting the bias current output by an adjustable current source, the photoelectric assembly depends on multiple input parameters, including, for example, the current value of the drive current and the optical power output by the photoelectric semiconductor device. As a result, simple linear control cannot be implemented, and the control rules are complex.

[0074] 3. The system requires additional current sampling circuitry, resulting in high hardware costs. Because current sampling circuitry needs to be added to detect the drive current, sometimes operational amplifiers need to be added to amplify the sampled value of the drive current to improve the resolution of detecting the drive current. This is detrimental to system miniaturization and cost reduction.

[0075] 4. To precisely control the drive current, the voltage or current fluctuations corresponding to the minimum weight bit for digital-to-analog or analog-to-digital conversion must reach a specific number of bits for the digital-to-analog or analog-to-digital conversion in the optoelectric assembly so as to satisfy the requirements for precise control. Typically, this needs to reach about 10 bits.

[0076] 5. The power-up sequences of different components in the system and the protection of optoelectronic semiconductor devices are not considered. As a result, optoelectronic semiconductor devices are easily burned out due to excessively high bias voltages.

[0077] Accordingly, embodiments of this application provide a photoelectric assembly, a light source pool including a photoelectric assembly, a photoelectric switching device including at least one of a photoelectric assembly or a light source pool, and a control method for a photoelectric assembly. A voltage conversion circuit in the photoelectric assembly provides a bias voltage to the photoelectric semiconductor device in the photoelectric assembly to adjust the output optical power output by the photoelectric semiconductor device. A photoelectric detection circuit in the photoelectric assembly receives light output by the photoelectric semiconductor device, detects the output optical power output by the photoelectric semiconductor device, and outputs a detection signal to a controller in the photoelectric assembly. Based on the detection signal, the controller may determine a control signal to be used to adjust the bias voltage and send the control signal to the voltage conversion circuit. The differential resistance Rdiff of the photoelectric semiconductor device within the range of target optical power satisfies 0.1Ω ≤ Rdiff ≤ 50Ω, where the differential resistance is the ratio of the voltage fluctuation to the current fluctuation corresponding to the voltage fluctuation. For example, the differential resistance Rdiff of the photoelectric semiconductor device within the range of target optical power satisfies 0.1Ω ≤ Rdiff ≤ 20Ω. In another example, the differential resistance Rdiff of an optoelectronic semiconductor device within the target optical power range satisfies either 1Ω ≤ Rdiff ≤ 15Ω, 2Ω ≤ Rdiff ≤ 10Ω, 2Ω ≤ Rdiff ≤ 8Ω, or 2Ω ≤ Rdiff ≤ 6Ω.

[0078] The voltage conversion circuit replaces the adjustable current source, providing a bias voltage to the optoelectronic semiconductor device and controlling the bias voltage output by the voltage conversion circuit by collecting only the output optical power output by the optoelectronic assembly as feedback, rather than collecting the current of the load link. Therefore, linear control is implemented and the control logic is simple. In addition, since the current sampling circuit for collecting the current of the load link is canceled, there is only the optoelectronic semiconductor device in the load link, there is no voltage drop caused by the current sampling circuit, and the power conversion efficiency of the power output by the voltage conversion circuit can reach 90% or even 93%. Compared to a solution in which an adjustable current source provides the drive current, this solution in this application improves the conversion efficiency by (90-66.5) / 66.5=35%. There is no operational amplifier. Therefore, this can reduce the cost of the optoelectronic assembly, improve integration, and facilitate miniaturization.

[0079] The optoelectronic assemblies, light source pools, optoelectronic switching devices, and control methods for optoelectronic assemblies provided in embodiments of this application may be applied to application scenarios requiring large drive currents, such as 10G passive optical networks (XGPON), 50G passive optical networks (50G PON), SOA, or autonomous driving lidar.

[0080] As shown in Figure 1, the optical-electric switching device 11 provided in this embodiment of the present application includes at least one of an optical-electric assembly 111 or a light source pool 112, a plurality of optical power splitters 113, a plurality of optical modulators 114, a plurality of wavelength division multiplexers 115, a multi-channel optical fiber array 116, a first optical-electric switching chip 117, and a controller 118.

[0081] Note that in the first implementation, the optoelectric switching device 11 may include a light source pool 112, an optical power splitter 113, an optical modulator 114, and a multi-channel optical fiber array 116. Alternatively, in the second implementation, the optoelectric switching device 11 may include an optoelectric assembly 111, an optical power splitter 113, an optical modulator 114, and a multi-channel optical fiber array 116. Alternatively, in the third implementation, the optoelectric switching device 11 may include a light source pool 112, an optical power splitter 113, an optical modulator 114, and a wavelength division multiplexer 115. Alternatively, the three implementations can be freely combined.

[0082] The light source pool 112 may include at least one photoelectric assembly 111. Each photoelectric assembly 111 is configured to output light of one wavelength (e.g., laser or fluorescence), and the wavelengths of the output light output by different photoelectric assemblies 111 may be the same or different. An optical power splitter 113 may split one path of output light output by one photoelectric assembly 111 based on optical power, outputting multiple paths of output light to multiple optical modulators 114. A first optic-electric switching chip 117 controls each of the optical modulators 114 to modulate one path of output light from the optical power splitter 113 to output a single optical signal. Each wavelength division multiplexer 115 is configured to multiplex multiple optical signals of different wavelengths and transmit the multiple optical signals to the receiving end 12 in a coarse wavelength division multiplexing (CWDM) manner through a single optical fiber, thereby reducing the amount of optical fiber. The multiplexing described herein may also be medium wavelength division multiplexing (MWDM), lane wavelength division multiplexing (LWDM), dense wavelength division multiplexing (DWDM), etc., based on different wavelength combinations of laser devices, or a combination of the above different wavelength division multiplexing methods, depending on the actual application. The optical fiber array 116 is configured to combine and output optical signals of multiple wavelengths through a multi-fiber push-on (MPO) connector and transmit the multiple optical signals to the receiving end 12 through a parallel single-mode optical fiber (PSM). The second opticoelectric switching chip 121 at the receiving end 12 demodulates the optical signals received by the high-speed optical module 122.For example, if each channel of the optical modulator 114 is 100 Gbps, the high-speed optical module 122 corresponding to the PSM solution may be a 400G DR4 optical module. Thus, the high-speed optical module 122 corresponding to the CWDM solution corresponding to each 100G channel may be a 400G FR4 optical module. For example, if each channel of the optical modulator 114 is 50 Gbps, and each of the optical fiber arrays 116 is connected to the eight silicon photonic links of the optical modulator 114, the high-speed optical module 122 corresponding to the LWDM solution may be a 400G LR8 optical module. In addition, if the receiving end 12 is also located on another optoelectronic switching device similar to the optoelectronic switching device 11, the high-speed optical module 122 may also be a silicon photonic receiving end on the corresponding optical modulator and is configured to receive and restore multiple optical signals.

[0083] The controller 118 determines a board control signal based on whether the value of the optical power output by the photoelectric switching device 11 satisfies the requirements, and outputs the board control signal to the controller of the photoelectric assembly 111 to request adjustment of the output optical power output by the photoelectric assembly 111, or outputs the board control signal to the controller of the light source pool 112 to request adjustment of the output optical power output by the light source pool 112, thereby increasing or decreasing the optical power output by the photoelectric switching device 11, or decreasing the output optical power to 0.

[0084] Typically, the power supply or power interface in the photoelectric assembly 111 or the light source pool 112 is located within the photoelectric switching device 11, and more specifically, on the board of the photoelectric switching device 11. More specifically, a compact parallel multipath drive with high driving efficiency on the light source pool 112 or the photoelectric assembly 111 is located on the board of the photoelectric switching device 11.

[0085] In copackaged optics, nearpackaged optics, or onboard optics communication systems of the optoelectronic switching device 11, the light source pool 112 or optoelectronic assembly 111 may be configured as a pluggable module to provide an external high-power light source for the copackaged optics, nearpackaged optics, or onboard optics communication system. The copackaged optics, nearpackaged optics, or onboard optics communication system can implement optical communications of 1.6 Tbps, 3.2 Tbps, ..., 25.6 Tbps, 21.2 Tbps, or even higher capacities. The optoelectronic assembly 111, light source pool 112, or optoelectronic switching device 11 is configured to output light to multiple silicon photonic links and has a high output optical power of up to approximately 100 mW. Improved driving efficiency can reduce the overall power consumption of the optoelectronic switching device 11. This is crucial for the power consumption and heat dissipation design of the entire copackaged optics, nearpackaged optics, or onboard optics communication system. In the case of a 10W light source pool, power consumption can be reduced by approximately 3W by using the photoelectric assembly in this application. This can significantly improve the thermal design, reliability, and external power supply pressure of the product, greatly extend its service life, and further enhance the overall competitiveness of the product. In addition, the compact structure of the drive circuit of the light source pool 112 or the photoelectric assembly 111 improves the panel utilization of the photoelectric switching device 11, helps to miniaturize the device and improve the communication capacity of the system, and further enhances the overall competitiveness of the product.

[0086] The following describes possible structures of the photoelectric assembly provided in the embodiments of this application.

[0087] As shown in Figures 2 and 3, the optoelectronic assembly includes a voltage conversion circuit 21, an optoelectronic semiconductor device 22, a photoelectric detection circuit 23, and a controller 24. Optionally, as shown in Figure 3, the optoelectronic assembly may further include a feedback network 31. When the controller 24 does not have an analog-to-digital conversion interface or a digital-to-analog conversion interface, or when the resources of the analog-to-digital conversion interface and digital-to-analog conversion interface of the controller 24 are insufficient, the optoelectronic assembly may further include an analog-to-digital converter (ADC) 32 and a digital-to-analog converter (DAC) 33. When the controller 24 has an analog-to-digital conversion interface (in other words, an analog signal can be directly input) and a digital-to-analog conversion interface (in other words, an analog signal can be directly output), or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are sufficient, the ADC32 may be the analog-to-digital conversion interface in the controller 24, and the DAC33 may be the digital-to-analog conversion interface in the controller 24.

[0088] Power supply 25 may supply power to the entire optoelectric assembly through M (M≧1) power interfaces, and the power supply voltages of the M power interfaces may be the same or different. A common optoelectric assembly is used as an example, and the power supply voltage of power supply 25 may be a fixed voltage of 3.3V.

[0089] The voltage conversion circuit 21 may be an adjustable voltage source, a DC-DC converter, a DC-DC converter chip, or a device or component with an adjustable voltage output. The input power supply voltage may be converted through DC-DC conversion to W (W≧1) bias voltages, which are output to the optoelectronic semiconductor device 22 to drive it. In addition, the bias voltages output by the voltage conversion circuit 21 may be individually adjusted based on W control signals Z output by the controller 24 to adjust the output optical power output by the optoelectronic semiconductor device 22. The voltage conversion circuit 21 may be used as a unique bias adjustment circuit for the optoelectronic semiconductor device 22. Specifically, the output optical power of the optoelectronic semiconductor device 22 is controlled solely by the bias voltages output by the voltage conversion circuit 21. Each of the bias voltages output by the voltage conversion circuit 21 must be greater than 1.0V, and the power supply voltage Vcc of the power supply 25 must be greater than 1.3V to turn on the optoelectronic semiconductor device 22 for normal operation. Each of the bias voltages output by the voltage conversion circuit 21 must be less than 0.9*Vcc in order to ensure that the voltage conversion circuit 21 has high energy conversion efficiency when performing voltage conversion.

[0090] A bias adjustment circuit is an adjustable voltage source or adjustable current source configured to adjust the bias voltage or bias current of a circuit, such as an optoelectronic semiconductor device.

[0091] Compared to conventional techniques in which a tunable current source provides the drive current to the optoelectronic semiconductor device 22, this technique provides the bias voltage to the optoelectronic semiconductor device 22 via a voltage conversion circuit 21. This can improve conversion efficiency. This is because the solution provided in this embodiment of the present application can be applied to application scenarios involving high power and high drive current. Optoelectronic assemblies, light source pools, or optoelectronic switching devices need to output light to multiple silicon photonic links, have high output optical power up to about 100 mW, require high carrier density, i.e., require high drive current injection. However, it is possible to know from an analysis of providing the drive current to the optoelectronic semiconductor device that larger drive currents result in larger additional voltage drops generated by the current sampling circuit and lower conversion efficiency for the entire optoelectronic assembly. The voltage conversion circuit (e.g., DC-DC converter) 21 provides the bias voltage to the optoelectronic semiconductor device 22. Essentially, voltage conversion is implemented through charging and discharging of high-frequency switches, inductors, capacitors, transformers, etc. Therefore, no large additional voltage drop is generated, and the conversion efficiency can reach 90% or even 93%.

[0092] As shown in Figure 4, the optoelectronic semiconductor device 22 may be a light source (e.g., an LED, laser, or lidar). In this case, a bias voltage is used to drive the optoelectronic semiconductor device 22 to emit light. Alternatively, as shown in Figure 5, the optoelectronic semiconductor device 22 may be an SOA. In this case, the optoelectronic semiconductor device 22 is further coupled to a light source 51. The light source 51 may be an external light source or a light source in the photoelectric assembly. A bias voltage is used to drive the optoelectronic semiconductor device 22 to amplify the light output by the light source 51. The optoelectronic semiconductor devices 22 are arranged within P load links, and the quantity of optoelectronic semiconductor devices 22 may be N (N≧1). The output light of the optoelectronic semiconductor device 22 consists of two parts. The first part is the output light of the entire photoelectric assembly (e.g., laser and fluorescence), and the second part (usually a backlight) is output to a photoelectric detection circuit 23 for detecting the optical power of the optoelectronic semiconductor device 22. To ensure that the APC loop operates within its normal range and that the current-voltage relationship curve of the optoelectronic semiconductor device 22 exhibits smooth linearity, the differential resistance Rdiff of the optoelectronic semiconductor device 22 within the target optical power range cannot be excessively small or large. Within the target optical power range, the differential resistance Rdiff of the optoelectronic semiconductor device 22 satisfies 0.1Ω ≤ Rdiff ≤ 50Ω.

[0093] In this embodiment of the present application, the target optical power is typically determined based on the optical power budget range of the optical link in the system in which the photoelectric assembly, light source pool, or photoelectric switching device is located, to ensure that the system can be in a normal operating state in which the bit error rate is smaller than a certain index. For example, four 100 GbpsTo support the normal operation of a silicon photonic modulation link, the target optical power of an optoelectronic assembly, light source pool, or optoelectronic switching device may range from 50mW to 150mW. Furthermore, the target optical power of an optoelectronic assembly, light source pool, or optoelectronic switching device may range from 64mW to 120mW. Furthermore, the target optical power of an optoelectronic assembly, light source pool, or optoelectronic switching device may range from 64mW to 100mW. This reduces the system's power consumption when the optical power budget of the system's optical link is guaranteed. In another example, eight 100 Gbps To support the normal operation of a silicon photonic modulation link, the target optical power of the optoelectric assembly, light source pool, or optoelectric switching device may range from 150mW to 300mW. Furthermore, the target optical power of the optoelectric assembly, light source pool, or optoelectric switching device may range from 150mW to 250mW.

[0094] In this embodiment of the present application, the differential resistance Rdiff of the optoelectronic semiconductor device within the range of the target optical power is dV / dI, where dI is the current fluctuation generated by the current flowing through the optoelectronic semiconductor device when the input voltage generates a voltage fluctuation dV. That is, the differential resistance Rdiff is the ratio of the voltage fluctuation dV to the current fluctuation dI corresponding to the voltage fluctuation dV.

[0095] In this embodiment of the present application, it should be noted that the controller 24 performs APC to keep the output laser light power stable within a specific range. The APC loop is formed by the voltage conversion circuit 21, the optoelectronic semiconductor device 22, the photoelectric detection circuit 23, and the controller 24, the controller 24 being able to detect the output light power output by the optoelectronic semiconductor device 22 through the photoelectric detection circuit 23. Furthermore, the bias voltage output to the optoelectronic semiconductor device 22 by the voltage conversion circuit 21 is controlled to adjust the output light power output by the optoelectronic semiconductor device 22, i.e., the controller 24 can implement APC on the optoelectronic semiconductor device 22. The APC loop operating within a normal range means that the bias voltage output by the voltage conversion circuit 21 is appropriate so that the optoelectronic semiconductor device 22 can normally emit light, and the output light power output by the optoelectronic semiconductor device 22 is within the range of the target light power. The load link includes a device coupled to the voltage output terminal of the voltage conversion circuit 21, for example, the optoelectronic semiconductor device 22.

[0096] When the differential resistance Rdiff of the photoelectronic semiconductor device 22 is excessively large within the target optical power range, the photoelectronic semiconductor device 22 needs to be able to receive large bias voltage fluctuations to generate small current fluctuations in its equivalent current. In other words, when the bias voltage input to the photoelectronic semiconductor device 22 has large fluctuations, the fluctuations in the equivalent current flowing through the photoelectronic semiconductor device 22 are small, and correspondingly, the carrier concentration fluctuations are small, which is insufficient to effectively adjust the output optical power output by the photoelectronic semiconductor device 22. For example, assume that the differential resistance Rdiff = 100Ω. A voltage fluctuation of 100mV is required to generate a current fluctuation of 1mA, which usually corresponds to a state before the turn-on threshold of the photoelectronic semiconductor device 22 is reached and is not possible to use for the normal operation of the APC loop. Even when the photoelectronic semiconductor device 22 is in a racing state above the turn-on threshold at this time, a voltage fluctuation of 1V is required to achieve a current fluctuation of 10mA. In actual application processes, it is difficult to apply this optoelectronic semiconductor device due to limitations in the voltage output capability and voltage conversion efficiency of the voltage conversion circuit 21.

[0097] When the differential resistance Rdiff of the photoelectronic semiconductor device 22 within the target optical power range is excessively small, small bias voltage fluctuations input to the photoelectronic semiconductor device 22 can cause large current fluctuations in the photoelectronic semiconductor device 22, and correspondingly, carrier concentration fluctuations become excessively large. The output optical power output by the photoelectronic semiconductor device 22 changes significantly, and within this range, the optical power may fall into an excessively large or excessively small range, or it may fall within the roll-off operating range of the photoelectronic semiconductor device 22 (i.e., the output optical power decreases with increasing injection current). Therefore, it is difficult to apply to APC. For example, assume that the differential resistance of the photoelectronic semiconductor device 22 within the target optical power range is 0.01Ω. When the input voltage fluctuation is 1mV, the current fluctuation of the current flowing through the photoelectronic semiconductor device 22 is 100mA. This is unacceptable for feedback adjustment of the APC loop.

[0098] Therefore, in this embodiment of the present application, the differential resistance Rdiff of the photoelectric semiconductor device 22 within the target optical power range satisfies the condition 0.1Ω ≤ Rdiff ≤ 50Ω. For example, the differential resistance of the photoelectric semiconductor device 22 within the target optical power range is 0.2Ω. When the bias voltage output by the voltage conversion circuit 21 fluctuates by 1mV, the current fluctuation flowing through the photoelectric semiconductor device 22 is 5mA. In the APC loop adjustment process, this is applicable when the equivalent adjustment current step is large. For example, the differential resistance of the photoelectric semiconductor device 22 within the target optical power range is 2Ω. When the bias voltage output by the voltage conversion circuit 21 fluctuates by 1mV, the current fluctuation flowing through the photoelectric semiconductor device 22 is 0.5mA. In the APC loop adjustment process, this is applicable when the equivalent adjustment current step is small. For example, the differential resistance of the photoelectric semiconductor device 22 within the target optical power range is 20Ω. When the bias voltage output by the voltage conversion circuit 21 fluctuates by 1 mV, the current flowing through the optoelectronic semiconductor device 22 fluctuates by 0.05 mA. In APC loop adjustment processing, this is applicable when the equivalent adjustment current step is fine.

[0099] In addition, when the APC loop operates within its normal range, the resistance of the optoelectronic semiconductor device 22 within the target optical power range is less than or equal to 60Ω. When the resistance of the optoelectronic semiconductor device 22 is small, it indicates that the optoelectronic semiconductor device 22 is well turned on and enters a good lathing state. In this case, the current-voltage relationship curve of the optoelectronic semiconductor device 22 changes smoothly and has clear linear characteristics, and the differential resistance of the optoelectronic semiconductor device 22 is also moderate, and a change in the bias voltage of the optoelectronic semiconductor device 22 can cause a linear change in the corresponding current of the optoelectronic semiconductor device 22, and subsequently a linear change in the carrier concentration of the optoelectronic semiconductor device 22. This allows the output optical power output by the optoelectronic semiconductor device 22 to change linearly. Conversely, when the resistance of the optoelectronic semiconductor device 22 is large, it indicates that the optoelectronic semiconductor device 22 is close to a threshold state, and the current-voltage relationship curve in a state close to the threshold changes abruptly and has unclear linear characteristics. In this case, a change in the bias voltage of the optoelectronic semiconductor device 22 can cause a nonlinear change in the corresponding current of the optoelectronic semiconductor device 22, which in turn can cause a nonlinear change in the carrier concentration of the optoelectronic semiconductor device 22. Linearly changing the output optical power produced by the optoelectronic semiconductor device 22 is difficult. The optoelectronic semiconductor device 22 is not suitable for operation within a specified range.

[0100] In addition, when the APC loop operates within its normal range, the output optical power output by the photoelectric semiconductor device 22 may be linearly varied to ensure that the voltage steps and corresponding current steps acquired during APC loop adjustment change uniformly, causing a linear change in the carrier concentration of the photoelectric semiconductor device 22. The selected differential resistance of the photoelectric semiconductor device 22 within the target optical power range may be uniform, i.e., the differential resistance value Rdiffsub of the photoelectric semiconductor device 22 within a specific sub-range of the target optical power is close to the mean differential resistance value Rdiffavg within the target optical power range. The mean differential resistance value Rdiffavg represents the ratio of the bias voltage fluctuation dV to the corresponding current fluctuation dI, corresponding to the lower and upper limits of optical power within the target optical power range.

[0101] For example, the differential resistance value Rdiffsub within a specific sub-range of the target optical power satisfies max(0.02*Rdiffavg,0.1Ω)≦Rdiffsub≦min(50*Rdiffavg,50Ω), where max(0.02*Rdiffavg,0.1Ω) represents the larger of 0.02*Rdiffavg and 0.1Ω, and min(50*Rdiffavg,50Ω) represents the smaller of 50*Rdiffavg and 50Ω.

[0102] For example, the differential resistance value Rdiffsub within a specific sub-range of the target optical power satisfies max(0.1*Rdiffavg,0.1Ω)≦Rdiffsub≦min(10*Rdiffavg,50Ω), where max(0.1*Rdiffavg,0.1Ω) represents the larger of 0.1*Rdiffavg and 0.1Ω, and min(10*Rdiffavg,50Ω) represents the smaller of 10*Rdiffavg and 50Ω.

[0103] For example, the differential resistance value Rdiffsub within a specific sub-range of the target optical power satisfies max(0.2*Rdiffavg,0.1Ω) ≤ Rdiffsub ≤ min(5*Rdiffavg,50Ω), where max(0.2*Rdiffavg,0.1Ω) represents the larger of 0.2*Rdiffavg and 0.1Ω, and min(5*Rdiffavg,50Ω) represents the smaller of 5*Rdiffavg and 50Ω.

[0104] For example, the differential resistance value Rdiffsub within a specific sub-range of the target optical power satisfies max(0.5*Rdiffavg,0.1Ω) ≤ Rdiffsub ≤ min(2*Rdiffavg,50Ω), where max(0.5*Rdiffavg,0.1Ω) represents the larger of 0.5*Rdiffavg and 0.1Ω, and min(2*Rdiffavg,50Ω) represents the smaller of 2*Rdiffavg and 50Ω.

[0105] For example, the differential resistance Rdiffsub within a specific sub-range of the target optical power satisfies max(0.8*Rdiffavg,0.1Ω)≦Rdiffsub≦min(1.25*Rdiffavg,50Ω), where max(0.8*Rdiffavg,0.1Ω) represents the larger of 0.8*Rdiffavg and 0.1Ω, and min(1.25*Rdiffavg,50Ω) represents the smaller of 1.25*Rdiffavg and 50Ω.

[0106] For example, the differential resistance value Rdiffsub within a specific subrange of the target optical power satisfies max(0.5*Rdiffavg,0.1Ω)≦Rdiffsub≦min(4*Rdiffavg,50Ω), where max(0.5*Rdiffavg,0.1Ω) is the larger of 0.5*Rdiffavg and 0.1Ω, and min(4*Rdiffavg,50Ω) is the smaller of 4*Rdiffavg and 50Ω. In another example, under the target optical power and bias voltage, the differential resistance value of the optoelectronic semiconductor device 22 is Rdiff1, where Rdiff1 satisfies 0.1Ω≦Rdiff1≦50Ω. In addition, within the range of the target optical power, the differential resistance Rdiff of the optoelectronic semiconductor device 22 satisfies max(0.1*Rdiff1,0.1Ω)≦Rdiff≦min(10*Rdiff1,50Ω), where max(0.1*Rdiff1,0.1Ω) represents the larger of 0.1*Rdiff1 and 0.1Ω, and min(10*Rdiff1,50Ω) represents the smaller of 10*Rdiff1 and 50Ω.

[0107] For example, under the target optical power, the differential resistance of the optoelectronic semiconductor device 22 under the bias voltage is Rdiff1, where Rdiff1 satisfies 0.1Ω ≤ Rdiff1 ≤ 50Ω. In addition, within the range of the target optical power, the differential resistance Rdiff of the optoelectronic semiconductor device 22 satisfies max(0.2*Rdiff1,0.1Ω) ≤ Rdiff ≤ min(5*Rdiff1,50Ω), where max(0.2*Rdiff1,0.1Ω) represents the larger of 0.2*Rdiff1 and 0.1Ω, and min(5*Rdiff1,50Ω) represents the smaller of 5*Rdiff1 and 50Ω.

[0108] For example, under the target optical power, the differential resistance of the optoelectronic semiconductor device 22 under the bias voltage is Rdiff1, where Rdiff1 satisfies 0.1Ω ≤ Rdiff1 ≤ 50Ω. In addition, within the range of the target optical power, the differential resistance Rdiff of the optoelectronic semiconductor device 22 satisfies max(0.5*Rdiff1,0.1Ω) ≤ Rdiff ≤ min(2*Rdiff1,50Ω), where max(0.5*Rdiff1,0.1Ω) represents the larger of 0.5*Rdiff1 and 0.1Ω, and min(2*Rdiff1,50Ω) represents the smaller of 2*Rdiff1 and 50Ω.

[0109] For example, under the target optical power and bias voltage, the differential resistance of the optoelectronic semiconductor device 22 is Rdiff1, where Rdiff1 satisfies 0.1Ω ≤ Rdiff1 ≤ 50Ω. In addition, within the range of the target optical power, the differential resistance Rdiff of the optoelectronic semiconductor device 22 satisfies max(0.8*Rdiff1,0.1Ω) ≤ Rdiff ≤ min(1.25*Rdiff1,50Ω), where max(0.8*Rdiff1,0.1Ω) represents the larger of 0.8*Rdiff1 and 0.1Ω, and min(1.25*Rdiff1,50Ω) represents the smaller of 1.25*Rdiff1 and 50Ω.

[0110] For example, under the target optical power and bias voltage, the differential resistance of the optoelectronic semiconductor device 22 is Rdiff1, where Rdiff1 satisfies 0.1Ω ≤ Rdiff1 ≤ 50Ω. In addition, within the range of the target optical power, the differential resistance Rdiff of the optoelectronic semiconductor device 22 satisfies max(0.5*Rdiff1,0.1Ω) ≤ Rdiff ≤ min(4*Rdiff1,50Ω), where max(0.5*Rdiff1,0.1Ω) represents the larger of 0.5*Rdiff1 and 0.1Ω, and min(4*Rdiff1,50Ω) represents the smaller of 4*Rdiff1 and 50Ω.

[0111] In this embodiment of the present application, the relationship between the amount P of the load links, the amount N of the optoelectronic semiconductor devices 22, and the amount W of the bias voltage output by the voltage conversion circuit 21 can be adjusted accordingly, based on different series-parallel connections of the load links and different series-parallel connections of the optoelectronic semiconductor devices 22 on the same load link. Typically, P=N=W, and specifically, each of the bias voltages output by the voltage conversion circuit 21 drives one load link, and each load link has one optoelectronic semiconductor device 22. More specifically, if the optoelectronic semiconductor devices 22 have good device performance consistency, multiple load links may be driven in parallel on one voltage output terminal of the voltage conversion circuit 21, and each link has at least one optoelectronic semiconductor device 22. For example, one voltage output terminal of the voltage conversion circuit 21 drives two load links connected in parallel, and each load link includes one optoelectronic semiconductor device 22. In this case, W=P / 2 and P=N. In another example, one voltage output terminal of the voltage conversion circuit 21 drives two load links connected in parallel, and two optoelectronic semiconductor devices are connected in series to each of the links. In this case, W = P / 2 and P = N / 2.

[0112] The photoelectric detection circuit 23 is configured to receive light output by the photoelectric semiconductor device 22, detect the output optical power output by the photoelectric semiconductor device 22, and output a detection signal to the controller 24, where the detection signal may indicate the output optical power output by the photoelectric semiconductor device 22. Typically, the photoelectric detection circuit 23 detects the output optical power output by the photoelectric semiconductor device 22 by detecting the backlight optical power output by the photoelectric semiconductor device 22 in N detection links. As shown in Figure 6, the photoelectric detection circuit 23 includes a photoelectric detector 2301 and a sampling resistor 2302 connected in series. When illuminated by the backlight, the reverse-biased photoelectric detector 2301 generates a photocurrent. When the photocurrent passes through the sampling resistor 2302, a detection signal proportional to the photocurrent is generated (a backlight sampling voltage Y is used as an example in this application, but is not intended to be limited thereto). The value of the photocurrent is proportional to the optical power of the backlight. Therefore, the backlight sampling voltage Y is proportional to the output optical power. The backlight sampling voltage Y output by the photoelectric detection circuit 23 is an analog signal.

[0113] The ADC32 is configured to convert the backlight sampling voltage Y generated by the photoelectric detection circuit 23 from an analog signal to a digital signal. The ADC32 may include a single ADC component or multiple ADC components, and the specifications of all ADC components may be the same or different.

[0114] When ADC32 contains a single ADC component, the amount of input analog channels Q supported by the ADC component is greater than or equal to N, and the amount of output digital channels R supported by the ADC component is greater than or equal to S, where S(S≧1) is the amount of digital channels of the controller 24 coupled to ADC32. More specifically, the amount of input analog channels Q supported by a single ADC component is N, and the amount of supported output digital channels R is S=1.

[0115] When ADC32 contains J (J≧2) ADC components, the amount of input analog channels supported by the i-th (2≦i≦J) ADC component is Qi, and the amount of output digital channels supported by the i-th ADC component is Ri. In this case, Q1+...+Qi+...+QJ≧N and R1+...+Ri+...+RJ≧S must be satisfied. Specifically, the amount of input analog channels supported by each of the J ADC components satisfies Q1+...+Qi+...+QJ=N, and the amount of output digital channels supported by each of the J ADC components satisfies Ri=1 (2≦i≦J).

[0116] The controller 24 is configured to perform a control method for the photoelectric assembly by providing signal processing and control for the entire drive system according to a control processing algorithm. Specifically, the controller 24 can implement APC by determining a control signal Z based on a detection signal (e.g., backlight sampling voltage Y) output by the photoelectric detection circuit 23, outputting the control signal Z to the feedback terminal of the voltage conversion circuit 21, and adjusting the bias voltage output by the voltage conversion circuit 21. The controller 24 can also be used for automatic gain control (AGC), optical pulse output control, etc. For example, the controller 24 may calculate the control signal Z according to the equation Z = B*Y + C, or obtain the control signal Z through a table lookup, where B is an adjustment rule corresponding to the backlight sampling voltage Y, and C is a fitting constant, and the values ​​of B and C can be obtained by looking up a pre-calibrated or pre-fitted table in the controller 24, or through real-time calculation. Furthermore, A, B, and C in the pre-calibrated or pre-fitted table in controller 24 can be corrected based on the actual accurate input. In other words, there is a linear relationship between the control signal Z and the detection signal (backlight sampling voltage Y). This simplifies the algorithmic design of controller 24 and facilitates control at the bias voltage.

[0117] Furthermore, the controller 24 may acquire additional load link information (how load link information is acquired is described below), where load link information includes the value of the bias voltage. The load link information can be a digital signal or an analog signal. Based on the load link information X and the detection signal (e.g., backlight sampling voltage Y), the controller 24 may determine a control signal Z and output the control signal Z to the feedback terminal of the voltage conversion circuit 21 to adjust the bias voltage output by the voltage conversion circuit 21.

[0118] If the load link information indicates the actual value of the bias voltage, the deviation between the theoretical and actual values ​​of the bias voltage caused by device parameter deviations and fluctuations in the feedback network 31 can be eliminated, and a more accurate input is provided to the controller 24 for obtaining the control signal Z. For example, the controller 24 may calculate the control signal Z according to the formula Z = A*X + B*Y + C, or obtain the control signal Z through a table lookup, where A is the tuning rule corresponding to the load link information X, B is the tuning rule corresponding to the backlight sampling voltage Y, and C is a fitting constant. The values ​​of A, B, and C can be obtained in the controller 24 by looking up a pre-calibrated or pre-fitted table, or through real-time calculation. Furthermore, A, B, and C in the pre-calibrated or pre-fitted table in the controller 24 can be corrected based on the actual accurate input.

[0119] The bit width of the digital signal processed by the controller 24 is at least 6 bits, and the voltage fluctuation corresponding to the minimum weight bit satisfies the requirement for fine-tuning the bias voltage output by the voltage conversion circuit 21, thereby enabling precise control of the bias voltage output by the voltage conversion circuit 21. If the digital signal processed by the controller 24 has only 4 bits, for example, if the internal reference voltage of the controller 24 is 2.5V and corresponds to the maximum value of a 4-bit binary number, the voltage fluctuation corresponding to the minimum weight bit of the control signal Z output by the controller 24 is 2.5V / 2^4 ≈ 156mV. This voltage adjustment accuracy is unacceptable. If the bit width of the digital signal processed by the controller 24 is 6 bits, for example, if the internal reference voltage of the controller 24 is 2.5V and corresponds to the maximum value of a 6-bit binary number, the voltage fluctuation corresponding to the minimum weight bit of the control signal Z output by the controller 24 is 2.5V / 2^6 ≈ 39mV. Even if the accuracy of the bias voltage output by the voltage conversion circuit 21 is the same as the voltage fluctuation of 39mV corresponding to the minimum weight bit of the control signal Z, if the differential resistance Rdiff of the optoelectronic semiconductor device 22 within the target optical power range is 10Ω and the bias voltage fluctuation output by the voltage conversion circuit 21 is 39mV, the current fluctuation of the current flowing through the optoelectronic semiconductor device 22 is 3.9mA. This can be considered a case where the equivalent adjustment current step is large in APC loop control, but this is also acceptable. If the bit width of the digital signal processed by the controller 24 is 8 bits, for example, if the internal reference voltage of the controller 24 is 2.5V and corresponds to the maximum value of an 8-bit binary number, then the voltage fluctuation corresponding to the minimum weight bit of the control signal Z output by the controller 24 is 2.5V / 2^8 = 9.8mV.Even when the accuracy of the bias voltage output by the voltage conversion circuit 21 is the same as the voltage fluctuation of 9.8mV corresponding to the minimum weight bit of the control signal Z, if the differential resistance Rdiff of the optoelectronic semiconductor device 22 within the target optical power range is 10Ω and the bias voltage fluctuation output by the voltage conversion circuit 21 is 9.8mV, the current fluctuation of the current flowing through the optoelectronic semiconductor device 22 is 0.98mA. This can be considered to be the case when the equivalent adjustment current step is small in APC loop control, which is acceptable. In combination with the feedback network 31, the accuracy of the control signal Z can be further improved, and the accuracy of the bias voltage output by the voltage conversion circuit 21 can be further improved, i.e., the resolution of the analog-to-digital conversion interface in the DAC 33 or controller 24 can be improved accordingly.

[0120] The number of digital channels of the controller 24 coupled to the ADC32 is S (S≧1), and the number of analog channels of the controller 24 coupled to the DAC33 is T (T≧1). The controller 24 may be a micro-control unit (MCU), a field-programmable gate array (FPGA), or the like.

[0121] The DAC33 is configured to convert the control signal Z generated by the controller 24 from a digital signal to an analog signal. The DAC33 may include a single DAC component or multiple DAC components, and the specifications of all DAC components may be the same or different.

[0122] When DAC33 contains a single DAC component, the amount of input digital channels U supported by the DAC component is greater than or equal to T, and the amount of output analog channels V supported by the DAC component is greater than W. T (T≧1) is the amount of digital channels of the controller 24 coupled to DAC33. More specifically, the amount of input digital channels U supported by a single DAC component is T=1, and the amount of output analog channels V supported by a single DAC component is W.

[0123] When DAC33 contains L (L≧2) DAC components, the amount of input digital channels supported by the i-th (2≦i≦L) DAC component is Ui, and the amount of output analog channels supported by the i-th DAC component is Vi. In this case, U1+...+Ui+...+UL≧T and V1+...+Vi+...+VL≧W must be satisfied. More specifically, the amount of input digital channels supported by each of the above L DAC components satisfies Ui=1 (2≦i≦L), and the amount of output analog channels supported by each of the above L DAC components satisfies V1+...+Vi+...+VL=W.

[0124] It should be noted that, in order to match the bit width of the digital signal processed by the controller 24, i.e., at least 6 bits, the bit widths of the DAC33 and ADC32 are matched to the bit width of the digital signal processed by the controller 24, thereby ensuring adjustment accuracy. Therefore, the bit widths of the DAC33 and ADC32 are also at least 6 bits.

[0125] The feedback network 31 is configured to increase or decrease the voltage range of the control signal Z to obtain a feedback control signal F, and to output the feedback control signal F to the voltage conversion circuit 21 to satisfy the requirements for the range of the signal input to the voltage conversion circuit 21 and improve the accuracy of the control signal Z. Thus, the feedback control signal F can be expressed as F = E*Z + G, where E is the corresponding adjustment rule of the feedback network 31 with respect to the control signal Z, and G is a fitting constant. In addition, when the voltage conversion circuit 21 is a DC-DC converter, the DC-DC converter typically includes an operational amplifier, and the feedback network 31 is coupled to the output terminal and the feedback terminal of the operational amplifier to form a feedback path for the operational amplifier. The feedback network 31 can provide the voltage conversion circuit 21 with W feedback control signals F corresponding to W output voltages.

[0126] In particular, when the voltage conversion circuit 21 has a voltage adjustment and transformation frequency input terminal or control terminal, the controller 24 may further provide the voltage conversion circuit 21 with another feedback control signal F2 based on the circuit status and characteristics of the voltage conversion circuit 21 to change the voltage adjustment and transformation frequency of the voltage conversion circuit 21. This can improve the voltage conversion efficiency of the voltage conversion circuit 21.

[0127] The feedback network 31 may be a voltage divider network comprising resistors. For example, as shown in Figure 6, the feedback network includes resistors Ra, Rb, and Rc. The second end of resistor Ra is grounded, the first end of resistor Ra, the second end of resistor Rb, and the first end of resistor Rc are coupled to the feedback terminal of the voltage conversion circuit 21, the first end of resistor Rb is coupled to the bias voltage output terminal of the voltage conversion circuit 21, and the second end of resistor Rc is coupled to the output terminal of the controller 24.

[0128] It is assumed that there is a functional relationship Vout = f(Vfb) between the bias voltage Vout output by the voltage conversion circuit 21 and the feedback voltage Vfb (i.e., the voltage of the feedback control signal F) input from the feedback terminal of the voltage conversion circuit 21, where f() represents a function, and this functional relationship is related to the design of the voltage conversion circuit 21. If this functional relationship is linear, it can be further expressed as Vout = a*Vfb + c, where a and c are constant coefficients related to the design of the voltage conversion circuit 21. When the voltage conversion circuit 21 is a DC-DC converter, a reference voltage Vref (which is usually a fixed value) inside the DC-DC converter is input from the input terminal of the operational amplifier in the DC-DC converter, and the voltage Vfb is input from another input terminal of the operational amplifier. The voltages Vout, Vfb, and reference voltage Vref have the following relationship when Rc is off. Vfb=Vref Equation 1 Vout = Vfb * (Ra + Rb) / Rb Equation 2

[0129] Specifically, the following can be obtained by combining the feedback network 31 with the resistor voltage divider network. Vout=(Vref / Ra-(Vadj-Vref) / Rc)*Rb+Vref Equation 3

[0130] Vadj is the voltage of the control signal Z output by the DAC33.

[0131] From Equation 3, it can be seen that, given resistances Ra, Rb, and Rc, the output voltage Vout of the DC-DC converter circuit can be adjusted based on the voltage Vadj of the control signal Z, i.e., Vout = f(Vadj), and that the control signal Z and the feedback control signal F have a linear relationship. Therefore, different resistances Ra, Rb, Rc, voltage Vadj, and reference voltage Vref are set to obtain different voltages Vout.

[0132] The feedback network based on the resistor-voltage divider network implements a linear increase or decrease of the control signal Z based on the feedback control signal F, thereby meeting the requirements for the range of the signal input by the voltage conversion circuit 21 and improving the accuracy of the control signal. In addition, the feedback network has a simple design and a compact structure. This facilitates miniaturization of the entire optoelectronic assembly.

[0133] It should be noted that this application provides only one feedback network based on a resistor voltage divider network, and various functional relations Vout=f(Vadj) can be further designed in combination with other devices such as digital and analog circuits. In addition, in combination with the controller 24 and based on the backlight sampling voltage Y, the functional relation Z=g(Y) of the control signal Z can be further determined, and Vout=f(Vadj)=f(g(Y)) can be obtained.

[0134] For example, using an example where the controller 24 determines the control signal Z based on the detection signal output by the photoelectric detection circuit 23 (e.g., the backlight sampling voltage Y), how the controller 24 calibrates each of the parameters in the equation Z = B * Y + C is explained.

[0135] Step 1: The controller 24 outputs a control signal Z. If there is a feedback network 31, the feedback network 31 converts the control signal Z into a feedback control signal F, and outputs the feedback control signal F to the voltage conversion circuit 21 to adjust the bias voltage output by the voltage conversion circuit 21. If there is no feedback network 31, the control signal Z is output to the voltage conversion circuit 21 to adjust the bias voltage output by the voltage conversion circuit 21. The bias voltage output by the voltage conversion circuit 21 generates a corresponding drive current (sometimes called bias current), and the optoelectronic semiconductor device 22 outputs light (power accounting for the main portion) and backlight (power accounting for the minor portion) under the action of the drive current. The output light power, measured by an external light power detector, is P. The photoelectric detection circuit 23 outputs a backlight sampling voltage Y. The backlight sampling voltage Y, the control signal Z, and the light power P are stored in the controller 24 as a parameter combination (Y, Z, P).

[0136] Within the range of the target optical power, the ratio of the backlight optical power output by the optoelectronic semiconductor device 22 to the output optical power P is basically stable, and the backlight optical power is proportional to the backlight sampling voltage Y. Therefore, the output optical power P is proportional to the backlight sampling voltage Y. Thus, the parameter combination (Y, Z, P) can be expressed as (Y, Z, P(Y)).

[0137] Step 2: The controller 24 modifies the output control signal Z to obtain more parameter combinations (Yi, Zi, Pi(Yi)) in Step 1 and stores the parameter combinations in the controller 24, where i is a positive integer. Alternatively, the controller 24 may obtain new parameter combinations through fitting based on multiple existing parameter combinations. After obtaining multiple combined parameters, the controller 24 may establish mapping relationships between B, C, Y, and Z in the equation Z = B*Y + C according to a specific algorithm and rules.

[0138] Step 3: The controller 24 sets a default parameter combination (Yo, Zo, Po(Y)) based on the target optical power Pg, and the controller 24 is configured to output a control signal Z based on the default parameter combination during initialization, where Po ≥ Pg.

[0139] In the actual system operation process, the controller 24 performs APC to maintain the output light power within a preset range. The controller 24 acquires the backlight sampling voltage Y in real time and acquires the control signal Z according to the calibrated formula Z = B*Y + C. Typically, the backlight sampling voltage Y acquired by the controller 24 is stable, and therefore the control signal Z is also stable.

[0140] When the output optical power of the optoelectronic semiconductor device 22 decreases due to the aging of the device or an increase in the ambient temperature, the backlight sampling voltage Yo decreases to Y'. In this case, the controller 24 adjusts the control signal Z according to Z = B * Y + C established in the calibration process so that the bias voltage output by the voltage conversion circuit 21 increases, provides a larger drive current, increases the carrier density, increases the output optical power, and further increases the backlight sampling voltage to Yt. The controller 24 compares Yt with Yo. When Yt < Yo, the adjustment of the control signal Z is continued so that the bias voltage output by the voltage conversion circuit 21 increases, provides a larger drive current, and increases the backlight sampling voltage Yt until |Yt - Yo| is less than the set error. When Yt > Yo, the controller continues to adjust the control signal Z so that the bias voltage output by the voltage conversion circuit 21 decreases, provides a smaller drive current, and decreases the backlight sampling voltage Yt until |Yt - Yo| is less than the set error. The adjustment direction and step of the control signal Z can be dynamically adjusted based on the change trend of the backlight sampling voltage Yt and according to the formula Z = B * Y + C. Finally, the entire system operates under the new parameter combination (Yo, Zt, Po(Yo)).

[0141] When the output optical power output by the optoelectronic semiconductor device 22 increases due to a decrease in the ambient temperature, the backlight sampling voltage Yo increases to Y'. In this case, the controller 24 adjusts the control signal Z according to the formula Z = B * Y + C established in the calibration process so that the bias voltage output by the voltage conversion circuit 21 decreases, provides a smaller drive current, reduces the carrier density, and further needs to reduce the backlight sampling voltage to Yt. The controller 24 compares Yt with Yo. When Yt > Yo, it continues to adjust the control signal Z so that the bias voltage output by the voltage conversion circuit 21 decreases, provides a smaller drive current, and reduces the backlight sampling voltage Yt until |Yt - Yo| is less than the set error. When Yt < Yo, the controller continues to adjust the control signal Z so that the bias voltage output by the voltage conversion circuit 21 increases, provides a larger drive current, and increases the backlight sampling voltage Yt until |Yt - Yo| is less than the set error. The adjustment direction and step of the control signal Z can be dynamically adjusted based on the change trend of the backlight sampling voltage Yt and according to the formula Z = B * Y + C. Finally, the entire system operates under the new parameter combination (Yo, Zt, Po(Yo)).

[0142] According to embodiments of this application, the efficiency of the photoelectric assembly is improved by a photoelectric assembly, a light source pool, and a control method for the photoelectric assembly. A voltage conversion circuit provides a bias voltage to a photoelectric semiconductor device to adjust the output optical power output by the photoelectric semiconductor device. A photoelectric detection circuit receives light output by the photoelectric semiconductor device, detects the output optical power output by the photoelectric semiconductor device, and outputs a detection signal to a controller. Based on the detection signal, the controller may determine a control signal to be used to adjust the bias voltage and send the control signal to the voltage conversion circuit. There is no need for another detection circuit to be coupled between the voltage conversion circuit and the photoelectric semiconductor device, no additional power output by the voltage conversion circuit is consumed, and most of the power output by the voltage conversion circuit is converted into output optical power output by the photoelectric semiconductor device. Therefore, this can improve the efficiency of the photoelectric assembly.

[0143] The power supply 25, the voltage conversion circuit 21, and the optoelectronic semiconductor device 22 can be coupled in several ways. The coupling methods between the power supply 25, the voltage conversion circuit 21, and the optoelectronic semiconductor device 22 will be described below with reference to Figures 7A, 7B, 7C, 7D, 7E, and 7F. For the sake of clarity, please refer to the descriptions in other accompanying drawings for the configuration, function, and coupling methods of other functional modules.

[0144] As shown in Figure 7A, the power supply 25 outputs two voltages Vcc1 and Vcc2, which are output to the first voltage conversion circuit 211 and the second voltage conversion circuit 212, respectively. Vcc1 and Vcc2 may be the same or different. The bias voltage output by the first voltage conversion circuit 211 is controlled by a control signal Z output by the controller to adjust the output optical power output by the optoelectronic semiconductor device in load link 1. The bias voltage output by the second voltage conversion circuit 212 is controlled by a control signal Z output by the controller to adjust the output optical power output by the optoelectronic semiconductor device in load link 2.

[0145] As shown in Figure 7B, the power supply 25 outputs voltage Vcc1 to the first voltage conversion circuit 211 and the second voltage conversion circuit 212. The bias voltage output by the first voltage conversion circuit 211 is controlled by the control signal Z output by the controller to adjust the output optical power output by the optoelectronic semiconductor device in load link 1. The bias voltage output by the second voltage conversion circuit 212 is controlled by the control signal Z output by the controller to adjust the output optical power output by the optoelectronic semiconductor device in load link 2.

[0146] As shown in Figure 7C, power supply 25 outputs two voltages Vcc1 and Vcc2, which are used in the first voltage conversion circuit. 211 and are output to the second voltage conversion circuit 212, respectively. Vcc1 and Vcc2 may be the same or different. Load links 1 and 2 are coupled in parallel to the voltage output terminals of the first voltage conversion circuit 211, and the bias voltage output by the first voltage conversion circuit 211 is controlled by a control signal Z output by the controller to adjust the output optical power output by the optoelectronic semiconductor device in load link 1 and the optoelectronic semiconductor device in load link 2. Load links 3 and 4 are, 2 Voltage conversion circuit 212The bias voltage, which is connected in parallel to the voltage output terminal of the second voltage conversion circuit 212 and output by the second voltage conversion circuit 212, is controlled by the control signal Z output by the controller, and the optoelectronic semiconductor device in the load link 3 and the load link 4 The output optical power is adjusted by the optoelectronic semiconductor device inside.

[0147] As shown in Figure 7D, the power supply 25 outputs voltage Vcc1 to the first voltage conversion circuit 211 and the second voltage conversion circuit 212. Load links 1 and 2 are coupled in parallel to the voltage output terminal of the first voltage conversion circuit 211, and the bias voltage output by the first voltage conversion circuit 211 is controlled by a control signal Z output by the controller to adjust the output optical power output by the optoelectronic semiconductor device in load link 1 and the optoelectronic semiconductor device in load link 2. Load links 3 and 4 are connected in parallel to the first 2 Voltage conversion circuit 212 The bias voltage, which is connected in parallel to the voltage output terminal of the second voltage conversion circuit 212 and output by the second voltage conversion circuit 212, is controlled by the control signal Z output by the controller, and the optoelectronic semiconductor device in the load link 3 and the load link 4 The output optical power is adjusted by the optoelectronic semiconductor device inside.

[0148] As shown in Figure 7E, multiple optoelectronic semiconductor devices (e.g., a first optoelectronic semiconductor device 221 and a second optoelectronic semiconductor device 222) may be connected in series to the load link, or as shown in Figure 7F, multiple optoelectronic semiconductor devices (e.g., a first optoelectronic semiconductor device 221 and a second optoelectronic semiconductor device 222) may be connected in parallel to the load link. That is, Figures 7E and 7F can be freely combined with Figures 7A through 7D. Note that in this case, each optoelectronic semiconductor device is paired with an independent photoelectric detection circuit.

[0149] In Figures 7E and 7F, the first photoelectric semiconductor device 221 is paired with a first photoelectric detection circuit, and the first photoelectric detection circuit detects the output optical power output by the first photoelectric semiconductor device 221, and the first detection The signal is configured to output to the controller 24. The second photoelectric semiconductor device 222 is paired with a second photoelectric detection circuit, which detects the output optical power output by the second photoelectric semiconductor device 222, and the second detection The signals are configured to output to the controller 24. The controller 24 can determine a control signal based on the first and second detection signals and send the control signal to the voltage conversion circuit 21. Since the first optoelectronic semiconductor device 221 and the second optoelectronic semiconductor device 222 are coupled to the voltage conversion circuit 21 through a load link, the bias voltage supplied to the first optoelectronic semiconductor device 221 and the second optoelectronic semiconductor device 222 can be adjusted based on the control signal.

[0150] Regardless of whether the first optoelectronic semiconductor device 221 and the second optoelectronic semiconductor device 222 are connected in series or in parallel, if the first detection signal is less than the second detection signal and the first detection signal is below a first threshold (in other words, the output optical power output by the optoelectronic semiconductor device is excessively low), the controller 24 determines a control signal based on the first detection signal, which may indicate to the voltage conversion circuit 21 to increase the bias voltage to increase the output optical power output by the first optoelectronic semiconductor device 221 and the second optoelectronic semiconductor device 222. That is, if the output optical power output by the optoelectronic assembly needs to be increased, the control signal is determined based on the detection signal corresponding to the smaller of the two output optical powers output by the two optoelectronic semiconductor devices.

[0151] Regardless of whether the first optoelectronic semiconductor device 221 and the second optoelectronic semiconductor device 222 are connected in series or in parallel, if the first detection signal is less than the second detection signal and the second detection signal is greater than a second threshold (in other words, the output optical power output by the optoelectronic semiconductor device is excessively high), the controller 24 determines a control signal based on the second detection signal, which may indicate to the voltage conversion circuit 21 to reduce the bias voltage and thereby reduce the output optical power output by the first optoelectronic semiconductor device 221 and the second optoelectronic semiconductor device 222. That is, if the output optical power output by the optoelectronic assembly needs to be reduced, the control signal is determined based on the detection signal corresponding to the larger of the two output optical powers output by the two optoelectronic semiconductor devices.

[0152] Various coupling methods between the power supply 25, the voltage conversion circuit 21, and the optoelectronic semiconductor device 22 provide greater flexibility for the design of the optoelectronic assembly. This can further reduce the number of devices, lower costs, and improve integration.

[0153] It should be noted that various combinations relating to Figures 7A, 7B, 7C, 7D, 7E, and 7F can be implemented by those skilled in the art, and all combinations can be considered embodiments of this application and fall within the scope of protection of this application. In addition, the various combination schemes in Figures 7A, 7B, 7C, 7D, 7E, and 7F require that all load links in the same voltage conversion circuit have good consistency and that all optoelectronic semiconductor devices in the same load link have good consistency. Otherwise, the tuning tendencies of the two optoelectronic semiconductor devices are likely to be inconsistent or power fluctuations are likely to occur. In addition, when a first threshold and a second threshold coexist, it is also required that the first threshold and the second threshold cannot be excessively close to each other. Otherwise, the tuning tendencies of the two optoelectronic semiconductor devices are likely to be inconsistent or power fluctuations are likely to occur.

[0154] The ADC32, DAC33, and controller 24 can be coupled in several ways. The coupling methods between the ADC32 and controller 24 are described below with reference to Figures 8A, 8B, 8C, and 8D, and the coupling methods between controller 24 and DAC33 are described with reference to Figures 9A, 9B, 9C, and 9D. For the sake of clarity, please refer to the descriptions in other attached drawings for the configuration, function, and coupling methods of other functional modules.

[0155] As shown in Figure 8A, the ADC32 includes four analog input ports (in1 to in4) and one digital output port (out1). The controller 24 includes one digital input port (in5), and the controller 24's digital input port in5 is coupled to the ADC32's digital output port out1. The four analog input ports (in1 to in4) of the ADC32 each receive four analog signals (backlight sampling voltage 1 to backlight sampling voltage 4) from the photoelectric detection circuit. The ADC32 performs analog-to-digital conversion on the four analog signals separately to obtain four digital signals and outputs the four digital signals sequentially in a specific order to the controller 24 through the ADC32's digital output port out1. After receiving the four digital signals, the controller 24 analyzes the four digital signals in a specific order to obtain the values ​​of the four backlight sampling voltages. The controller 24 obtains one control signal based on each of the four backlight sampling voltages and can send the four control signals to the corresponding voltage conversion circuits to adjust the output bias voltage.

[0156] As shown in Figure 8B, the first ADC321 includes two analog input ports (in1 and in2) and one digital output port (out1), and the second ADC322 includes two analog input ports (in3 and in4) and one digital output port (out2). The controller 24 includes two digital input ports (in5 and in6). The digital input port in5 of the controller 24 is coupled to the digital output port out1 of the first ADC321, and the digital input port in6 of the controller 24 is coupled to the digital output port out2 of the second ADC322. The two analog input ports (in1 and in2) of the first ADC321 receive two analog signals (backlight sampling voltage 1 and backlight sampling voltage 2) from the photoelectric detection circuit, respectively. The first ADC321 performs analog-to-digital conversion on two analog signals separately to obtain two digital signals, and outputs the two digital signals sequentially in a specific order to the controller 24 through its digital output port out1. After receiving the two digital signals, the controller 24 analyzes them in a specific order to obtain the values ​​of the two backlight sampling voltages. The two analog input ports (in3 and in4) of the second ADC322 receive two analog signals (backlight sampling voltage 3 and backlight sampling voltage 4) from the photoelectric detection circuit, respectively. The second ADC322 performs analog-to-digital conversion on two analog signals separately to obtain two digital signals, and outputs the two digital signals sequentially in a specific order to the controller 24 through its digital output port out2. After receiving the two digital signals, the controller 24 analyzes them in a specific order to obtain the values ​​of the two backlight sampling voltages. The controller 24 can acquire one control signal based on each of the four backlight sampling voltages and send the four control signals to the corresponding voltage conversion circuits to adjust the output bias voltage.

[0157] As shown in Figure 8C, the ADC32 has four analog input ports (in1 to in4) and 2 Two digital output ports (out1 and out2) and ). Controller 24 includes two digital input ports (in5 and in6). Controller 24's digital input port in5 is coupled to ADC32's digital output port out1, and Controller 24's digital input port in6 is coupled to ADC32's digital output port out2. ADC32's two analog input ports (in1 and in2) each receive two analog signals (backlight sampling voltage 1 and backlight sampling voltage 2) from the photoelectric detection circuit. ADC32 performs analog-to-digital conversion on the two analog signals separately to obtain two digital signals and outputs the two digital signals to Controller 24 in a specific order through ADC32's digital output port out1. After receiving the two digital signals, Controller 24 analyzes the two digital signals in a specific order to obtain the values ​​of the two backlight sampling voltages. ADC32's two analog input ports (in3 and in4) each receive two analog signals (backlight sampling voltage 3 and backlight sampling voltage 4) from the photoelectric detection circuit. The ADC32 performs analog-to-digital conversion on two analog signals separately to obtain two digital signals, and outputs these two digital signals sequentially in a specific order to the controller 24 through the ADC32's digital output port out2. After receiving the two digital signals, the controller 24 analyzes them in a specific order to obtain the values ​​of two backlight sampling voltages. The controller 24 can obtain one control signal based on each of the four backlight sampling voltages and send the four control signals to the corresponding voltage conversion circuits to adjust the output bias voltage. While it is more common for the total number of digital signals output from the ADC32's output ports out1 and out2 to be four, the number of digital signals output from output ports out1 and out2 respectively, and the correspondence between this number and the corresponding backlight sampling voltages 1 through 4, are not limited.

[0158] As shown in Figure 8D, the first ADC321 includes four analog input ports (in1 to in4) and one digital output port (out1), and the second ADC322 includes two analog input ports (in5 and in6) and one digital output port (out2). The controller 24 includes two digital input ports (in7 and in8). The digital input port in7 of the controller 24 is coupled to the digital output port out1 of the first ADC321, and the digital input port in8 of the controller 24 is coupled to the digital output port out2 of the second ADC322. The four analog input ports (in1 to in4) of the first ADC321 each receive four analog signals (backlight sampling voltage 1 to backlight sampling voltage 4) from the photoelectric detection circuit. The first ADC321 performs analog-to-digital conversion on four analog signals separately to obtain four digital signals, and outputs these four digital signals sequentially in a specific order to the controller 24 through its digital output port out1. After receiving the four digital signals, the controller 24 analyzes them in a specific order to obtain the values ​​of the four backlight sampling voltages. The two analog input ports (in5 and in6) of the second ADC322 receive two analog signals (backlight sampling voltage 5 and backlight sampling voltage 6) from the photoelectric detection circuit, respectively. The second ADC322 performs analog-to-digital conversion on the two analog signals separately to obtain two digital signals, and outputs these two digital signals sequentially in a specific order to the controller 24 through its digital output port out2. After receiving the two digital signals, the controller 24 analyzes them in a specific order to obtain the values ​​of the two backlight sampling voltages.

[0159] As shown in Figure 9A, the DAC33 includes four analog output ports (out1 to out4) and one digital input port (in1). The controller 24 includes one digital output port (out5). The controller 24's digital output port out5 is coupled to the DAC33's digital input port in1. The controller 24 outputs four control signals (control signal 1 to control signal 4) to the DAC33 sequentially in a specific order through its digital output port out5. After receiving the four digital signals, the DAC33 analyzes the four digital signals in a specific order to obtain the four control signals and outputs them separately to the four control signals. Digital Analog The conversion is performed to obtain four analog signals, and these four analog signals are output separately through the DAC33's four analog output ports (out1 to out4).

[0160] As shown in Figure 9B, the first DAC331 includes two analog output ports (out1 and out2) and one digital input port (in1). The second DAC332 includes two analog output ports (out3 and out4) and one digital input port (in2). The controller 24 includes two digital output ports (out5 and out6). The digital output port out5 of the controller 24 is coupled to the digital input port in1 of the first DAC331, and the digital output port out6 of the controller 24 is coupled to the digital input port in2 of the second DAC332. The controller 24 outputs two control signals (control signal 1 and control signal 2) to the first DAC331 sequentially in a specific order through its digital output port out5. After receiving the two digital signals, the first DAC331 analyzes the two digital signals in a specific order to obtain the two control signals and applies them separately to the two control signals. Digital Analog Perform a conversion to obtain two analog signals, and the first DAC 331The controller outputs two analog signals separately through its two analog output ports (out1 and out2). The controller 24 outputs two control signals (control signal 3 and control signal 4) sequentially in a specific order to the second DAC332 through its digital output port out6. After receiving the two digital signals, the second DAC332 analyzes the two digital signals in a specific order to obtain the two control signals and outputs them separately to the two control signals. Digital Analog The conversion is performed to obtain two analog signals, and these two analog signals are output separately through the two analog output ports (out3 and out4) of the second DAC332.

[0161] As shown in Figure 9C, the DAC33 includes four analog output ports (out1 to out4) and two digital input ports (in1 and in2). The controller 24 includes two digital output ports (out5 and out6). The controller 24's digital output port out5 is coupled to the DAC33's digital input port in1, and the controller 24's digital output port out6 is coupled to the DAC33's digital input port in2. The controller 24 outputs two control signals (control signal 1 and control signal 2) to the DAC33 sequentially in a specific order through its digital output port out5. After receiving the two digital signals, the DAC33 analyzes the two digital signals in a specific order to obtain the two control signals and outputs them separately to the two control signals. Digital Analog The controller 24 performs a conversion to obtain two analog signals and outputs the two analog signals separately through the two analog output ports (out1 and out2) of the DAC33. The controller 24 outputs two control signals (control signal 3 and control signal 4) to the DAC33 sequentially in a specific order through its digital output port out6. After receiving the two digital signals, the DAC33 analyzes the two digital signals in a specific order to obtain the two control signals and outputs them separately for the two control signals. Digital AnalogThe conversion is performed to obtain two analog signals, which are then output separately through the two analog output ports (out3 and out4) of the DAC33. While it is more common for the total number of digital signals input from input ports in1 and in2 of the DAC33 to be four, the number of digital signals input from input ports in1 and in2 respectively, and the correspondence between these numbers and the corresponding control signals 1 through 4, are not limited.

[0162] As shown in Figure 9D, the first DAC331 includes four analog output ports (out1 to out4) and one digital input port (in1). The second DAC332 includes two analog output ports (out5 and out6) and one digital input port (in2). The controller 24 includes two digital output ports (out7 and out8). The digital output port out7 of the controller 24 is coupled to the digital input port in1 of the first DAC331, and the digital output port out8 of the controller 24 is coupled to the digital input port in2 of the second DAC332. The controller 24 outputs four control signals (control signals 1 to control signals 4) sequentially in a specific order to the first DAC331 through its digital output port out7. After receiving the four digital signals, the first DAC331 analyzes the four digital signals in a specific order to obtain the four control signals and analyzes the four control signals separately Digital Analog The first DAC331 performs a conversion to obtain four analog signals and outputs the four analog signals separately through its four analog output ports (out1 to out4). The controller 24 outputs two control signals (control signal 5 and control signal 6) sequentially in a specific order to the second DAC332 through its digital output port out8. After receiving the two digital signals, the second DAC332 analyzes the two digital signals in a specific order to obtain the two control signals and outputs them separately to the two control signals. Digital AnalogThe conversion is performed to obtain two analog signals, and these two analog signals are output separately through the two analog output ports (out5 and out6) of the second DAC332.

[0163] The coupling schemes shown in Figures 8A, 8B, 8C, 8D, 9A, 9B, 9C, and 9D improve the design flexibility of optoelectronic assemblies, further reduce resource requirements for analog-to-digital and digital-to-analog conversion interfaces, reduce the number of ADCs and DACs, lower costs, improve integration, and facilitate miniaturization of optoelectronic assemblies. For example, when an ADC converts two analog signals into one digital signal, it is possible to reduce the number of ADCs by 50%. When an ADC can convert more analog signals into one digital signal, it is possible to reduce the number of ADCs by more. When a DAC converts two digital signals into one analog signal, it is possible to reduce the number of DACs by 50%. When a DAC can convert more digital signals into one analog signal, it is possible to reduce the number of DACs by more.

[0164] The following section will explain the specific coupling method between the ADC32, DAC33, and controller24, with reference to Figure 10.

[0165] As shown in Figure 10, the power supply 25 provides power supply voltages Vcc1 and Vcc2 to the entire photoelectric assembly. The first voltage conversion circuit 211 converts voltage Vcc1 to bias voltage 1 and provides bias voltage 1 to the first photoelectric semiconductor device 221. The bias voltage 1 output by the first voltage conversion circuit 211 can be adjusted based on a control signal Z1 output by the controller 24. The second voltage conversion circuit 212 converts voltage Vcc2 to bias voltage 2 and provides bias voltage 2 to the second photoelectric semiconductor device 222. The bias voltage 2 output by the second voltage conversion circuit 212 can be adjusted based on a control signal Z2 output by the controller 24. At least one of the first voltage conversion circuit 211 and the second voltage conversion circuit 212 may be a DC-DC converter. For example, 0.9*Vcc1 > bias voltage 1 > 1.0V and Vcc1 > 1.3V, 0.9*Vcc2 > bias voltage 2 > 1.0V and Vcc2 > 1.3V.

[0166] While this embodiment of the present application is described using an example in which two voltage conversion circuits provide bias voltages to two optoelectronic semiconductor devices, it should be noted that this is not intended to be limited thereto. For example, more voltage conversion circuits may provide bias voltages to more optoelectronic semiconductor devices.

[0167] The output light of the first photoelectric semiconductor device 221 consists of two parts. The first part is output light 1, and the second part (backlight 1) is output to a first photoelectric detection circuit 231 for detecting the optical power of the first photoelectric semiconductor device 221. The output light of the second photoelectric semiconductor device 222 consists of two parts. The first part is output light 2, and the second part (backlight 2) is output to a second photoelectric detection circuit 232 for detecting the optical power of the second photoelectric semiconductor device 222. Within the target optical power range, the resistance values ​​of both the first photoelectric semiconductor device 221 and the second photoelectric semiconductor device 222 are less than or equal to 60Ω, and within the target optical power range, the differential resistance value Rdiff of the first photoelectric semiconductor device and the second photoelectric semiconductor device satisfies 0.1Ω ≤ Rdiff ≤ 50Ω.

[0168] The first photoelectric detection circuit 231 is configured to detect the output optical power output by the first photoelectric semiconductor device 221, and the second photoelectric detection circuit 232 is configured to detect the output optical power output by the second photoelectric semiconductor device 222.

[0169] The ADC32 includes two analog input ports, which receive the backlight sampling voltage Y1 (analog signal) from the first photoelectric detection circuit 231 and the backlight sampling voltage Y2 (analog signal) from the second photoelectric detection circuit 232, respectively. The ADC32 converts the backlight sampling voltage Y1 (analog signal) to a backlight sampling voltage Y1 (digital signal) and the backlight sampling voltage Y2 (analog signal) to a backlight sampling voltage Y2 (digital signal), and outputs the two digital signals sequentially in a specific order to the controller 24 through the digital output port. The ADC converts two signals into one signal, which can reduce ADC resources by 50%.

[0170] The controller 24 analyzes the backlight sampling voltage (digital signal) in a specific order according to the rule that the ADC 32 outputs the backlight sampling voltage (digital signal), thereby determining the corresponding backlight sampling voltage Y1 (digital signal). signal The controller 24 obtains the backlight sampling voltage Y1 (digital signal) and the backlight sampling voltage Y2 (digital signal). The controller 24 generates a control signal Z1 (digital signal) based on the backlight sampling voltage Y1 (digital signal) and a control signal Z2 (digital signal) based on the backlight sampling voltage Y2 (digital signal), and outputs the two control signals to the DAC33 in a specific order through the digital output port.

[0171] DAC33 acquires control signals Z1 (digital signal) and Z2 (digital signal) in a specific order according to the corresponding rules for which controller 24 outputs control signals. DAC33 performs a digital-to-analog conversion on control signal Z1 (digital signal) to acquire control signal Z1 (analog signal) and outputs control signal Z1 (analog signal) to the first feedback network 311 through the analog output port. DAC33 performs a digital-to-analog conversion on control signal Z2 (digital signal) to acquire control signal Z2 (analog signal) and outputs control signal Z2 (analog signal) to the second feedback network 312 through the analog output port. The DAC converts one signal into two signals. This can reduce DAC resources by 50%.

[0172] The first feedback network 311 is configured to obtain a feedback control signal F1 by increasing or decreasing the voltage range of the control signal Z1, and to output the feedback control signal F1 to the feedback terminal of the first voltage conversion circuit 211, thereby satisfying the requirements for the range of the signal input by the first voltage conversion circuit 211 and equivalently improving the accuracy of the control signal Z1. The second feedback network 312 is configured to obtain a feedback control signal F2 by increasing or decreasing the voltage range of the control signal Z2, and to output the feedback control signal F2 to the feedback terminal of the second voltage conversion circuit 212, thereby satisfying the requirements for the range of the signal input by the second voltage conversion circuit 212 and equivalently improving the accuracy of the control signal Z2. The bias voltage 1 output by the first voltage conversion circuit 211 may be adjusted based on the feedback control signal F1, and the bias voltage 2 output by the second voltage conversion circuit 212 may be adjusted based on the feedback control signal F2.

[0173] The following describes how the controller 24 obtains load link information X.

[0174] In a possible implementation shown in Figure 11 based on Figure 2, when the controller 24 has an analog-to-digital conversion interface (in other words, analog signals can be directly input) and a digital-to-analog conversion interface (in other words, analog signals can be directly output), or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are sufficient, the controller 24 can directly obtain load link information X from the bias voltage output terminal of the voltage conversion circuit 21.

[0175] In another possible implementation shown in Figure 12 based on Figure 3, when the controller 24 does not have an analog-to-digital conversion interface or a digital-to-analog conversion interface, or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are insufficient, the optoelectric assembly may further include a second ADC 34. The analog input port of the second ADC 34 is coupled to the bias voltage output terminal of the voltage conversion circuit 21, and the digital output port of the second ADC 34 is coupled to the input terminal of the controller 24. The controller 24 may use the second ADC 34 to obtain load link information X from the bias voltage output terminal of the voltage conversion circuit 21. When the controller 24 has an analog-to-digital conversion interface (in other words, analog signals can be directly input), or when the analog-to-digital conversion interface of the controller 24 Resources When sufficient, the second ADC34 can be the analog-to-digital conversion interface of the controller 24.

[0176] In addition, the second ADCs 34 and 32 may be ADCs having two analog inputs and one digital output, the two analog input ports of the ADCs may be coupled to the bias voltage output terminal of the voltage conversion circuit 21 and the output terminal of the photoelectric detection circuit 23, respectively. The ADCs may output load link information X and backlight sampling voltage Y to the controller 24 in a specific order, and the controller 24 may obtain the load link information X and backlight sampling voltage Y by analyzing them in a specific order. This can reduce the number of ADCs, lower costs, improve integration, and facilitate miniaturization of the photoelectric assembly.

[0177] In yet another possible implementation shown in Figure 13 based on Figure 10, when the controller 24 does not have an analog-to-digital conversion interface or a digital-to-analog conversion interface, or when the resources of the analog-to-digital conversion interface and the digital-to-analog conversion interface of the controller 24 are insufficient, the optoelectric assembly may further include a second ADC 34. The two analog input ports of the second ADC 34 are coupled to the output terminals of the first voltage conversion circuit 211 and the output terminals of the second voltage conversion circuit 212, respectively, and the digital output port of the second ADC 34 is coupled to the controller 24. The controller 24 may use the second ADC 34 to obtain load link information X1 from the output terminals of the first voltage conversion circuit 211, and may use the second ADC 34 to obtain load link information X2 from the output terminals of the second voltage conversion circuit 212. The second ADC34 performs analog-to-digital conversion separately on load link information X1 and load link information X2 to obtain two digital signals, and outputs the two digital signals sequentially in a specific order to the controller 24 through the digital output port of the second ADC34. The controller 24 can obtain load link information X1 and load link information X2 by analyzing them in a specific order. The controller 24 can determine a control signal Z1 based on load link information X1 and backlight sampling voltage Y1, and output the control signal Z1 to the first voltage conversion circuit 211. The controller 24 can determine a control signal Z2 based on load link information X2 and backlight sampling voltage Y2, and output the control signal Z2 to the second voltage conversion circuit 212. When the controller 24 has an analog-to-digital conversion interface (in other words, analog signals can be directly input), or the analog-to-digital conversion interface of the controller 24 Resources When sufficient, the second ADC34 can be the analog-to-digital conversion interface of the controller 24.

[0178] In addition, the second ADC34 and ADC32 may be ADCs having four analog inputs and one digital output. The four analog input ports of the ADC may be coupled to the output terminals of the first voltage conversion circuit 211, the output terminals of the second voltage conversion circuit 212, the output terminals of the first photoelectric detection circuit 231, and the output terminals of the second photoelectric detection circuit 232, respectively. 32 teeth, Second ADC3 4 The load link information X1, load link information X2, backlight sampling voltage Y1, and backlight sampling voltage Y2 can be output to the controller 24 in a specific order through the digital output port. The controller 24 can obtain the load link information X1, load link information X2, backlight sampling voltage Y1, and backlight sampling voltage Y2 by analyzing them in a specific order. This can reduce the number of ADCs, lower costs, improve integration, and facilitate miniaturization of the optoelectronic assembly.

[0179] In yet another possible implementation shown in Figure 14 based on Figure 2, the voltage conversion circuit 21 further has an information output terminal, which is coupled to the information input terminal of the controller 24, and the information output terminal is configured to output load link information X to the controller 24.

[0180] In yet another possible implementation shown in Figure 15 based on Figure 3, the voltage conversion circuit 21 further has an information output terminal, which is configured to output load link information X, where load link information X is an analog signal. When the controller 24 does not have an analog-to-digital conversion interface or a digital-to-analog conversion interface, or when the controller 24 has insufficient resources for analog-to-digital conversion interfaces and digital-to-analog conversion interfaces, the optoelectric assembly may further include a second ADC 34. The analog input port of the second ADC 34 is coupled to the information output terminal of the voltage conversion circuit 21, and the digital output port of the second ADC 34 is coupled to the input terminal of the controller 24. The second ADC 34 performs analog-to-digital conversion on the load link information X to obtain a digital signal and outputs the digital signal to the controller 24 through the digital output port of the second ADC 34.

[0181] In addition, the second ADCs 34 and 32 may be ADCs having two analog inputs and one digital output, the two analog input ports of the ADCs may be coupled to the information output terminal of the voltage conversion circuit 21 and the output terminal of the photoelectric detection circuit 23, respectively. The ADCs may output load link information X and backlight sampling voltage Y to the controller 24 in a specific order, and the controller 24 may obtain the load link information X and backlight sampling voltage Y by analyzing them in a specific order. This can reduce the number of ADCs, lower costs, improve integration, and facilitate miniaturization of the photoelectric assembly.

[0182] In addition, the photoelectric assembly may further include a temperature control drive circuit and a temperature control circuit. The temperature control drive circuit is configured to supply power to the temperature control circuit. The temperature control circuit is configured to perform temperature control (e.g., cooling or heating) on ​​the photoelectric semiconductor device 22 so that the photoelectric semiconductor device 22 operates at a preset operating temperature to increase the output optical power or extend the service life of the photoelectric semiconductor device 22. For example, the temperature control circuit may be a thermoelectric cooler (TEC).

[0183] As shown in Figure 16 based on Figure 2, in possible implementations, the photoelectric assembly may further include a temperature control drive circuit 41 and a temperature control circuit 42. A power supply 25 is configured to power the entire photoelectric assembly and may have at least three voltage output terminals to supply power supply voltage Vcc_a to the voltage conversion circuit 21, power supply voltage Vcc_b to the temperature control drive circuit 41, and power supply voltage Vcc_c to the controller 24. For example, the power supply 25 is located outside the entire photoelectric assembly and has three Power supply voltage Vcc_a, Vcc_b, and Vcc_c are supplied to the photoelectric assembly. The power supply voltages Vcc_a, Vcc_b, and Vcc_c may be the same or different, and the power supply voltage values ​​may be determined based on the current or voltage characteristics of the device coupled to the power supply 25. In addition, power supply voltage Vcc_c may be used to power other devices such as ADCs and DACs.

[0184] In addition, the value of the power supply voltage Vcc_a may be optimized and set based on the input output voltage change efficiency curve of the voltage conversion circuit 21 in order to improve the voltage conversion efficiency of the voltage conversion circuit 21 as much as possible. The value of the power supply voltage Vcc_b may be optimized and set based on the voltage, current, cooling capacity, heating capacity, cooling power consumption, heating power consumption, etc. of the temperature control drive circuit 41 and the temperature control circuit 42 in order to improve the power supply energy efficiency of the temperature control circuit 42. The value of the power supply voltage Vcc_c may be optimized and set based on the voltage, current, power consumption of devices such as the controller 24, ADC, and DAC in order to ensure the normal operation of the devices and improve system stability.

[0185] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0186] The power supply voltage Vcc_b may be in the range of 2V to 18V. For example, the power supply voltage Vcc_b may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_b may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_b may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0187] The power supply voltage Vcc_c may be in the range of 1.5V to 6V. For example, the power supply voltage Vcc_c may be in the range of 1.8V to 3.6V. Furthermore, the power supply voltage Vcc_c may be 3.3V. The deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0188] The voltage ripple obtained by filtering the bias voltage output from the voltage conversion circuit 21 is 50m V It is less than or equal to . Furthermore, the voltage ripple is less than or equal to 40mV. Furthermore, the voltage ripple is less than or equal to 30mV. Furthermore, the voltage ripple is less than or equal to 20mV. Furthermore, the voltage ripple is less than or equal to 10mV. Also, furthermore, the voltage ripple is less than or equal to 5mV. The smaller the voltage ripple, the smaller the current change in the optoelectronic semiconductor device caused by the voltage ripple, and the smaller the impact on the target optical power.

[0189] The following describes the coupling method between the power supply 25, the voltage conversion circuit 21, the temperature control drive circuit 41, and the controller 24, with reference to Figure 17. For the sake of clarity, please refer to the descriptions in the other attached drawings for the configuration, function, and coupling method of other functional modules.

[0190] In a possible implementation, as shown in Figure 17A, power supply 25 is configured to power the entire photoelectric assembly, and power supply 25 may have at least one voltage output terminal to supply the power supply voltage Vcc_a to the voltage conversion circuit 21, the temperature control drive circuit 41, and the controller 24. The value of the power supply voltage Vcc_a may be determined based on the current or voltage characteristics of the devices coupled to power supply 25. In addition, the power supply voltage Vcc_a may also be used to power other devices such as ADCs and DACs.

[0191] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be in the range of 2V to 6V. Furthermore, the power supply voltage Vcc_a may be in the range of 2V to 3.6V. Furthermore, the power supply voltage Vcc_a may be 3.3V. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0192] In another possible implementation, as shown in Figure 17B, power supply 25 is configured to power the entire photoelectric assembly and may have at least two voltage output terminals: one for supplying power supply voltage Vcc_a to the voltage conversion circuit 21 and the temperature control drive circuit 41, and another for supplying power supply voltage Vcc_c to the controller 24. Power supply voltages Vcc_a and Vcc_c may be the same or different, and the values ​​of the power supply voltages may be determined based on the current or voltage characteristics of the devices coupled to power supply 25. In addition, power supply voltage Vcc_c may also be used to power other devices such as ADCs and DACs.

[0193] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0194] The power supply voltage Vcc_c may be in the range of 1.5V to 6V. For example, the power supply voltage Vcc_c may be in the range of 1.8V to 3.6V. Furthermore, the power supply voltage Vcc_c may be 3.3V. The deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0195] In yet another possible implementation, as shown in Figure 17C, power supply 25 is configured to power the entire photoelectric assembly and may have at least two voltage output terminals: power supply voltage Vcc_a to supply voltage conversion circuit 21 and controller 24, and power supply voltage Vcc_b to temperature control drive circuit 41. Power supply voltages Vcc_a and Vcc_b may be the same or different, and the values ​​of the power supply voltages may be determined based on the current or voltage characteristics of the devices coupled to power supply 25. In addition, power supply voltage Vcc_a may also be used to power other devices such as ADCs and DACs.

[0196] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0197] The power supply voltage Vcc_b may be in the range of 2V to 18V. For example, the power supply voltage Vcc_b may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_b may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_b may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0198] In yet another possible implementation, as shown in Figure 17D, power supply 25 is configured to power the entire photoelectric assembly, and power supply 25 may have at least two voltage output terminals to supply power supply voltage Vcc_c to the temperature control drive circuit 41 and controller 24, and to supply power supply voltage Vcc_a to the voltage conversion circuit 21. Power supply voltages Vcc_a and Vcc_c may be the same or different, and the values ​​of the power supply voltages may be determined based on the current or voltage characteristics of the devices coupled to power supply 25. In addition, power supply voltage Vcc_c may also be used to power other devices such as ADCs and DACs.

[0199] The power supply voltage Vcc_a may be in the range of 1.8V to 18V. For example, the power supply voltage Vcc_a may be 3.3V, 5V, 12V, etc. The deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_a may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0200] The power supply voltage Vcc_c may be in the range of 1.5V to 6V. For example, the power supply voltage Vcc_c may be in the range of 1.8V to 3.6V. Furthermore, the power supply voltage Vcc_c may be 3.3V. The deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 20%. Furthermore, the deviation accuracy of the power supply voltage Vcc_c may be less than or equal to 10%. Moreover, the deviation accuracy of the power supply voltage may be less than or equal to 5%.

[0201] In various coupling methods between the power supply 25, voltage conversion circuit 21, temperature control drive circuit 41, and controller 24, the power supply voltage supplied by the power supply 25 is determined based on the load characteristics of the device coupled to the power supply 25. This can improve power supply energy efficiency, reduce power consumption, and improve system stability.

[0202] In addition, the voltage conversion circuit 21 may further have an enable terminal. When an enable signal is input from the enable terminal, the voltage conversion circuit 21 is enabled and outputs a bias voltage to the photoelectric semiconductor device 22 to drive the device to emit light or amplify light from the light source. When a disable signal is input from the enable terminal, the voltage conversion circuit 21 is disabled and does not output a bias voltage to the photoelectric semiconductor device 22, so the photoelectric semiconductor device 22 does not emit light or amplify light from the light source. Note that the enable signal and the disable signal may be signals of different levels.

[0203] For example, as shown in Figure 18 based on Figure 10, each of the first voltage conversion circuit 211 and the second voltage conversion circuit 212 may further have an enable terminal, and the enable terminals of all voltage conversion circuits 21 may be controlled separately by different pins of the controller 24, or centrally by the same pin of the controller 24. If the enable terminals of all voltage conversion circuits 21 are controlled separately by different pins of the controller 24, the controller 24 can enable or disable at least one of the first voltage conversion circuit 211 and the second voltage conversion circuit 212, i.e., separate control can be implemented for different load links, so that all optoelectronic semiconductor devices 22 are turned on or off separately. If the enable terminals of multiple voltage conversion circuits 21 are centrally controlled by the same pin of the controller 24, multiple optoelectronic semiconductor devices 22 can be turned on or off together. This saves pin resources of the controller 24.

[0204] Once the entire optoelectronic assembly is initialized, the controller 24 outputs a disable signal to disable all voltage conversion circuits 21 (at least one of the first voltage conversion circuit 211 and the second voltage conversion circuit 212). After outputting a pre-set control signal, the controller 24 outputs an enable signal to enable all voltage conversion circuits 21. Alternatively, during the initialization process of the controller 24, the disable signal can be input from the enable terminal of the voltage conversion circuit 21 based on a fixed high / low level as input, or via another logic gate circuit, so that the voltage conversion circuit 21 is disabled during the initialization process of the controller 24. Alternatively, the enable terminal of the voltage conversion circuit 21 may be coupled to a soft-start circuit. During the initialization process of the controller 24, after the soft-start circuit is powered on for soft startup, the soft-start circuit outputs an enable signal to enable the voltage conversion circuit 21, thereby turning on the optoelectronic semiconductor device 22. This avoids the excessively large bias voltage output by the voltage conversion circuit 21 caused by an unstable control signal Z during the initialization process. Otherwise, if the voltage conversion circuit 21 is enabled before the controller 24 outputs the control signal Z, the bias voltage output by the voltage conversion circuit 21 will not be controlled and may therefore become excessively large. As a result, the optoelectronic semiconductor device 22 in the load link may burn out. In addition, these methods can be combined.

[0205] As shown in Figure 19, if the photoelectric assembly shown in Figure 3 includes one voltage conversion circuit 21, and for example, if the controller 24 performs enable control to turn the voltage conversion circuit 21 on or off, the controller 24 may perform the following control methods on the photoelectric assembly.

[0206] S101: The controller 24 performs initialization after the photoelectric assembly is powered on.

[0207] S102: The controller 24 outputs a disable signal to the enable terminal of the voltage conversion circuit 21, thereby disabling the voltage conversion circuit 21.

[0208] S103: The controller 24 outputs a pre-set control signal to the feedback terminal of the voltage conversion circuit 21.

[0209] A pre-set control signal can control the voltage conversion circuit 21 to output a default bias voltage to the optoelectronic semiconductor device 22. The DAC 33 can perform digital-to-analog conversion on the pre-set control signal, and the feedback network 31 can increase or decrease the pre-set control signal.

[0210] S104: The controller 24 outputs an enable signal to the enable terminal of the voltage conversion circuit 21, thereby enabling the voltage conversion circuit 21.

[0211] The photoelectric semiconductor device 22 emits light or amplifies light from a light source, and the photoelectric detection circuit 23 outputs a backlight sampling voltage Y.

[0212] S105: The controller 24 obtains the backlight sampling voltage Y from the photoelectric detection circuit 23, calculates the photocurrent of the photoelectric detection circuit 23 based on the backlight sampling voltage Y, and further calculates the optical power of the photoelectric semiconductor device 22 to determine whether the optical power meets the requirements.

[0213] If the requirements are met, step S106 is executed and then step S105 is executed again; otherwise, step S107 is executed and then step S105 is executed again to implement dynamic real-time APC.

[0214] S106: The controller 24 maintains the previously outputted control signal Z.

[0215] In this step, the bias voltage output by the voltage conversion circuit 21 is stabilized within a specific range, and furthermore, the output optical power output by the optoelectronic semiconductor device 22 is stabilized within a specific range.

[0216] S107: The controller 24 acquires a control signal Z based on the backlight sampling voltage Y and outputs the control signal Z to the feedback terminal of the voltage conversion circuit 21.

[0217] In this step, the bias voltage output by the voltage conversion circuit 21 changes, thereby changing the output optical power output by the optoelectronic semiconductor device 22.

[0218] As shown in Figure 20, when the photoelectric assembly shown in Figure 18 includes multiple voltage conversion circuits 21, the controller 24 may perform the following control methods on the photoelectric assembly.

[0219] S201: Controller 24 performs initialization after the photoelectric assembly is powered on.

[0220] S202: The controller 24 outputs a disable signal 1 to the enable terminal of the first voltage conversion circuit 211, thereby disabling the first voltage conversion circuit 211. 2 This is output to the enable terminal of the second voltage conversion circuit 212, thereby disabling the second voltage conversion circuit 212.

[0221] S203: The controller 24 outputs a preset control signal to the feedback terminal of the first voltage conversion circuit 211 and the feedback terminal of the second voltage conversion circuit 212.

[0222] A preset control signal output by the controller 24 to the feedback terminal of the first voltage conversion circuit 211 can control the first voltage conversion circuit 211 to output a preset bias voltage to the first optoelectronic semiconductor device 221. A preset control signal output by the controller 24 to the feedback terminal of the second voltage conversion circuit 212 can control the second voltage conversion circuit 212 to output a preset bias voltage to the second optoelectronic semiconductor device 222. The two preset control signals may be the same or different. The two preset control signals may be transmitted to the DAC 33 in a specific order, and the DAC 33 may perform digital-to-analog conversion on the two preset control signals, or the two preset control signals may be increased or decreased by the first feedback network 311 and the second feedback network 312, respectively.

[0223] S204: The controller 24 outputs enable signal 1 to the enable terminal of the first voltage conversion circuit 211 to enable the first voltage conversion circuit 211, and outputs enable signal 2 to the enable terminal of the second voltage conversion circuit 212 to enable the second voltage conversion circuit 212.

[0224] The first photoelectric semiconductor device 221 emits light or amplifies light from a light source, and the first photoelectric detection circuit 231 outputs a backlight sampling voltage Y1. The second photoelectric semiconductor device 222 emits light or amplifies light from a light source, and the second photoelectric detection circuit 232 outputs a backlight sampling voltage Y2. The ADC 32 can perform analog-to-digital conversion on the backlight sampling voltages Y1 and Y2, and the signals obtained through the analog-to-digital conversion are then output to the controller 24 in a specific order.

[0225] S205: The controller 24 obtains the backlight sampling voltage from the photoelectric detection circuit of the i-th APC loop, calculates the photocurrent of the photoelectric detection circuit of the i-th APC loop based on the backlight sampling voltage, and further calculates the optical power of the photoelectric semiconductor device of the i-th APC loop to determine whether the optical power meets the requirements.

[0226] For example, the photoelectric assembly shown in Figure 18 includes two APC loops, where the value of i may be 1 or 2. In the first APC loop, the controller 24 obtains a backlight sampling voltage Y1 from the first photoelectric detection circuit 231, calculates the photocurrent of the first photoelectric detection circuit 231 based on the backlight sampling voltage Y1, and further calculates the optical power of the first photoelectric semiconductor device 221 to determine whether the optical power meets the requirements. In the second APC loop, the controller 24 obtains a backlight sampling voltage Y2 from the second photoelectric detection circuit 232, calculates the photocurrent of the second photoelectric detection circuit 232 based on the backlight sampling voltage Y2, and further calculates the optical power of the second photoelectric semiconductor device 222 to determine whether the optical power meets the requirements.

[0227] If the requirements are met, step S205 is executed again after step S206 is executed, or if the requirements are not met, step S205 is executed again after step S207 is executed to implement dynamic real-time APC for the i-th APC loop.

[0228] If the output optical power output by one APC loop meets the requirements, but the output optical power output by another APC loop does not, the controller 24 may set a software delay so that the two APC loops enter step S205 again simultaneously after different step procedures, simplifying the design of the program control algorithm and implementing synchronization of different APC loops.

[0229] Alternatively, the controller 24 may synchronize the two APC loops when outputting control signals Z from different APC loops to the DAC 33. The controller 24 converts the two parallel control signals Z into a serial signal according to a specific rule and outputs the serial signal to the DAC 33. The DAC 33 decomposes and converts the serial digital signal into two analog signals according to the corresponding rule and outputs the two analog signals separately to the feedback terminal of the first feedback network 311 and the feedback terminal of the second feedback network 312.

[0230] S206: Controller 24 maintains the previously outputted control signal Zi for the i-th APC loop.

[0231] In this step, the bias voltage output by the voltage conversion circuit 21 of the i-th APC loop is stabilized within a specific range, and furthermore, the output optical power output by the optoelectronic semiconductor device 22 of the i-th APC loop is stabilized within a specific range.

[0232] S207: The controller 24 acquires a control signal based on the backlight sampling voltage output by the photoelectric detection circuit of the i-th APC loop and outputs the control signal Zi to the feedback terminal of the voltage conversion circuit of the i-th APC loop.

[0233] In this step, the bias voltage output by the voltage conversion circuit 21 of the i-th APC loop changes, thereby changing the output optical power output by the optoelectronic semiconductor device 22 of the i-th APC loop.

[0234] For example, in the first APC loop, the controller 24 acquires a control signal Z1 based on the backlight sampling voltage Y1 and outputs the control signal Z1 to the feedback terminal of the first voltage conversion circuit 211. In the second APC loop, the controller 24 acquires a control signal Z2 based on the backlight sampling voltage Y2 and outputs the control signal Z2 to the feedback terminal of the second voltage conversion circuit 212.

[0235] The control method can be extended to scenarios with multiple APC loops. This allows for the implementation of independent control for each APC loop.

[0236] According to the control method for an optoelectronic assembly provided in the embodiments of this application, when the controller is initialized, the voltage conversion circuit is first disabled, and then the voltage conversion circuit is enabled after the controller outputs a control signal to the voltage conversion circuit. Alternatively, in the controller initialization process, the voltage conversion circuit may be disabled based on a fixed high / low level as an input, or via another logic gate circuit. Alternatively, in the controller initialization process, the voltage conversion circuit may be enabled via a soft-start circuit to turn on the optoelectronic semiconductor device. In this way, the optoelectronic semiconductor device can be prevented from burning out due to unstable control signals in the initialization process and excessively high bias voltages output by the voltage conversion circuit.

[0237] It should be understood that the sequence numbers of the processes described above do not represent the execution order in the embodiments of this application. The execution order of these processes should be determined based on the function and internal logic of the processes and should not constitute any limitation on the implementation method of the embodiments of this application.

[0238] Those skilled in the art will recognize, in combination with the examples described in the embodiments disclosed herein, that modules and algorithmic steps may be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on the specific application and the design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementations should not be considered to be beyond the scope of this application.

[0239] For the sake of a simple and concise explanation, it will be readily apparent to those skilled in the art that the detailed operation of the aforementioned systems, devices, and modules can be described by referring to the corresponding processes in the method embodiments described above, and such details are not described again herein.

[0240] In some embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the described device embodiments are merely examples. For example, the division into modules is merely a logical functional division, and other divisions may be used in actual implementation. For example, multiple modules or components may be combined or integrated to form a separate device, or some features may be ignored or not implemented. In addition, the mutual coupling, direct coupling, or communication connection shown or discussed may be implemented through some interfaces. Indirect coupling or communication connection between devices or modules may be implemented in electrical, mechanical, or other forms.

[0241] Modules described as separate parts may or may not be physically separated, and parts shown as modules may or may not be physical modules, and may be located on one device or distributed across multiple devices. Some or all of the modules may be selected based on the actual requirements for achieving the objectives of the solution of the embodiment.

[0242] In addition, the functional modules in the embodiments of this application may be integrated into a single device, or each module may exist physically independently, or two or more modules may be integrated into a single device.

[0243] All or part of the embodiments described above may be implemented by software, hardware, firmware, or any combination thereof. If a software program is used to implement an embodiment, all or part of the embodiment may be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When a computer program instruction is loaded into a computer and executed, all or part of the procedures or functions according to the embodiments of this application are generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or another programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, fiber optic cable, or Digital Subscriber Line (DSL)) or wireless (e.g., infrared, radio, or microwave) means. Computer-readable storage media may be any available media accessible by a computer, or a data storage device such as a server or data center that integrates one or more available media. Available media may be magnetic media (e.g., floppy disks, hard disk drives, or magnetic tapes), optical media (e.g., DVDs), semiconductor media (e.g., solid-state drives (SSDs)), or similar.

[0244] The foregoing description merely outlines a specific implementation of the present application and is not intended to limit the scope of protection of this application. Any modifications or substitutions readily conceivable by a person skilled in the art within the technical scope disclosed in this application shall fall within the scope of protection of this application. Accordingly, the scope of protection of this application shall be determined by the scope of protection of the claims.

Claims

1. A photoelectric assembly comprising a voltage conversion circuit, a photoelectric semiconductor device, a photoelectric detection circuit, and a controller, The voltage conversion circuit is configured to supply a bias voltage to the photoelectric semiconductor device and adjust the output optical power output by the photoelectric semiconductor device by changing the bias voltage, wherein the differential resistance Rdiff of the photoelectric semiconductor device within the range of the target optical power satisfies 0.1Ω ≤ Rdiff ≤ 50Ω, and the differential resistance is the ratio of the voltage fluctuation to the current fluctuation corresponding to the voltage fluctuation. The photoelectric detection circuit is configured to detect the output optical power output by the photoelectric semiconductor device and to output a detection signal to the controller. The controller is configured to determine a control signal based on the detection signal and output the control signal to the voltage conversion circuit, and the control signal is used to adjust the bias voltage in the photoelectric assembly.

2. The differential resistance Rdiffsub of the optoelectronic semiconductor device within the subrange of the target optical power, and the average differential resistance Rdiffavg within the range of the target optical power, satisfy max(0.02 * Rdiffavg, 0.1Ω) ≤ Rdiffsub ≤ min(50 * Rdiffavg, 50Ω), max(0.02*Rdiffavg, 0.1Ω) represents the larger of 0.02*Rdiffavg and 0.1Ω, and min(50*Rdiffavg, 50Ω) represents the smaller of 50*Rdiffavg and 50Ω. The photoelectric assembly according to claim 1, wherein the mean differential resistance Rdiffavg represents the ratio of the bias voltage fluctuation to the current fluctuation corresponding to the lower and upper limits of the optical power of the photoelectric semiconductor device within the range of the target optical power.

3. The photoelectric assembly according to claim 1 or 2, wherein the photoelectric semiconductor device is a light source, and the resistance of the light source is less than 60 Ω or equal to 60 Ω within the range of the target light power.

4. The photoelectric assembly according to claim 1 or 2, wherein the photoelectric semiconductor device is an optical amplifier, and the resistance of the optical amplifier is less than 60 Ω or equal to 60 Ω within the range of the target optical power.

5. The photoelectric assembly according to claim 3 or 4, wherein the voltage conversion circuit is a unique bias adjustment circuit for the photoelectric semiconductor device.

6. The photoelectric assembly according to any one of claims 1 to 5, wherein the bit width of the digital signal processed by the controller is greater than or equal to 6 bits.

7. The aforementioned controller, Enable or disable the aforementioned voltage conversion circuit. The photoelectric assembly according to any one of claims 1 to 6, further configured as follows.

8. The aforementioned controller, The photoelectric assembly according to any one of claims 1 to 7, configured to acquire load link information and determine the control signal based on the load link information and the detection signal, wherein the load link information comprises the value of the bias voltage.

9. The photoelectric assembly according to any one of claims 1 to 8, further comprising a temperature control drive circuit and a temperature control circuit, wherein the temperature control drive circuit is configured to supply power to the temperature control circuit, and the temperature control circuit is configured to perform temperature control on the photoelectric semiconductor device.

10. The photoelectric assembly according to claim 9, wherein the power supply voltage input by the temperature control drive circuit ranges from 2V to 18V.

11. The photoelectric assembly according to any one of claims 1 to 10, wherein the power supply voltage input by the voltage conversion circuit ranges from 1.8V to 18V.

12. The photoelectric assembly according to any one of claims 1 to 11, wherein the power supply voltage input by the controller ranges from 1.5V to 6V.

13. The photoelectric assembly according to any one of claims 1 to 12, wherein the voltage ripple obtained by performing filtering on the bias voltage output by the voltage conversion circuit is less than 50 mV or equal to 50 mV.

14. The voltage conversion circuit comprises a first voltage conversion circuit and a second voltage conversion circuit, the photoelectric semiconductor device comprises a first photoelectric semiconductor device and a second photoelectric semiconductor device, and the photoelectric detection circuit comprises a first photoelectric detection circuit and a second photoelectric detection circuit. The first photoelectric detection circuit is configured to detect the output optical power output by the first photoelectric semiconductor device and to output a first detection signal to the controller. The second photoelectric detection circuit is configured to detect the output optical power output by the second photoelectric semiconductor device and to output a second detection signal to the controller. The photoelectric assembly according to any one of claims 1 to 13, wherein the controller is configured to determine a first control signal based on a first detection signal and send the first control signal to a first voltage conversion circuit, the first control signal being used to adjust the bias voltage supplied to the first photoelectric semiconductor device, and to determine a second control signal based on a second detection signal and send the second control signal to a second voltage conversion circuit, the second control signal being used to adjust the bias voltage supplied to the second photoelectric semiconductor device.

15. The aforementioned photoelectric assembly further comprises a digital-to-analog converter, The controller is configured to continuously send the first control signal and the second control signal to the digital-to-analog converter. The photoelectric assembly according to claim 14, wherein the digital-to-analog converter is configured to perform digital-to-analog conversion in the first control signal and output the signal obtained through the digital-to-analog conversion to the first voltage conversion circuit, and to perform digital-to-analog conversion in the second control signal and output the signal obtained through the digital-to-analog conversion to the second voltage conversion circuit.

16. The optical-electric assembly according to claim 15, wherein the bit width of the digital-to-analog converter is greater than or equal to 6 bits.

17. The photoelectric semiconductor device comprises a first photoelectric semiconductor device and a second photoelectric semiconductor device, and the photoelectric detection circuit comprises a first photoelectric detection circuit and a second photoelectric detection circuit. The first photoelectric detection circuit is configured to detect the output optical power output by the first photoelectric semiconductor device and to output a first detection signal to the controller. The second photoelectric detection circuit is configured to detect the output optical power output by the second photoelectric semiconductor device and to output a second detection signal to the controller. The photoelectric assembly according to any one of claims 1 to 13, wherein the controller is configured to determine the control signal based on the first detection signal and the second detection signal, and to send the control signal to the voltage conversion circuit, the control signal being used to adjust the bias voltage provided to the first photoelectric semiconductor device and the bias voltage provided to the second photoelectric semiconductor device.

18. The photoelectric assembly according to any one of claims 14 to 17, further comprising an analog-to-digital converter, wherein the analog-to-digital converter is configured to perform an analog-to-digital conversion on a first detection signal, perform an analog-to-digital conversion on a second detection signal, and continuously output the first detection signal and the second detection signal obtained through the analog-to-digital conversion to the controller.

19. The optical-electric assembly according to claim 18, wherein the bit width of the analog-to-digital converter is greater than or equal to 6 bits.

20. The photoelectric assembly according to any one of claims 1 to 19, further comprising a feedback network, wherein the feedback network is configured to increase or decrease the voltage range of the control signal.

21. The feedback network comprises a first resistor, a second resistor, and a third resistor, the second end of the first resistor being grounded, the first end of the first resistor, the second end of the second resistor, and the first end of the third resistor being coupled to the feedback terminal of the voltage conversion circuit, the first end of the second resistor being coupled to the output terminal of the voltage conversion circuit, and the second end of the third resistor being coupled to the output terminal of the controller. The photoelectric assembly according to claim 20, wherein the output terminal of the controller is configured to output the control signal, and the feedback terminal of the voltage conversion circuit is configured to receive the control signal, which increases or decreases the voltage range.

22. The photoelectric assembly according to any one of claims 1 to 21, wherein the voltage conversion circuit is a DC-DC conversion circuit.

23. The photoelectric assembly according to any one of claims 1 to 22, wherein the photoelectric assembly is a light source or an optical amplifier separated from the optical modulator.

24. A light source pool comprising at least one photoelectric assembly according to any one of claims 1 to 23.

25. An optoelectric switching device comprising at least one of the photoelectric assembly described in any one of claims 1 to 23 or the light source pool described in claim 24, an optical modulator, and a switching chip, wherein the photoelectric assembly or the light source pool is configured to output light, and the switching chip is configured to control the optical modulator to modulate the light.

26. The photoelectric switching device according to claim 25, wherein the photoelectric switching device comprises a first controller, the first controller is configured to output a signal to a controller in the photoelectric assembly to adjust the output optical power output by the photoelectric assembly, or to output a signal to a controller in the light source pool to adjust the output optical power output by the light source pool.

27. A control method for a photoelectric assembly, applicable to the photoelectric assembly described in any one of claims 1 to 23, wherein the method is: A step of receiving a detection signal from a photoelectric detection circuit in the photoelectric assembly, wherein the detection signal indicates the output optical power output by a photoelectric semiconductor device in the photoelectric assembly. A step of determining a control signal based on the detection signal and sending the control signal to a voltage conversion circuit in the photoelectric assembly, wherein the control signal is used to adjust the bias voltage. A control method for a photoelectric assembly, including the following.

28. The steps of disabling the voltage conversion circuit, outputting a pre-set control signal to the voltage conversion circuit, and enabling the voltage conversion circuit. The method according to claim 27, further comprising:

29. The aforementioned method, A step of acquiring load link information, wherein the load link information includes the value of the bias voltage. It further includes, The method according to claim 27 or 28, wherein the step of determining a control signal based on the detection signal includes the step of determining the control signal based on the load link information and the detection signal.

30. A step of continuously sending a first control signal and a second control signal to a digital-to-analog converter in the photoelectric assembly, wherein the first control signal is used to adjust the bias voltage supplied to a first photoelectric semiconductor device, and the second control signal is used to adjust the bias voltage supplied to a second photoelectric semiconductor device. The method according to any one of claims 27 to 29, further comprising:

31. A step of determining a control signal based on a first detection signal and a second detection signal, and sending the control signal to the voltage conversion circuit, wherein the control signal is used to adjust the bias voltage supplied to a first optoelectronic semiconductor device and the bias voltage supplied to a second optoelectronic semiconductor device, the first detection signal indicates the output optical power output by the first optoelectronic semiconductor device, and the second detection signal indicates the output optical power output by the second optoelectronic semiconductor device. The method according to any one of claims 27 to 29, further comprising:

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