Hybrid power control for short-range wireless communication systems

Abstract

To provide hybrid power control for short-range wireless communication systems. [Solution] The method comprises the steps of controlling a short-range wireless communication assembly of a computing device during a sequence of multiple periods, each period having a polling sub-period, and performing the control by transmitting a first polling signal from the short-range wireless communication assembly during a first period in the sequence according to a first power level during the polling sub-period of the first period, and by transmitting a second polling signal from the short-range wireless communication assembly during a second period in the sequence according to a second power level during the polling sub-period of the second period.

Description

Background Art

[0001]

[0001] In some computing devices, a near-field communication (NFC) antenna may be placed physically close to an electromagnetic field-sensitive component, such as a display panel. The operation of the NFC antenna in such a device can affect the performance of the display, leading to, for example, visual artifacts.

Summary of the Invention

[0002]

[0002] The accompanying drawings, in which like reference numerals refer to the same or functionally similar elements throughout the separate views, are incorporated herein and form a part of this specification, along with the following detailed description, and further illustrate embodiments of the concepts including the claimed invention and serve to explain the various principles and advantages of those embodiments.

Brief Description of the Drawings

[0003] [Figure 1]

[0003] A diagram of a computing device. [Figure 2]

[0004] A diagram of a near-field communication (NFC) control cycle. [Figure 3]

[0005] A flowchart of a method for hybrid NFC power control in the device of FIG. 1. [Figure 4]

[0006] A diagram showing exemplary configuration data employed in the method of FIG. 3. [Figure 5]

[0007] A diagram showing an exemplary execution of the method of FIG. 3.

Modes for Carrying Out the Invention

[0004]

[0008] Those skilled in the art will understand that the elements in the figures are shown for conciseness and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated compared to others in order to help improve the understanding of embodiments of the invention.

[0005]

[0009] Components of the apparatus and methods are represented in the drawings by conventional symbols where appropriate, and only specific details relevant to understanding embodiments of the invention are shown so as not to obscure this disclosure with details that would be readily apparent to a person of ordinary skill in the art who would benefit from the description herein.

[0006]

[0010] Examples disclosed herein include a method for controlling a short-range wireless communication assembly of a computing device during a sequence of periods, each period having a polling sub-period, wherein during a first period in the sequence, the short-range wireless communication assembly transmits a first polling signal according to a first power level during the polling sub-period of the first period, and during a second period in the sequence, the short-range wireless communication assembly transmits a second polling signal according to a second power level during the polling sub-period of the second period.

[0007]

[0011] Further examples disclosed herein relate to a computing device comprising a short-range wireless communication assembly including an antenna and a processor configured to control the short-range wireless communication assembly during a sequence of periods, each period having a polling sub-period, wherein the processor performs the control by transmitting a first polling signal from the short-range wireless communication assembly during a first period in the sequence according to a first power level during the polling sub-period of the first period, and by transmitting a second polling signal from the short-range wireless communication assembly during a second period in the sequence according to a second power level during the polling sub-period of the second period.

[0008]

[0012] Figure 1 shows a computing device 100, such as a mobile computer or smartphone. Device 100 can be implemented in various other form factors, including tablet computers, laptop computers, barcode scanners, and RFID readers.

[0009]

[0013] Specific internal components of device 100 are shown in Figure 1. Device 100 includes a processor 104, such as a central processing unit (CPU) and a graphics processing unit (GPU), connected to a non-temporary computer-readable medium, such as memory 108. The processor 104 and memory 108 are implemented as one or more integrated circuits (ICs). Device 100 also includes a communication interface 112 that enables communication between device 100 and other computing devices via appropriate wired and / or wireless links, including any appropriate combination of local area networks, wide area networks, and peer-to-peer links.

[0010]

[0014] Device 100 further includes a display 116, such as an organic light-emitting diode (OLED) based display panel or other suitable panel. The display 116 is controllable by the processor 104 to present various information, for example, for viewing by an operator of device 100. In some examples, device 100 may also include other output devices (for example, devices configured to produce an output perceptible to an operator of device 100), such as a speaker or a motor for tactile output. Device 100 further includes an input device 120 configured to receive input from an operator of device 100. The input device 120 may include any one of the following, or any combination thereof, a keypad, a touchscreen (for example, integrated with the display 116), a microphone, etc.

[0011]

[0015] Device 100 also includes a short-range wireless communication assembly 124, such as a near-field communication (NFC) assembly. The short-range wireless communication assembly 124 is configured to facilitate short-range (e.g., over a distance of less than approximately 10 cm) exchange of information between Device 100 and other computing devices, such as payment terminals or other mobile computers. Assembly 124 can also enable Device 100 to read data from items such as smart payment cards. Assembly 124 includes a controller 128 and an antenna 132. The controller 128 can be configured to transmit and receive data via the antenna 132 at a frequency of approximately 13.5 MHz. Data received via the antenna 132 can be provided by the controller 128 to the processor 104, and data can be received from the processor 104 to the controller 128 for transmission via the antenna 132. The controller 128 can be implemented as a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC), among others. In some cases, the controller 128 can be implemented by the processor 104 (for example, as a dedicated hardware part of the processor 104, or in software).

[0012]

[0016] The components of device 100 can be supported by the housing 136. For example, as shown in section S1 (simplified for illustrative purposes), the housing 136 can support the display 116 (and the input unit 120, if the input unit 120 includes a touchscreen), and the interior of the device enclosed by the housing 136 and the display 116 can contain other components of device 100. For example, device 100 can include a mainboard such as one printed circuit board (PCB) or multiple PCBs that hold the processor 104, memory 108, and communication interface 112. In some examples, board 140 can also hold the controller 128.

[0013]

[0017] In this example, antenna 132 is positioned "behind" the display 116, for example, between the display 116 and the main board 140. Antenna 132 can be configured to radiate through the display 116 rather than away from the display 116 through the back surface 144 of the housing 136. As will be understood by those skilled in the art, the display 116 can include multiple layers of conductive material. If the input section 120 includes a touchscreen, the touchscreen can also be implemented as one or more additional layers of conductive material between antenna 132 and the front surface of device 100. Thus, the display 116 (and, in some examples, the touchscreen) may attenuate the radiation emitted by antenna 132. Attenuation of radiation from antenna 132 may adversely affect the performance of assembly 124, for example, by reducing the effective range of assembly 124. An approach to mitigating such performance impacts is to increase the transmission power applied to antenna 132 (for example, by controller 128). However, due to the relatively low operating frequency of antenna 132 (compared to, for example, the operating frequency of a cellular or wireless local area network antenna employed by interface 112, which is close to or several GHz), transmissions from antenna 132 may interfere with the display 116, causing, for example, flickering, ghosting, or other visual artifacts.

[0014]

[0018] In other words, improving the performance of antenna 132 may negatively impact the performance of display 116, and avoiding such negative impacts may instead impact the performance of antenna 132. Therefore, device 100 is configured to implement a hybrid power control mechanism for antenna 132, as discussed below. The processor 104 and / or controller 128 are configured to apply separate power levels to antenna 132 at separate time intervals. The control mechanism discussed herein mitigates the negative impact on NFC operation to display 116 for at least some periods by operating antenna 132 at reduced power. For other periods, device 100 operates antenna 132 at increased power for periods that are short enough and / or sufficiently spaced so that visual artifacts on display 116 caused by antenna 132 are avoided or less perceptible.

[0015]

[0019] Memory 108 stores multiple applications executable by processor 104, including an NFC control application 148. The execution of the NFC control application 148 by processor 104 configures processor 104 to perform various actions to bring about hybrid power control for assembly 124. In some examples, the functionality described below as being performed by application 148 can be performed by controller 128 instead of processor 104. For example, application 148 can be implemented in the firmware of controller 128. In other examples, the functionality of application 148 can be implemented in a separate hardware element, such as another ASIC or FPGA, that is decoupled from processor 104 and controller 128.

[0016]

[0020] Before discussing the functionality performed by device 100, an exemplary NFC control mechanism is shown in Figure 2. An NFC assembly, such as assembly 124, can be configured, upon activation, to repeat a polling cycle, for example, according to specifications established by the NFC Forum. Assembly 124 can be configured to transmit a polling signal and monitor for any response to the polling signal and / or any polling signals from other devices over a period 200, three examples of period 200, 200-1, 200-2, and 200-3, are shown in Figure 2. During each period 200, assembly 124 can repeat the same set of actions. In this example, period 200-1 is shown in detail on the right side of Figure 2. Period 200-1 includes a polling portion 204-1, during which assembly 124 is configured to transmit one or more polling signals via antenna 132 and monitor for any response to such polling signals from, for example, a payment card. Period 200-1 also includes emulation sub-period 208-1.

[0017]

[0021] The polling section 204-1 can be subdivided into polling sub-periods 212 and listening sub-periods 216. In this example, each period 200 includes five polling sub-periods 212 and five listening sub-periods 216. Each pair of polling sub-periods 212 and listening sub-periods 216 can be configured to detect and / or receive data from nearby devices or items implementing various NFC standards (e.g., NFC Type A, Type B, Type F, or 424 kbit / s FeliCa®, Type F, or 212 kbit / s FeliCa®). The detailed diagram on the right of Figure 2 shows the power levels applied to the antenna 132 by the controller 128 during each sub-period. That is, during the polling sub-period 212, the controller 128 can apply a first power level 220, e.g., default or maximum design power, to the antenna 132. During the listening sub-period 216, the antenna 132 can be passive (i.e., no power is applied to the antenna 132). The controller 128, in other words, can apply an idle power level 224 to the antenna 132 during the listening sub-period. The idle power level can be zero in some examples, but does not need to be strictly zero.

[0018]

[0022] During the emulation sub-period 208-1 of period 200-1, assembly 124 can be configured to monitor or listen for external polling signals from another device, for example, performing the polling portion 204-1. In other words, during the polling sub-period 212 and listening sub-period 216, device 100 searches for a nearby NFC device, such as a payment card. During the emulation sub-period 208-1, device 100 emulates a payment card, etc., and waits for polling signals from a nearby reader device (if any polling signals are present). Thus, the idle power level 224 is also used during the emulation sub-period 208-1.

[0019]

[0023] The length of time occupied by the polling portion 204-1 and the emulation sub-period 208-1 can be defined by any appropriate standard. In this example, the total length of period 200-1 can be approximately 600 ms, with the polling portion occupying approximately 150 ms and the emulation sub-period 208-1 occupying approximately 450 ms. Each pair of polling sub-period 212 and listening sub-period can occupy approximately 30 ms. However, various other configurations can also be applied.

[0020]

[0024] Once period 200-1 is complete, assembly 124 can be configured to repeat the configuration shown above during periods 200-2, 200-3, etc., until assembly 124 is deactivated (e.g., put into sleep state, disabled, etc.). In this configuration, the power levels applied to antenna 132 during each polling sub-period 212 can be substantially equal and equivalent to the default or maximum design power for assembly 124. In other examples, as discussed below, device 100 is configured to use separate power levels during different periods to mitigate performance adverse effects on display 116 and / or assembly 124.

[0021]

[0025] Referring to Figure 3, a hybrid power control method 300 for short-range wireless communication is shown. Method 300 is described in relation to the execution of Method 300 in device 100, in particular by the processor 104, via the execution of application 148.

[0022]

[0026] In block 305, device 100 is configured to activate assembly 124. Block 305 can be executed, for example, when device 100 is powered on or when an application or other function of device 100 requires enabling assembly 124 (such as to initiate a payment transaction). When assembly 124 is activated, device 100 (such as processor 104 configured via execution of application 148) can be configured to obtain an NFC control sequence that defines a plurality of periods each having at least one polling sub-period.

[0023]

[0027] The control mechanism shown in FIG. 2 uses the same configuration for each successive period 200 (such as in that assembly 124 uses the same power level 220 for the polling signal transmitted during polling sub-period 212 in each period 200), while the control sequence obtained in block 305 defines distinct period configurations and the pattern followed when those period configurations are implemented by assembly 124. The control sequence can be obtained in block 305, for example, by retrieval from memory 108. In other examples, the control sequence can be encoded in application 148 or stored in a memory element of controller 128. Storing the control sequence in memory 108, for example, in the form of a configuration file, can facilitate the deployment of the operation of various short-range wireless communication assemblies across different devices (such as having various form factors, display hardware, etc.) without necessarily requiring modification to assembly 124. For example, a plurality of devices 100 having different housings 136, displays 116, etc. can be configured to control assembly 124 according to model-specific configuration files, even if those devices use the same type of assembly 124.

[0024]

[0028] Figure 4 shows two exemplary configuration data sets 400a and 400b (collectively referred to as configuration data 400) that can be obtained in block 305. Various other forms of configuration data will also be conceivable to those skilled in the art. Configuration data 400a specifies a first power level and a second power level. In this example, the first power level is a “low” power level, selected to mitigate or avoid interference to the display 116 when antenna 132 is transmitting. The second power level is a “high” power level, which may correspond to a default power level (for example, the maximum power level that controller 128 is designed to apply to antenna 132). In this example, the power levels are expressed as voltages applied to antenna 132, but in other examples, other forms of power level specifications may be used. In this example, the low power level configures controller 128 to apply 2.6V to antenna 132, and the high power level configures controller 128 to apply 5.6V to antenna 132. The specific voltages defined in configuration data 400a may vary depending on the specific embodiment.

[0025]

[0029] The configuration data 400a further defines the number of periods for each control sequence, and the association between each period and one of the first power level and the second power level. Each period corresponds to one cycle of a polling portion (i.e., at least one polling sub-period and at least one listening sub-period) and an emulation sub-period. In this example, the configuration data 400a includes a count "5" indicating the number of periods in the control sequence. In other examples, such a count can be omitted, as described below in relation to the configuration data 400b. Thus, the sequence defined by the configuration data 400a includes five periods, each of which has a length (e.g., 600 ms as described above) implemented by the assembly 124 according to the appropriate standard. In other examples, the duration of the period can also be specified in the configuration data 400a.

[0026]

[0030] Configuration data 400a further indicates which periods in the sequence correspond to lower power levels and which periods correspond to higher power levels. In other words, configuration data 400a specifies a pattern of which power levels should be applied to antenna 132 during which periods in order to generate a polling signal. In this example, configuration data 400a is a control sequence 402a having a length of five periods, of which the first three periods 404-1, 404-2, and 404-3 are low-power periods (i.e., periods in which a first, i.e., "low" power level is used), and the remaining two periods 408-4 and 408-5 are high-power periods (i.e., periods in which a second, i.e., "high" power level is used). Control sequence 402a, in other words, includes two types of periods, one type labeled 404 and the other type labeled 408. The suffixed numbers indicate the position of each period in time. That is, period 404-1 can have a duration of 600 ms, and therefore period 404-2 can start at the end of period 404-1 and continue for another 600 ms (ending 1.2 seconds after the entire control sequence has started).

[0027]

[0031] Configuration data 400b also defines the control sequence 402b by specifying low power and high power values ​​and power levels for each period, as described above. In this example, configuration data 400b indicates that the first and third periods 408-1 and 408-3 are associated with high power levels, and that the second and fourth periods 404-2 and 404-4 are associated with low power levels. Therefore, the control sequence 402b has a length of four periods (for example, a total length of 2.4s in this example).

[0028]

[0032] As will be understood by those skilled in the art, various configuration data 400 can be deployed to any given device 100, such as specifying a control sequence having fewer than four periods or more than five periods. It is also possible to specify any of the various patterns of low-power periods and high-power periods.

[0029]

[0033] Returning to Figure 3, in block 310, device 100 is configured to obtain configuration settings for the next period defined by the sequence obtained in block 305. For example, device 100 can be configured to obtain the power level (e.g., high power level) associated with the first period 404-1 according to configuration data 400b. In some examples, processor 104 can obtain the power level in block 310, and controller 128 can obtain the duration of the period, polling sub-period configuration, etc. (for example, these can be encoded or otherwise stored in controller 128).

[0030]

[0034] In block 315, device 100 is configured to control assembly 124 according to the period settings obtained in block 310. For example, processor 104 can be configured to send a command to controller 128, for example, according to the NFC Controller Interface (NCI) standard, which includes the power level for the current period defined in configuration data 400b. Controller 128 can be configured to apply its power level to antenna 132 according to a predefined sub-period structure.

[0031]

[0035] Controlling assembly 124 according to the period settings from block 310 includes transmitting a polling signal during one or more polling sub-periods, each polling sub-period followed by a corresponding listening sub-period. Controlling assembly 124 may also include an emulation sub-period following the polling and listening sub-periods, during which the controller 128 monitors for any external polling signals detected at antenna 132.

[0032]

[0036] In block 320, device 100 is configured to determine whether the current period is complete, for example, whether one cycle of the polling subperiod, listening subperiod, and emulation subperiod has been completed. If the determination in block 320 is negative, device 100 continues to transmit a polling signal, listen for a response to the polling signal, or listen for an external polling signal. If the determination in block 320 is positive, device 100 proceeds to block 325 to determine whether the control sequence obtained in block 305 is complete. For example, if configuration data 400b is retrieved in block 305, then in block 325, device 100 is configured to determine whether all four periods of sequence 402b have been executed through the continuous execution of block 315. The processor 104 and / or controller 128 may, for example, maintain a counter indicating which period in sequence 402b is the current period.

[0033]

[0037] If the determination in block 325 is negative, device 100 returns to block 310 to obtain a setting (e.g., power level) for the next period in the sequence (e.g., for period 404-2 in sequence 402b). Device 100 is then configured to repeat the subsequent blocks of method 300 for the current period. For example, processor 104 can send further NCI commands to controller 128 along with the power level for the current period.

[0034]

[0038] If the determination in block 325 is positive, device 100 can be configured to reset the sequence in block 330 and return to block 310. That is, assembly 124 can be configured to repeat the control sequence from block 305 until it is disabled (for example, by being automatically put into sleep mode if no activity is detected for a period of time, or by being explicitly disabled by another application).

[0035]

[0039] Referring to Figure 5, an exemplary execution of Method 300 is shown based on control sequence 402b. In block 310, device 100 selects a setting for a first period 408-1. The first period 408-1 includes a polling portion 504-1 followed by an emulation sub-period 508-1. In block 315, during one or more polling sub-periods 512 (five in this example) of the polling portion 504-1, controller 128 applies a first power level 510 to antenna 132 to transmit each polling signal. Controller 128 then monitors for any response to the polling signal during each listening sub-period 516. After the last listening sub-period 516, controller 128 monitors for any external polling signals during the emulation sub-period 508-1. If the emulation subperiod 508-1 has ended, the determination in block 320 is positive, and device 100 returns to block 310 to get set up for the next period 404-2, which includes a polling portion 504-2, and the polling portion 504-2 also includes a set of polling subperiod 512 and listening subperiod 516. Period 404-2 also includes the emulation subperiod 508-2.

[0036]

[0040] As shown in Figure 5, in block 315, the controller 128 applies a second power level 520, which is lower than the first power level 510, to the antenna 132 during the polling sub-period 512. As will be understood by those skilled in the art, following period 404-2 and another negative determination in block 325, the device 100 is configured to control assembly 124 according to the settings of periods 408-3 and 404-4 (including their respective polling portions 504-3 and 504-4, and their respective emulation sub-periods 508-3 and 508-4) as specified in configuration data 400b. The polling signal transmitted in polling portion 508-3 uses the high power setting, while the polling signal transmitted in polling portion 508-4 uses the low power setting. As can be seen in Figure 5, if sequence 402b is completed, at the completion of period 404-4, device 100 in block 330 can start a repetition of sequence 402b, beginning from another instance of period 408-1.

[0037]

[0041] As will be apparent to those skilled in the art in light of the above discussion, the control sequence 402b (or any other suitable control sequence, such as sequence 402a) implemented by device 100 can improve the overall performance of device 100 by reducing the amount of time during which assembly 124 may cause visual artifacts on display 116. This is because the low-power period 404 mitigates or avoids such artifacts. The high-power period 408 may result in visual artifacts, but the limited duration of such effects can make those artifacts imperceptible to the operator of device 100. Furthermore, the low-power period 404 may reduce the performance of assembly 124, for example by reducing the effective NFC range of assembly 124, while the high-power period 408 still allows device 100 to interact with the device beyond such reduced effective range. Thus, the impact on NFC performance is also limited. Moreover, the use of hybrid power levels in the control sequences discussed above can reduce power consumption in assembly 124.

[0038]

[0042] The aforementioned specification describes specific embodiments. However, it will be understood by those with ordinary skill in the art that various modifications and changes can be made without departing from the scope of the invention as described in the following claims. Accordingly, this specification and the figures should be considered illustrative rather than restrictive, and all such modifications are intended to be within the scope of this teaching.

[0039]

[0043] No benefit, advantage, solution to a problem, or any element that may cause any benefit, advantage, or solution to occur or become more prominent should be construed as an essential, required, or indispensable feature or element of any or all of the claims. The present invention is defined solely by the appended claims, including any amendments made during the pendency of this application, and all equivalents of those claims issued.

[0040]

[0044] Furthermore, in this document, terms indicating relationships such as first and second, upper and lower may be used only to distinguish one entity or action from another entity or action, and do not necessarily require or imply any actual relationship or order between such entities or actions. The terms “comprises,” “comprising,” “has,” “having,” “includes,” “including,” “contains,” and “containing,” or any other variations thereof, are intended to cover non-exclusive inclusion, thereby allowing a process, method, article, or apparatus that comprises, has, includes, or contains a list of elements to include not only those elements but also other elements not expressly listed or specific to such process, method, article, or apparatus. An element preceded by “comprises a…”, “has a…”, “includes a…”, or “contains a…” does not preclude the presence of further identical elements in processes, methods, articles, or apparatus that comprise, have, include, or contain that element, unless further constraints apply. The terms “a” and “an” are defined as one or multiple, unless expressly stated herein otherwise. The terms “substantially”, “essentially”, “approximately”, “about”, or any other variation thereof are defined as “close to”, as understood by a person of ordinary skill in the art, and in one non-limiting embodiment, the term is defined as being within 10%, in another embodiment within 5%, in another embodiment within 1%, and in another embodiment within 0.5%.As used herein, the term “combined” is defined as “connected,” but this does not necessarily mean direct or mechanical. A device or structure “configured” in a particular way is configured in at least that way, but may also be configured in ways not listed.

[0041]

[0045] In this specification, certain expressions may be used to list combinations of elements. Examples of such expressions include: “at least one of A, B, and C,” “one or more of A, B, and C,” “at least one of A, B, or C,” and “one or more of A, B, or C.” Unless otherwise specified, the above expressions encompass any combination of A and / or B and / or C.

[0042]

[0046] It will be understood that some embodiments may consist of one or more dedicated processors (or “processing devices”), such as microprocessors, digital signal processors, customized processors, and field-programmable gate arrays (FPGAs), and a set of unique stored program instructions (including both software and firmware) that control the one or more processors to perform some, most, or all of the functions of the methods and / or apparatus described herein in conjunction with specific non-processor circuits. Alternatively, some or all of the functions may be performed by a state machine that does not have stored program instructions, or in one or more application-specific integrated circuits (ASICs) in which some of the functions, or some combinations of some of those functions, are performed as custom logic. Of course, combinations of these two approaches may be used.

[0043]

[0047] Furthermore, embodiments can be implemented as computer-readable storage media storing computer-readable code for programming a computer (including, for example, a processor) to perform the methods described and claimed herein. Examples of such computer-readable storage media include, but are not limited to, hard disks, CD-ROMs, optical storage devices, magnetic storage devices, ROMs (Read Only Memory), PROMs (Programmable Read Only Memory), EPROMs (Erasable Programmable Read Only Memory), EEPROMs (Electrically Erasable Programmable Read Only Memory), and flash memory. Moreover, it is expected that a person of ordinary skill would be able to easily generate such software instructions and programs and ICs with minimal experimentation, guided by the concepts and principles disclosed herein, regardless of the considerable effort and numerous design choices that could be considered, motivated by, for example, available time, current technology, and economic considerations.

[0044]

[0048] This abstract of the disclosure is provided to enable readers to quickly confirm the nature of the technical disclosure. The abstract is presented with the understanding that it is not used to interpret or limit the scope or meaning of the claims. In addition, it is possible to understand that in the aforementioned “Modes for Carrying Out the Invention,” various features are grouped together in various embodiments for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than are explicitly listed in each claim. Rather, as reflected in the claims below, the inventive subject matter lies in fewer features than all the features of a single disclosed embodiment. Therefore, the claims below are incorporated into the “Modes for Carrying Out the Invention,” with each claim standing independently as individually claimed subject matter.

Claims

1. A method comprising the step of controlling a short-range wireless communication assembly of a computing device during a sequence of multiple periods, wherein each period has a polling sub-period. During the first period in the sequence, From the short-range wireless communication assembly, a first polling signal is transmitted according to a first power level during the polling sub-period of the first period. During the second period of the sequence, From the short-range wireless communication assembly, a second polling signal is transmitted according to a second power level during the polling sub-period of the second period. A method for performing the aforementioned control.

2. Each of the plurality of periods in the sequence further includes a listening sub-period following the polling sub-period, The method described above is The steps include monitoring whether there is a first response to the first polling signal during the listening sub-period of the first period, The steps include monitoring whether there is a second response to the second polling signal during the listening sub-period of the second period, and The method according to claim 1, further comprising:

3. Each of the plurality of periods in the sequence further includes an emulation subperiod, The method described above is The steps include monitoring whether there is a first external polling signal during the emulation sub-period of the first period, The steps include monitoring whether there is a second external polling signal during the emulation sub-period of the second period, and The method according to claim 1, further comprising:

4. The method according to claim 1, wherein one of the first power level and the second power level is smaller than the other of the first power level and the second power level.

5. The method according to claim 1, wherein one of the first power level and the second power level is selected to reduce visual artifacts on the display of the computing device during the transmission of at least one of the first polling signal or the second polling signal.

6. The method according to claim 1, wherein the first period and the second period of the sequence have equal lengths.

7. During the third period of the sequence, Steps to transmit a third polling signal from the short-range wireless communication assembly according to one of the first power level and the second power level during the polling sub-period of the third period. The method according to claim 1, further comprising:

8. Before controlling the short-range wireless communication assembly, Steps to obtain configuration data including the first power level and the second power level. The method according to claim 1, further comprising:

9. The aforementioned configuration data The sequence consisting of multiple periods, and For each of the aforementioned multiple periods, the relationship between the period and one of the first power level and the second power level. The method according to claim 8, further comprising:

10. The method according to claim 1, wherein the short-range wireless communication assembly is a near-field communication (NFC) assembly.

11. A computing device, A short-range wireless communication assembly including an antenna, The system comprises a processor configured to control the short-range wireless communication assembly during a sequence of multiple periods, each period having a polling sub-period, and the processor, During the first period in the sequence, the short-range wireless communication assembly transmits a first polling signal according to a first power level during the polling sub-period of the first period. During the second period of the sequence, the short-range wireless communication assembly transmits a second polling signal according to a second power level during the polling sub-period of the second period. A computing device that performs the aforementioned control.

12. Each of the plurality of periods in the sequence further includes a listening sub-period following the polling sub-period, The aforementioned processor further, During the listening sub-period of the first period, monitor whether there is a first response to the first polling signal. During the listening sub-period of the second period, monitor whether there is a second response to the second polling signal. The computing device according to claim 11, configured as described above.

13. Each of the plurality of periods in the sequence further includes an emulation subperiod, The aforementioned processor further, During the emulation sub-period of the first period, monitor whether there is a first external polling signal. During the emulation sub-period of the second period, monitor whether there is a second external polling signal. The computing device according to claim 11, configured as described above.

14. The computing device according to claim 11, wherein one of the first power level and the second power level is smaller than the other of the first power level and the second power level.

15. Equipped with an additional display, The computing device according to claim 11, wherein the antenna is arranged to transmit the first and second polling signals through the display.

16. The computing device according to claim 15, wherein one of the first power level and the second power level is selected to reduce visual artifacts in the display during the transmission of at least one of the first polling signal or the second polling signal.

17. The computing device according to claim 11, wherein the first period and the second period of the sequence have equal lengths.

18. The processor, during the third period of the sequence, Steps to transmit a third polling signal from the short-range wireless communication assembly according to one of the first power level and the second power level during the polling sub-period of the third period. The computing device according to claim 11, further configured to perform the following:

19. Before the processor controls the short-range wireless communication assembly, Steps to obtain configuration data including the first power level and the second power level. The computing device according to claim 11, further configured to perform the following:

20. The aforementioned configuration data The sequence consisting of multiple periods, and For each of the aforementioned multiple periods, the relationship between the period and one of the first power level and the second power level. A computing device according to claim 19, including the following:

21. The computing device according to claim 11, wherein the short-range wireless communication assembly is a near-field communication (NFC) assembly.

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