Display board and method for manufacturing the same, display device

Abstract

The present invention provides a display board, a method for manufacturing the same, and a display device. [Solution] A display board, a method for manufacturing the same, and a display device. The display board includes a base board including a pixel array region and a peripheral region, a first scanning drive circuit provided in the peripheral region and located on the first side of the base board, a plurality of power lines, a first signal line group and a second signal line group. The first scanning drive circuit includes a plurality of cascaded first shift registers, the plurality of power lines are configured to supply a plurality of power voltages to the plurality of cascaded first shift registers included in the first scanning drive circuit, the first signal line group includes at least one timing signal line, and the second signal line group includes a first trigger signal line configured to supply a first trigger signal to the first stage first shift register, the first trigger signal line is located between the plurality of power lines and the pixel array region. The display board facilitates the introduction of signal lines and is advantageous for realizing the display of large-size display panels.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] In the field of display technology, for example, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines intersecting the gate lines. The driving of the gate lines may be realized by an integrated driving circuit to be bonded. In recent years, with the continuous improvement of the manufacturing process of amorphous silicon thin film transistors or oxide thin film transistors, it has also become possible to directly integrate a gate line driving circuit on a thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA including a plurality of cascaded shift register units can be used to supply on / off voltage signals (scanning signals) to a plurality of rows of gate lines of a pixel array, thereby, for example, controlling a plurality of rows of gate lines to be sequentially turned on, forming a gradation voltage required for each gradation of a display image in each pixel cell, and supplying a data signal to the pixel cells of the corresponding row in the pixel array by a data line so as to display one frame of an image.

Summary of the Invention

Means for Solving the Problems

[0003] In at least one embodiment of the present disclosure, a display board is provided, comprising a base substrate including a pixel array region and a peripheral region, and a first scanning drive circuit, a plurality of power lines, a first signal line group, and a second signal line group provided within the peripheral region and located on the first side of the base substrate. The first scanning drive circuit includes a plurality of cascaded first shift registers, the plurality of power lines are configured to supply a plurality of power voltages to the plurality of cascaded first shift registers included in the first scanning drive circuit, the first signal line group includes at least one timing signal line configured to supply at least one timing signal to the plurality of cascaded first shift registers included in the first scanning drive circuit, and the second signal line group includes a first trigger signal line connected to the first stage of the plurality of cascaded first shift registers included in the first scanning drive circuit and configured to supply a first trigger signal to the first stage first shift register, the first trigger signal line being located between the plurality of power lines and the pixel array region.

[0004] For example, in a display substrate according to at least one embodiment of the present disclosure, the second signal line group is located on the side of the first scanning drive circuit closer to the pixel array area, and the first signal line group is located on the other side of the first scanning drive circuit opposite to the side where the second signal line group is located.

[0005] For example, in a display substrate according to at least one embodiment of the present disclosure, the pixel array region includes a first display region and a second display region that are parallel to each other and do not overlap, the first scanning drive circuit is connected to the first display region and drives the first display region to display, and the display substrate further includes a second scanning drive circuit provided in the peripheral region and located on the first side of the base substrate, sequentially arranged with the first scanning drive circuit along the scanning direction of the pixel array, and connected to the second display region and drives the second display region to display. The second scanning drive circuit includes a plurality of cascaded second shift registers, and the second signal line group further includes a second trigger signal line connected to the first stage of the plurality of cascaded second shift registers included in the second scanning drive circuit and supplying a second trigger signal to the first stage of the second shift register included in the second scanning drive circuit.

[0006] For example, in a display board according to at least one embodiment of the present disclosure, the extended length of the first trigger signal line and the second trigger signal line is the same as the arrangement length of the first scanning drive circuit and the second scanning drive circuit.

[0007] For example, in a display board according to at least one embodiment of the present disclosure, the first trigger signal line and the second trigger signal line are arranged side by side.

[0008] For example, in a display board according to at least one embodiment of the present disclosure, the plurality of power lines include a first power line and a second power line, and the first power line and the second power line are configured to supply the same first power voltage.

[0009] For example, in a display board according to at least one embodiment of the present disclosure, the orthogonal projection of the first power line onto the base board partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base board, and the orthogonal projection of the second power line onto the base board is located between the orthogonal projection of the first power line onto the base board and the orthogonal projection of the second signal line group onto the base board.

[0010] For example, a display board according to at least one embodiment of the present disclosure further includes at least one first resistor, the first resistor located away from the first shift register of the first stage of the first scanning drive circuit, and the first trigger signal line is connected to the first shift register of the first stage of the first scanning drive circuit via the at least one first resistor.

[0011] For example, a display board according to at least one embodiment of the present disclosure further includes at least one second resistor, the second resistor located between the final stage first shift register of the first scanning drive circuit and the first stage second shift register of the second scanning drive circuit, and the second trigger signal line is connected to the first stage second shift register of the second scanning drive circuit via the at least one second resistor.

[0012] For example, in the display board according to at least one embodiment of the present disclosure, the resistance values ​​of the first resistor and the second resistor are different.

[0013] For example, a display substrate according to at least one embodiment of the present disclosure further includes a fold line located between the first display area and the second display area, the second resistor being located in the direction of extension of the fold line, and the direction of extension of the fold line being perpendicular to the direction of extension of the first signal line group and the second signal line group.

[0014] For example, in a display board according to at least one embodiment of the present disclosure, the orthogonal projection of the at least one second resistor onto the base board is located between the orthogonal projection of the first shift register of the final stage of the first scanning drive circuit onto the base board and the orthogonal projection of the second shift register of the first stage of the second scanning drive circuit onto the base board.

[0015] For example, in a display substrate according to at least one embodiment of the present disclosure, the at least one first resistor is located between the base substrate and the second signal line group in a direction perpendicular to the base substrate, and the orthographic projection of the at least one first resistor onto the base substrate is located on the side away from the pixel array region of the orthographic projection of the second signal line group onto the base substrate.

[0016] For example, in the display substrate according to at least one embodiment of the present disclosure, the material of the first resistor is a semiconductor material.

[0017] For example, a display board according to at least one embodiment of the present disclosure further includes at least one first connection line and at least one second connection line, wherein the first connection line connects one end of the at least one first resistor to the first shift register of the first stage of the first scanning drive circuit, and the second connection line connects the other end of the at least one first resistor to the first trigger signal line.

[0018] For example, in a display board according to at least one embodiment of the present disclosure, the first connection line and the second connection line are located on the side of the at least one first resistor away from the base board.

[0019] For example, a display substrate according to at least one embodiment of the present disclosure further includes a first conductive connection portion, a second conductive connection portion, a first insulating layer, and a second insulating layer, wherein the first conductive connection portion and the second conductive connection portion are located on the side of the first connection line and the second connection line away from the base substrate and are provided in the same layer as the plurality of power lines, the first signal line group and the second signal line group, the first insulating layer is located between the at least one first resistor and the first connection line and the second connection line in a direction perpendicular to the base substrate, and the second insulating layer is located between the first connection line and the second connection line and the first conductive connection portion and the second conductive connection portion in a direction perpendicular to the base substrate. One end of the first conductive connection is connected to one end of the first connecting line via a through-hole penetrating the second insulating layer; the other end of the first conductive connection is connected to one end of the at least one first resistor via a through-hole penetrating the first insulating layer and the second insulating layer; the other end of the first connecting line is connected to the first shift register of the first scanning drive circuit; one end of the second conductive connection is connected to one end of the second connecting line via a through-hole penetrating the second insulating layer; the other end of the second conductive connection is connected to the other end of the at least one first resistor via a through-hole penetrating the first insulating layer and the second insulating layer; and the other end of the second connecting line is connected to the first trigger signal line via a through-hole penetrating the second insulating layer.

[0020] For example, in a display board according to at least one embodiment of the present disclosure, each first shift register of the first scanning drive circuit includes a first component transistor connected to the first power line, and a second and third component transistor connected to the second power line, wherein the orthogonal projection of the first component transistor onto the base board is located between the orthogonal projection of the first signal line group onto the base board and the orthogonal projection of the first power line onto the base board, and is close to the orthogonal projection of the first power line onto the base board, and the orthogonal projection of the second and third component transistors onto the base board is located between the orthogonal projection of the first power line onto the base board and the orthogonal projection of the second power line onto the base board, and is close to the orthogonal projection of the second power line onto the base board.

[0021] For example, in a display board according to at least one embodiment of the present disclosure, the plurality of power lines include a third power line and a fourth power line, the third power line and the fourth power line are configured to supply the same second power supply voltage, the orthogonal projection of the fourth power line onto the base board partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base board, and the orthogonal projection of the third power line onto the base board is located between the orthogonal projection of the fourth power line onto the base board and the orthogonal projection of the first signal line group onto the base board.

[0022] For example, in a display board according to at least one embodiment of the present disclosure, each first shift register of the first scanning drive circuit further includes a fourth component transistor connected to the third power line and a fifth component transistor connected to the fourth power line, wherein the orthogonal projection of the fourth component transistor onto the base board is located on the side of the orthogonal projection of the third power line onto the base board that is away from the orthogonal projection of the first signal line group onto the base board, and is close to the orthogonal projection of the third power line onto the base board, and the orthogonal projection of the fifth component transistor onto the base board is located between the orthogonal projection of the fourth power line onto the base board and the orthogonal projection of the second signal line group onto the base board, and is close to the orthogonal projection of the fourth power line onto the base board.

[0023] In at least one embodiment of the present disclosure, a display board is provided that includes a base substrate including a pixel array region and a peripheral region, a first scanning drive circuit provided in the peripheral region and located on the first side of the base substrate, a plurality of power lines, a first signal line group and a second signal line group. The first scanning drive circuit includes a plurality of cascaded first shift registers, the plurality of power lines configured to supply a plurality of power voltages to the plurality of cascaded first shift registers included in the first scanning drive circuit, the first signal line group includes at least one timing signal line configured to supply at least one timing signal to the plurality of cascaded first shift registers included in the first scanning drive circuit, the second signal line group includes a first trigger signal line configured to supply a first trigger signal to the first stage first shift register of the plurality of cascaded first shift registers included in the first scanning drive circuit, the first scanning drive circuit includes a first transistor, a second transistor, and a third transistor, the first transistor, the second transistor, and the third transistor each connected to the first signal line group, and the extending direction of the channels of the first transistor, the second transistor, and the third transistor is parallel to the extending direction of the first signal line group and the second signal line group.

[0024] For example, in a display board according to at least one embodiment of the present disclosure, the first scanning drive circuit further includes a sixth transistor and a seventh transistor, each connected to the first signal line group, wherein the extending directions of the channels of the sixth transistor and the seventh transistor are parallel to the extending directions of the first signal line group and the second signal line group.

[0025] In at least one embodiment of the present disclosure, a display device including a display substrate according to any embodiment of the present disclosure is further provided.

[0026] In at least one embodiment of the present disclosure, a method for manufacturing a display substrate includes providing a base substrate, and forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in this order in a direction perpendicular to the base substrate. The power line, the first signal line group, and the second signal line group are located in the third conductive layer, the first scanning drive circuit is formed in the semiconductor layer, the first conductive layer, and the second conductive layer, and the first scanning drive circuit is connected to the power line, the first signal line group, and the second signal line group respectively through through-holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer.

Brief Description of Drawings

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is clear that the drawings in the following description relate only to some embodiments of the present invention and do not limit the present invention.

[0028] [Figure 1] It is a circuit diagram of a light emission control shift register. [Figure 2] It is a signal timing chart during the operation of the light emission control shift register shown in FIG. 1. [Figure 3] It is a schematic diagram of a first resistor and a second resistor according to at least one embodiment of the present disclosure. [Figure 4] It is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 5A] It is a layout schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 5B] It is a layout schematic diagram of a display substrate including the first-stage shift register of the second scanning drive circuit. [Figure 6A] It is a plan view of the wiring of each layer of the display substrate shown in FIG. 5A. [Figure 6B] It is a plan view of the wiring of each layer of the first-stage shift register included in the display substrate shown in FIG. 5B. [Figure 7A]Figure 5A is a plan view of the wiring in each layer of the display board. [Figure 7B] Figure 5B is a plan view of the wiring of each layer of the first-stage shift register included in the display board. [Figure 8] Figure 5A shows a plan view of the wiring of each layer of the display board, and Figure 5B shows a plan view of the wiring of each layer of the first-stage shift register included in the display board. [Figure 9A] Figure 5A is a plan view of the wiring in each layer of the display board. [Figure 9B] Figure 5B is a plan view of the wiring of each layer of the first-stage shift register included in the display board. [Figure 10] Figure 5B is a cross-sectional view of the display board in the AA' direction. [Figure 11] This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. [Figure 12] This is a flowchart of a method for manufacturing a display substrate according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0029] To further clarify the object, technical solution, and advantages of the embodiments of the present invention, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments. Clearly, the embodiments described are some, but not all, embodiments of the present invention. All other embodiments that can be obtained without creative work by those skilled in the art based on the embodiments of the present invention described are all within the scope of protection of the present invention.

[0030] Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meanings as understood by a person of general skill in the art to which the invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but merely distinguish different components. Similarly, similar terms such as “one,” “one,” and “the” do not limit a quantity, but indicate that there is at least one. Similar terms such as “includes” and “contains” mean that the elements or objects mentioned, and their equivalents, are included, but do not exclude other elements or objects. Similar terms such as “connected” and “connected to one another” are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. “Up,” “down,” “left,” and “right,” etc., are merely used to indicate relative positions, and such relative positions may change if the absolute position of the subject changes.

[0031] The present disclosure will be illustrated below with reference to several specific embodiments. Detailed descriptions of known functions and known components may be omitted in order to make the following descriptions of embodiments of the present invention clear and concise. If any component of an embodiment of the present invention is shown in one or more drawings, the same reference numeral will be used for that component in each drawing.

[0032] Figure 1 is a circuit diagram of the light emission control shift register. Figure 2 is a signal timing chart of the operation of the light emission control shift register shown in Figure 1. The operation process of the light emission control shift register will be briefly explained below with reference to Figures 1 and 2.

[0033] As shown in Figure 1, the light emission control shift register 100 includes 10 transistors (first transistor T1, second transistor T2, ..., tenth transistor T10) and three capacitors (first capacitor C1, second capacitor C2, third capacitor C3). For example, when multiple light emission control shift registers 100 are cascaded, the first pole of the first transistor T1 of the first stage shift register 100 is connected to the first trigger signal line ESTV1 to receive the first trigger signal ESTV1, and the first pole of the first transistor T1 of each of the other stages of light emission control shift register 100 is connected to the preceding light emission control shift register 100 to receive the first output signal EM output from the preceding light emission control shift register 100.

[0034] In Figures 1 and 2, CK indicates the first clock signal terminal, ECK indicates the first clock signal line and the first clock signal, and the first clock signal terminal CK is connected to the first clock signal line ECK to receive the first clock signal. CB indicates the second clock signal terminal, ECB indicates the second clock signal line and the second clock signal, and the second clock signal terminal CB is connected to the second clock signal line ECB to receive the second clock signal. For example, the first clock signal ECK and the second clock signal ECB may use pulse signals with a duty cycle greater than 50%. VGH1 indicates the first power supply line and the first power supply voltage supplied by the first power supply line, for example, the first power supply voltage is a high DC level. VGL1 indicates the third power supply line and the second power supply voltage supplied by the third power supply line, for example, the second power supply voltage is a low DC level and the first power supply voltage is greater than the second power supply voltage. N1, N2, N3, and N4 indicate the first node, second node, third node, and fourth node, respectively.

[0035] As shown in Figure 1, the gate of the first transistor T1 is connected to the first clock signal terminal CK (i.e., the first clock signal line ECK) to receive the first clock signal, the first pole of the first transistor T1 is connected to the input terminal IN, and the second pole of the first transistor T1 is connected to the first node N1. For example, if the light emission control shift register is the first stage shift register, the input terminal IN is connected to the first trigger signal line ESTV1 to receive the first trigger signal, and if the light emission control shift register is a shift register of any stage other than the first stage shift register, the input terminal IN is connected to the output terminal OUT of the preceding light emission control shift register.

[0036] The gate of the second transistor T2 is connected to the first node N1, the first pole of the second transistor T2 is connected to the first clock signal line ECK to receive the first clock signal, and the second pole of the second transistor T2 is connected to the second node N2.

[0037] The gate of the third transistor T3 is connected to the first clock signal line ECK to receive the first clock signal, the first pole of the third transistor T3 is connected to the third power supply line VGL1 to receive the second power supply voltage, and the second pole of the third transistor T3 is connected to the second node N2.

[0038] The gate of the fourth transistor T4 is connected to the second clock signal terminal CB (i.e., the second clock signal line ECB) to receive the second clock signal, the first pole of the fourth transistor T4 is connected to the first node N1, and the second pole of the fourth transistor T4 is connected to the first pole of the fifth transistor T5.

[0039] The gate of the fifth transistor T5 is connected to the second node N2, and the second pole of the fifth transistor T5 is connected to the first power line VGH to receive the first power supply voltage.

[0040] The gate of the sixth transistor T6 is connected to the second node N2, the first pole of the sixth transistor T6 is connected to the second clock signal line ECB to receive the second clock signal, and the second pole of the sixth transistor T6 is connected to the third node N3.

[0041] The first terminal of the first capacitor C1 is connected to the second node N2, and the second terminal of the first capacitor C2 is connected to the third node N3.

[0042] The gate of the seventh transistor T7 is connected to the second clock signal line ECB to receive the second clock signal, the first gate of the seventh transistor T7 is connected to the third node N3, and the second gate of the seventh transistor T7 is connected to the fourth node N4.

[0043] The gate of the eighth transistor T8 is connected to the first node N1, the first pole of the eighth transistor T8 is connected to the first power line VGH1 to receive the first power supply voltage, and the second pole of the eighth transistor T8 is connected to the fourth node N4.

[0044] The gate of the ninth transistor T9 is connected to the fourth node N4, the first pole of the ninth transistor T9 is connected to the first power supply line VGH1 to receive the first power supply voltage, and the second pole of the ninth transistor T9 is connected to the output terminal OUT.

[0045] The first terminal of the third capacitor C3 is connected to the fourth node N4, and the second terminal of the third capacitor C3 is connected to the first power supply line VGH1 to receive the first power supply voltage.

[0046] The gate of the 10th transistor T10 is connected to the first node N1, the first pole of the 10th transistor T10 is connected to the third power line VGL1 to receive the second power supply voltage, and the second pole of the 10th transistor T10 is connected to the output terminal OUT.

[0047] The first end of the second capacitor C2 is connected to the second clock signal line ECB to receive the second clock signal, and the second end of the second capacitor C2 is connected to the first node N1.

[0048] In the light emission control shift register 100 shown in Figure 1, all transistors are described using P-type transistors as an example; that is, each transistor turns on when a low level is input to the gate and turns off when a high level is input. In this case, the first pole may be the source and the second pole may be the drain.

[0049] The embodiments of this disclosure include, but are not limited to, the configuration shown in Figure 1. For example, each transistor in the light emission control shift register 100 may be an N-type transistor, or a combination of a P-type transistor and an N-type transistor may be used. At the same time, the port polarity of the selected type of transistor should be connected according to the port polarity of the corresponding transistor in the embodiments of this disclosure.

[0050] Figure 2 is a signal timing chart of the operation of the light emission control shift register shown in Figure 1. The operation process of the light emission control shift register will be described in detail below with reference to Figures 1 and 2. For example, the operation principle of the first stage light emission control shift register 100 will be explained, and the operation principles of the other stages of the light emission control shift register 100 are similar and will not be described in detail. As shown in Figure 2, the operation process of the light emission control shift register includes six stages, which are the first stage P1, the second stage P2, the third stage P3, the fourth stage P4, the fifth stage P5, and the sixth stage P6, and Figure 2 shows the time-series waveforms of each signal in each stage.

[0051] In the first stage P1, as shown in Figure 2, the first clock signal ECK is low level, so the first transistor T1 and the third transistor T3 turn on. The first transistor T1, now on, transmits a high-level first trigger signal ESTV1 to the first node N1, causing the level of the first node N1 to become high, which in turn turns off the second transistor T2, the eighth transistor T8, and the tenth transistor T10. The third transistor T3, now on, transmits a low-level second power supply voltage VGL1 to the second node N2, causing the level of the second node N2 to become low, which in turn turns on the fifth transistor T5 and the sixth transistor T6. Since the second clock signal ECB is high level, the seventh transistor T7 turns off. The accumulation effect of the third capacitor C3 keeps the level of the fourth node N4 high, which in turn turns off the ninth transistor T9. In the first stage P1, both the ninth transistor T9 and the tenth transistor T10 are turned off, so the first output signal output from the output terminal OUT_1 of the light emission control shift register 100 is held at the previous low level.

[0052] In the second stage P2, as shown in Figure 4, the second clock signal ECB is at a low level, so the fourth transistor T4 and the seventh transistor T7 are turned on. The first clock signal ECK is at a high level, so the first transistor T1 and the third transistor T3 are turned off. Due to the accumulation effect of the first capacitor C1, the second node N2 can continue to be held at the low level of the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on. The high-level first power supply voltage VGH1 is transmitted to the first node N1 via the turned-on fifth transistor T5 and the fourth transistor T4, so the level of the first node N1 continues to be held at the high level of the previous stage, so the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are turned off. Furthermore, when the low-level second clock signal ECB is transmitted to the fourth node N4 via the turned-on sixth transistor T6 and seventh transistor T7, the level of the fourth node N4 becomes low, so the ninth transistor T9 turns on, and the turned-on ninth transistor T9 outputs a high-level first power supply voltage VGH1. Therefore, in the second stage P2, the first output signal output from the output terminal OUT_1 of the light emission control shift register 100 is high level.

[0053] In the third stage P3, as shown in Figure 4, the first clock signal ECK is low level, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal ECB is high level, so the fourth transistor T4 and the seventh transistor T7 are turned off. Due to the storage action of the third capacitor C3, the level of the fourth node N4 is held at the low level of the previous stage, which keeps the ninth transistor T9 in the ON state. Since the ON ninth transistor T9 outputs a high level first power supply voltage VGH1, in the third stage P3, the output signal output from the output terminal OUT_1 of the light emission control shift register 100 is still high level. At the same time, in this stage, a high level is output from the output terminal OUT_2 of the second stage light emission control shift register 100 (specifically, the operation process of the first stage light emission control shift register in the second stage P2 described above may be referred to).

[0054] In the fourth stage P4, as shown in Figure 4, the first clock signal ECK is at a high level, so the first transistor T1 and the third transistor T3 are turned off. The second clock signal ECB is at a low level, so the fourth transistor T4 and the seventh transistor T7 are turned on. Due to the accumulation effect of the second capacitor C2, the level of the first node N1 is held at the high level of the previous stage, so the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off. Due to the accumulation effect of the first capacitor C1, the second node N2 continues to be held at the low level of the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on. Furthermore, when the low-level second clock signal ECB is transmitted to the fourth node N4 via the 6th transistor T6 and the 7th transistor T7, which are turned on, the level of the fourth node N4 becomes low, so the 9th transistor T9 turns on, and the turned-on 9th transistor T9 outputs a high-level first power supply voltage VGH1. Therefore, in the second stage P2, the first output signal output from the output terminal OUT_1 of the light emission control shift register 100 is still at a high level. At the same time, in this stage, the output terminal OUT_2 of the second stage light emission control shift register 100 outputs a high level (specifically, refer to the operation process of the first stage light emission control shift register in the third stage P3 described above).

[0055] In the fifth stage P5, as shown in Figure 4, the first clock signal ECK is at a low level, so the first transistor T1 and the third transistor T3 are turned on. The second clock signal ECB is at a high level, so the fourth transistor T4 and the seventh transistor T7 are turned off. The first transistor T1, which is turned on, transmits a low-level first trigger signal ESTV to the first node N1 so that the level of the first node N1 becomes low.

[0056] For example, in the fifth stage P5, the low-level voltage of the first clock signal ECK is -6V, the low-level voltage of the first trigger signal ESTV1 is -6V, and the threshold voltage Vth of the first transistor T1 is -1.5V. Since the first transistor T1 is a P-type transistor, the gate and source voltages Vgs of the first transistor T1 must be smaller than the threshold voltage Vth of the first transistor T1 in order for the first transistor T1 to turn on. Therefore, when the first node N1 is charged to -4.5V, the first transistor T1 turns off, and in this case, charging to the first node N1 stops. That is, at this stage, since the low-level voltage of the first node N1 is -4.5V, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 turn on. The turned-on second transistor T2 transmits a low-level first clock signal ECK to the second node N2, further lowering the level of the second node N2. As a result, the second node N2 remains at the previous low level, which turns on the fifth transistor T5 and the sixth transistor T6. The turned-on eighth transistor T8 transmits a high-level first power supply voltage VGH1 to the fourth node N4, raising the level of the fourth node N4, which turns off the ninth transistor T9. The turned-on tenth transistor T10 responds to the low level of the first node N1 (e.g., -4.5V) by outputting a low-level second power supply voltage VGL (e.g., -6V). Similarly, the threshold voltage Vth of the 10th transistor T10 is -1.5V, and in order for the 10th transistor T10 to turn on, the gate and source voltages Vgs of the 10th transistor T10 must be smaller than the threshold voltage Vth of the 10th transistor T10. Therefore, when the voltage output from the output terminal OUT is -3V, the 10th transistor T10 turns off. That is, at this stage, the low-level voltage at the output terminal OUT is -3V, so in the 5th stage P5, the output signal output from the output terminal OUT_1 of the light emission control shift register 100 becomes the first low level (for example, -3V).At the same time, a high level is output from the output terminal OUT_2 of the second stage light emission control shift register 100 (specifically, refer to the operation process of the first stage light emission control shift register in the fourth stage P4 described above).

[0057] In the sixth stage P6, as shown in Figure 4, the first clock signal ECK is at a high level and the second clock signal ECB is at a low level, so the fourth transistor T4 and the seventh transistor T7 are turned on. As the second clock signal ECB changes from a high level in the fifth stage P5 to a low level, for example, if the amount of change is Δt (e.g., greater than 6V), the bootstrap effect of the second capacitor C2 causes the level of the first node N1 to change from a low level in the fifth stage P5 (e.g., -4.5V) to an even lower low level (e.g., -4.5V-Δt), thereby turning on the second transistor T2 and the tenth transistor T10 under the control of the low level of the first node N1 (e.g., -4.5V-Δt). Due to the conduction characteristics of the tenth transistor T10, the low level second power supply voltage VGL (e.g., -6V) can be completely output to the output terminal OUT. For example, in this sixth stage P6, the voltage output from the output terminal OUT is the second low level (e.g., -6V). At the same time, in this stage, a low level (e.g., -3V, specifically, refer to the operation process of the first shift register in the first stage in the fourth stage P4 above) is output from the output terminal OUT_2 of the second stage first shift register 100.

[0058] For example, as shown in Figure 1, the wiring is densely packed on the left side of the display board, leaving relatively little space for the first trigger signal line ESTV1, making it inconvenient to introduce multiple trigger signal lines. Furthermore, as shown in Figure 1, there is only one first power supply line VGH1, and the fifth transistor T5, eighth transistor T8, and ninth transistor T9 are wound around to connect to the first power supply line VGH1, which increases the vertical space occupied by the display board, making it disadvantageous for the layout design of the display board.

[0059] In at least one embodiment of the present disclosure, a display board is provided, comprising a base substrate including a pixel array region and a peripheral region, a first scanning drive circuit provided in the peripheral region and located on the first side of the base substrate, a plurality of power lines, a first signal line group and a second signal line group. The first scanning drive circuit includes a plurality of cascaded first shift registers, the plurality of power lines are configured to supply a plurality of power voltages to the plurality of cascaded first shift registers included in the first scanning drive circuit, the first signal line group includes at least one timing signal line configured to supply at least one timing signal to the plurality of cascaded first shift registers included in the first scanning drive circuit, and the second signal line group includes a first trigger signal line located between the plurality of power lines and the pixel array region, configured to supply a first trigger signal to the first stage first shift register among the plurality of cascaded first shift registers included in the first scanning drive circuit.

[0060] In at least one embodiment of this disclosure, a display device corresponding to the above-mentioned display substrate and a method for manufacturing it are further provided.

[0061] The display board according to the above embodiment of this disclosure has a first trigger signal line provided between multiple power lines and a pixel array area, which facilitates the introduction of signal lines and is advantageous for realizing the display of a large-size display panel.

[0062] The embodiments and some examples thereof of this disclosure will be described in detail below with reference to the attached drawings.

[0063] In at least one embodiment of the present disclosure, a display board is provided. For example, the display board may be applied to a scanning drive circuit with one driver per row, i.e., an output signal from a single-stage shift register drives only one row of pixel cells. A scanning drive circuit with one driver per row has a stronger driving capability than a scanning drive circuit with two drivers per row because the load that needs to be driven is halved, and is therefore more suitable for displaying larger display panels.

[0064] Furthermore, the display board may also be applied to a single-row dual-drive scanning drive circuit; that is, the output signal from a single-stage shift register can drive two rows of pixel cells, and the embodiments of this disclosure are not limited to this.

[0065] Figure 4 is a schematic diagram of a display board according to at least one embodiment of the present disclosure. This display board 1 includes, for example, a base board 10, a first scanning drive circuit 130, a plurality of power lines 140, a first signal line group 150, and a second signal line group 160, as shown in Figure 4.

[0066] For example, the base substrate 100 can be made of suitable materials such as glass, plastic, or quartz, and the embodiments of this disclosure are not limited thereto. For example, the base substrate 10 includes a pixel array region 110 and a peripheral region 120, and a first scanning drive circuit 130, a plurality of power lines 140, a first signal line group 150, and a second signal line group 160 are provided in the peripheral region 120 and located on the first side of the base substrate 10, for example, on the left side of the base substrate 10.

[0067] The pixel array region 110 includes, for example, a plurality of pixel cells P arranged in an array. For example, each of the plurality of pixel cells P includes a pixel circuit and may further include, for example, a light-emitting element (not shown).

[0068] For example, the first scanning drive circuit 130 includes a plurality of cascaded first shift registers 100, including, for example, a plurality of shift registers 100 as shown in Figure 1. For clarity and brevity of explanation, the first shift registers 100 will be abbreviated as shift registers 100 below. The same applies to the following embodiments, which will not be explained in detail. For example, the output terminals of the plurality of shift registers 100 are connected to the light emission control terminals of the pixel circuits of each row located in the pixel array region, and by supplying output signals (e.g., light emission control signals) to the pixel circuits of each row, the light-emitting elements are driven to emit light. For example, the pixel circuits may include pixel circuits with circuit configurations such as 2T1C, 4T2C, 8T2C, etc., which will not be explained in detail here.

[0069] For example, the first scanning drive circuit 130 includes at least one transistor, and the extension direction of the channel of the at least one transistor is parallel to the extension directions of the first signal line group 150 and the second signal line group 160. This reduces the area of ​​the channel of the first scanning drive circuit 130 in the direction perpendicular to the length direction, improves process matching, and produces a relatively favorable channel effect.

[0070] For example, the first scanning drive circuit 130 includes a first transistor T1, a second transistor T2, and a third transistor T3, each connected to a first clock signal ECK of a first signal line group 150, for example. For example, the channel extension direction of the first transistor T1, the second transistor T2, and the third transistor T3 is parallel to the extension direction of the first signal line group 150 and the second signal line group 160. For example, the channel extension direction is the extension direction from the first pole to the second pole of the transistor, for example, the extension direction from the first pole to the second pole of the first transistor T1.

[0071] For example, the first scanning drive circuit 130 further includes a sixth transistor T6 and a seventh transistor T7 connected to the first signal line group 150, respectively, and the channel extension direction of the sixth transistor T6 and the seventh transistor T7 is parallel to the extension direction of the first signal line group 150 and the second signal line group 160.

[0072] For example, the multiple power lines 140 are configured to supply multiple power supply voltages, such as a first power supply voltage (e.g., a high level DC) and a second power supply voltage (e.g., a low level DC), to multiple shift registers 100 that are cascaded together and included in the first scanning drive circuit 130.

[0073] The first signal line group 150 includes at least one timing signal line, for example, the first clock signal line ECK and the second clock signal line ECB, configured to supply at least one timing signal, for example, a first clock signal ECK and a second clock signal ECB, to a plurality of cascaded shift registers 100 included in the first scanning drive circuit 130.

[0074] For example, in at least one example, the second signal line group 160 includes a first trigger signal line ESTV1 configured to supply a first trigger signal to the first-stage shift register of a plurality of cascaded shift registers 100 included in the first scanning drive circuit 150. For example, the first trigger signal line ESTV1 is located between a plurality of power lines 140 and the pixel array area 110. For example, as shown in Figure 4, the first trigger signal line ESTV1 may be located to the right of the first scanning drive circuit 130, i.e., the orthographic projection of the first trigger signal line ESTV1 onto the base substrate 10 is located between the orthographic projection of the first scanning drive circuit 130 onto the base substrate 10 and the orthographic projection of the pixel array area 110 onto the base substrate 10. Naturally, it may be located between the transistors of the first scanning drive circuit 130, that is, the orthographic projection of the first trigger signal line ESTV1 onto the base substrate 10 overlaps at least partially with the orthographic projection of the first scanning drive circuit 130 onto the base substrate 10, and it is sufficient that it is placed in an area where wiring is not densely packed in order to facilitate the introduction of the trigger signal line, and the embodiments of this disclosure are not limited thereto.

[0075] The display board may further include a plurality of scanning drive circuits and a plurality of trigger signal lines connected to the first-stage shift registers of the plurality of scanning drive circuits, and the embodiments of this disclosure are not limited thereto.

[0076] For example, in some cases, the display board further includes a plurality of scanning drive circuits, such as a second scanning drive circuit and a third scanning drive circuit. The display board further includes a plurality of trigger signal lines, such as a second trigger signal line ESTV2 connected to the first stage shift register of the second scanning drive circuit and a third trigger signal line connected to the first stage shift register of the third scanning drive circuit. For example, the plurality of scanning drive circuits, such as the second scanning drive circuit and the third scanning drive circuit, have the same configuration as the first scanning drive circuit, are arranged sequentially from the first scanning drive circuit, and together drive the pixel array area of ​​the display board. For example, the pixel array area includes a plurality of display areas that do not overlap with each other (e.g., are arranged side by side), and the plurality of scanning drive circuits, such as the first scanning drive circuit, the second scanning drive circuit and the third scanning drive circuit, each drive the corresponding display area.

[0077] For example, if the system includes multiple scanning drive circuits, the second signal line group 160 further includes multiple trigger signal lines. For example, the multiple trigger signal lines may be located between the multiple power lines 140 and the pixel array area 110, for example, to the right of each scanning drive circuit, or at least overlapping with each scanning drive circuit, provided that they are located in an area where wiring is not densely packed in order to facilitate the introduction of the trigger signal lines, and the embodiments of this disclosure are not limited thereto.

[0078] The display board according to the above embodiment of this disclosure, by adjusting the position of the first trigger signal line, avoids problems such as the inability to introduce more signal lines due to dense wiring and the need for winding connections, which is advantageous for realizing a narrow bezel design for the display panel, and thereby is advantageous for realizing the display of a large-size display panel.

[0079] Figure 5A is a schematic layout diagram of a display board according to at least one embodiment of the present disclosure. Figure 5B is a schematic layout diagram of a display board including the first stage shift register of the second scanning drive circuit. Figure 10 is a cross-sectional view of the display board shown in Figure 5B in the AA' direction. Naturally, Figure 10 may be used to illustrate the stacked configuration shown in Figure 5A.

[0080] The stacked configuration of the first-stage shift register shown in Figure 5B may also be applied to the first-stage shift register of each scanning drive circuit, provided that the connection to the corresponding trigger signal is changed. Specifically, the first-stage shift register of the first scanning drive circuit is connected to the first trigger signal line ESTV1, the first-stage shift register of the second scanning drive circuit is connected to the second trigger signal line ESTV2, and so on.

[0081] Figures 6A, 7A, 8, and 9A show plan views of the wiring of each layer of the display substrate shown in Figure 5A, respectively. Figure 6A is a plan view of the semiconductor layer of the display substrate according to at least one embodiment of the present disclosure, Figure 7A is a plan view of the first conductive layer of the display substrate according to at least one embodiment of the present disclosure, Figure 8 is a plan view of the second conductive layer of the display substrate according to at least one embodiment of the present disclosure, and Figure 9A is a plan view of the third conductive layer of the display substrate according to at least one embodiment of the present disclosure.

[0082] For example, interlayer insulating layers (including, for example, a first insulating layer, a second insulating layer, a third insulating layer, etc.) may be located between the layer configurations shown in Figures 6A to 9A. For example, a first insulating layer 350 (as shown in Figure 10) is located between the semiconductor layer 310 shown in Figure 6A and the first conductive layer 320 shown in Figure 7A, a second insulating layer 360 (as shown in Figure 10) is located between the first conductive layer 320 shown in Figure 7A and the second conductive layer 330 shown in Figure 8, and a third insulating layer 370 (as shown in Figure 10) is located between the second conductive layer 330 shown in Figure 8 and the third conductive layer 340 shown in Figure 9A.

[0083] For example, as shown in Figure 10, the display substrate further includes a fourth insulating layer 380, which is located on the third conductive layer 340 and is used to protect the third conductive layer 340.

[0084] For example, the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370, and the fourth insulating layer 380 may include, for example, inorganic insulating materials such as SiNx, SiOx, and SiNxOy, organic insulating materials such as organic resins, or other suitable materials, and the embodiments of this disclosure are not limited thereto.

[0085] Furthermore, using the display board shown in Figure 5A, the layout design of one shift register in the first scanning drive circuit and the signal lines connected to it will be explained as an example. Other layout embodiments for the shift registers in each stage may refer to the layout configuration shown in Figure 5A, and will not be described in detail here. Needless to say, other layout configurations may be adopted, and the embodiments of this disclosure are not limited thereto. Naturally, the shift registers in each stage of the other scanning drive circuits may also refer to the layout configuration shown in Figure 5A, or other layout configurations may be used, and the embodiments of this disclosure are not limited thereto.

[0086] A display substrate according to at least one embodiment of this disclosure will be described in detail below with reference to Figures 5A to 9A.

[0087] For example, the first to tenth transistors T10 of the shift register 100 shown in Figure 5A may be formed on the semiconductor layer 310 shown in Figure 6A. The semiconductor layer 310 may be formed by patterning a semiconductor material. This semiconductor layer 310 may be in the shape of a short rod, or a curved or bent shape as needed, as shown in Figure 6A, and may be used to manufacture the active layers of the first to tenth transistors T10. Each active layer may include a source region, a drain region, and a channel region located between the source region and the drain region. For example, the channel region can acquire semiconductor properties by doping with impurities, and the source region and drain region are located on either side of the channel region and can acquire conductivity by doping with impurities. For example, the source region corresponds to the source (also called the first pole) of the transistor, and the drain region corresponds to the drain (also called the second pole) of the transistor. For example, as shown in Figure 10, taking the first transistor T1 as an example, the active layer of the first transistor T1 includes a source region S1, a drain region D1 (as shown by the dashed line in Figure 10), and a channel region P1. The first transistor T1 further includes a gate G1, which is located in the first conductive layer 320 and will be explained below, so it will not be explained in detail here. Note that the drain region D1 of the first transistor T1 is not shown in the cross-sectional view in the AA' direction of Figure 5B, but in order to clarify the explanation, the drain region D1 of the first transistor T1 is added as a dashed line in Figure 10.

[0088] For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon and high-temperature polycrystalline silicon, etc., and the embodiments of this disclosure are not limited thereto. The source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of this disclosure are not limited thereto.

[0089] In other examples, the first and second poles of each transistor may be located in other conductive layers and connected to the corresponding active layer via through-holes in an insulating layer located between the semiconductor layer, and the embodiments of this disclosure are not limited thereto.

[0090] Figure 7A shows the first conductive layer 320 of the display substrate. The first conductive layer 320 is insulated from the semiconductor layer 310 by being provided on the first insulating layer. For example, the first conductive layer 320 may include the first electrodes CE11, CE12, CE13 of the first capacitors C1 to the third capacitors C3 and the gates of the first transistors T1 to the tenth transistors T10, and accordingly, the first insulating layer is also a gate insulating layer. As shown in Figure 7A, the gates of the first transistors T1 to the tenth transistors T10 are the parts where the semiconductor layer configuration of each transistor and the wiring of the first conductive layer 320 overlap.

[0091] Figure 8 shows the second conductive layer 330 of the display substrate. The second conductive layer 330 includes the second electrodes CE21, CE22, and CE23 of the first capacitors C1 to the third capacitors C3. For example, the second electrode CE21 overlaps with the first electrode CE11 to form the first capacitor C1, the second electrode CE22 overlaps with the first electrode CE12 to form the second capacitor C2, and the second electrode CE23 overlaps with the first electrode CE13 to form the third capacitor C3.

[0092] Figure 9A shows the third conductive layer 340 of this display board. The third conductive layer 340 includes a first signal line group 150, a plurality of power lines 140, and a second signal line group 160. The third conductive layer further includes conductive connection parts that connect each transistor, capacitor, and signal line. As shown in Figures 5A and 9A, the first signal line group 150, the plurality of power lines 140, and the second signal line group 160 are connected to transistors in the other layers that require connection via at least one through-hole, and each transistor is also connected via at least one through-hole or bridged via conductive connection parts, which will not be explained in detail here.

[0093] For example, the material of the third conductive layer 340 may include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, and the embodiments of this disclosure are not limited thereto. For example, the materials of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, and these will not be described in detail here.

[0094] Figure 5A is a diagram showing the stacking positional relationship between the semiconductor layer 310 shown in Figure 6A, the first conductive layer 320 shown in Figure 7A, the second conductive layer 330 shown in Figure 8, and the third conductive layer 340 shown in Figure 9A.

[0095] As shown in Figures 5A and 9A, in at least one example, the display board includes a first signal line group 150 (for example, including a first clock signal line ECK and a second clock signal line ECB) arranged sequentially along the row direction, a plurality of power lines 140 (for example, including a third power line VGL1, a first power line VGH1 and a fourth power line VGL2), and a second signal line group 160 (for example, including a first trigger signal line ESTV1). If a second scanning drive circuit is included, for example, the second signal line group 160 further includes a second trigger signal line ESTV2.

[0096] In some embodiments, as shown in Figure 4 or Figure 5A, the second signal line group 160 is located on the side of the first scanning drive circuit 130 closer to the pixel array area 110, and the first signal line group 150 is located on the other side of the first scanning drive circuit 130 opposite to the side where the second signal line group 160 is located. For example, as shown in Figure 4 or Figure 5A, the second signal line group 160 is located to the right of the shift register 100, and the first signal line group 150 is located to the left of the shift register 100.

[0097] In this embodiment, the second group of signal lines 160, including the first trigger signal line ESTV1 and the second trigger signal line ESTV2, is provided to the right of the shift register, that is, away from the first group of signal lines 150 and the multiple power lines 140. This avoids the congestion of wiring caused by having too many signal lines on the left side. This prevents the space remaining for the trigger signal lines from becoming too small due to wiring congestion, which would affect the introduction of other signal lines.

[0098] In some other examples, as shown in Figure 5A, the multiple power lines 140 include a first power line VGH1, a second power line VGH2, a third power line VGL1, and a fourth power line VGL2. For example, the first power line VGH1 and the second power line VGH2 supply the same first power supply voltage, for example, a high DC voltage.

[0099] For example, the orthogonal projection of the first power line VGH1 onto the base board 10 partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base board 10, and the orthogonal projection of the second power line VGH2 onto the base board 10 is located between the orthogonal projection of the first power line VGH1 onto the base board 10 and the orthogonal projection of the second signal line group 160 onto the base board 10.

[0100] Since the orthogonal projection of the first scanning drive circuit onto the base substrate 10 is not a continuous region, the orthogonal projection of the first power line VGH1 onto the base substrate 10 only needs to partially overlap with the orthogonal projections of some transistors and capacitors of the first scanning drive circuit onto the base substrate 10. The embodiments of this disclosure are not limited to this. For example, as shown in Figure 5A, the orthogonal projection of the first power line VGH1 onto the base substrate 10 overlaps with the wiring in the first conductive layer 320. For example, it partially overlaps with the wiring connecting the gate of the third transistor T3 and the gate of the first transistor T1, the wiring connecting the gate of the fourth transistor T4, the wiring connecting the gate of the fifth transistor T5, and the wiring connecting the gate of the second transistor T2.

[0101] For example, as shown in Figure 5A, each shift register of the first scanning drive circuit includes a first component transistor connected to a first power line VGH1, and second and third component transistors connected to a second power line VGH2. For example, the fifth transistor T5 is an example of the first component transistor, the eighth transistor T8 is an example of the second component transistor, and the ninth transistor T9 is an example of the third component transistor. Hereinafter, the first component transistor will be described as the fifth transistor T5, the second component transistor as the eighth transistor T8, and the third component transistor as the ninth transistor T9, but the embodiments of this disclosure are not limited to this. The following embodiments are similar and will not be described in detail.

[0102] For example, the orthogonal projection of the fifth transistor T5 onto the base board 10 lies between the orthogonal projection of the first signal line group 150 onto the base board 10 and the orthogonal projection of the first power line VGH1 onto the base board 10, and is close to the orthogonal projection of the first power line VGH1 onto the base board 10. The orthogonal projections of the eighth transistor T8 and the ninth transistor T9 onto the base board 10 lies between the orthogonal projection of the first power line VGH1 onto the base board 10 and the orthogonal projection of the second power line VGH2 onto the base board 10, and is close to the orthogonal projection of the second power line VGH2 onto the base board 10. In other words, by providing the first power line VGH1 in a position close to the fifth transistor T5, and providing the eighth transistor T8 and the ninth transistor T9 in a position close to the second power line VGH2, it is possible to avoid winding the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 so that they are all connected to a single power line (for example, the first power line VGH1). This avoids the need to occupy space by winding wiring in the vertical direction of the display board.

[0103] For example, the third power line VGL1 and the fourth power line VGL2 are configured to supply the same second power supply voltage, for example, a low DC voltage. For example, the first power supply voltage is higher than the second power supply voltage. For example, the orthogonal projection of the fourth power line VGL2 onto the base board 10 partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base board 10, and the orthogonal projection of the third power line VGL1 onto the base board 10 is located between the orthogonal projection of the third power line VGL1 onto the base board 10 and the orthogonal projection of the first signal line group 150 onto the base board 10.

[0104] As described above, the orthogonal projection of the first scanning drive circuit onto the base substrate 10 is not a continuous region, so the orthogonal projection of the fourth power line VGL2 onto the base substrate 10 only needs to partially overlap with the orthogonal projections of some transistors and capacitors of the first scanning drive circuit onto the base substrate 10. The embodiments of this disclosure are not limited to this. For example, as shown in Figure 5A, the orthogonal projection of the fourth power line VGL2 onto the base substrate 10 overlaps with the wiring in the first conductive layer 320. For example, it partially overlaps with the wiring connecting the gate of the eighth transistor T8, the wiring connecting the gate of the tenth transistor T10, and the first electrode CE12 of the second capacitor C2.

[0105] For example, each shift register in the first scanning drive circuit further includes a fourth component transistor connected to a third power line VGL1, and in addition, a fifth component transistor connected to a fourth power line VGL2. For example, the third transistor T3 is an example of a fourth component transistor, and the tenth transistor T10 is an example of a fifth component transistor. Hereinafter, we will describe the case where the third transistor T3 is a fourth component transistor and the tenth transistor T10 is a fifth component transistor as an example, but the embodiments of this disclosure are not limited thereto. The following embodiments are similar and will not be described in detail.

[0106] For example, the orthogonal projection of the third transistor T3 onto the base board 10 is on the side of the orthogonal projection of the third power line VGL1 onto the base board 10 that is away from the orthogonal projection of the first signal line group 150 onto the base board 10, and is close to the orthogonal projection of the third power line VGL1 onto the base board 10. For example, the orthogonal projection of the tenth transistor T10 onto the base board 10 is between the orthogonal projection of the fourth power line VGL2 onto the base board 10 and the orthogonal projection of the second signal line group 160 onto the base board 10, and is close to the orthogonal projection of the tenth transistor T10 onto the base board 10. In other words, by positioning the third power line VGL1 close to the third transistor T3 and the tenth transistor T10 close to the fourth power line VGL2, it is possible to avoid winding the third transistor T3 and the tenth transistor T10 so that they are both connected to a single power line (for example, the third power line VGL1), or to the third power line VGL1 and the fourth power line VGL2 located on the left side of the display board, respectively. This avoids the space occupied by winding the wiring in the vertical direction of the display board.

[0107] In at least one embodiment of this disclosure, by providing the first power line VGH1, the second power line VGH2, the third power line VGL1, and the fourth power line VGL2 near the transistors to which they are connected, it is possible to avoid winding the power lines so that each transistor is connected to a single power line. This avoids the space occupied by winding the wiring in the vertical direction of the display board, which is advantageous for realizing a narrow bezel design.

[0108] In some other embodiments, the pixel array region 110 includes a first display region and a second display region (not shown) that are parallel to each other and do not overlap, and a first scanning drive circuit 130 is connected to the first display region and drives the first display region to display.

[0109] The display board further includes a second scanning drive circuit provided in the peripheral region and located on one side of the base board. For example, the second scanning drive circuit is arranged sequentially from the first scanning drive circuit along the scanning direction of the pixel array (e.g., the column direction), connected to a second display area, and drives the second display area to display. For example, the second scanning drive circuit includes a plurality of cascaded second shift registers (e.g., the first-stage shift register 132 shown in Figure 5B). For example, the configuration of the second shift register is the same as the circuit configuration of the first shift register, and both employ the circuit configuration of the shift register shown in Figure 1. Naturally, the configuration of the second shift register may differ from the circuit configuration of the first shift register, and the embodiments of this disclosure are not limited thereto. For clarity and brevity of description, the second shift register will be abbreviated as a shift register below. The following embodiments are similar and will not be described in detail.

[0110] For example, the display board is a folded display board and further includes a folding line located between a first display area and a second display area. For example, a second resistor R2 is located in the direction of extension of the folding line, and the direction of extension of the folding line is perpendicular to the direction of extension of the first signal line group 150 and the second signal line group 160, so that the signal lines can penetrate the entire display board, for example, the direction of extension of the first signal line group 150 and the second signal line group 160 is the vertical direction as shown in Figure 4, and the direction of extension of the folding line is the horizontal direction.

[0111] For example, as shown in Figure 5B, the second signal line group 160 further includes a second trigger signal line ESTV2, which is connected to the first stage shift register 132 of a plurality of cascaded shift registers included in the second scan drive circuit, supplying a second trigger signal to the first stage shift register 132 included in the second scan drive circuit. For example, the first trigger signal line ESTV1 and the second trigger signal line ESTV2 are arranged adjacent to each other. The first trigger signal line ESTV1 and the second trigger signal line ESTV2 extend in parallel, and the extension lengths of both are the same as the arrangement lengths of the first scan drive circuit and the second scan drive circuit, and can, for example, penetrate the entire display panel. This makes it possible to avoid the difference in wiring resistance due to the difference in length between the first trigger signal line ESTV1 and the second trigger signal line ESTV2 affecting the trigger signals transmitted by each. Accordingly, for example, if a plurality of scanning drive circuits are included, each of the other trigger signal lines may be arranged adjacent to the first trigger signal line ESTV1 and the second trigger signal line ESTV2, and their respective lengths may be the same as the lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2.

[0112] Note that Figure 5B schematically shows only the shift register 131 in the final stage of the first scanning drive circuit and the shift register 132 in the first stage of the second scanning drive circuit. The layout configurations of the shift registers in the other stages can be seen by referring to the layout configuration shown in Figure 5A, and will not be explained in detail.

[0113] Figures 6B, 7B, 8, and 9B show plan views of the wiring of each layer of the first-stage shift register included in the display board shown in Figure 5B, respectively. A display board according to at least one embodiment of this disclosure will be described in detail below with reference to Figures 5B to 9B.

[0114] The semiconductor layer shown in Figure 6B is the same as the semiconductor layer shown in Figure 6A, the difference being that it further includes at least one resistor (for example, a second resistor R2). The first conductive layer 320 shown in Figure 7B is the same as the first conductive layer 320 shown in Figure 7A, the difference being that it further includes a first connecting line L1 and a second connecting line L2. The third conductive layer 340 shown in Figure 9B is the same as the third conductive layer 340 shown in Figure 9A, the difference being that it further includes a first conductive connection part 341 and a second conductive connection part 342. The specific connection relationships will be explained in detail below.

[0115] For example, when an output signal is output from the shift register 131 at the final stage of the first scanning drive circuit, the second trigger signal line ESTV2 supplies a second trigger signal to the first stage shift register 132 of the second scanning drive circuit, driving the cascaded shift registers included therein to output an output signal one row at a time. The embodiments of this disclosure are not limited to this, as long as the pixel cells in the pixel array area of ​​the display board are driven so that they can operate by supplying a first trigger signal to the first scanning drive circuit with the first trigger signal line ESTV1 and a second trigger signal to the second scanning drive circuit with the second trigger signal line ESTV2.

[0116] For example, in some cases, as shown in Figure 3, the display board further includes at least one first resistor R1 (as shown in Figure 3). For example, the first resistor R1 is located away from the first shift register of the first stage of the first scanning drive circuit 130. For example, the first trigger signal line ESTV1 is connected to the first shift register of the first scanning drive circuit 130 (e.g., the first transistor T1 of the first stage shift register) via the first resistor R1. For example, if the display board includes a second scanning drive circuit 230, as shown in Figure 5B, the display board may further include at least one second resistor R2. For example, the second resistor R2 is located between the first shift register of the final stage of the first scanning drive circuit 130 and the second shift register of the first stage of the second scanning drive circuit 230. For example, the second trigger signal line ESTV2 is connected to the second shift register of the first stage of the second scanning drive circuit 230 via the second resistor R2, and is connected to the first transistor T1 of the first stage shift register 132 of the second scanning drive circuit 230, for example.

[0117] For example, the resistance value of the first resistor R1 is different from the resistance value of the second resistor R2. For example, in some cases, the first trigger signal line ESTV1 is connected to the controller 20 from the top of the display board to receive the first trigger signal, and the second trigger signal line ESTV2 is inserted through the center of the display board and connected to the controller to receive the second trigger signal. As a result, the wiring resistance (load) of the first trigger signal line ESTV1 and the second trigger signal line ESTV2 is different. For example, if the load of the first trigger signal line ESTV1 is greater than the load of the second trigger signal line ESTV2, then the first resistor R1 is smaller than the second resistor R2, and the value obtained by adding the resistance value of the first resistor to the wiring resistance value of the first trigger signal line ESTV1 is approximately equal to the value obtained by adding the resistance value of the second resistor to the wiring resistance value of the second trigger signal line ESTV1. For example, in some cases, the resistance of the first resistor R1 is 5000 ohms, the resistance of the second resistor R2 is 5500 ohms, the resistance of the wiring in the first trigger signal line ESTV1 is 1000 ohms, and the resistance of the wiring in the second trigger signal line ESTV1 is 500 ohms.

[0118] Furthermore, if the display board includes multiple scanning drive circuits, the display board may further include multiple resistors connecting the first-stage shift registers of the multiple scanning drive circuits to the corresponding trigger signal lines. For example, if the display board includes multiple scanning drive circuits such as a third scanning drive circuit and a fourth scanning drive circuit, the display board may further include a third resistor, a fourth resistor, etc., connected to the first transistor T1 of the first-stage shift register, respectively, and the embodiments of this disclosure are not limited thereto. For example, the installation of other resistors may all be described in detail by referring to the installation of the first resistor and the second resistor R2.

[0119] For example, the first resistor and the second resistor may be the same or different, and may be specifically determined according to the actual circumstances, and the embodiments of this disclosure are not limited thereto. For example, the materials of the first resistor and the second resistor may be semiconductor materials, and may be provided in the same layer as the active layer of the transistor. The first resistor and the second resistor are located in the semiconductor layer shown in Figure 6B, for example.

[0120] Figure 5B shows the connection configuration of the second resistor, so the following explanation will use the second resistor R2 shown in Figure 5B as an example. Figure 10 is a cross-sectional view of the display board shown in Figure 5B in the AA' direction. The following explanation will describe in detail the connection configurations of each resistor, using the second resistor as an example, with reference to Figures 5B and 10.

[0121] As shown in Figures 5B and 10, the second resistor R2 is located between the base substrate 10 and the second signal line group 160 (i.e., in the semiconductor layer 310) in a direction perpendicular to the base substrate 10, and the orthographic projection of the second resistor R2 onto the base substrate 10 is located on the side away from the pixel array region of the orthographic projection of the second signal line group 160 onto the base substrate 10. Accordingly, the first resistor is located between the base substrate 10 and the second signal line group 160 (i.e., in the semiconductor layer 310) in a direction perpendicular to the base substrate 10, and the orthographic projection of the first resistor onto the base substrate 10 is located on the side away from the pixel array region of the orthographic projection of the second signal line group 160 onto the base substrate 10. Note that the first resistor and the second resistor R2 are not limited to the positions shown in Figure 5B, but may be provided in other suitable positions, as long as they are located in a position that facilitates connection between the trigger signal line and the first transistor T1, and the embodiments of this disclosure are not limited thereto.

[0122] As shown in Figure 5B, the display board further includes at least one first connection line L1 and at least one second connection line L2. The first connection line L1 connects one end of a second resistor R2 to the first stage shift register (e.g., first transistor T1) of the second scanning drive circuit, and the second connection line L2 connects the other end of the second resistor R2 to the second trigger signal line ESTV2.

[0123] The display board further includes a plurality of first and second connection lines that correspond one-to-one with resistors corresponding to other scanning drive circuits. Each first resistor or other resistor is connected to the corresponding scanning drive circuit and trigger signal line via the corresponding first and second connection lines. For example, the first connection line connects one end of the first resistor to the first stage shift register of the first scanning drive circuit, and the second connection line connects the other end of the first resistor to the first trigger signal line. These details will not be explained here.

[0124] For example, the first connection line L1 and the second connection line L2 are located on the side of the second resistor R2 away from the base substrate 10, that is, the first connection line L1 and the second connection line L2 are located on the first conductive layer 320 shown in Figure 7B, so when they are provided on the third conductive layer 340, signal disturbance due to crossing with the fourth power line VGL2 can be avoided.

[0125] For example, the display board further includes at least one first conductive connection part L3 and a second conductive connection part L4 so that each resistor is bridged to the first connection line and the second connection line. For example, the first conductive connection part L3 and the second conductive connection part L4 are located on the side of the first connection line L1 and the second connection line L2 away from the base board 10 and are provided in the same layer as the multiple power lines 140, the first signal line group 150 and the second signal line 160, that is, the first conductive connection part L3 and the second conductive connection part L4 are located in the third conductive layer 340 shown in Figure 9B.

[0126] For example, as described above, the display substrate 1 further includes a first insulating layer 350, a second insulating layer 360, and a third insulating layer 370. For example, the first insulating layer 350 is located in a direction perpendicular to the base substrate 10 between the second resistor R2 (i.e., semiconductor layer 310) and the first connection line L1 and the second connection line L2 (first conductive layer 320), and the second insulating layer 360 is located in a direction perpendicular to the base substrate 10 between the first connection line L1 and the second connection line L2 (i.e., first conductive layer 320) and the first conductive connection part L3 and the second conductive connection part L4 (i.e., third conductive layer 340). Furthermore, between the second insulating layer 360 and the third conductive layer 340, there is a second conductive layer 330 as shown in Figure 8, and a third insulating layer 370 located between the second conductive layer 330 and the third conductive layer 340. A detailed explanation can be found in the above description, and will not be explained in detail here.

[0127] For example, as shown in Figures 5B and 10, one end of the first conductive connection part L3 is connected to one end of the first connecting line L1 via a through-hole 133 that penetrates the second insulating layer 360 (and the third insulating layer 370), and the other end of the first conductive connection part L3 is connected to one end of the second resistor R2 via a through-hole 134 that penetrates the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). For example, the other end of the first connecting line L1 is connected to the first stage shift register of the first scanning drive circuit (for example, the source S1 of the first transistor T1) via a through-hole 135 that penetrates the second insulating layer 360 and the third insulating layer 370, and a through-hole 139 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. For example, if the orthographic projection of the other end of the first connecting line L1 onto the base substrate 10 overlaps at least partially with the orthographic projection of the source S1 of the first transistor T1 onto the base substrate 10, the other end of the first connecting line L1 may be connected to the source S1 of the first transistor T1 via a through-hole (not shown) penetrating the first insulating layer 350, and the embodiments of this disclosure are not limited thereto.

[0128] One end of the second conductive connection part L4 is connected to one end of the second connecting line L2 via a through-hole 136 that penetrates the second insulating layer 350 (and the third insulating layer 360), and the other end of the second conductive connection part L4 is connected to the other end of the second resistor R2 via a through-hole 137 that penetrates the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). The other end of the second connecting line L2 is connected to the second trigger signal line ESTV2 via a through-hole 138 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0129] The display board further includes a plurality of first conductive connection parts and second conductive connection parts that correspond one-to-one with resistors corresponding to other scanning drive circuits, and each first resistor or other resistor is connected to the corresponding first connection line and second connection line via the corresponding first conductive connection part and second conductive connection part, which will not be explained in detail here.

[0130] For example, one end of the first conductive connection is connected to one end of the first connecting wire via a through-hole penetrating the second insulating layer, the other end of the first conductive connection is connected to one end of the first resistor via a through-hole penetrating the first and second insulating layers, the other end of the first connecting wire is connected to the first stage shift register of the first scanning drive circuit, one end of the second conductive connection is connected to one end of the second connecting wire via a through-hole penetrating the second insulating layer, the other end of the second conductive connection is connected to the other end of the first resistor via a through-hole penetrating the first and second insulating layers, and the other end of the second connecting wire is connected to the first trigger signal line via a through-hole penetrating the second insulating layer.

[0131] In the embodiments of this disclosure, the first-stage shift register of each scanning drive circuit is connected to the corresponding trigger signal via each resistor, thereby avoiding the influence of static electricity generated at the moment the device is powered on on each signal (e.g., trigger signal, clock signal, etc.). This makes the output signal from the scanning drive circuit more accurate and improves the display quality of the display panel.

[0132] At least one embodiment of the present disclosure further provides a display device. Figure 11 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 11, the display device 2 includes a display substrate 1 according to any embodiment of the present disclosure, for example, the display substrate 1 shown in Figure 4, Figure 5A, or Figure 5B.

[0133] The display device 2 may be any product or component having a display function, such as an OLED panel, OLED television, mobile phone, tablet computer, notebook computer, digital photo frame, or navigation system. The display device 2 may further include other components, and the embodiments of this disclosure are not limited thereto.

[0134] For the sake of clarity and conciseness, the embodiments of this disclosure do not represent all components of the display device. Those skilled in the art can provide and implement other configurations (not shown) to realize the substrate functions of the display device, according to their specific needs, and the embodiments of this disclosure are not limited thereto.

[0135] The technical effects of the display device 2 according to the above embodiment may be explained in detail here, as they can be described by referring to the technical effects of the display substrate 1 according to the embodiment of this disclosure.

[0136] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate. Figure 12 is a flowchart of a method for manufacturing a display substrate according to at least one embodiment of the present disclosure. This manufacturing method can be applied, for example, to the manufacturing of a display substrate according to any embodiment of the present disclosure. For example, it can be applied to the manufacturing of the display substrate shown in Figure 5A or Figure 5B.

[0137] As shown in Figure 12, the method for manufacturing the display board includes steps S110 to S120.

[0138] Step S110: Provide the base board.

[0139] Step S120: A first scanning drive circuit, a plurality of power lines, a first signal line group, and a second signal line group are formed in the peripheral region of the base substrate, on the first side of the base substrate.

[0140] With respect to step S110, the base substrate 10 may be made of, for example, glass, plastic, quartz, or other suitable material, and the embodiments of this disclosure are not limited thereto. The base substrate 10 includes, for example, a pixel array region 110 and a peripheral region 120.

[0141] With respect to step S120, for example, the first scanning drive circuit 130, the multiple power lines 140, the first signal line group 150, and the second signal line group 160 are provided within the peripheral region 120 and on the first side of the base board 10, for example, on the left side of the base board 10.

[0142] For example, the first scanning drive circuit 130 includes a plurality of cascaded shift registers 100, including, for example, a plurality of shift registers as shown in Figure 1. For example, the first transistor T1 to the tenth transistor T10 of the shift register may be formed on a semiconductor layer 310 as shown in Figure 6A. For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of this disclosure are not limited thereto. The source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of this disclosure are not limited thereto.

[0143] For example, the first electrodes CE11, CE12, and CE13 of the first capacitors C1 to the third capacitors C3, and the gates of the first transistors T1 to the tenth transistors T10, may be formed in the first conductive layer 320 shown in Figure 7A. As shown in Figure 7A, the gates of the first transistors T1 to the tenth transistors T10 are the parts where the semiconductor layer configuration of each transistor and the wiring in the first conductive layer 320 overlap.

[0144] For example, the second electrodes CE21, CE22, and CE23 of the first capacitor C1 to the third capacitor C3 may be formed on the second conductive layer 330 shown in Figure 8. For example, the second electrode CE21 may overlap at least partially with the first electrode CE11 to form the first capacitor C1, the second electrode CE22 may overlap at least partially with the first electrode CE12 to form the second capacitor C2, and the second electrode CE23 may overlap at least partially with the first electrode CE13 to form the third capacitor C3.

[0145] For example, multiple power lines 140, a first signal line group 150, and a second signal line group may be formed on the third conductive layer 340 shown in Figure 9A. The third conductive layer further includes conductive connection parts that connect each transistor, capacitor, and signal line. As shown in Figures 5A and 9A, the first signal line group 150, multiple power lines 140, and the second signal line group 160 are connected to transistors in the other layers that require connection via at least one through-hole, and each transistor is also connected via at least one through-hole or bridged via conductive connection parts, which will not be explained in detail here.

[0146] For example, the material of the third conductive layer 340 may include aluminum, aluminum alloy, copper, copper alloy, or any other suitable material, and the embodiments of this disclosure are not limited thereto. For example, the materials of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, and these will not be described in detail here.

[0147] For example, multiple power lines 140 are configured to supply power voltages to multiple cascaded shift registers 100 included in the first scanning drive circuit 130. For example, they supply a first power supply voltage (e.g., having a high DC level) and a second power supply voltage (e.g., having a low DC level).

[0148] For example, the first signal line group 150 includes at least one timing signal line, and for example, a first clock signal line ECK and a second clock signal line ECB configured to supply timing signals, for example, the first clock signal ECK and the second clock signal ECB, to a plurality of cascaded shift registers 100 included in the first scanning drive circuit 130.

[0149] For example, in at least one example, the second signal line group 160 includes a first trigger signal line ESTV1 configured to supply a first trigger signal to the first stage shift register of a plurality of cascaded shift registers 100 included in the first scanning drive circuit 150. The first trigger signal line ESTV1 is provided, for example, between a plurality of power lines 140 and the pixel array area 110.

[0150] In some embodiments, as shown in Figure 4 or Figure 5A, the second signal line group 160 is formed on the side of the first scanning drive circuit 130 closer to the pixel array area 110, and the first signal line group 150 is formed on the other side of the first scanning drive circuit 130 opposite to the side where the second signal line group 160 is located. For example, as shown in Figure 4 or Figure 5A, the second signal line group 160 is located to the right of the shift register 100, and the first signal line group 150 is located to the left of the shift register 100.

[0151] In this embodiment, the first trigger signal line ESTV1 is provided to the right of the shift register, that is, away from the first signal line group 150 and the multiple power lines 140, thereby avoiding wiring congestion caused by too many signal lines on the left side. This prevents the space remaining for the trigger signal line from becoming too small due to wiring congestion, which would affect the introduction of other signal lines.

[0152] For example, step S120 further includes the steps of forming a first power line VGH1, a second power line VGH2, and a third power line VGL1 on the base substrate 10, and forming a fifth transistor T5 connected to the first power line VGH1, an eighth transistor T8 and a ninth transistor T9 connected to the second power line VGH2, a third transistor T3 connected to the third power line VGHL1, and a tenth transistor T10 connected to the fourth power line VGL2 on the base substrate 10. For example, the first power line VGH1 and the second power line VGH2 supply the same first power supply voltage, for example, a high DC voltage.

[0153] For example, the orthogonal projection of the first power line VGH1 onto the base board 10 partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base board 10, and the orthogonal projection of the second power line VGH2 onto the base board 10 is located between the orthogonal projection of the first power line VGH1 onto the base board 10 and the orthogonal projection of the second signal line group 160 onto the base board 10.

[0154] For example, by forming the first power line VGH1 near the fifth transistor T5 and the second power line VGH2 near the eighth transistor T8 and the ninth transistor T9, it is possible to avoid winding the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 to be connected to a single power line (e.g., the first power line VGH1), thereby avoiding the space occupied by wiring winding in the vertical direction of the display board.

[0155] For example, the third power line VGL1 and the fourth power line VGL2 are supplied with the same second power supply voltage, for example, a low DC voltage. For example, the first power supply voltage is higher than the second power supply voltage. For example, the orthogonal projection of the fourth power line VGL2 onto the base board 10 partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base board 10, and the orthogonal projection of the third power line VGL1 onto the base board 10 is located between the orthogonal projection of the third power line VGL1 onto the base board 10 and the orthogonal projection of the first signal line group 150 onto the base board 10.

[0156] For example, by forming a third power line VGL1 near the third transistor T3 and a fourth power line VGL2 near the tenth transistor T10, it is possible to avoid winding the wiring so that both the third transistor T3 and the tenth transistor T10 are connected to a single power line (e.g., the third power line VGL1), or to connect them to the third power line VGL1 and the fourth power line VGL2 located on the left side of the display board, respectively, thereby avoiding the space occupied by wiring winding in the vertical direction of the display board.

[0157] For example, in some cases, the method for manufacturing the display board further includes the step of forming a second scanning drive circuit in a peripheral region and on the first side of the base board 10. For example, the second scanning drive circuit includes a plurality of cascaded shift registers (e.g., the first stage shift register 132 shown in Figure 5B). For example, as shown in Figure 5B, the second signal line group 160 further includes a second trigger signal line ESTV2 that is connected to the first stage shift register 132 of the plurality of cascaded shift registers included in the second scanning drive circuit and supplies a second trigger signal to the first stage shift register 132 included in the second scanning drive circuit.

[0158] For example, the extended lengths of the first trigger signal line ESTV1 and the second trigger signal line ESTV2 are the same as the arrangement lengths of the first and second scan drive circuits. This avoids the effect of differences in wiring resistance due to differences in the extended lengths of the first and second trigger signal lines ESTV1 and ESTV2 on the trigger signals transmitted by each. Accordingly, for example, if multiple scan drive circuits are included, the extended lengths of each of the other trigger signal lines may be the same as the extended lengths of the first and second trigger signal lines ESTV1 and ESTV2.

[0159] For example, in some cases, the method for manufacturing the display board further includes the step of forming at least one first resistor and at least one second resistor between the base board 10 and the second signal line group 160 in a direction perpendicular to the base board 10.

[0160] Furthermore, if the display board includes a plurality of scanning drive circuits (for example, a third scanning drive circuit, a fourth scanning drive circuit, etc.), the method for manufacturing the display board further includes the step of forming resistors corresponding to the plurality of scanning drive circuits between the base board 10 and the second signal line group in a direction perpendicular to the base board 10, and the embodiments of this disclosure are not limited thereto.

[0161] As shown in Figures 5B and 10, the second resistor R2 is located between the base substrate 10 and the second signal line group 160 (i.e., in the semiconductor layer 310) in a direction perpendicular to the base substrate 10, and the orthographic projection of the second resistor R2 onto the base substrate 10 is located on the side away from the pixel array region of the orthographic projection of the second signal line group 160 onto the base substrate 10. Accordingly, the first resistor is located between the base substrate 10 and the second signal line group 160 in a direction perpendicular to the base substrate 10, and the orthographic projection of the first resistor onto the base substrate 10 is located on the side away from the pixel array region of the orthographic projection of the second signal line group 160 onto the base substrate 10. Note that the first resistor R2 and the second resistor R2 are not limited to the positions shown in Figure 5B, but may be provided in other suitable positions.

[0162] For example, in some cases, the method for manufacturing the display board further includes the step of forming at least one first connection line and at least one second connection line on the side of the first resistor R1 and second resistor R2 away from the base substrate 10, i.e., on the first conductive layer 320. Thus, signal disturbance due to crossing with the fourth power line VGL2 when provided on the third conductive layer 340 can be avoided.

[0163] For example, the first connection line connects one end of the first resistor to the first stage shift register of the first scanning drive circuit, and the second connection line connects the other end of the first resistor to the first trigger signal line. The first connection line L1 connects one end of the second resistor R2 to the first stage shift register of the second scanning drive circuit (for example, the first transistor T1), and the second connection line L2 connects the other end of the second resistor R2 to the second trigger signal line ESTV2.

[0164] For example, in some cases, the method for manufacturing the display board further includes the steps of forming a plurality of power lines 140, a first signal line group 150, and a second signal line group 160, as well as a first conductive connection part L3 and a second conductive connection part L4 provided in the same layer on a base board 10; forming a first insulating layer 350 between a first resistor R1 (i.e., semiconductor layer 310) and a first connection line L1 and a second connection line L2 (first conductive layer 320) in a direction perpendicular to the base board 10; and forming a second insulating layer 360 between the first connection line L1 and a second connection line L2 (first conductive layer 320) and a first conductive connection part L3 and a second conductive connection part L4 (i.e., third conductive layer 340) in a direction perpendicular to the base board 10. The manufacturing method of the display substrate further includes the step of forming a second conductive layer 330, as shown in Figure 8, between the second insulating layer 360 and the third conductive layer 340, and a third insulating layer 370 located between the second conductive layer 330 and the third conductive layer 340. A detailed explanation may be given by referring to the above description, and will not be explained in detail here.

[0165] For example, as shown in Figures 5B and 10, one end of the first conductive connection part L3 is connected to one end of the first connecting line L1 via a through-hole 133 that penetrates the second insulating layer 360 (and the third insulating layer 370), and the other end of the first conductive connection part L3 is connected to one end of the second resistor R2 via a through-hole 134 that penetrates the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). For example, the other end of the first connecting line L1 is connected to the first stage shift register of the first scanning drive circuit (for example, the source S1 of the first transistor T1) via a through-hole 135 that penetrates the second insulating layer 360 and the third insulating layer 370, and a through-hole 139 that penetrates the first insulating layer 350, the second insulating layer 360, and the third insulating layer 370. For example, if the orthographic projection of the other end of the first connecting line L1 onto the base substrate 10 overlaps at least partially with the orthographic projection of the source S1 of the first transistor T1 onto the base substrate 10, the other end of the first connecting line L1 may be connected to the source S1 of the first transistor T1 via a through-hole (not shown) penetrating the first insulating layer 350, and the embodiments of this disclosure are not limited thereto.

[0166] One end of the second conductive connection part L4 is connected to one end of the second connecting line L2 via a through-hole 136 that penetrates the second insulating layer 360 (and the third insulating layer 370), and the other end of the second conductive connection part L4 is connected to the other end of the second resistor R2 via a through-hole 137 that penetrates the first insulating layer 350 and the second insulating layer 360 (and the third insulating layer 370). The other end of the second connecting line L2 is connected to the second trigger signal line ESTV2 via a through-hole 138 that penetrates the second insulating layer 360 and the third insulating layer 370.

[0167] In the embodiments of this disclosure, the first-stage shift register of each scanning drive circuit is connected to the corresponding trigger signal via each resistor, thereby preventing static electricity generated at the moment the device is powered on from affecting each signal (e.g., trigger signal, clock signal, etc.). This makes the output signal from the scanning drive circuit more accurate and improves the display quality of the display panel.

[0168] In some embodiments of this disclosure, the flow of the method for manufacturing the display substrate may include more or fewer operations, which may be performed sequentially or in parallel. The above-mentioned flow of the manufacturing method includes a plurality of operations that appear in a specific order, but it is clear that the order of the plurality of operations is not limited. The above-mentioned manufacturing method may be performed once or multiple times according to predetermined conditions.

[0169] Regarding the technical effects of the method for manufacturing the display substrate according to the above embodiment, you may refer to the technical effects of the display substrate according to the embodiment of this disclosure, and will not provide a detailed explanation here.

[0170] The following points need to be explained. (1) The drawings of the embodiments of the present disclosure relate only to the configurations relating to the embodiments of the present disclosure, and other configurations may refer to general designs. (2) New embodiments can be obtained by combining the embodiments and features of the embodiments herein, provided that they do not contradict each other.

[0171] The foregoing are merely exemplary embodiments of the present disclosure and do not limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims. [Explanation of symbols]

[0172] 10 base boards 20 controllers 100 Light emission control shift register 110 pixel array area 120 surrounding area 130 First Scanning Drive Circuit 132 Shift Registers 133-139 Through Hole 140 Power line 150 First signal line group 160 Second signal line group 230 Second Scanning Drive Circuit 310 Semiconductor layer 320 First conductive layer 330 Second conductive layer 340 Third conductive layer 341 First conductive connection 342 Second conductive connection 350 First insulating layer 360 Second insulating layer 360 Second insulating layer 370 Third insulating layer 380 Fourth insulating layer

Claims

1. A base substrate including a pixel array region and a peripheral region, It includes a first scanning drive circuit provided within the peripheral region and located on the first side of the base substrate, a plurality of power lines, a first signal line group and a second signal line group, The first scanning drive circuit includes a plurality of first shift registers connected in cascade, The plurality of power lines are configured to supply a plurality of power voltages to a plurality of cascaded first shift registers included in the first scanning drive circuit. The first signal line group includes at least one timing signal line configured to supply at least one timing signal to a plurality of cascaded first shift registers included in the first scanning drive circuit, The second group of signal lines includes a first trigger signal line configured to be connected to the first stage of a plurality of cascaded first shift registers included in the first scanning drive circuit, and to supply a first trigger signal to the first stage of the first shift register. The first trigger signal line is located between the plurality of power lines and the pixel array area on the display board.

2. The second group of signal lines is located on the side of the first scanning drive circuit that is closer to the pixel array region. The display board according to claim 1, wherein the first signal line group is located on the other side of the first scanning drive circuit opposite to the side where the second signal line group is located.

3. The pixel array region includes a first display region and a second display region that are parallel to each other and do not overlap, and the first scanning drive circuit is connected to the first display region and drives the first display region to display. The display board further includes a second scanning drive circuit, which is provided within the peripheral region and located on the first side of the base board, arranged sequentially from the first scanning drive circuit along the scanning direction of the pixel array, and connected to the second display region to drive the second display region for display, The second scanning drive circuit includes a plurality of second shift registers connected in cascade, The display board according to claim 1 or 2, wherein the second group of signal lines further includes a second trigger signal line configured to supply a second trigger signal to the first stage second shift register of a plurality of cascaded second shift registers included in the second scanning drive circuit.

4. The display board according to claim 3, wherein the extended lengths of the first trigger signal line and the second trigger signal line are the same as the arrangement length of the first scanning drive circuit and the second scanning drive circuit.

5. The display board according to claim 3 or 4, wherein the first trigger signal line and the second trigger signal line are arranged side by side.

6. The aforementioned plurality of power lines include a first power line and a second power line, The display board according to any one of claims 1 to 5, wherein the first power line and the second power line are configured to supply the same first power supply voltage.

7. The orthogonal projection of the first power line onto the base substrate partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base substrate. The display board according to claim 6, wherein the orthogonal projection of the second power line onto the base board is located between the orthogonal projection of the first power line onto the base board and the orthogonal projection of the second signal line group onto the base board.

8. Further including at least one first resistor, The display board according to claim 3, wherein the first resistor is located on the side away from the first shift register of the first stage of the first scanning drive circuit, and the first trigger signal line is connected to the first shift register of the first stage of the first scanning drive circuit via the at least one first resistor.

9. It further includes at least one second resistor, The display board according to claim 8, wherein the second resistor is located between the first shift register of the final stage of the first scanning drive circuit and the second shift register of the first stage of the second scanning drive circuit, and the second trigger signal line is connected to the second shift register of the first stage of the second scanning drive circuit via at least one second resistor.

10. The display board according to claim 9, wherein the resistance values ​​of the first resistor and the second resistor are different.

11. The display further includes a folding line located between the first display area and the second display area, The display board according to claim 9, wherein the second resistor is located in the direction of extension of the folded line, and the direction of extension of the folded line is perpendicular to the direction of extension of the first signal line group and the second signal line group.

12. The display board according to any one of claims 9 to 11, wherein the orthogonal projection of the at least one second resistor onto the base board is located between the orthogonal projection of the first shift register of the final stage of the first scanning drive circuit onto the base board and the orthogonal projection of the second shift register of the first stage of the second scanning drive circuit onto the base board.

13. The display board according to any one of claims 8 to 12, wherein the at least one first resistor is located between the base substrate and the second signal line group in a direction perpendicular to the base substrate, and the orthographic projection of the at least one first resistor onto the base substrate is located on the side away from the pixel array region of the orthographic projection of the second signal line group onto the base substrate.

14. The display substrate according to any one of claims 8 to 13, wherein the material of the first resistor is a semiconductor material.

15. It further includes at least one first connection line and at least one second connection line, The first connection line connects one end of the at least one first resistor to the first shift register of the first stage of the first scanning drive circuit. The display board according to any one of claims 8 to 14, wherein the second connecting line connects the other end of the at least one first resistor to the first trigger signal line.

16. The display board according to claim 15, wherein the first connection line and the second connection line are located on the side of the at least one first resistor away from the base substrate.

17. It further includes a first conductive connection part, a second conductive connection part, a first insulating layer, and a second insulating layer. The first conductive connection portion and the second conductive connection portion are located on the side of the first connection line and the second connection line that is away from the base substrate, and are provided on the same layer as the plurality of power lines, the first signal line group and the second signal line group. The first insulating layer is located between the at least one first resistor and the first and second connecting wires in a direction perpendicular to the base substrate, and the second insulating layer is located between the first and second connecting wires and the first and second conductive connecting portion in a direction perpendicular to the base substrate. One end of the first conductive connection portion is connected to one end of the first connecting wire via a through-hole penetrating the second insulating layer, and the other end of the first conductive connection portion is connected to one end of the at least one first resistor via a through-hole penetrating the first insulating layer and the second insulating layer. The other end of the first connection line is connected to the first shift register of the first stage of the first scanning drive circuit. One end of the second conductive connection portion is connected to one end of the second connecting wire via a through-hole penetrating the second insulating layer, and the other end of the second conductive connection portion is connected to the other end of the at least one first resistor via a through-hole penetrating the first insulating layer and the second insulating layer. The display board according to claim 15 or 16, wherein the other end of the second connecting line is connected to the first trigger signal line via a through-hole penetrating the second insulating layer.

18. Each first shift register of the first scanning drive circuit includes a first component transistor connected to the first power line, and a second component transistor and a third component transistor connected to the second power line. The orthogonal projection of the first constituent transistor onto the base substrate is located between the orthogonal projection of the first signal line group onto the base substrate and the orthogonal projection of the first power line onto the base substrate, and is close to the orthogonal projection of the first power line onto the base substrate. The display board according to claim 3, wherein the orthogonal projections of the second and third constituent transistors onto the base substrate are located between the orthogonal projection of the first power line onto the base substrate and the orthogonal projection of the second power line onto the base substrate, and are close to the orthogonal projection of the second power line onto the base substrate.

19. The aforementioned plurality of power lines include a third power line and a fourth power line, The third power line and the fourth power line are configured to supply the same second power supply voltage. The orthogonal projection of the fourth power line onto the base board partially overlaps with the orthogonal projection of the first scanning drive circuit onto the base board. The display board according to any one of claims 1 to 18, wherein the orthogonal projection of the third power line onto the base board is located between the orthogonal projection of the fourth power line onto the base board and the orthogonal projection of the first signal line group onto the base board.

20. Each first shift register of the first scanning drive circuit further includes a fourth component transistor connected to the third power line and a fifth component transistor connected to the fourth power line, The orthogonal projection of the fourth component transistor onto the base substrate is located on the side of the orthogonal projection of the third power line onto the base substrate that is away from the orthogonal projection of the first signal line group onto the base substrate, and is close to the orthogonal projection of the third power line onto the base substrate. The display board according to claim 19, wherein the orthogonal projection of the fifth constituent transistor onto the base substrate is located between the orthogonal projection of the fourth power line onto the base substrate and the orthogonal projection of the second signal line group onto the base substrate, and is close to the orthogonal projection of the fourth power line onto the base substrate.

21. A base substrate including a pixel array region and a peripheral region, It includes a first scanning drive circuit provided within the peripheral region and located on the first side of the base substrate, a plurality of power lines, a first signal line group and a second signal line group, The first scanning drive circuit includes a plurality of first shift registers connected in cascade, The plurality of power lines are configured to supply a plurality of power voltages to a plurality of cascaded first shift registers included in the first scanning drive circuit. The first signal line group includes at least one timing signal line configured to supply at least one timing signal to a plurality of cascaded first shift registers included in the first scanning drive circuit, The second group of signal lines includes a first trigger signal line configured to be connected to the first stage of a plurality of cascaded first shift registers included in the first scanning drive circuit, and to supply a first trigger signal to the first stage of the first shift register. The first scanning drive circuit includes a first transistor, a second transistor, and a third transistor, and the first transistor, the second transistor, and the third transistor are each connected to the first signal line group. A display board in which the extending directions of the channels of the first transistor, the second transistor, and the third transistor are parallel to the extending directions of the first signal line group and the second signal line group.

22. The first scanning drive circuit further includes a sixth transistor and a seventh transistor, each connected to the first signal line group, The display board according to claim 21, wherein the extending direction of the channels of the sixth transistor and the seventh transistor is parallel to the extending direction of the first signal line group and the second signal line group.

23. A display device comprising a display board according to any one of claims 1 to 22.

24. The steps include providing a base substrate and The process includes the step of sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer in a direction perpendicular to the base substrate, The power line, the first signal line group, and the second signal line group are located in the third conductive layer. The first scanning drive circuit is formed in the semiconductor layer, the first conductive layer, and the second conductive layer. A method for manufacturing a display board according to any one of claims 1 to 22, wherein the first scanning drive circuit is connected to the power line, the first signal line group, and the second signal line group, respectively, via through-holes penetrating the first insulating layer, the second insulating layer, and the third insulating layer.

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