LED display device and method for manufacturing the same

Abstract

To provide a display device and a manufacturing method that can prevent the occurrence of cracks. [Solution] The display device according to the embodiment of this specification includes a display area on a substrate that includes a plurality of pixels, a plurality of insulating layers disposed in the display area, a first bank and a second bank disposed on the plurality of insulating layers, a first electrode disposed on the first bank and the second bank, and a first optical layer that includes at least one microLED disposed on the first bank and the second bank and a portion of the first bank and the at least one microLED, and a second electrode disposed on the upper and side surfaces of the first optical layer and connected to the connecting electrode.

Description

Technical Field

[0001] The present disclosure relates to an LED display device and a manufacturing method thereof, and particularly to a micro LED display device and a manufacturing method thereof that can improve the phenomenon of cracking or breaking of electrodes due to connection between electrodes when a second electrode is connected to a connection electrode.

Background Art

[0002] In recent years, with the increase in the size of display devices, the demand for flat display elements with less space occupation has been increasing, and organic light-emitting display devices (organic electroluminescent display (OLED) devices) including liquid crystal display (LCD) devices or organic light-emitting diodes (OLEDs) have been developing at a rapid pace in the technology of flat display devices.

[0003] In recent years, in order to overcome the above problems of liquid crystal display devices and / or organic light-emitting display devices, LED display devices using LEDs (Light emitting diodes) as light-emitting elements have been proposed. In LED display devices, small LEDs such as mini LEDs or ultra-small LEDs such as micro LEDs can be used.

[0004] Such an LED display device is a display device that arranges ultra-small LEDs of mini or micro units in each subpixel to embody an image, and has great advantages in terms of low power consumption and miniaturization.

[0005] In the case of a vertical (Vertical) structure LED where the cathode above the LED is connected to the second electrode and the anode below the LED is connected to the first electrode, the LED is arranged, the second electrode is arranged above the LED, and the pixel driving circuit of the substrate and the cathode of the LED can be electrically connected. The LED and the insulating layer can be arranged on the pixel driving circuit of the substrate, and a contact hole of the insulating layer can be formed for the electrical connection between the second electrode and the pixel driving circuit.

[0006] As the second electrode is formed inside the contact hole to connect to the pixel driving circuit at the bottom of the contact hole, cracks may occur in the second electrode, causing it to break or snap depending on the depth of the contact hole.

[0007] A method is needed to prevent the occurrence of such cracks in the second electrode. [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] This disclosure aims to solve the above-mentioned problems and to provide a display device and manufacturing method that can prevent cracks from occurring when the second electrode, which is connected to the upper part of a vertical LED, is connected to a pixel driving circuit on a substrate. [Means for solving the problem]

[0009] The display device according to the embodiment of the present disclosure may include a display area on a substrate containing a plurality of pixels, a plurality of insulating layers disposed in the display area, a first bank and a second bank disposed on the plurality of insulating layers, a first electrode disposed on the first bank and the second bank, and a first optical layer that includes at least one microLED disposed on the first bank and the second bank and a portion of the first bank and the at least one microLED, and a second electrode disposed on the first bank and the upper and side surfaces of the first optical layer and connected to the connecting electrode.

[0010] A method for manufacturing a display device according to an embodiment of the present disclosure includes the steps of forming a pixel driving circuit on a substrate, forming a plurality of insulating layers on the pixel driving circuit, forming a first bank and a second bank on the plurality of insulating layers, forming a connecting electrode on the first bank, and arranging at least one microLED on the first bank and the second bank, and further includes the steps of forming a first optical layer surrounding the first bank, the second bank and the at least one microLED, and arranging a second electrode on the first optical layer, wherein the second electrode is connected to a connecting electrode on the first bank, and the connecting electrode and the second electrode may be formed extending along the side surface of the first bank.

[0011] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0012] This disclosure can prevent cracks from occurring in the second electrode of an LED display device, thereby providing a long-life, low-power display device.

[0013] This disclosure makes it possible to reduce process costs by minimizing the steps required to connect the second electrode and the connecting electrode.

[0014] The effects of this disclosure are not limited to those mentioned above, and any other effects not mentioned can be clearly understood by those skilled in the art from the description of the claims. [Brief explanation of the drawing]

[0015] [Figure 1] This is an exploded perspective view of a display device according to one embodiment of this specification. [Figure 2] This is a plan view of a display device according to one embodiment of this specification. [Figure 3] This is a plan view of the display device, enlarged from the three regions shown in Figure 2. [Figure 4] This is a cross-sectional view along line A-A' in Figure 3 relating to one embodiment of this specification. [Figure 5]It is a plan view of a display device according to an embodiment of the present specification. [Figure 6] It is an enlarged view of a light-emitting element according to an embodiment of the present specification. [Figure 7a] It is a cross-sectional view taken along the line a-a' of FIG. 5 according to an embodiment of the present specification. [Figure 7b] It is a cross-sectional view taken along the line b-b' of FIG. 5 according to an embodiment of the present specification. [Figure 7c] It is a cross-sectional view taken along the line c-c' of FIG. 5 according to an embodiment of the present specification. [Figure 8] It is a plan view of a display device according to another embodiment of the present specification. [Figure 9a] It is a cross-sectional view taken along the line a1-a1' of FIG. 8 according to another embodiment of the present specification. [Figure 9b] It is a cross-sectional view taken along the line b1-b1' of FIG. 8 according to another embodiment of the present specification. [Figure 10] It is a plan view showing a display device according to an embodiment of the present invention.

Mode for Carrying Out the Invention

[0016] The advantages, features, and methods for achieving them of the present specification will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but is embodied in various different forms. Merely, these embodiments are provided so that the disclosure of the present specification becomes complete and that those having ordinary knowledge in the technical field to which the present specification pertains are fully informed of the scope of the invention.

[0017] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so this specification is not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining this specification, if it is determined that a detailed description of related known technologies may muddy the gist of this specification, the detailed description thereof will be omitted. When terms such as "including", "having", or "made" mentioned in this specification are used, other parts can be added as long as terms such as "only" are not used. When a component is expressed in the singular, it includes the case of including a plurality unless there are specific descriptions to the contrary.

[0018] When interpreting a component, it is interpreted as including an error range even if there is no separate explicit description about the error range.

[0019] When it is an explanation about a positional relationship, for example, when a positional relationship between two parts is described such as "above", "on the upper part", "on the lower part", "next to", or "adjacent to", one or more other parts may be located between the two parts as long as terms such as "immediately", "directly", or "close" are not used.

[0020] When it is an explanation about a temporal relationship, when a temporal precedence relationship is described such as "after", "subsequent to", "next", or "before", it may include cases where it is not continuous as long as terms such as "immediately" or "directly" are not used.

[0021] The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical idea of this specification.

[0022] In describing the components of this specification, terms such as 1st, 2nd, A, B, (a), or (b) may be used. Such terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of the component in question.

[0023] Where it is stated that one component is “connected,” “joined,” “attached,” or “pasted” to another component, it should be understood that the component may be directly connected, joined, attached, or pasted to the other component, but other components may be interposed between each component that may be indirectly connected, joined, attached, or pasted unless otherwise explicitly stated.

[0024] Where it is stated that a component or layer "contacts" or "overlays" another component or layer, it should be understood that the component or layer may directly contact or overlap with another component or layer, but other components may be interposed between each component that may indirectly contact or overlap, unless otherwise explicitly stated.

[0025] "At least one" should be understood to include all combinations of one or more related components. For example, "at least one of the first, second, and third components" means not just the first, second, or third component, but all combinations of two or more of the first, second, and third components.

[0026] The terms "first direction," "second direction," "third direction," and "axial direction" should not be interpreted solely as geometric relationships where the relationships are perpendicular to each other, but may mean that there are broader directions within the scope in which the configuration of this specification can function.

[0027] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0028] Various embodiments of this specification will be described in detail below with reference to the attached drawings.

[0029] Figure 1 is a perspective view showing a display device according to one embodiment of this specification. Figure 2 is a plan view of the display device according to one embodiment of this specification. Figure 3 is an enlarged view of the display device according to one embodiment of this specification, and Figure 4 is a cross-sectional view along line A-A' in Figure 3 according to one embodiment of this specification.

[0030] Referring to Figures 1 to 4, a display device 1000 according to one embodiment of this specification may include a display panel 100, a polarizing layer 293, an adhesive layer 295, a cover member 200, a support substrate 300, a ductile circuit board 400, and a printed circuit board 500. The cover member 200 can be attached to the display panel 100 using the adhesive layer 295. The adhesive layer 295 may also be placed between the display panel 100 and the polarizing layer 293, or between the display panel 100 and the support substrate 300.

[0031] The adhesive layer 295 may include, but is not limited to, an optically clear adhesive (OCA), an optically clear resin (OCR), or a pressure-sensitive adhesive (PSA).

[0032] For example, the display panel 100 of the display device 1000 may include a substrate 110. The substrate 110 may be a member that supports other components of the display device 1000. The substrate 110 may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. The substrate 110 may also be made of a flexible material. For example, the substrate 110 may be made of a flexible plastic material such as polyimide (PI). However, the examples in this specification are not limited thereto.

[0033] The display panel 100 can embody information, video, and / or images provided to the user. For example, the display panel 100 may include a display area AA and a non-display area NA. For example, the substrate 110 may include a display area AA and a non-display area NA. The display area AA and non-display area NA are not limited to the substrate 110, but may be described in relation to the display device 1000 in general.

[0034] Display area AA may be the area where the image is displayed. Display area AA may contain multiple pixels PX. Each of the multiple pixels PX may consist of multiple subpixels. Each of the multiple subpixels may have multiple microLEDs arranged within it.

[0035] Multiple micro-LEDs may be configured differently depending on the type of display device 1000.

[0036] The non-display area NA may be an area where no image is displayed. Various wirings and circuits for driving multiple pixels PX of the display area AA may be arranged in the non-display area NA. For example, various wirings and drive circuits may be mounted in the non-display area NA, and a pad portion PAD to which integrated circuits and printed circuits are connected may be arranged, but the embodiments of this specification are not limited thereto.

[0037] For example, the drive circuit may be a data drive circuit and / or a gate drive circuit, but the embodiments herein are not limited thereto. Wiring may be provided to supply control signals for controlling the drive circuit. For example, the control signals may include various timing signals, including a clock signal, an input data enable signal, and a synchronization signal, but the embodiments herein are not limited thereto. The control signals may be received through a pad section PAD. For example, a link wiring LL for transmitting signals may be provided in a non-display area NA. For example, drive components such as a ductile circuit board 400 and a printed circuit board 500 may be connected to the pad section PAD.

[0038] According to this specification, the non-display area NA may include a first non-display area NA1, a bending area BA, and a second non-display area NA2. For example, the first non-display area NA1 may be an area surrounding at least a portion of the display area AA. The bending area BA is an area extending from at least one of the multiple sides of the first non-display area NA1 and may be a bendable area. The second non-display area NA2 is an area extending from the bending area BA and may have a pad portion PAD. For example, the bending area BA may be in a bent state, and the remaining area of ​​the substrate 110 excluding the bending area BA may be in a flat state. In this case, the bending of the bending area BA may cause the second non-display area NA2 to be located on the back surface of the display area AA. However, the embodiments of this specification are not limited thereto.

[0039] The display area AA of the substrate 110 or the display device 1000 can be configured in various shapes depending on the design of the display device 1000. For example, the display area AA may be configured in a rectangular shape with rounded corners, but the embodiments described herein are not limited to this. To give other examples, the display area AA may be configured in a rectangular shape with right-angled corners, a circular shape, etc., but the embodiments described herein are not limited to these.

[0040] According to this specification, the width of the second non-display area NA2, where multiple pad electrodes PE are arranged, may be wider than the width of the bending area BA, where only multiple link wirings LL are arranged. Similarly, the width of the display area AA, where multiple subpixels are arranged, may be wider than the width of the bending area BA, where only multiple link wirings LL are arranged. In the drawings, the width of the bending area BA is shown to be narrower than the width of other areas of the substrate 110, but the shape of the substrate 110 including the bending area BA is illustrative, and the embodiments described herein are not limited thereto.

[0041] Referring to Figure 4, multiple pixel driver circuits PD can be arranged in display area AA. The multiple pixel driver circuits PD may be circuits for driving multiple sub-pixel micro-LEDs. Each of the multiple pixel driver circuits PD includes multiple transistors, including a drive transistor, and a storage capacitor, etc., and can supply control signals, power, and drive current to the multiple sub-pixel micro-LEDs to control the light emission operation of the multiple micro-LEDs. For example, the pixel driver circuit PD may include power supply wiring and signal wiring for controlling the on / off and / or light emission time of the micro-LEDs. For example, the multiple pixel driver circuits PD may be drive drivers manufactured on a semiconductor substrate using a MOSFET (Metal-oxide-silicon field effect transistor) manufacturing process, but the embodiments described herein are not limited thereto. A drive driver includes multiple pixel driver circuits PD and can drive multiple sub-pixels.

[0042] Referring together with Figure 1, a ductile circuit board 400 and a printed circuit board 500 may be arranged at the bottom of the display panel 100. The ductile circuit board 400 and the printed circuit board 500 may be arranged at least on one side edge of the display panel 100, but the embodiments herein are not limited thereto.

[0043] A pad section PAD containing multiple pad electrodes PE may be arranged in the second non-display area NA2. A drive component including one or more ductile circuit boards (or flexible films) 400 and printed circuit boards 500 may be attached to or bonded to the pad section PAD. The multiple pad electrodes PE of the pad section PAD are electrically connected to one or more ductile circuit boards (or flexible films) 400, and can transmit various signals (or power) from the printed circuit boards 500 and ductile circuit boards (or flexible films) 400 to multiple pixel drive circuits PD of the display area AA.

[0044] The ductile circuit board (or flexible film) 400 may be a film in which various components are arranged on a ductile base film. For example, a drive IC such as a gate driver IC or a data driver IC may be arranged on the ductile circuit board (or flexible film) 400, but the embodiments herein are not limited thereto.

[0045] Referring to Figures 1 to 3, multiple link wirings LL may be arranged in the non-display area NA. The multiple link wirings LL may be wirings that transmit various signals from one or more ductile circuit boards (or flexible films) 400 and printed circuit boards 500 to the display area AA. The multiple link wirings LL may extend from multiple pad electrodes PE in the second non-display area NA2 toward the bending area BA and the first non-display area NA1 and be electrically connected to multiple drive wirings VL in the display area AA.

[0046] Multiple drive wirings VL can be arranged in the display area AA and electrically connected to each of the multiple pixel drive circuits PD.

[0047] When the bending region BA is bent, a portion of the multiple link wirings LL may also be bent. Stress may concentrate on the bent portion of the link wirings LL, which may cause cracks to form in the link wirings LL. Therefore, the multiple link wirings LL may be made of a highly ductile conductive material to reduce cracking when the bending region BA is bent. For example, the multiple link wirings LL may be made of a highly ductile conductive material such as gold (Au), silver (Ag), or aluminum (Al), but the embodiments described herein are not limited to these. Furthermore, the multiple link wirings LL may be made of one of the various conductive materials used in the display region AA. For example, the multiple link wirings LL may be made of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloy of silver (Ag) and magnesium (Mg), or alloys thereof, but the embodiments described herein are not limited to these. The multiple link wirings LL may be made of a multilayer structure containing various conductive materials. For example, multiple link wirings LL may be constructed in a triple-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments described herein are not limited thereto.

[0048] On the other hand, for illustrative purposes, Figure 3 shows that the cutting line A-A' does not overlap with the drive wiring VL and link wiring LL. However, the cutting line A-A' in Figure 3 is intended to indicate the same position as the adjacent drive wiring VL and link wiring LL.

[0049] Referring to Figure 4, the first buffer layer 111a and the second buffer layer 111b may be arranged in the remaining area of ​​the substrate 110 excluding the bending region BA.

[0050] The first buffer layer 111a and the second buffer layer 111b may be arranged in the display area AA, the first non-display area NA1, and the second non-display area NA2. The first buffer layer 111a and the second buffer layer 111b can reduce the penetration of moisture or impurities through the substrate 110. The first buffer layer 111a and the second buffer layer 111b may consist of an inorganic insulating material. For example, the first buffer layer 111a and the second buffer layer 111b may consist of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the embodiments herein are not limited thereto.

[0051] For example, portions of the first buffer layer 111a and the second buffer layer 111b located on the bending region BA may be removed. The upper surface of the substrate 110 located in the bending region BA may be exposed from the first buffer layer 111a and the second buffer layer 111b. By removing the first buffer layer 111a and the second buffer layer 111b, which are made of inorganic insulating material, in the bending region BA, cracks in the first buffer layer 111a and the second buffer layer 111b that may occur during bending can be minimized.

[0052] Multiple alignment keys MK may be placed between the first buffer layer 111a and the second buffer layer 111b. These multiple alignment keys MK may be configured to identify the position of the pixel drive circuit PD during the manufacturing process of the display device 1000. For example, they may be configured to align the positions of the pixel drive circuit PD transferred onto the adhesive layer 112. Alternatively, the multiple alignment keys MK may be omitted.

[0053] An adhesive layer 112 may be placed on the second buffer layer 111b. The adhesive layer 112 may be placed in the display area AA, the first non-display area NA1, the bending area BA, and the second non-display area NA2. In other examples, at least a portion of the adhesive layer 112 may be removed in the non-display area NA, including the bending area BA. For example, the adhesive layer 112 may consist of one of the following: an adhesive polymer, an epoxy resin, a UV-curable resin, a polyimide series, an acrylate series, a urethane series, and polydimethylsiloxane (PDMS), but the examples herein are not limited to these.

[0054] A pixel drive circuit PD may be placed on the adhesive layer 112 in the display area AA. When the pixel drive circuit PD is embodied in a drive driver, the drive driver may be mounted on the adhesive layer 112 by a transfer process, but the embodiments herein are not limited thereto.

[0055] The first protective layer 113a and the second protective layer 113b may be arranged on the adhesive layer 112 and the upper or side surface of the pixel drive circuit PD. The first protective layer 113a and the second protective layer 113b may be arranged to surround the side surface of the pixel drive circuit PD, but the embodiments herein are not limited thereto. For example, the second protective layer 113b may be arranged to cover at least a portion of the upper surface of the pixel drive circuit PD.

[0056] For example, at least one of the first protective layer 113a and the second protective layer 113b, which are located on the bending region BA, may be omitted. For example, the first protective layer 113a may be located entirely on the display region AA and the non-display region NA, and the second protective layer 113b may be located partially on the display region AA, the first non-display region NA1, and the second non-display region NA2. For example, a portion of the second protective layer 113b located on the bending region BA may be removed. However, the embodiments of this specification are not limited thereto.

[0057] The first protective layer 113a and the second protective layer 113b may be composed of an organic insulating material, but the examples herein are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the examples herein are not limited thereto. For example, the first protective layer 113a and the second protective layer 113b may be an overcoating layer or an insulating layer, but the examples herein are not limited thereto.

[0058] According to this specification, a plurality of first connection wires 121 may be arranged on the second protective layer 113b in the display area AA. The plurality of first connection wires 121 may be wires for electrically connecting the pixel drive circuit PD to other components. For example, the pixel drive circuit PD may be electrically connected to a plurality of signal wires TL and a plurality of connection electrodes CCE, etc., through the plurality of first connection wires 121. For example, the plurality of first connection wires 121 may include a 1-1 connection wire 121a, a 1-2 connection wire 121b, a 1-3 connection wire 121c, and a 1-4 connection wire 121d, and the 1-1 connection wire 121a, a 1-2 connection wire 121b, a 1-3 connection wire 121c, and a 1-4 connection wire 121d may be electrically connected through contact holes formed in the insulating layer between each connection wire, but the embodiments herein are not limited thereto. Each of the multiple first connection lines 121 is a line that points to a signal line located on the same layer, and the multiple first connection lines 121 may include signal lines to which different signals are applied.

[0059] For example, a third protective layer 114 may be placed on the second protective layer 113b. The third protective layer 114 may be placed entirely over the display area AA, the dam area DA, and the non-display area NA.

[0060] In the bending region BA, the third protective layer 114 can cover or overlap the sides of the second protective layer 113b and the top surface of the first protective layer 113a. The third protective layer 114 may be composed of an organic insulating material. For example, the third protective layer 114 may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the examples herein are not limited thereto. For example, the first protective layer 113a, the second protective layer 113b, and the third protective layer 114 may be composed of the same material, but the examples herein are not limited thereto.

[0061] A plurality of first-to-second connection wirings 121b may be arranged on the third protective layer 114, and a first insulating layer 115a may be arranged on the plurality of first-to-second connection wirings 121b. The first insulating layer 115a may be arranged entirely over the display area AA and the non-display area NA, but the embodiments herein are not limited thereto. The first insulating layer 115a may be composed of an organic insulating material, but the embodiments herein are not limited thereto. For example, the first insulating layer 115a may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the embodiments herein are not limited thereto.

[0062] Multiple first- to third connection wires 121c may be arranged on the first insulating layer 115a. Multiple first- to third connection wires 121c may be electrically connected to multiple first- to second connection wires 121b. For example, the first- to third connection wires 121c may be electrically connected to the first- to second connection wires 121b through contact holes in the first insulating layer 115a.

[0063] A second insulating layer 115b may be placed on a plurality of first-to-third connection wirings 121c. The second insulating layer 115b may be placed in the remaining area excluding the bending area BA, but the embodiments herein are not limited thereto. The second insulating layer 115b may be placed in the display area AA, the first non-display area NA1, and the second non-display area NA2, but the embodiments herein are not limited thereto. For example, a portion of the second insulating layer 115b placed in the bending area BA may be removed. The second insulating layer 115b may be composed of an organic insulating material, but the embodiments herein are not limited thereto. For example, the second insulating layer 115b may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the embodiments herein are not limited thereto.

[0064] Multiple first- to fourth connection wires 121d may be arranged on the second insulating layer 115b. Multiple first- to fourth connection wires 121d may be electrically connected to multiple first- to third connection wires 121c. For example, the first- to fourth connection wires 121d may be electrically connected to the first- to third connection wires 121c through contact holes in the second insulating layer 115b.

[0065] Multiple signal lines TL may be arranged on the third insulating layer 115c in display area AA. Multiple signal lines TL may extend into areas between multiple banks BNK. For example, multiple signal lines TL may be arranged adjacent to any one of the multiple banks BNK.

[0066] According to this specification, a plurality of second connection lines 122 may be arranged on the second protective layer 113b in the non-display area NA. The plurality of second connection lines 122 may be wiring for transmitting signals transmitted to the pad portion PAD on the ductile circuit board (or flexible film) 400 and the printed circuit board 500 (see Figure 1) to the pixel driving circuit PD of the display area AA. For example, the plurality of second connection lines 122 may be electrically connected to a plurality of pad electrodes PE and be able to receive signals applied from the ductile circuit board (or flexible film) 400 and the printed circuit board 500.

[0067] For example, multiple second connection wires 122 can extend from the pad portion PAD toward the display area AA and transmit signals to the wiring of the display area AA. In this case, the multiple second connection wires 122 can function as link wires LL. The multiple second connection wires 122 may include 2-1 connection wires 122a, 2-2 connection wires 122b, 2-3 connection wires 122c, and 2-4 connection wires 122d. Thus, signals from the ductile circuit board (or flexible film) 400 and the printed circuit board 500 can be transmitted to the 2-1 connection wire 122a through the 2-4 connection wires 122d, 2-3 connection wires 122c, and 2-2 connection wires 122b.

[0068] The multiple first connecting wires 121 and the multiple second connecting wires 122 may be formed from either a conductive material with excellent ductility or one of a variety of conductive materials used in the display area AA.

[0069] For example, the multiple first connecting wires 121 and the multiple second connecting wires 122 may be composed of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of silver (Ag) and magnesium (Mg), or alloys thereof, but the embodiments herein are not limited thereto.

[0070] A third insulating layer 115c may be placed on a plurality of first connection wires 121 and a plurality of second connection wires 122. The third insulating layer 115c may be placed in the remaining area excluding the bending area BA, but the embodiments herein are not limited thereto. The third insulating layer 115c may be placed in the display area AA, the dam area DA, the first non-display area NA1, and the second non-display area NA2. A portion of the third insulating layer 115c in the bending area BA may be removed. The third insulating layer 115c may be composed of an organic insulating material, but the embodiments herein are not limited thereto. For example, the third insulating layer 115c may be composed of a photoresist, polyimide (PI), or photoacrylic material, but the embodiments herein are not limited thereto.

[0071] In the bending region BA, the substrate 110 is bent, and the second non-display region NA2 may overlap the display region AA in at least a portion. In order for the substrate 110 to be bent, the layers placed on the substrate 110 may be minimized to prevent the occurrence of cracks. Therefore, it is not necessary to form the first buffer layer 111a, the second buffer layer 111b, the second protective layer 113b, the second insulating layer 115b, or the third insulating layer 115c in the bending region BA, but the embodiments of this specification are not limited thereto.

[0072] Multiple banks BNK may be arranged on the third insulating layer 115c in display area AA. Multiple banks BNK may be arranged so as to superimpose on each of multiple subpixels. One or more micro-LEDEDs emitting light of the same hue may be placed on top of each of the multiple banks BNK.

[0073] Referring to Figure 5, the multiple banks BNK may include a first bank BNK1 and a second bank BNK2. The first bank BNK1 and the second bank BNK2 may be formed in the same process, and the first bank BNK1 and the second bank BNK2 may be formed having a first width in the first direction X and a second width in the second direction Y. In this case, the second width of the first bank BNK1 may be formed to be larger than the second width of the second bank BNK2.

[0074] Multiple bank BNKs may consist of photoresists, polyimides (PI), or photoacrylic materials, but the examples herein are not limited to these.

[0075] Multiple connection electrodes CCE can be arranged on the third insulating layer 115c in the display area AA. The multiple connection electrodes CCE can supply the cathode voltage from the pixel driving circuit PD to the second electrode CE2.

[0076] A first electrode CE1 may be positioned on bank BNK. For example, the first electrode CE1 may extend from an adjacent signal trace TL toward the top of bank BNK. The first electrode CE1 may be positioned on the top surface and the side surface of bank BNK. For example, the first electrode CE1 may extend from a signal trace TL on the top surface of the third insulating layer 115c toward the side surface and the top surface of bank BNK.

[0077] The first electrode CE1 may be composed of multiple conductive layers. For example, the first electrode CE1 may include a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d, but the examples herein are not limited thereto.

[0078] The first conductive layer CE1a may be placed on bank BNK. The second conductive layer CE1b may be placed on the first conductive layer CE1a. The third conductive layer CE1c may be placed on the second conductive layer CE1b. The fourth conductive layer CE1d may be placed on the third conductive layer CE1c. For example, the first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d may each be composed of titanium (Ti), molybdenum (Mo), aluminum (Al), or titanium (Ti) and indium tin oxide (ITO), but the examples herein are not limited thereto.

[0079] According to this specification, a solder pattern SDP may be placed on the first electrode CE1 for each of several subpixels. The solder pattern SDP can be used to bond a micro-LEDED to the first electrode CE1, thereby electrically connecting the first electrode CE1 and the micro-LEDED. For example, the first electrode CE1 and the anode electrode 134 of the micro-LEDED can be electrically connected through eutectic bonding using the solder pattern SDP, but the embodiments herein are not limited thereto. For example, if the solder pattern SDP is made of indium (In) and the anode electrode 134 of the micro-LEDED is made of gold (Au), the solder pattern SDP and the anode electrode 134 can be bonded by applying heat and pressure during the transfer process of the micro-LEDED. The micro-LEDED can be bonded to the solder pattern SDP and the first electrode CE1 through eutectic bonding without the need for a separate adhesive.

[0080] According to this specification, the passivation layer 116 may be placed on a plurality of signal lines TL, a plurality of first electrodes CE1, a plurality of connecting electrodes CCE, and a third insulating layer 115c. For example, the passivation layer 116 may be placed in a display area AA, a first non-display area NA1, and a second non-display area NA2. A portion of the passivation layer 116 placed in the bending area BA may be removed. A portion of the passivation layer 116 covering a plurality of pad electrodes PE in the second non-display area NA2 may be removed. Since the passivation layer 116 is placed to cover the remaining area excluding the bending area BA, the plurality of pad electrodes PE, and the area where the solder pattern SDP is placed, the penetration of moisture or impurities into the micro-LEDED placed on top of the insulating layer formed of organic material can be reduced. For example, the passivation layer 116 may consist of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the embodiments herein are not limited thereto.

[0081] A micro-LEDED may be placed on the solder pattern SDP for each of the multiple sub-pixels. A first micro-LED130 may be placed on the first sub-pixel SP1. A second micro-LED140 may be placed on the second sub-pixel SP2.

[0082] According to this specification, a first optical layer 117a may be arranged to surround a plurality of micro-LEDEDs in a display area AA. The first optical layer 117a may be arranged continuously across a plurality of pixels PX. For example, the first optical layer 117a may be arranged to cover a plurality of micro-LEDEDs and a bank BNK in the area of ​​a plurality of subpixels. For example, the first optical layer 117a may cover the area between the bank BNK, a portion of the passivation layer 116, and a plurality of micro-LEDEDs. The first optical layer 117a may be arranged to cover the area between a plurality of micro-LEDEDs contained in a single pixel PX, and between a plurality of bank BNKs. For example, the first optical layer 117a may extend in a first direction X and be arranged to be separated from each other in a second direction Y that intersects the first direction X. For example, the first optical layer 117a may be arranged to surround at least a portion of the side of a micro-LEDED and a bank BNK between the passivation layer 116 and the second electrode CE2, but the embodiments herein are not limited thereto.

[0083] The first optical layer 117a may include an organic insulating material in which fine particles are dispersed, but the examples herein are not limited thereto. For example, the first optical layer 117a may consist of a siloxane in which fine metal particles, such as titanium dioxide (TiO2) particles, are dispersed, but the examples herein are not limited thereto. Light from multiple micro-LEDEDs can be scattered by the fine particles dispersed in the first optical layer 117a and emitted outside the display device 1000. Thus, the first optical layer 117a can improve the extraction efficiency of light emitted by the multiple micro-LEDEDs.

[0084] For example, the first optical layer 117a may be placed in each of several pixels PX, or it may be placed together in some of the pixels PX arranged in the same row, but the embodiments herein are not limited thereto. For example, each of several pixels PX may have a first optical layer 117a, or several pixels PX may share one first optical layer 117a. Another example is that each of several subpixels may separately include a first optical layer 117a, but the embodiments herein are not limited thereto.

[0085] The cathode electrode 135 of the micro-LEDED may be exposed, and thereafter, a portion of the first optical layer 117a on the cathode electrode 135 may be removed in order to connect it with the second electrode CE2.

[0086] A second electrode CE2 may be formed on the micro-LEDED and the first optical layer 117a of the display area AA. For example, the second electrode CE2 may be electrically connected to a connecting electrode CCE located on the second bank BNK2. The connecting electrode CCE may be electrically connected to the pixel driving circuit PD through a plurality of connecting wires. Referring to Figure 7a, the connecting electrode CCE may be formed on the third insulating layer 115c, extending along the side of the second bank BNK2 in the second direction Y, and formed on the top of the second bank BNK2. The second electrode CE2 may be located on a plurality of micro-LEDEDs and electrically connected to the cathode electrode 135 of the micro-LEDs. For example, the second electrode CE2 may include, but is not limited to, a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0087] A second optical layer 117b may be disposed on a passivation layer 116 where the first optical layer 117a is not disposed. For example, the second optical layer 117b may be disposed so as to surround the first optical layer 117a. For example, the second optical layer 117b may be formed on the side surface of the first optical layer 117a. For example, the second optical layer 117b may be disposed in the region between a plurality of pixels PX. However, the embodiments herein are not limited thereto. For example, the second optical layer 117b may be a diffusion layer, a diffusion layer window, or a window diffusion layer, etc., but the embodiments herein are not limited thereto.

[0088] A third optical layer 117c may be placed on the second electrode CE2. The third optical layer 117c may be placed so as to overlap the plurality of micro-LEDEDs and the first optical layer 117a. Since the third optical layer 117c is placed on top of the second electrode CE2 and the plurality of micro-LEDEDs, it can improve unevenness that may occur in some of the plurality of micro-LEDEDs, and the light emitted by the plurality of micro-LEDEDs is uniformly diffused by the third optical layer 117c and extracted to the outside of the display device 1000, so the brightness uniformity of the display device 1000 can be improved.

[0089] The third optical layer 117c may consist of an organic insulating material in which fine particles are dispersed, but the examples herein are not limited thereto. For example, the third optical layer 117c may consist of a siloxane in which fine metal particles such as titanium dioxide (TiO2) particles are dispersed, but the examples herein are not limited thereto. For example, the third optical layer 117c may consist of the same material as the first optical layer 117a, but the examples herein are not limited thereto.

[0090] In the display area AA, a black matrix BM can be arranged on the second electrode CE2, the first optical layer 117a, the second optical layer 117b, and the third optical layer 117c.

[0091] The black matrix BM is configured to cover the display area AA, thereby reducing the mixing of light from multiple subpixels and external light reflection.

[0092] For example, the black matrix BM may consist of an opaque material, but the examples herein are not limited thereto. For example, the black matrix BM may be an organic insulating material to which a black pigment or black dye has been added, but the examples herein are not limited thereto.

[0093] A cover layer 118 may be placed on the black matrix BM in display area AA. The cover layer 118 can protect the structure beneath it. For example, the cover layer 118 may be made of an organic insulating material, but the examples herein are not limited thereto. For example, the cover layer 118 may be made of a photoresist, polyimide (PI), or photoacrylic material, but the examples herein are not limited thereto. For example, the cover layer 118 may be an overcoating layer or an insulating layer, but the examples herein are not limited thereto.

[0094] The cover layer 118 may be formed to be thicker than the adhesive layer 112, the first protective layer 113a, the third protective layer 114, and the first insulating layer 115a, which are placed in the bending region BA to protect the micro-LEDED and electrodes of the display region AA. If the cover layer 118 extends beyond the bending region BA, the total thickness of the layers placed in the bending region BA will increase, which may cause bending defects.

[0095] A polarizing layer 293 may be placed on the cover layer 118 via a first adhesive layer 291. Furthermore, a cover member 200 may be placed on the polarizing layer 293 via a second adhesive layer 295. For example, the first adhesive layer 291 and the second adhesive layer 295 may include optically clear adhesive (OCA), optically clear resin (OCR), or pressure-sensitive adhesive (PSA), but the examples herein are not limited thereto.

[0096] Figures 5 to 9b are plan views and cross-sectional views of a display device according to one embodiment of this specification.

[0097] For example, Figure 5 is an enlarged plan view of a display area containing multiple pixels.

[0098] Referring to Figure 5, multiple signal lines TL, multiple communication lines NL, multiple first electrodes CE1, multiple connection electrodes CCE, multiple banks BNK, multiple micro-LEDEDs, and second electrodes CE2 are shown, but the embodiments described herein are not limited thereto.

[0099] Referring to Figure 5, multiple pixels PX, each composed of multiple subpixels, can be arranged in the display area AA. Each of the multiple subpixels includes a micro-LEDED and can emit light independently. The multiple subpixels can be arranged in a matrix configuration with multiple rows and multiple columns, where the row direction may be the first direction X and the column direction may be the second direction Y.

[0100] Each of the multiple pixels PX may include one or more first subpixels SP1, one or more second subpixels SP2, and one or more third subpixels SP3. For example, one pixel PX may include a pair of first subpixels SP1, a pair of second subpixels SP2, and a pair of third subpixels SP3. A pair of first subpixels SP1 may consist of a 1-1 subpixel SP1a and a 1-2 subpixel SP1b. A pair of second subpixels SP2 may consist of a 2-1 subpixel SP2a and a 2-2 subpixel SP2b. A pair of third subpixels SP3 may consist of a 3-1 subpixel SP3a and a 3-2 subpixel SP3b. For example, one pixel PX may include a 1-1 subpixel SP1a and a 1-2 subpixel SP1b, a 2-1 subpixel SP2a and a 2-2 subpixel SP2b, and a 3-1 subpixel SP3a and a 3-2 subpixel SP3b, but the embodiments herein are not limited thereto.

[0101] The first-first subpixel SP1a and the first-second subpixel SP1b of a pair of first subpixels SP1 may be equipped with a first-first microLED 130a and a first-second microLED 130b, respectively, and the embodiments herein are not limited thereto.

[0102] The second-first subpixel SP2a and the second-second subpixel SP2b of a pair of second subpixels SP2 may be equipped with a second-first microLED 140a and a second-second microLED 140b, respectively, and the embodiments herein are not limited thereto.

[0103] The third-first subpixel SP3a and the third-second subpixel SP3b of a pair of third subpixels SP3 may be equipped with a third-first microLED 150a and a third-second microLED 150b, and the embodiments herein are not limited thereto.

[0104] Multiple subpixels constituting a single pixel PX can be arranged in various ways. For example, in a single pixel PX, a pair of first subpixels SP1 may be arranged in the same column, a pair of second subpixels SP2 in the same column, and a pair of third subpixels SP3 in the same column. The first subpixels SP1, the second subpixels SP2, and the third subpixels SP3 may be arranged in the same row. The row direction may be the first direction X, and the column direction may be the second direction Y. The number and arrangement of multiple subpixels constituting a single pixel PX are exemplary, and the embodiments herein are not limited thereto.

[0105] Multiple signal lines TL may be arranged in the region between multiple subpixels. Multiple signal lines TL may extend in the column direction between multiple subpixels. Multiple signal lines TL may be lines that transmit the anode voltage from a pixel drive circuit PD to multiple subpixels. For example, multiple signal lines TL may be electrically connected to multiple pixel drive circuits PD and multiple first electrodes CE1 of multiple subpixels. The anode voltage output by the pixel drive circuit PD can be transmitted to the multiple first electrodes CE1 of multiple subpixels through the multiple signal lines TL. For example, the first electrode CE1 may be an electrode electrically connected to the anode electrode 134 of a micro-LEDED. Thus, the anode voltage from the signal lines TL can be transmitted to the anode electrode 134 of the micro-LEDED through the first electrode CE1.

[0106] Multiple signal lines TL may include a first signal line TL1, a second signal line TL2, a third signal line TL3, a fourth signal line TL4, a fifth signal line TL5, and a sixth signal line TL6. The first signal line TL1 and the second signal line TL2 may each be electrically connected to a pair of first subpixels SP1. The third signal line TL3 and the fourth signal line TL4 may each be electrically connected to a pair of second subpixels SP2. The fifth signal line TL5 and the sixth signal line TL6 may each be electrically connected to a pair of third subpixels SP3.

[0107] A first signal wiring TL1 may be located on one side of a pair of first subpixels SP1, and a second signal wiring TL2 may be located on the other side of the pair of first subpixels SP1. The first signal wiring TL1 may be electrically connected to the first electrode CE1 of one of the pair of first subpixels SP1, for example, the 1-1 subpixel SP1a. The second signal wiring TL2 may be electrically connected to the first electrode CE1 of the remaining first subpixel SP1 of the pair, for example, the 1-2 subpixel SP1b.

[0108] A third signal wiring TL3 may be located on one side of a pair of second subpixels SP2, and a fourth signal wiring TL4 may be located on the other side of the pair of second subpixels SP2. For example, the third signal wiring TL3 may be located adjacent to the second signal wiring TL2. The third signal wiring TL3 may be electrically connected to the first electrode CE1 of one of the second subpixels SP2 of the pair, for example, subpixel 2-1 SP2a. The fourth signal wiring TL4 may be electrically connected to the first electrode CE1 of the remaining second subpixel SP2 of the pair, for example, subpixel 2-2 SP2b.

[0109] A fifth signal wiring TL5 may be located on one side of a pair of third subpixels SP3, and a sixth signal wiring TL6 may be located on the other side of the pair of third subpixels SP3. For example, the fifth signal wiring TL5 may be located adjacent to the fourth signal wiring TL4. The sixth signal wiring TL6 may be located adjacent to the first signal wiring TL1 connected to an adjacent pixel PX. The fifth signal wiring TL5 may be electrically connected to the first electrode CE1 of one of the pair of third subpixels SP3, for example, the 3-1 subpixel SP3a. The sixth signal wiring TL6 may be electrically connected to the first electrode CE1 of the remaining third subpixel SP3 of the pair, for example, the 3-2 subpixel SP3b.

[0110] Multiple signal lines TL may consist of conductive materials. For example, multiple signal lines TL may consist of single or multilayer structures of conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the examples herein are not limited to these.

[0111] Multiple communication lines NL may be arranged in the region between multiple pixels PX. Multiple communication lines NL may extend from the region between the multiple pixels PX in a first direction X. Multiple communication lines NL may be arranged in the region between multiple second electrodes CE2 and may not superimpose on the multiple second electrodes CE2. For example, multiple communication lines NL may be lines used for short-range communication such as NFC (Near Field Communication). Multiple communication lines NL can function as antennas. For example, multiple communication lines NL may be multiple connection lines, etc., but the embodiments herein are not limited thereto.

[0112] According to this specification, a bank BNK may be arranged for each of a plurality of subpixels. The plurality of bank BNKs may be structures on which a plurality of microLEDEDs are attached. The plurality of bank BNKs can guide the position of the plurality of microLEDEDs in a transfer step of transferring the plurality of microLEDEDs to the display device 1000. The plurality of microLEDEDs can be transferred onto the plurality of bank BNKs in the transfer step of the plurality of microLEDEDs. The plurality of bank BNKs may be a bank pattern or a structure, etc., but the embodiments herein are not limited thereto.

[0113] Multiple banks BNK may include a first bank BNK1 and a second bank BNK2. The first bank BNK1 may be located in the second subpixel SP2, and the second bank BNK2 may be located in the first subpixel SP1 and the third subpixel SP3. The second bank BNK2 of the first subpixel SP1, the first bank BNK1 of the second subpixel SP2, and the second bank BNK2 of the third subpixel SP3 may be located spaced apart from each other. That is, the second bank BNK2 of the first subpixel SP1, the first bank BNK1 of the second subpixel SP2, and the second bank BNK2 of the third subpixel SP3 may be configured to be separated from each other.

[0114] In this case, the width of the first bank BNK1 in the second direction Y may be formed to be wider than the width of the second bank BNK2 in the second direction Y.

[0115] Therefore, when different types of micro-LEDEDs are transferred, they can be easily identified as the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0116] For example, the first bank BNK1 and the second bank BNK2 may consist of an organic insulating material. The first bank BNK1 and the second bank BNK2 may consist of a single or multiple layer of the organic insulating material. For example, multiple banks BNK may consist of photoresist, polyimide (PI), or acrylic-based materials, but the examples herein are not limited to these.

[0117] A first electrode CE1 may be placed on each of multiple subpixels. The first electrode CE1 may be placed on the first bank BNK1 and the second bank BNK2. For example, each first electrode CE1 may be placed on the top surface and one side surface of the first bank BNK1 and the second bank BNK2.

[0118] At least a portion of the first electrode CE1 may extend outside the first bank BNK1 and the second bank BNK2 and be electrically connected to the signal wiring TL closest to the first electrode CE1. For example, a portion of the first electrode CE1 of the first-1 subpixel SP1a may extend to one side of the first-1 subpixel SP1a and be electrically connected to the first signal wiring TL1, and a portion of the first electrode CE1 of the first-2 subpixel SP1b may extend to the other side of the first-2 subpixel SP1b and be electrically connected to the second signal wiring TL2.

[0119] The first electrode CE1 is electrically connected to the anode electrode 134 of the micro-LEDED and can transmit the anode voltage from the pixel driving circuit PD to each of the multiple sub-pixel micro-LEDEDs via the signal wiring TL. Different voltages may be applied to the first electrode CE1 of each of the multiple sub-pixels depending on the displayed image. For example, different voltages may be applied to the first electrode CE1 of each of the multiple sub-pixels. Therefore, the first electrode CE1 may be a pixel electrode, and the embodiments described herein are not limited thereto.

[0120] At least one connecting electrode CCE may be provided for each pixel PX. The connecting electrode CCE may be provided on the upper part of the third insulating layer 115c, the upper surface of the second bank BNK2, and on another side where the first electrode CE1 is not formed. The connecting electrode CCE may be electrically connected to the lower wiring and pixel driving circuit PD outside the second bank BNK2. The second bank BNK2 where the connecting electrode CCE is provided may be formed larger than the first bank BNK1 where the connecting electrode CCE is not provided, because it includes the area where the connecting electrode CCE is provided.

[0121] The connecting electrode CCE is electrically connected to the cathode electrode 135 of the microLEDED, and can transmit the cathode voltage from the pixel driving circuit PD to each of the multiple subpixel microLEDEDs through the connecting wiring.

[0122] The multiple micro-LEDEDs may include a first micro-LED 130, a second micro-LED 140, and a third micro-LED 150. The first micro-LED 130 may be located in a first sub-pixel SP1. The second micro-LED 140 may be located in a second sub-pixel SP2. The third micro-LED 150 may be located in a third sub-pixel SP3. For example, one of the first micro-LED 130, the second micro-LED 140, and the third micro-LED 150 may be a red micro-LED, another may be a green micro-LED, and the rest may be blue micro-LEDs, but the embodiments herein are not limited thereto. Thus, by combining the red, green, and blue light emitted by the multiple micro-LEDEDs, a variety of hues of light, including white, can be realized. The types of multiple micro-LEDEDs are illustrative, and the embodiments herein are not limited thereto.

[0123] A second electrode CE2 may be placed on each of multiple subpixels. The second electrode CE2 may be placed on a microLEDED. The second electrode CE2 may be placed sequentially on multiple pixels PX. The second electrode CE2 may be electrically connected to a pixel drive circuit PD through multiple connecting electrodes CCE.

[0124] For example, the second electrode CE2 is electrically connected to the cathode electrode 135 of the micro-LEDED, and can transmit the cathode voltage from the pixel driving circuit PD to the micro-LEDED. The same cathode voltage may be applied to the second electrode CE2 of each of the multiple sub-pixels. For example, the same voltage may be applied to the second electrode CE2 of each of the multiple sub-pixels and the cathode electrode 135 of the micro-LEDED. Therefore, the second electrode CE2 may be a common electrode, but the embodiments described herein are not limited to this.

[0125] At least some of the subpixels can share the second electrode CE2. At least some of the second electrode CE2 of each of the subpixels can be electrically connected to one another. By applying the same voltage to the second electrode CE2, at least some of the second electrode CE2 of subpixels can be shared and used. For example, the second electrode CE2 of at least some of the pixels PX of a group of pixels PX arranged in the same first direction X can be connected to one another. For example, one second electrode CE2 can be placed on multiple pixels PX. One second electrode CE2 can be placed for every n subpixels.

[0126] For example, some of the second electrodes CE2 of each of multiple subpixels may be arranged separately from each other. For instance, the second electrode CE2 connected to the pixel PX of the nth row and the second electrode CE2 connected to the pixel PX of the (n+1)th row may be arranged separately from each other. For example, multiple second electrodes CE2 may be arranged separately from each other, separated by multiple communication lines NL extending in a first direction X which is the row direction.

[0127] Multiple second electrodes CE2 are made of a transparent conductive material, and light emitted by the micro-LEDED can be directed towards the top of the second electrodes CE2. For example, the second electrodes CE2 may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but the examples herein are not limited to these.

[0128] A connecting electrode CCE may be placed on the first bank BNK1. For example, the first bank BNK1 may be formed to be wider in the second direction Y than the second bank BNK2. At least one microLEDED may be placed on the first bank BNK1, and a connecting electrode CCE may be placed in the region in the second direction Y above the first bank BNK1.

[0129] The connecting electrode CCE extends to the other side of the first bank BNK and can be electrically connected to the lower connecting wiring.

[0130] Each second electrode CE2 can be superimposed on at least one connecting electrode CCE. For example, one second electrode CE2 can be superimposed on multiple connecting electrodes CCE.

[0131] For example, multiple connection electrodes CCE can be electrically connected to multiple second electrodes CE2. Multiple connection electrodes CCE are placed between the substrate 110 and the multiple second electrodes CE2, and can transmit the cathode voltage from the pixel driving circuit PD to the second electrodes CE2.

[0132] The second electrode CE2 may be formed to protrude in the second direction Y in order to connect with the connecting electrode CCE. The more the second electrode CE2 overlaps with the lower signal wiring TL, the more parasitic capacitance may be generated between the second electrode CE2 and the signal wiring TL, potentially degrading the performance of the display device. Therefore, the second electrode CE2 may be formed to protrude in the second direction Y only in the area where the connecting electrode CCE is located.

[0133] When using microLEDs as microLEDEDs, multiple microLEDs can be formed on a wafer, and the display device 1000 can be manufactured by transferring the microLEDs to the substrate 110 of the display device 1000. Various defects can occur during the process of transferring multiple microLEDEDs of a fine size from the wafer to the substrate 110. For example, in some subpixels, a non-transfer defect may occur where the microLEDED is not transferred, and in other subpixels, a defect may occur where the microLEDED is transferred outside its designated position due to alignment errors. Also, even if the transfer process proceeds normally, the transferred microLEDED itself may be defective. Therefore, taking into account defects during the transfer process of multiple microLEDEDs, multiple microLEDEDs emitting light of the same hue can be transferred to a single subpixel. After conducting lighting tests on the multiple microLEDEDs, only the one microLEDED that is ultimately judged to be normal can be used.

[0134] For example, both the 1-1 microLED 130a and the 1-2 microLED 130b can be transferred to a single pixel PX, and their defects can be checked. If both the 1-1 microLED 130a and the 1-2 microLED 130b are determined to be normal, only the 1-1 microLED 130a can be used, and the 1-2 microLED 130b does not need to be used. Therefore, even if multiple microLEDs emitting light of the same hue are transferred to a single pixel PX, ultimately only one microLED may be used.

[0135] Therefore, one of the pair of micro-LEDEDs may be the main (or primary) micro-LEDED, and the other micro-LEDED may be a redundant micro-LEDED. The redundant micro-LEDED may be an extra micro-LEDED that is transferred in case of failure of the main micro-LEDED. When the main micro-LEDED fails, the redundant micro-LEDED can be used as a substitute. Thus, by transferring both the main micro-LEDED and the redundant micro-LEDED to a single pixel PX, the degradation of display quality due to failure of the main micro-LEDED and the redundant micro-LEDED can be minimized.

[0136] Ultimately, a black matrix BM can be formed in the display area AA and non-display area NA of a redundant micro-LEDED or main micro-LEDED, excluding the light-emitting area of ​​the micro-LED used in each subpixel, thereby preventing the light emitted from micro-LEDs not used in each subpixel from being emitted upwards.

[0137] Figure 6 is an enlarged view of a light-emitting element according to one embodiment of this specification. Referring to Figure 6, the first micro-LED 130, which is a light-emitting element, may include an anode electrode 134, a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a cathode electrode 135, and a sealing film 136, but the embodiments of this specification are not limited thereto. For example, the sealing film 136 may not be included in the first micro-LED 130.

[0138] For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 may be embodied in a compound semiconductor such as a III-V or II-VI semiconductor, and may be doped with an impurity (or dopant). For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 may be a semiconductor layer doped with an n-type impurity, and the other may be a semiconductor layer doped with a p-type impurity, but the examples of this specification are not limited thereto. For example, one or more of the first semiconductor layer 131 and the second semiconductor layer 133 may be layers doped with n-type or p-type impurities in substances such as gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenide (AlGaAs), or gallium arsenide (GaAs), but the examples of this specification are not limited thereto.

[0139] The active layer 132 may be disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 can emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. For example, the active layer 132 may be configured as one of a single-well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum beam structure, but the examples herein are not limited thereto. For example, the active layer 132 may be composed of indium gallium nitride (InGaN) or gallium nitride (GaN), but the examples herein are not limited thereto.

[0140] An anode electrode 134 may be positioned below the first semiconductor layer 131. The anode electrode 134 may be composed of a conductive material capable of eutectic bonding with the solder pattern SDP. For example, the anode electrode 134 may be composed of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), and copper (Cu), or alloys thereof, but the examples herein are not limited thereto.

[0141] The cathode electrode 135 may be positioned on the second semiconductor layer 133. For example, the cathode electrode 135 can electrically connect the second semiconductor layer 133 and the second electrode CE2. The cathode voltage output by the pixel driving circuit PD can be applied to the second semiconductor layer 133 through the connecting electrode CCE, the second electrode CE2, and the cathode electrode 135. The cathode electrode 135 may be made of a transparent conductive material so that light emitted by the micro-LEDED can be directed towards the top of the micro-LEDED, but the embodiments herein are not limited thereto. For example, the cathode electrode 135 may be made of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), but the embodiments herein are not limited thereto.

[0142] The encapsulation film 136 may be placed on at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135. For example, the encapsulation film 136 may surround at least a portion of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135.

[0143] For example, the encapsulation film 136 can protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. For example, the encapsulation film 136 may be placed on the sides of the first semiconductor layer 131, the sides of the active layer 132, and the sides of the second semiconductor layer 133. For example, the encapsulation film 136 may be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but the examples herein are not limited thereto.

[0144] Figure 7a is a cross-sectional view along line a-a' in Figure 5 relating to one embodiment of this specification.

[0145] A second micro-LED 140 may be arranged on a first bank BNK1, and the first optical layer 117a may be formed to surround a portion of the first bank BNK1 and the second micro-LED 140, and the embodiments herein are not limited thereto.

[0146] Thereafter, the first optical layer 117a can be partially removed through the etching process so that the cathode electrode 135 of the second micro-LED 140 is exposed, and the embodiments herein are not limited thereto.

[0147] The second electrode CE2 is formed on the first optical layer 117a and can be electrically connected to the cathode electrode 135 of the second micro-LED 140 and the connecting electrode CCE on the first bank BNK1. The second electrode CE2 may be positioned extending along the side portion of the first optical layer 117a. The connecting electrode CCE is formed and positioned extending along the top and one side of the first bank BNK1, and the second electrode CE2 can be in contact with the connecting electrode CCE extending along one side of the first bank BNK1, and the embodiments herein are not limited thereto.

[0148] The second electrode CE2 may be positioned such that the width in the second direction Y intersecting the first direction X is wider than the width in the second direction of the first bank BNK1 and the second bank BNK2, and the embodiments herein are not limited thereto.

[0149] The passivation layer 116 positioned on top of the connecting electrode CCE may be partially removed at the contact portion between the second electrode CE2 and the connecting electrode CCE, and the embodiments herein are not limited thereto.

[0150] The second optical layer 117b, which is placed on the passivation layer 116, is positioned on the side of the first optical layer 117a, and the second electrode CE2 may be positioned between the first optical layer 117a and the second optical layer 117b.

[0151] Figure 7b is a cross-sectional view along line b-b' of Figure 5 relating to one embodiment of this specification.

[0152] In regions where the first optical layer 117a is not present, the second electrode CE2 and the connecting electrode CCE may be connected on the first bank BNK1, and the embodiments herein are not limited thereto.

[0153] The second electrode CE2 may be positioned extending along the side of the first bank BNK1.

[0154] Figure 7c is a cross-sectional view along line c-c' of Figure 5 relating to one embodiment of this specification.

[0155] The second electrode CE2 may be formed on the upper and side surfaces of the first optical layer 117a. The second optical layer 117b may be formed on the upper surface of the passivation layer 116 and on the side surfaces of the first optical layer 117a. The second electrode CE2 may be positioned between the first optical layer 117a and the second optical layer 117b, and the embodiments herein are not limited thereto.

[0156] Figure 8 is a plan view of a display device according to another embodiment of this specification. Descriptions of components shown in Figure 8 that are identical or corresponding to those in Figure 6 are omitted or simplified.

[0157] The wider the second electrode CE2, the lower its resistance can be. However, the more the second electrode CE2 overlaps with the signal wiring TL and communication wiring NL below it, the greater the parasitic capacitance can be. Therefore, the width of the second electrode CE2 can be maximized at a position where the signal wiring TL and communication wiring NL are not formed below the second electrode CE2.

[0158] Referring to Figure 8, the second electrode CE2 may extend in the first direction X and be arranged to continuously superimpose on multiple pixels, and may include multiple protrusions extending in the second direction Y for each subpixel SP. The width of the second electrode in the second direction Y may be formed to be the same for each subpixel SP.

[0159] Figure 9a is a cross-sectional view along the line a1-a1' of Figure 8 relating to another embodiment of this specification.

[0160] The second electrode CE2 is formed on the first optical layer 117a and can be electrically connected to the cathode electrode 135 of the second micro-LED 140 and the connecting electrode CCE on the first bank BNK1. The second electrode CE2 may be positioned extending along the side portion of the first optical layer 117a. The connecting electrode CCE is formed and positioned extending along the top and one side of the first bank BNK1, and the second electrode CE2 can be in contact with the connecting electrode CCE extending along one side of the first bank BNK1, and the embodiments herein are not limited thereto.

[0161] The passivation layer 116 positioned on top of the connecting electrode CCE may be partially removed at the contact portion between the second electrode CE2 and the connecting electrode CCE, and the embodiments herein are not limited thereto.

[0162] The second electrode CE2 may be formed wider than the width of the first optical layer 117a and the first bank BNK1 in the second direction Y, and may extend to the top of the passivation layer 116, but the embodiments herein are not limited thereto.

[0163] Figure 9b is a cross-sectional view along line b1-b1' of Figure 8 relating to another embodiment of this specification.

[0164] In the subpixel SP region where the first optical layer 117a is not placed and the first bank BNK1 is placed, the second electrode CE2 and the connecting electrode CCE can be connected on the first bank BNK1.

[0165] The second electrode CE2 may be formed with the same width for each subpixel SP in the second direction Y. In the subpixel SP region where the second bank BNK2 is located, the second electrode CE2 may be formed and positioned on the passivation layer 116 between the signal wiring TL.

[0166] Figure 10 is an example of a device to which the display device according to the embodiments of this specification is applied, and according to Figure 10, the electronic device may be included in the wearable device 1100. The display device 1000 according to the embodiments of this specification may be applied to a mobile device, a laptop computer, a monitor or a TV, but the embodiments of this specification are not limited thereto.

[0167] Such an electronic device may include a case 1005, a display panel 100, and a display device 1000.

[0168] A display device according to one or more embodiments of this specification may be described as follows.

[0169] A display device according to one embodiment of this specification can be described as follows.

[0170] The display device according to the embodiment of this specification may include a display area on a substrate containing a plurality of pixels, a plurality of insulating layers disposed in the display area, a first bank and a second bank disposed on the plurality of insulating layers, a first electrode disposed on the first bank and the second bank, and a first optical layer that includes at least one microLED disposed on the first bank and the second bank and a portion of the first bank and the at least one microLED, and a connecting electrode disposed on the first bank, and a second electrode disposed on the upper and side surfaces of the first optical layer and connected to the connecting electrode.

[0171] According to some embodiments of this specification, the first bank and the second bank each have a first width in the first direction and a second width in the second direction, and the second width of the first bank may be greater than the second width of the second bank.

[0172] According to some embodiments of this specification, the first optical layer and the second electrode may be arranged extending in a first direction in the display area.

[0173] According to some embodiments of this specification, the width of the second electrode in the second direction may be wider than the second width of the first bank and the second width of the second bank.

[0174] According to some embodiments of this specification, the first optical layer and the second electrode may be arranged sequentially across a plurality of pixels.

[0175] According to some embodiments of this specification, a connecting electrode is arranged extending along one side of a first bank, and a second electrode may be in contact with the connecting electrode extending along one side of the first bank.

[0176] According to some embodiments of this specification, the system further includes a second optical layer disposed on a substrate and positioned on the side of the first optical layer, and a second electrode may be disposed between the first optical layer and the second optical layer.

[0177] According to some embodiments of this specification, a third optical layer disposed on the second electrode may be further included.

[0178] According to some embodiments of this specification, the configuration further includes a pixel driving circuit disposed on a substrate, and connecting electrodes may be electrically connected to the pixel driving circuit.

[0179] According to some embodiments of this specification, a plurality of pixels each include subpixels, and a first bank or a second bank may be arranged in the subpixels.

[0180] According to some embodiments of this specification, the width of the second electrode in the second direction may be the same for each subpixel.

[0181] A method for manufacturing a display device according to embodiments of this specification includes the steps of forming a pixel driving circuit on a substrate, forming a plurality of insulating layers on the pixel driving circuit, forming a first bank and a second bank on the plurality of insulating layers, forming a connecting electrode on the first bank, and arranging at least one microLED on the first bank and the second bank, and further including the steps of forming a first optical layer surrounding the first bank, the second bank and the at least one microLED, and arranging a second electrode on the first optical layer, wherein the second electrode is connected to a connecting electrode on the first bank, and the connecting electrode and the second electrode may be formed extending along the side surface of the first bank.

[0182] According to some embodiments of this specification, the second electrode may be formed extending along the side surface of the first optical layer.

[0183] According to some embodiments of this specification, the process further includes the step of forming a second optical layer on the side surface of a first optical layer on a substrate, and the second electrode may be positioned between the side surface of the first optical layer and the second optical layer.

[0184] According to some embodiments of this specification, the process may further include the step of forming a third optical layer on a second electrode.

[0185] According to some embodiments of this specification, the first optical layer and the second electrode may extend in a first direction and be arranged in a plurality of pixels.

[0186] According to some embodiments of this specification, the width of the first bank in the second direction intersecting the first direction may be wider than the width of the second bank in the second direction.

[0187] According to some embodiments of this specification, the second electrode may be formed to protrude in a second direction intersecting the first direction at subpixels located in each of the plurality of pixels.

[0188] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways without deviating from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Accordingly, the embodiments described above should be understood in all respects as illustrative and not limiting. The scope of protection of this specification should be interpreted as defined by the claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of this specification. [Explanation of Symbols]

[0189] 100 Display Panels 110 circuit boards

Claims

1. circuit board and The substrate has a display area including multiple pixels, Multiple insulating layers arranged in the display area, The first bank and the second bank are arranged on the plurality of insulating layers, A first electrode arranged on the first bank and the second bank, At least one microLED arranged on the first bank and the second bank, The first bank and the second bank and a first optical layer surrounding a portion of at least one microLED, A connecting electrode arranged on the first bank, A display device comprising a second electrode disposed on the upper and side surfaces of the first optical layer and connected to the connecting electrode.

2. The first bank and the second bank each have a first width in the first direction and a second width in the second direction, The display device according to claim 1, wherein the second width of the first bank is greater than the second width of the second bank.

3. The display device according to claim 2, wherein the first optical layer and the second electrode are arranged to extend in a first direction within the display area.

4. The display device according to claim 3, wherein the width of the second electrode in the second direction is wider than the second width of the first bank and the second width of the second bank.

5. The display device according to claim 1, wherein the first optical layer and the second electrode are arranged continuously on the plurality of pixels.

6. The connecting electrode is arranged extending along one side of the first bank, The display device according to claim 1, wherein the second electrode is in contact with the connecting electrode extending along one side of the first bank.

7. The present invention further includes a second optical layer disposed on the substrate and positioned on the side surface of the first optical layer, The display device according to claim 1, wherein the second electrode is disposed between the first optical layer and the second optical layer.

8. The display device according to claim 1, further comprising a third optical layer disposed on the second electrode.

9. The substrate further includes a pixel driving circuit arranged on the substrate, The display device according to claim 1, wherein the connecting electrode is electrically connected to the pixel driving circuit.

10. Each of the aforementioned multiple pixels includes a subpixel, The display device according to claim 1, wherein the first bank or the second bank is arranged in the subpixels.

11. The display device according to claim 10, wherein the width of the second electrode in the second direction is the same for each subpixel.

12. The display device according to claim 2, characterized in that the second electrode is formed to protrude in the second direction only at the location where the connecting electrode is arranged.

13. The steps include forming a pixel driving circuit on a substrate, The steps include forming a plurality of insulating layers on the pixel driving circuit, The steps include forming a first bank and a second bank on the plurality of insulating layers, The steps include forming a connecting electrode in the first bank, The steps include: placing at least one microLED on the first bank and the second bank; The steps include forming a first optical layer surrounding the first bank, the second bank and the at least one microLED, The process includes the step of placing a second electrode on the first optical layer, The second electrode is connected to the connecting electrode on the first bank, A method for manufacturing a display device, wherein the connecting electrode and the second electrode are formed extending along the side surface of the first bank.

14. The method for manufacturing a display device according to claim 13, wherein the second electrode is formed extending along the side surface of the first optical layer.

15. The method further includes the step of forming a second optical layer on the side surface of the first optical layer on the substrate, The method for manufacturing a display device according to claim 14, wherein the second electrode is disposed between the side surface of the first optical layer and the second optical layer.

16. The method for manufacturing a display device according to claim 13, further comprising the step of forming a third optical layer on the second electrode.

17. The method for manufacturing a display device according to claim 13, wherein the first optical layer and the second electrode extend in a first direction and are arranged in a plurality of pixels.

18. The method for manufacturing a display device according to claim 17, wherein the width of the first bank in the second direction intersecting the first direction is wider than the width of the second bank in the second direction.

19. The method for manufacturing a display device according to claim 17, wherein the second electrode is formed to protrude in a second direction that intersects with the first direction at each of the plurality of pixels in the subpixels.

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