Package substrate and semiconductor package including the same

Abstract

The present invention provides a package substrate having improved electrical characteristics and a semiconductor package containing the same. [Solution] The package substrate according to the present invention comprises a core including glass, which includes a first and second flat surface facing each other in the vertical direction and a first recess formed on the first surface; a first adhesive layer that contacts the first surface of the core and fills the first recess; a through electrode that penetrates the core and extends vertically, and is horizontally separated from the first recess; a first wiring structure disposed on the first adhesive layer and in contact with the through electrode; a first insulating film structure disposed on the first adhesive layer and at least partially covering the first wiring structure; and a first protective film disposed on the first insulating film structure and covering the upper surface of a part of the first wiring structure.

Description

Technical Field

[0001] The present invention relates to a package substrate and a semiconductor package including the same, and more particularly, to a package substrate having improved electrical characteristics and a semiconductor package including the same.

Background Art

[0002] A package substrate includes a core, insulating films disposed on the upper and lower portions of the core, and a wiring structure disposed within the insulating films.

[0003] As the area of the package substrate increases, a warpage phenomenon occurs in the package substrate, and in order to eliminate this, means for increasing the rigidity of the core are required.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the above-described conventional package substrate, and an object of the present invention is to provide a package substrate having improved electrical characteristics. Another object of the present invention is to provide a semiconductor package having improved electrical characteristics.

Means for Solving the Problems

[0005] A package substrate according to the present invention made to achieve the above object includes flat first and second surfaces facing each other in a vertical direction, includes a first recess formed on the first surface, a core including glass, a first adhesive layer contacting the first surface of the core and filling the first recess, a through electrode extending in the vertical direction through the core and horizontally spaced from the first recess, a first wiring structure disposed on the first adhesive layer and contacting the through electrode, a first insulating film structure disposed on the first adhesive layer and at least partially covering the first wiring structure, and a first protective film disposed on the first insulating film structure and covering an upper surface of a part of the first wiring structure.

[0006] Furthermore, the present invention, made to achieve the above objective, is characterized by comprising: a core including glass, which includes a first surface and a second surface facing each other in the vertical direction, and a first recess formed on the first surface; a first adhesive layer disposed in the first recess and containing a first organic insulating material; a second adhesive layer in contact with the first surface of the core and the upper surface of the first adhesive layer and containing a second organic insulating material different from the first organic insulating material; a through electrode penetrating the core, extending in the vertical direction and separated horizontally from the first recess; a first wiring structure disposed on the first adhesive layer and in contact with the through electrode; a first insulating film structure disposed on the first insulating film structure and covering at least partially the first wiring structure; and a first protective film disposed on the first insulating film structure and covering a part of the upper surface of the first wiring structure.

[0007] To achieve the above objective, the semiconductor package according to the present invention is characterized by comprising: a core including glass, which includes a first and second flat surface facing each other in the vertical direction and includes a first recess formed on the first surface; a first adhesive layer that contacts the first surface of the core and fills the first recess; a through electrode that penetrates the core, extends in the vertical direction and is horizontally separated from the first recess; a first wiring structure disposed on the first adhesive layer and in contact with the through electrode; a first insulating film structure disposed on the first adhesive layer and at least partially covering the first wiring structure; a first protective film disposed on the first insulating film structure and covering the upper surface of a part of the first wiring structure; a semiconductor chip disposed on the package substrate and including a conductive pad; a first conductive connecting member that contacts the conductive pad included in the semiconductor chip and is electrically connected to a part of the first wiring structure; and a molded member disposed on the package substrate and covering the side walls of the semiconductor chip and the first conductive connecting member. [Effects of the Invention]

[0008] According to the present invention, the package substrate and the semiconductor package including it are formed on the surface of the core, which increases the contact area between the adhesive layer in contact with the core surface and the core, and also increases the adhesion force between the adhesive layer portion formed in each recess and the core. As a result, the delamination phenomenon between the core and the adhesive layer of the package substrate is mitigated, ensuring improved structural stability and electrical properties. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view showing the schematic configuration of a package substrate according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view illustrating a method for manufacturing a package substrate according to an embodiment of the present invention. [Figure 3] This is a cross-sectional view illustrating a method for manufacturing a package substrate according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view illustrating a method for manufacturing a package substrate according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view illustrating a method for manufacturing a package substrate according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view illustrating a method for manufacturing a package substrate according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view showing a schematic configuration of a package substrate according to another embodiment of the present invention. [Figure 8] This is a cross-sectional view showing a schematic configuration of a package substrate according to another embodiment of the present invention. [Figure 9] This is a cross-sectional view showing a schematic configuration of a package substrate according to another embodiment of the present invention. [Figure 10] This is a cross-sectional view showing a schematic configuration of a package substrate according to another embodiment of the present invention. [Figure 11] This is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 12] This is a cross-sectional view showing the schematic configuration of an electronic device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0010] Next, specific examples of embodiments for implementing the package substrate and semiconductor package containing the same according to the present invention will be described with reference to the drawings.

[0011] In this specification, when a substance, layer (film), region, pad, electrode, pattern, structure, or process is referred to as “first,” “second,” and / or “third,” it is not intended to limit such components, but merely to distinguish each substance, layer (film), region, electrode, pad, pattern, structure, and process. Therefore, the "first," "second," and / or "third" can be used selectively or interchangeably for each material, layer (film), region, electrode, pad, pattern, structure, and process, respectively.

[0012] Figure 1 is a cross-sectional view showing a schematic configuration of a package substrate according to an embodiment of the present invention. Referring to Figure 1, the package substrate 100 includes a core 110 having a first surface 112 and a second surface 114 formed facing each other in the vertical direction and having recesses 150 formed thereon; a through electrode 130 extending vertically through the core 110; a first adhesive layer 160 formed above or below each of the first and second surfaces (112, 114) of the core 110 to fill the recesses 150; an insulating film structure 300 sequentially laminated vertically above or below the first adhesive layer 160; and first and second protective films (222, 224). A wiring structure 310 is positioned between the first adhesive layer 160 and the first and second protective films (222, 224).

[0013] In one embodiment, the core 110 includes glass. In one embodiment, the core 110 has a thickness of approximately 400 μm to 800 μm in the vertical direction. Each of the first and second faces (112, 114) of the core 110 is flat. In one embodiment, a plurality of recesses 150 may be formed horizontally spaced apart from each other above or below each of the first and second surfaces (112, 114) of the core 110. However, in the drawings, only two exemplary recesses 150 are shown among these. Here, the recesses 150 can be arranged in various layouts when viewed from above or below.

[0014] Each recess 150 has a shape such as a circular shape, an elliptical shape, a polygonal shape, or a rounded polygonal shape when viewed from above or below. In one embodiment, the horizontal width of each recess 150 is constant along the vertical direction, whereby the side walls of each recess 150 extend in the vertical direction. In one embodiment, the horizontal width of each recess 150 has a value of at least approximately 5 μm, and the vertical depth of each recess 150 has a value of at least approximately 10 μm.

[0015] On the other hand, in the drawings, it is shown that the recesses 150 are arranged in the same layout with respect to each other at the upper and lower parts of the first and second surfaces (112, 114) of the core 110. However, the present invention is not limited to this, and they can also be arranged in different layouts with respect to each other at the upper and lower parts of the core 110. That is, in the drawings, the recesses 150 respectively formed at the upper and lower parts of the first and second surfaces (112, 114) of the core 110 are arranged in a line-symmetric shape with respect to the line crossing the center of the core 110, whereby it is shown that the recesses 150 respectively formed at the upper and lower parts of the first and second surfaces (112, 114) of the core 110 overlap each other in the vertical direction. However, the present invention is not limited to this. That is, at least a part of the recess 150 formed on the first surface 112 may not overlap with the recess 150 formed under the second surface 114 in the vertical direction. Also, the recesses 150 can be formed only on the first surface 112 of the core 110, or can be formed only under the second surface 114 of the core 110.

[0016] Multiple through electrodes 130 are formed horizontally, spaced apart from each other; however, only four of these through electrodes 130 are shown in the drawing as an example. Here, the through-electrode 130 can be arranged in various layouts when viewed from above or below. In one embodiment, each through electrode 130 is horizontally separated from the recess 150. The through electrode 130 contains a metal such as copper or aluminum.

[0017] By forming recesses 150 above or below each of the first and second surfaces (112, 114) of the core 110, the area in contact between the first adhesive layer 160 and each of the first and second surfaces (112, 114) is increased. On the other hand, the first adhesive layer 160 formed on the first surface 112 of the core 110 has a flat upper surface, and the first adhesive layer 160 formed below the second surface 114 of the core 110 has a flat lower surface. In one embodiment, the first adhesive layer 160 includes a polymer such as epoxy. In other embodiments, the first adhesive layer 160 may also contain an insulating material such as ABF (Ajinomoto Build-up Film) (registered trademark).

[0018] In one embodiment, the insulating film structure 300 includes first and second insulating films (180, 200) sequentially laminated vertically above or below the first adhesive layer 160. However, this is merely illustrative, and the present invention is not limited thereto. The insulating film structure 300 may also include more insulating films stacked along the vertical direction. Each of the first and second insulating films (180, 200) may include an insulating material such as ABF®.

[0019] In one embodiment, the wiring structure 310 includes first to third vias (170, 190, 210) sequentially stacked vertically above or below the first adhesive layer 160, and first to third wirings (175, 195, 215) sequentially stacked vertically. However, this is merely illustrative, and the present invention is not limited thereto. The wiring structure 310 may also include more vias and wiring stacked vertically.

[0020] The first via 170 is in contact with the upper or lower surface of the through electrode 130 and is surrounded by the first adhesive layer 160. The first wiring 175 contacts the first via 170 and is formed on the first adhesive layer 160. Here, a portion of the upper or lower surface of the first wiring 175 is referred to as the first pad. The second via 190 contacts the upper or lower surface of the first pad of the first wiring 175 and is surrounded by the first insulating film 180. The second wiring 195 contacts the second via 190 and is formed on the first insulating film 180. Here, a portion of the upper or lower surface of the second wiring 195 is referred to as the second pad. The third via 210 contacts the upper or lower surface of the second pad of the second wiring 195 and is surrounded by the second insulating film 200. The third wiring 215 contacts the third via 210 and is formed on the second insulating film 200. Here, a portion of the upper or lower surface of the third wiring 215 is referred to as the third pad. Each of the first to third vias (170, 190, 210) and each of the first to third wirings (175, 195, 215) contains a metal such as copper or aluminum.

[0021] On the other hand, while the drawings exemplify the arrangement of the first to third vias (170, 190, 210) and the first to third wirings (175, 195, 215) in the same layout at the top and bottom of the core 110, the present invention is not limited to this, and these can also be arranged in different layouts at the top and bottom of the core 110. In other words, the drawings show that the first to third vias (170, 190, 210) and the first to third wirings (175, 195, 215) are arranged in a symmetrical shape with respect to a line crossing the center of the core 110, but the present invention is not limited thereto.

[0022] The first and second protective films (222, 224) are formed on the upper and lower parts of the second insulating film 220, respectively, and cover the third wiring 215. However, a second opening 225 is formed at the upper or lower part of each of the first and second protective films (222, 224) to expose the third pad of the third wiring 215. Each of the first and second protective films (222, 224) includes an insulating material such as solder resist (SR).

[0023] In one embodiment, the package substrate 100 is, for example, a printed circuit board (PCB).

[0024] As described above, recesses 150 are formed on the upper and lower parts of the first and second surfaces (112, 114) of the core 110 contained in the package substrate 100. As a result, the total area of ​​the first adhesive layer 160 in contact with the first and second surfaces (112, 114) of the core 110 increases, and the portion of the first adhesive layer 160 formed within each recess 150 has greater adhesion to the core 110 compared to the portion of the first adhesive layer 160 in contact with a flat surface where no recesses 150 are formed. In other words, if the first and second surfaces (112, 114) of the glass-containing core 110 are flat, the first adhesive layer 160, which comes into contact with these surfaces and contains an insulating material different from the glass, does not adhere tightly to the core 110 and can be partially peeled off.

[0025] However, in one embodiment, recesses 150 are formed on the first and second surfaces (112, 114) of the core 110, increasing the contact area between the first adhesive layer 160 and the core 110. Furthermore, the adhesion force between the portion of the first adhesive layer 160 formed within each recess 150 and the core 110 is increased. As a result, even if partial delamination occurs between the core 110 and the first adhesive layer 160, the overall adhesion force between the first adhesive layer 160 and the core 110 is improved.

[0026] Figures 2 to 6 are cross-sectional views illustrating a method for manufacturing a package substrate according to an embodiment of the present invention. Referring to Figure 2, a via hole 120 is formed that penetrates the core 110, which includes the first and second surfaces (112, 114) formed facing each other in the vertical direction.

[0027] In one embodiment, the core 110 includes glass. In one embodiment, the via holes 120 are formed, for example, using a laser drill, and multiple via holes are formed spaced apart from each other along the horizontal direction.

[0028] Referring to Figure 3, a first seed film is formed on the first and second surfaces (112, 114) of the core 110 and on the inner walls of the via holes 120. After forming a through-electrode film that fills the via holes 120 on the first seed film by, for example, an electroplating process or an electroless plating process, a planarization process is performed on the through-electrode film until the first and second surfaces (112, 114) of the core 110 are exposed. As a result, a through-electrode 130 is formed within each via hole 120, extending vertically through the core 110. In one embodiment, the planarization process includes a chemical mechanical polishing (CMP) process.

[0029] Referring to Figure 4, a first mask 140 is formed on each of the first and second surfaces (112, 114) of the core 110 to cover the upper surface of the through electrode 130. Then, the portion of the core 110 not covered by the first mask 140 is partially removed to form a recess 150. In one embodiment, the recess 150 is formed by an etching process. In other embodiments, the recess 150 can also be formed, for example, by a drilling process using a laser drill. In one embodiment, multiple recesses 150 are formed spaced apart from each other along the horizontal direction. Here, each recess 150 can have a shape such as a circle, an ellipse, a polygon, or a polygon with rounded corners when viewed from above. In one embodiment, the horizontal width of each recess 150 is constant along the vertical direction, so that the side walls of each recess 150 extend in the vertical direction.

[0030] Referring to Figure 5, the first mask 140 is removed to expose the first and second surfaces (112, 114) of the core 110 and the upper and lower surfaces of the through electrode 130. Then, a first adhesive layer 160 for filling the recess 150 is formed on each of the first and second surfaces (112, 114) of the core 110 and on the upper and lower surfaces of the through electrode 130. In one embodiment, the first adhesive layer 160 is formed on the first and second surfaces (112, 114) of the core 110 and on the upper and lower surfaces of the through electrode 130 by a lamination or coating process.

[0031] Referring to Figure 6, the first adhesive layer 160 is partially removed to form a first opening that exposes the upper or lower surface of each through electrode 130. A second seed film is formed on the upper and lower surfaces of the through electrodes 130 exposed by the first opening and on the first adhesive layer 160. A second mask is then formed that partially covers the second seed film and has a second opening that is superimposed perpendicularly to the through electrodes 130. For example, a conductive film that fills the second opening is formed on the second seed film by an electroplating process or an electroless plating process, and then the second mask is removed. This forms a first via 170 and a first wiring 175 that contact the upper or lower surface of each through electrode 130.

[0032] Referring again to Figure 1, the first and second insulating films (180, 200), the second and third vias (190, 210), and the second and third wirings (195, 215) are formed by performing a process that is substantially the same as or similar to the process described in Figure 6. Here, the vertically stacked first and second insulating films (180, 200) together can form an insulating film structure 300, and the vertically stacked first to third vias (170, 190, 210) and first to third wirings (175, 195, 215) together form a wiring structure 310.

[0033] Subsequently, first and second protective films (222, 224) covering the third wiring 215 are formed on the second insulating film 200. The first and second protective films (222, 224) are partially removed to form a third opening 225 that exposes a portion of the surface of the third wiring 215, thereby completing the manufacturing of the package substrate 100.

[0034] Figure 7 is a cross-sectional view showing the schematic configuration of a package substrate according to another embodiment of the present invention. The package substrate is substantially identical or similar to the package substrate described in Figure 1, except that it further includes a second adhesive layer, so redundant explanations are omitted. Referring to Figure 7, the package substrate 100 further includes a second adhesive layer 165 in addition to the first adhesive layer 160.

[0035] Here, the first adhesive layer 160 contacts the flat portions of each of the first and second surfaces (112, 114) of the core 110, i.e., the first and second surfaces (112, 114) where the recess 150 is not formed, and the second adhesive layer 165 is formed within the recess 150 and contacts the upper surfaces of the core 110 and the first adhesive layer 160. In one embodiment, the second adhesive layer 165 contains an organic insulating material different from that of the first adhesive layer 160. For example, the second adhesive layer 165 contains an organic insulating material that has high adhesive strength to the glass contained in the core 110 and the polymer contained in the first adhesive layer 160.

[0036] Figures 8 to 10 are cross-sectional views showing the schematic configuration of a package substrate according to another embodiment of the present invention. Each package substrate is substantially identical or similar to the package substrate described in Figure 1, except for the shape of the recesses, so redundant explanations will be omitted. On the other hand, although not shown in the figure, the shape of the recesses formed on each package substrate can also be applied to the package substrate described in Figure 7.

[0037] Referring to Figure 8, the horizontal width of the recess 150 gradually decreases as it moves away from the first and second surfaces (112, 114) of the core 110. As a result, the side walls of the recess 150 are inclined with respect to the vertical.

[0038] Referring to Figure 9, the vertical cross-section of the recess 150 has a semicircular shape. For example, the recess 150 is formed by an isotropic etching process on the core 110, i.e., a wet etching process, so that the horizontal width of the recess 150 gradually increases as it moves away from the first and second surfaces (112, 114) of the core 110, and then decreases again.

[0039] Referring to Figure 10, the horizontal width of the recess 150 decreases in a stepwise manner as it moves away from the first and second surfaces (112, 114) of the core 110. As a result, the vertical cross-section of the recess 150 has a stepped shape.

[0040] Figure 11 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. Since the semiconductor package includes the package substrate shown in Figure 1, a redundant explanation regarding it will be omitted. However, the semiconductor package may include not only the package substrate shown in Figure 1, but also the package substrates shown in Figures 7 to 10.

[0041] Referring to Figure 11, the semiconductor package includes a package substrate 100, a semiconductor chip 400 disposed on a first protective film 222 contained in the package substrate 100, a first conductive connecting member 420 sandwiched between them, a molding member 500 disposed on the first protective film 222 and covering the semiconductor chip 400 and the first conductive connecting member 420, and a second conductive connecting member 250 disposed beneath a second protective film 224 contained in the package substrate 100.

[0042] The semiconductor chip 400 is, for example, a logic chip including logic elements, or a memory chip including memory elements. A conductive pad 410 is formed on one surface of the semiconductor chip 400, and the first conductive connecting member 420 contacts the lower surface of the conductive pad 410 and the upper surface of the third pad of the third wiring 215, which is exposed by a third opening 225 formed in the first protective film 222. The first conductive connecting member 420 is, for example, a conductive bump or conductive ball containing solder.

[0043] The mold component 500 includes, for example, an epoxy molding compound (EMC). The second conductive connecting member 250 contacts the lower surface of the third pad of the third wiring 215, which is exposed through the third opening 225 formed in the second protective film 224. The second conductive connecting member 250 is, for example, a conductive bump or conductive ball containing solder. In one embodiment, the recesses 150 formed on the first and second surfaces (112, 114) of the core 110 contained in the package substrate 100 do not overlap the semiconductor chip 400 in a perpendicular direction.

[0044] As explained in Figure 1, the recess 150 improves the adhesion between the core 110 contained in the package substrate 100 and the first adhesive layer 160, so that the semiconductor package including the package substrate 100 can ensure improved structural stability and electrical characteristics.

[0045] Figure 12 is a cross-sectional view showing a schematic configuration of an electronic device according to an embodiment of the present invention. Since the electronic device includes the package substrate shown in Figure 1, a redundant explanation regarding it will be omitted. However, the electronic device may also include package substrates as shown in Figures 7 to 10, in addition to the package substrate shown in Figure 1.

[0046] Referring to Figure 12, the electronic device 10 includes a package substrate 100, an interposer 30, and first and second semiconductor devices (40, 50). Furthermore, the electronic device 10 further includes first to third underfill members (34, 44, 54), a heat slug 60, and a heat dissipation member 62.

[0047] In one embodiment, the electronic device 10 is a memory module having a 2.5D package structure, and includes an interposer 30 for electrically connecting the first and second semiconductor devices (40, 50) to each other. In one embodiment, the first semiconductor device 40 includes a logic device, and the second semiconductor device 50 includes a memory device. Logic devices are application-specific integrated circuit (ASIC) chips, including, for example, central processing units (CPUs), graphics processing units (GPUs), microprocessors, microcontrollers, application processors (APs), and digital signal processing cores. The memory device may include, for example, a semiconductor package such as an HBM package.

[0048] The interposer 30 is mounted on the package substrate 100 via a third conductive connecting member 32. In one embodiment, the interposer 30 is positioned inside the region where the package substrate 100 is formed, as viewed from above, and the surface area of ​​the interposer 30 is smaller than the surface area of ​​the package substrate 100. The interposer 30 is a silicon interposer or rewiring interposer that includes multiple wirings formed inside it. The first semiconductor device 40 and the second semiconductor device 50 are connected to each other via wiring within the interposer 30, or are electrically connected to the package substrate 100 via the third conductive connecting member 32. The third conductive connection portion 32 includes, for example, microbumps. The silicon interposer can provide high-density interconnection between the first and second semiconductor devices (40, 50).

[0049] The first semiconductor device 40 is placed on the interposer 30 and mounted on the interposer 30, for example, by a flip-chip bonding method. Here, the first semiconductor device 40 is positioned downwards so that the active surface on which the conductive pads are formed faces the interposer 30, and is mounted on the interposer 30. The conductive pads of the first semiconductor device 40 are electrically connected to the conductive pads of the interposer 30 via the fourth conductive connecting member 42. The fourth conductive connecting member 42 includes, for example, microbumps. In contrast, the first semiconductor device 40 can also be mounted on the interposer 30 using a wire bonding method, in which case the active surface of the first semiconductor device 40 is positioned on top.

[0050] The second semiconductor device 50 is positioned on the interposer 30 and is horizontally separated from the first semiconductor device 40. The second semiconductor device 50 is mounted on the interposer 30, for example, by a flip-chip bonding method. Here, the conductive pads of the second semiconductor device 50 are electrically connected to the conductive pads of the interposer 30 via the fifth conductive connecting member 52. Although the drawing shows that only one first semiconductor device 40 and one second semiconductor device 50 are arranged on the interposer 30, the present invention is not limited thereto, and multiple first and second semiconductor devices (40, 50) can be arranged on the interposer 30.

[0051] In one embodiment, the first underfill member 34 fills the space between the interposer 30 and the package substrate 100, and the second and third underfill members (44, 54) fill the space between the first semiconductor device 40 and the interposer 30, and the space between the second semiconductor device 50 and the interposer 30, respectively. The first to third underfill members (34, 44, 54) contain a material with relatively high fluidity so as to effectively fill the small space between the first and second semiconductor devices (40, 50) and the interposer 30, or the small space between the interposer 30 and the package substrate 100. For example, each of the first to third underfill members (34, 44, 54) may contain an adhesive containing an epoxy substance.

[0052] In one embodiment, the second semiconductor device 50 includes a buffer die and a plurality of memory dies (chips) sequentially stacked on the buffer die. The buffer die and memory die are electrically connected to each other via through-electrodes, such as through-silicon vias (TSVs), and the through-electrodes are electrically connected to each other via bonding pads. The buffer die and memory die communicate data signals and control signals via through-hole electrodes. In one embodiment, the heat slag 60 covers the first and second semiconductor devices (40, 50) on the package substrate 100 so as to be in thermal contact with them.

[0053] On the other hand, heat dissipation members 62 are arranged on the upper surfaces of each of the first and second semiconductor devices (40, 50), and the heat dissipation members 62 include, for example, a thermal interface material (TIM). The heat slag 60 makes thermal contact with the first and second semiconductor devices (40, 50) via the heat dissipation member 62. In one embodiment, the recesses 150 formed on the first and second surfaces (112, 114) of the core 110 contained in the package substrate 100 do not overlap the first and second semiconductor devices (40, 50) in a perpendicular direction. The electronic device 10 is mounted on a module substrate (not shown) via a second conductive connecting member 250 to constitute a memory module.

[0054] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0055] 10 Electronic equipment 32, 42, 52 (3rd to 5th) conductive connecting members 34, 44, 54 (1st to 3rd) underfill members 40, 50 (1st, 2nd) Semiconductor Devices 60 Heat Slags 62 Heat dissipation components 100 Package Substrates 110 cores 112, 114 Core's first and second faces 120 Beer Hall 130 Through electrode 140 First Mask 150 recesses 160, 165 (1st, 2nd) adhesive layer 170, 190, 210 (1st to 3rd) Beer 175, 195, 215 (1st to 3rd) wiring 180, 200 (1st, 2nd) insulating film 222, 224 (1st, 2nd) protective film 225 Third opening 300 Insulating Film Structures 310 Wiring structures 410 Conductive Pads 420, 250 (1st, 2nd) conductive connecting members 500 molded components

Claims

1. A core comprising a glass core, which includes a first and second flat surface facing each other in the vertical direction, and a first recess formed on the first surface, A first adhesive layer that contacts the first surface of the core and fills the first recess, A through electrode that penetrates the core and extends in the vertical direction, and is spaced horizontally apart from the first recess, A first wiring structure is disposed on the first adhesive layer and in contact with the through electrode, A first insulating film structure is disposed on the first adhesive layer and covers the first wiring structure at least partially, A package substrate characterized by having a first protective film disposed on the first insulating film structure and covering the upper surface of a part of the first wiring structure.

2. The package substrate according to claim 1, characterized in that the width of the first recess in the horizontal direction is constant along the vertical direction.

3. The package substrate according to claim 1, characterized in that the width of the first recess gradually decreases in the horizontal direction as it moves away from the first surface along the vertical direction.

4. The package substrate according to claim 1, characterized in that the width of the first recess gradually increases along the vertical direction as it moves away from the first surface, and then gradually decreases.

5. The package substrate according to claim 1, characterized in that the cross-section of the first recess in the vertical direction has a stepped shape.

6. The package substrate according to claim 1, characterized in that a plurality of the first recesses are formed spaced apart from each other along the horizontal direction.

7. The first adhesive layer contains epoxy, The package substrate according to claim 1, characterized in that the first insulating film structure includes ABF (Ajinomoto build-up film) (registered trademark).

8. The package substrate according to claim 1, characterized in that the core further includes a second recess formed below the second surface.

9. A second adhesive layer that contacts the second surface of the core and fills the second recess, A second wiring structure is positioned beneath the second adhesive layer and in contact with the through electrode, A second insulating film structure is disposed beneath the second adhesive layer and covers the second wiring structure at least partially, The package substrate according to claim 8, further comprising a second protective film disposed beneath the second insulating film structure and covering the lower surface of a portion of the second wiring structure.

10. The package substrate according to claim 9, characterized in that the first recess and the second recess are arranged in a line-symmetrical shape with respect to a line that crosses the core in the horizontal direction.

11. A core comprising a first surface and a second surface facing each other in the vertical direction, a first recess formed on the first surface, and a glass core, Displaced within the first recess, a first adhesive layer containing a first organic insulating material, A second adhesive layer, which is in contact with the first surface of the core and the upper surface of the first adhesive layer, and which contains a second organic insulating material different from the first organic insulating material, A through electrode extends vertically through the core and is spaced horizontally apart from the first recess, A first wiring structure is disposed on the first adhesive layer and in contact with the through electrode, A first insulating film structure is disposed on the first adhesive layer and covers the first wiring structure at least partially, A package substrate characterized by having a first protective film disposed on the first insulating film structure and covering the upper surface of a part of the first wiring structure.

12. The package substrate according to claim 11, characterized in that the width of the first recess gradually decreases along the vertical direction as it moves away from the first surface.

13. The package substrate according to claim 11, characterized in that the width of the first recess gradually increases along the vertical direction as it moves away from the first surface, and then gradually decreases.

14. The package substrate according to claim 11, characterized in that the vertical cross-section of the first recess has a stepped shape.

15. The package substrate according to claim 11, characterized in that a plurality of the first recesses are formed spaced apart from each other along the horizontal direction.

16. The core further includes a second recess formed beneath the second surface, A third adhesive layer that contacts the second surface of the core and fills the second recess, A second wiring structure is positioned beneath the third adhesive layer and in contact with the through electrode, A second insulating film structure is disposed beneath the third adhesive layer and at least partially covers the second wiring structure, The package substrate according to claim 11, further comprising a second protective film disposed beneath the second insulating film structure and covering the upper surface of a portion of the second wiring structure.

17. A core comprising a glass core, which includes a first and second flat surface facing each other in the vertical direction, and a first recess formed on the first surface, A first adhesive layer that contacts the first surface of the core and fills the first recess, A through electrode extends vertically through the core and is spaced horizontally apart from the first recess, A first wiring structure is disposed on the first adhesive layer and in contact with the through electrode, A first insulating film structure is disposed on the first adhesive layer and covers the first wiring structure at least partially, A package substrate including a first protective film disposed on the first insulating film structure and covering the upper surface of a portion of the first wiring structure, A semiconductor chip, including a conductive pad, is disposed on the aforementioned package substrate. A first conductive connecting member that contacts the conductive pad included in the semiconductor chip and is electrically connected to a part of the first wiring structure, A semiconductor package characterized by having a mold member disposed on the package substrate and covering the side walls of the semiconductor chip and the first conductive connecting member.

18. The core of the package substrate further includes a second recess formed below the first surface, The aforementioned package substrate is A second adhesive layer that contacts the second surface of the core and fills the second recess, A second wiring structure is positioned beneath the second adhesive layer and in contact with the through electrode, A second insulating film structure is disposed beneath the second adhesive layer and covers the second wiring structure at least partially, The present invention further includes a second protective film disposed beneath the second insulating film structure and covering the upper surface of a portion of the second wiring structure, The semiconductor package according to claim 17, further comprising a second conductive connecting member that contacts the lower surface of a part of the second wiring structure.

19. The semiconductor package according to claim 17, characterized in that the first recess does not overlap the semiconductor chip in the vertical direction.

20. An interposer is disposed between the package substrate and the first conductive connecting member and is electrically connected to the first wiring structure and the first conductive connecting member, A heat dissipation member that contacts the upper surface of the semiconductor chip, The semiconductor package according to claim 17, further comprising a heat slag that contacts the heat dissipation member.

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